drivers/clk/samsung/clk-exynos5260.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   4  * Author: Rahul Sharma <rahul.sharma@samsung.com>
   5  *
   6  * Common Clock Framework support for Exynos5260 SoC.
   7  */
   8
   9 #include <linux/of.h>
  10 #include <linux/of_address.h>
  11
  12 #include "clk-exynos5260.h"
  13 #include "clk.h"
  14 #include "clk-pll.h"
  15
  16 #include <dt-bindings/clock/exynos5260-clk.h>
  17
  18 /* NOTE: Must be equal to the last clock ID increased by one */
  19 #define CLKS_NR_TOP                     (PHYCLK_USBDRD30_UDRD30_PHYCLOCK + 1)
  20 #define CLKS_NR_EGL                     (EGL_DOUT_EGL1 + 1)
  21 #define CLKS_NR_KFC                     (KFC_DOUT_KFC1 + 1)
  22 #define CLKS_NR_MIF                     (MIF_SCLK_LPDDR3PHY_WRAP_U0 + 1)
  23 #define CLKS_NR_G3D                     (G3D_CLK_G3D + 1)
  24 #define CLKS_NR_AUD                     (AUD_SCLK_I2S + 1)
  25 #define CLKS_NR_MFC                     (MFC_CLK_SMMU2_MFCM0 + 1)
  26 #define CLKS_NR_GSCL                    (GSCL_SCLK_CSIS0_WRAP + 1)
  27 #define CLKS_NR_FSYS                    (FSYS_PHYCLK_USBHOST20 + 1)
  28 #define CLKS_NR_PERI                    (PERI_SCLK_PCM1 + 1)
  29 #define CLKS_NR_DISP                    (DISP_MOUT_HDMI_PHY_PIXEL_USER + 1)
  30 #define CLKS_NR_G2D                     (G2D_CLK_SMMU3_G2D + 1)
  31 #define CLKS_NR_ISP                     (ISP_SCLK_UART_EXT + 1)
  32
  33 /*
  34  * Applicable for all 2550 Type PLLS for Exynos5260, listed below
  35  * DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL.
  36  */
  37 static const struct samsung_pll_rate_table pll2550_24mhz_tbl[] __initconst = {
  38         PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
  39         PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
  40         PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
  41         PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
  42         PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
  43         PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),
  44         PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
  45         PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
  46         PLL_35XX_RATE(24 * MHZ, 933000000, 311, 4, 1),
  47         PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1),
  48         PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1),
  49         PLL_35XX_RATE(24 * MHZ, 733000000, 733, 12, 1),
  50         PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
  51         PLL_35XX_RATE(24 * MHZ, 667000000, 667, 12, 1),
  52         PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1),
  53         PLL_35XX_RATE(24 * MHZ, 620000000, 310, 3, 2),
  54         PLL_35XX_RATE(24 * MHZ, 600000000, 400, 4, 2),
  55         PLL_35XX_RATE(24 * MHZ, 543000000, 362, 4, 2),
  56         PLL_35XX_RATE(24 * MHZ, 533000000, 533, 6, 2),
  57         PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2),
  58         PLL_35XX_RATE(24 * MHZ, 450000000, 300, 4, 2),
  59         PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2),
  60         PLL_35XX_RATE(24 * MHZ, 350000000, 175, 3, 2),
  61         PLL_35XX_RATE(24 * MHZ, 300000000, 400, 4, 3),
  62         PLL_35XX_RATE(24 * MHZ, 266000000, 266, 3, 3),
  63         PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3),
  64         PLL_35XX_RATE(24 * MHZ, 160000000, 160, 3, 3),
  65 };
  66
  67 /*
  68  * Applicable for 2650 Type PLL for AUD_PLL.
  69  */
  70 static const struct samsung_pll_rate_table pll2650_24mhz_tbl[] __initconst = {
  71         PLL_36XX_RATE(24 * MHZ, 1600000000, 200, 3, 0, 0),
  72         PLL_36XX_RATE(24 * MHZ, 1200000000, 100, 2, 0, 0),
  73         PLL_36XX_RATE(24 * MHZ, 1000000000, 250, 3, 1, 0),
  74         PLL_36XX_RATE(24 * MHZ, 800000000, 200, 3, 1, 0),
  75         PLL_36XX_RATE(24 * MHZ, 600000000, 100, 2, 1, 0),
  76         PLL_36XX_RATE(24 * MHZ, 532000000, 266, 3, 2, 0),
  77         PLL_36XX_RATE(24 * MHZ, 480000000, 160, 2, 2, 0),
  78         PLL_36XX_RATE(24 * MHZ, 432000000, 144, 2, 2, 0),
  79         PLL_36XX_RATE(24 * MHZ, 400000000, 200, 3, 2, 0),
  80         PLL_36XX_RATE(24 * MHZ, 394073128, 459, 7, 2, 49282),
  81         PLL_36XX_RATE(24 * MHZ, 333000000, 111, 2, 2, 0),
  82         PLL_36XX_RATE(24 * MHZ, 300000000, 100, 2, 2, 0),
  83         PLL_36XX_RATE(24 * MHZ, 266000000, 266, 3, 3, 0),
  84         PLL_36XX_RATE(24 * MHZ, 200000000, 200, 3, 3, 0),
  85         PLL_36XX_RATE(24 * MHZ, 166000000, 166, 3, 3, 0),
  86         PLL_36XX_RATE(24 * MHZ, 133000000, 266, 3, 4, 0),
  87         PLL_36XX_RATE(24 * MHZ, 100000000, 200, 3, 4, 0),
  88         PLL_36XX_RATE(24 * MHZ, 66000000, 176, 2, 5, 0),
  89 };
  90
  91 /* CMU_AUD */
  92
  93 static const unsigned long aud_clk_regs[] __initconst = {
  94         MUX_SEL_AUD,
  95         DIV_AUD0,
  96         DIV_AUD1,
  97         EN_ACLK_AUD,
  98         EN_PCLK_AUD,
  99         EN_SCLK_AUD,
 100         EN_IP_AUD,
 101 };
 102
 103 PNAME(mout_aud_pll_user_p) = {"fin_pll", "fout_aud_pll"};
 104 PNAME(mout_sclk_aud_i2s_p) = {"mout_aud_pll_user", "ioclk_i2s_cdclk"};
 105 PNAME(mout_sclk_aud_pcm_p) = {"mout_aud_pll_user", "ioclk_pcm_extclk"};
 106
 107 static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
 108         MUX(AUD_MOUT_AUD_PLL_USER, "mout_aud_pll_user", mout_aud_pll_user_p,
 109                         MUX_SEL_AUD, 0, 1),
 110         MUX(AUD_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_i2s_p,
 111                         MUX_SEL_AUD, 4, 1),
 112         MUX(AUD_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
 113                         MUX_SEL_AUD, 8, 1),
 114 };
 115
 116 static const struct samsung_div_clock aud_div_clks[] __initconst = {
 117         DIV(AUD_DOUT_ACLK_AUD_131, "dout_aclk_aud_131", "mout_aud_pll_user",
 118                         DIV_AUD0, 0, 4),
 119
 120         DIV(AUD_DOUT_SCLK_AUD_I2S, "dout_sclk_aud_i2s", "mout_sclk_aud_i2s",
 121                         DIV_AUD1, 0, 4),
 122         DIV(AUD_DOUT_SCLK_AUD_PCM, "dout_sclk_aud_pcm", "mout_sclk_aud_pcm",
 123                         DIV_AUD1, 4, 8),
 124         DIV(AUD_DOUT_SCLK_AUD_UART, "dout_sclk_aud_uart", "mout_aud_pll_user",
 125                         DIV_AUD1, 12, 4),
 126 };
 127
 128 static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
 129         GATE(AUD_SCLK_I2S, "sclk_aud_i2s", "dout_sclk_aud_i2s",
 130                         EN_SCLK_AUD, 0, CLK_SET_RATE_PARENT, 0),
 131         GATE(AUD_SCLK_PCM, "sclk_aud_pcm", "dout_sclk_aud_pcm",
 132                         EN_SCLK_AUD, 1, CLK_SET_RATE_PARENT, 0),
 133         GATE(AUD_SCLK_AUD_UART, "sclk_aud_uart", "dout_sclk_aud_uart",
 134                         EN_SCLK_AUD, 2, CLK_SET_RATE_PARENT, 0),
 135
 136         GATE(AUD_CLK_SRAMC, "clk_sramc", "dout_aclk_aud_131", EN_IP_AUD,
 137                         0, 0, 0),
 138         GATE(AUD_CLK_DMAC, "clk_dmac", "dout_aclk_aud_131",
 139                         EN_IP_AUD, 1, 0, 0),
 140         GATE(AUD_CLK_I2S, "clk_i2s", "dout_aclk_aud_131", EN_IP_AUD, 2, 0, 0),
 141         GATE(AUD_CLK_PCM, "clk_pcm", "dout_aclk_aud_131", EN_IP_AUD, 3, 0, 0),
 142         GATE(AUD_CLK_AUD_UART, "clk_aud_uart", "dout_aclk_aud_131",
 143                         EN_IP_AUD, 4, 0, 0),
 144 };
 145
 146 static const struct samsung_cmu_info aud_cmu __initconst = {
 147         .mux_clks       = aud_mux_clks,
 148         .nr_mux_clks    = ARRAY_SIZE(aud_mux_clks),
 149         .div_clks       = aud_div_clks,
 150         .nr_div_clks    = ARRAY_SIZE(aud_div_clks),
 151         .gate_clks      = aud_gate_clks,
 152         .nr_gate_clks   = ARRAY_SIZE(aud_gate_clks),
 153         .nr_clk_ids     = CLKS_NR_AUD,
 154         .clk_regs       = aud_clk_regs,
 155         .nr_clk_regs    = ARRAY_SIZE(aud_clk_regs),
 156 };
 157
 158 static void __init exynos5260_clk_aud_init(struct device_node *np)
 159 {
 160         samsung_cmu_register_one(np, &aud_cmu);
 161 }
 162
 163 CLK_OF_DECLARE(exynos5260_clk_aud, "samsung,exynos5260-clock-aud",
 164                 exynos5260_clk_aud_init);
 165
 166
 167 /* CMU_DISP */
 168
 169 static const unsigned long disp_clk_regs[] __initconst = {
 170         MUX_SEL_DISP0,
 171         MUX_SEL_DISP1,
 172         MUX_SEL_DISP2,
 173         MUX_SEL_DISP3,
 174         MUX_SEL_DISP4,
 175         DIV_DISP,
 176         EN_ACLK_DISP,
 177         EN_PCLK_DISP,
 178         EN_SCLK_DISP0,
 179         EN_SCLK_DISP1,
 180         EN_IP_DISP,
 181         EN_IP_DISP_BUS,
 182 };
 183
 184 PNAME(mout_phyclk_dptx_phy_ch3_txd_clk_user_p) = {"fin_pll",
 185                         "phyclk_dptx_phy_ch3_txd_clk"};
 186 PNAME(mout_phyclk_dptx_phy_ch2_txd_clk_user_p) = {"fin_pll",
 187                         "phyclk_dptx_phy_ch2_txd_clk"};
 188 PNAME(mout_phyclk_dptx_phy_ch1_txd_clk_user_p) = {"fin_pll",
 189                         "phyclk_dptx_phy_ch1_txd_clk"};
 190 PNAME(mout_phyclk_dptx_phy_ch0_txd_clk_user_p) = {"fin_pll",
 191                         "phyclk_dptx_phy_ch0_txd_clk"};
 192 PNAME(mout_aclk_disp_222_user_p) = {"fin_pll", "dout_aclk_disp_222"};
 193 PNAME(mout_sclk_disp_pixel_user_p) = {"fin_pll", "dout_sclk_disp_pixel"};
 194 PNAME(mout_aclk_disp_333_user_p) = {"fin_pll", "dout_aclk_disp_333"};
 195 PNAME(mout_phyclk_hdmi_phy_tmds_clko_user_p) = {"fin_pll",
 196                         "phyclk_hdmi_phy_tmds_clko"};
 197 PNAME(mout_phyclk_hdmi_phy_ref_clko_user_p) = {"fin_pll",
 198                         "phyclk_hdmi_phy_ref_clko"};
 199 PNAME(mout_phyclk_hdmi_phy_pixel_clko_user_p) = {"fin_pll",
 200                         "phyclk_hdmi_phy_pixel_clko"};
 201 PNAME(mout_phyclk_hdmi_link_o_tmds_clkhi_user_p) = {"fin_pll",
 202                         "phyclk_hdmi_link_o_tmds_clkhi"};
 203 PNAME(mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p) = {"fin_pll",
 204                         "phyclk_mipi_dphy_4l_m_txbyte_clkhs"};
 205 PNAME(mout_phyclk_dptx_phy_o_ref_clk_24m_user_p) = {"fin_pll",
 206                         "phyclk_dptx_phy_o_ref_clk_24m"};
 207 PNAME(mout_phyclk_dptx_phy_clk_div2_user_p) = {"fin_pll",
 208                         "phyclk_dptx_phy_clk_div2"};
 209 PNAME(mout_sclk_hdmi_pixel_p) = {"mout_sclk_disp_pixel_user",
 210                         "mout_aclk_disp_222_user"};
 211 PNAME(mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p) = {"fin_pll",
 212                         "phyclk_mipi_dphy_4l_m_rxclkesc0"};
 213 PNAME(mout_sclk_hdmi_spdif_p) = {"fin_pll", "ioclk_spdif_extclk",
 214                         "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"};
 215
 216 static const struct samsung_mux_clock disp_mux_clks[] __initconst = {
 217         MUX(DISP_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user",
 218                         mout_aclk_disp_333_user_p,
 219                         MUX_SEL_DISP0, 0, 1),
 220         MUX(DISP_MOUT_SCLK_DISP_PIXEL_USER, "mout_sclk_disp_pixel_user",
 221                         mout_sclk_disp_pixel_user_p,
 222                         MUX_SEL_DISP0, 4, 1),
 223         MUX(DISP_MOUT_ACLK_DISP_222_USER, "mout_aclk_disp_222_user",
 224                         mout_aclk_disp_222_user_p,
 225                         MUX_SEL_DISP0, 8, 1),
 226         MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH0_TXD_CLK_USER,
 227                         "mout_phyclk_dptx_phy_ch0_txd_clk_user",
 228                         mout_phyclk_dptx_phy_ch0_txd_clk_user_p,
 229                         MUX_SEL_DISP0, 16, 1),
 230         MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH1_TXD_CLK_USER,
 231                         "mout_phyclk_dptx_phy_ch1_txd_clk_user",
 232                         mout_phyclk_dptx_phy_ch1_txd_clk_user_p,
 233                         MUX_SEL_DISP0, 20, 1),
 234         MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH2_TXD_CLK_USER,
 235                         "mout_phyclk_dptx_phy_ch2_txd_clk_user",
 236                         mout_phyclk_dptx_phy_ch2_txd_clk_user_p,
 237                         MUX_SEL_DISP0, 24, 1),
 238         MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH3_TXD_CLK_USER,
 239                         "mout_phyclk_dptx_phy_ch3_txd_clk_user",
 240                         mout_phyclk_dptx_phy_ch3_txd_clk_user_p,
 241                         MUX_SEL_DISP0, 28, 1),
 242
 243         MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CLK_DIV2_USER,
 244                         "mout_phyclk_dptx_phy_clk_div2_user",
 245                         mout_phyclk_dptx_phy_clk_div2_user_p,
 246                         MUX_SEL_DISP1, 0, 1),
 247         MUX(DISP_MOUT_PHYCLK_DPTX_PHY_O_REF_CLK_24M_USER,
 248                         "mout_phyclk_dptx_phy_o_ref_clk_24m_user",
 249                         mout_phyclk_dptx_phy_o_ref_clk_24m_user_p,
 250                         MUX_SEL_DISP1, 4, 1),
 251         MUX(DISP_MOUT_PHYCLK_MIPI_DPHY_4L_M_TXBYTE_CLKHS,
 252                         "mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs",
 253                         mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p,
 254                         MUX_SEL_DISP1, 8, 1),
 255         MUX(DISP_MOUT_PHYCLK_HDMI_LINK_O_TMDS_CLKHI_USER,
 256                         "mout_phyclk_hdmi_link_o_tmds_clkhi_user",
 257                         mout_phyclk_hdmi_link_o_tmds_clkhi_user_p,
 258                         MUX_SEL_DISP1, 16, 1),
 259         MUX(DISP_MOUT_HDMI_PHY_PIXEL,
 260                         "mout_phyclk_hdmi_phy_pixel_clko_user",
 261                         mout_phyclk_hdmi_phy_pixel_clko_user_p,
 262                         MUX_SEL_DISP1, 20, 1),
 263         MUX(DISP_MOUT_PHYCLK_HDMI_PHY_REF_CLKO_USER,
 264                         "mout_phyclk_hdmi_phy_ref_clko_user",
 265                         mout_phyclk_hdmi_phy_ref_clko_user_p,
 266                         MUX_SEL_DISP1, 24, 1),
 267         MUX(DISP_MOUT_PHYCLK_HDMI_PHY_TMDS_CLKO_USER,
 268                         "mout_phyclk_hdmi_phy_tmds_clko_user",
 269                         mout_phyclk_hdmi_phy_tmds_clko_user_p,
 270                         MUX_SEL_DISP1, 28, 1),
 271
 272         MUX(DISP_MOUT_PHYCLK_MIPI_DPHY_4LMRXCLK_ESC0_USER,
 273                         "mout_phyclk_mipi_dphy_4lmrxclk_esc0_user",
 274                         mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p,
 275                         MUX_SEL_DISP2, 0, 1),
 276         MUX(DISP_MOUT_SCLK_HDMI_PIXEL, "mout_sclk_hdmi_pixel",
 277                         mout_sclk_hdmi_pixel_p,
 278                         MUX_SEL_DISP2, 4, 1),
 279
 280         MUX(DISP_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif",
 281                         mout_sclk_hdmi_spdif_p,
 282                         MUX_SEL_DISP4, 4, 2),
 283 };
 284
 285 static const struct samsung_div_clock disp_div_clks[] __initconst = {
 286         DIV(DISP_DOUT_PCLK_DISP_111, "dout_pclk_disp_111",
 287                         "mout_aclk_disp_222_user",
 288                         DIV_DISP, 8, 4),
 289         DIV(DISP_DOUT_SCLK_FIMD1_EXTCLKPLL, "dout_sclk_fimd1_extclkpll",
 290                         "mout_sclk_disp_pixel_user",
 291                         DIV_DISP, 12, 4),
 292         DIV(DISP_DOUT_SCLK_HDMI_PHY_PIXEL_CLKI,
 293                         "dout_sclk_hdmi_phy_pixel_clki",
 294                         "mout_sclk_hdmi_pixel",
 295                         DIV_DISP, 16, 4),
 296 };
 297
 298 static const struct samsung_gate_clock disp_gate_clks[] __initconst = {
 299         GATE(DISP_MOUT_HDMI_PHY_PIXEL_USER, "sclk_hdmi_link_i_pixel",
 300                         "mout_phyclk_hdmi_phy_pixel_clko_user",
 301                         EN_SCLK_DISP0, 26, CLK_SET_RATE_PARENT, 0),
 302         GATE(DISP_SCLK_PIXEL, "sclk_hdmi_phy_pixel_clki",
 303                         "dout_sclk_hdmi_phy_pixel_clki",
 304                         EN_SCLK_DISP0, 29, CLK_SET_RATE_PARENT, 0),
 305
 306         GATE(DISP_CLK_DP, "clk_dptx_link", "mout_aclk_disp_222_user",
 307                         EN_IP_DISP, 4, 0, 0),
 308         GATE(DISP_CLK_DPPHY, "clk_dptx_phy", "mout_aclk_disp_222_user",
 309                         EN_IP_DISP, 5, 0, 0),
 310         GATE(DISP_CLK_DSIM1, "clk_dsim1", "mout_aclk_disp_222_user",
 311                         EN_IP_DISP, 6, 0, 0),
 312         GATE(DISP_CLK_FIMD1, "clk_fimd1", "mout_aclk_disp_222_user",
 313                         EN_IP_DISP, 7, 0, 0),
 314         GATE(DISP_CLK_HDMI, "clk_hdmi", "mout_aclk_disp_222_user",
 315                         EN_IP_DISP, 8, 0, 0),
 316         GATE(DISP_CLK_HDMIPHY, "clk_hdmiphy", "mout_aclk_disp_222_user",
 317                         EN_IP_DISP, 9, 0, 0),
 318         GATE(DISP_CLK_MIPIPHY, "clk_mipi_dphy", "mout_aclk_disp_222_user",
 319                         EN_IP_DISP, 10, 0, 0),
 320         GATE(DISP_CLK_MIXER, "clk_mixer", "mout_aclk_disp_222_user",
 321                         EN_IP_DISP, 11, 0, 0),
 322         GATE(DISP_CLK_PIXEL_DISP, "clk_pixel_disp", "mout_aclk_disp_222_user",
 323                         EN_IP_DISP, 12, CLK_IGNORE_UNUSED, 0),
 324         GATE(DISP_CLK_PIXEL_MIXER, "clk_pixel_mixer", "mout_aclk_disp_222_user",
 325                         EN_IP_DISP, 13, CLK_IGNORE_UNUSED, 0),
 326         GATE(DISP_CLK_SMMU_FIMD1M0, "clk_smmu3_fimd1m0",
 327                         "mout_aclk_disp_222_user",
 328                         EN_IP_DISP, 22, 0, 0),
 329         GATE(DISP_CLK_SMMU_FIMD1M1, "clk_smmu3_fimd1m1",
 330                         "mout_aclk_disp_222_user",
 331                         EN_IP_DISP, 23, 0, 0),
 332         GATE(DISP_CLK_SMMU_TV, "clk_smmu3_tv", "mout_aclk_disp_222_user",
 333                         EN_IP_DISP, 25, 0, 0),
 334 };
 335
 336 static const struct samsung_cmu_info disp_cmu __initconst = {
 337         .mux_clks       = disp_mux_clks,
 338         .nr_mux_clks    = ARRAY_SIZE(disp_mux_clks),
 339         .div_clks       = disp_div_clks,
 340         .nr_div_clks    = ARRAY_SIZE(disp_div_clks),
 341         .gate_clks      = disp_gate_clks,
 342         .nr_gate_clks   = ARRAY_SIZE(disp_gate_clks),
 343         .nr_clk_ids     = CLKS_NR_DISP,
 344         .clk_regs       = disp_clk_regs,
 345         .nr_clk_regs    = ARRAY_SIZE(disp_clk_regs),
 346 };
 347
 348 static void __init exynos5260_clk_disp_init(struct device_node *np)
 349 {
 350         samsung_cmu_register_one(np, &disp_cmu);
 351 }
 352
 353 CLK_OF_DECLARE(exynos5260_clk_disp, "samsung,exynos5260-clock-disp",
 354                 exynos5260_clk_disp_init);
 355
 356
 357 /* CMU_EGL */
 358
 359 static const unsigned long egl_clk_regs[] __initconst = {
 360         EGL_PLL_LOCK,
 361         EGL_PLL_CON0,
 362         EGL_PLL_CON1,
 363         EGL_PLL_FREQ_DET,
 364         MUX_SEL_EGL,
 365         MUX_ENABLE_EGL,
 366         DIV_EGL,
 367         DIV_EGL_PLL_FDET,
 368         EN_ACLK_EGL,
 369         EN_PCLK_EGL,
 370         EN_SCLK_EGL,
 371 };
 372
 373 PNAME(mout_egl_b_p) = {"mout_egl_pll", "dout_bus_pll"};
 374 PNAME(mout_egl_pll_p) = {"fin_pll", "fout_egl_pll"};
 375
 376 static const struct samsung_mux_clock egl_mux_clks[] __initconst = {
 377         MUX(EGL_MOUT_EGL_PLL, "mout_egl_pll", mout_egl_pll_p,
 378                         MUX_SEL_EGL, 4, 1),
 379         MUX(EGL_MOUT_EGL_B, "mout_egl_b", mout_egl_b_p, MUX_SEL_EGL, 16, 1),
 380 };
 381
 382 static const struct samsung_div_clock egl_div_clks[] __initconst = {
 383         DIV(EGL_DOUT_EGL1, "dout_egl1", "mout_egl_b", DIV_EGL, 0, 3),
 384         DIV(EGL_DOUT_EGL2, "dout_egl2", "dout_egl1", DIV_EGL, 4, 3),
 385         DIV(EGL_DOUT_ACLK_EGL, "dout_aclk_egl", "dout_egl2", DIV_EGL, 8, 3),
 386         DIV(EGL_DOUT_PCLK_EGL, "dout_pclk_egl", "dout_egl_atclk",
 387                         DIV_EGL, 12, 3),
 388         DIV(EGL_DOUT_EGL_ATCLK, "dout_egl_atclk", "dout_egl2", DIV_EGL, 16, 3),
 389         DIV(EGL_DOUT_EGL_PCLK_DBG, "dout_egl_pclk_dbg", "dout_egl_atclk",
 390                         DIV_EGL, 20, 3),
 391         DIV(EGL_DOUT_EGL_PLL, "dout_egl_pll", "mout_egl_b", DIV_EGL, 24, 3),
 392 };
 393
 394 static const struct samsung_pll_clock egl_pll_clks[] __initconst = {
 395         PLL(pll_2550xx, EGL_FOUT_EGL_PLL, "fout_egl_pll", "fin_pll",
 396                 EGL_PLL_LOCK, EGL_PLL_CON0,
 397                 pll2550_24mhz_tbl),
 398 };
 399
 400 static const struct samsung_cmu_info egl_cmu __initconst = {
 401         .pll_clks       = egl_pll_clks,
 402         .nr_pll_clks    = ARRAY_SIZE(egl_pll_clks),
 403         .mux_clks       = egl_mux_clks,
 404         .nr_mux_clks    = ARRAY_SIZE(egl_mux_clks),
 405         .div_clks       = egl_div_clks,
 406         .nr_div_clks    = ARRAY_SIZE(egl_div_clks),
 407         .nr_clk_ids     = CLKS_NR_EGL,
 408         .clk_regs       = egl_clk_regs,
 409         .nr_clk_regs    = ARRAY_SIZE(egl_clk_regs),
 410 };
 411
 412 static void __init exynos5260_clk_egl_init(struct device_node *np)
 413 {
 414         samsung_cmu_register_one(np, &egl_cmu);
 415 }
 416
 417 CLK_OF_DECLARE(exynos5260_clk_egl, "samsung,exynos5260-clock-egl",
 418                 exynos5260_clk_egl_init);
 419
 420
 421 /* CMU_FSYS */
 422
 423 static const unsigned long fsys_clk_regs[] __initconst = {
 424         MUX_SEL_FSYS0,
 425         MUX_SEL_FSYS1,
 426         EN_ACLK_FSYS,
 427         EN_ACLK_FSYS_SECURE_RTIC,
 428         EN_ACLK_FSYS_SECURE_SMMU_RTIC,
 429         EN_SCLK_FSYS,
 430         EN_IP_FSYS,
 431         EN_IP_FSYS_SECURE_RTIC,
 432         EN_IP_FSYS_SECURE_SMMU_RTIC,
 433 };
 434
 435 PNAME(mout_phyclk_usbhost20_phyclk_user_p) = {"fin_pll",
 436                         "phyclk_usbhost20_phy_phyclock"};
 437 PNAME(mout_phyclk_usbhost20_freeclk_user_p) = {"fin_pll",
 438                         "phyclk_usbhost20_phy_freeclk"};
 439 PNAME(mout_phyclk_usbhost20_clk48mohci_user_p) = {"fin_pll",
 440                         "phyclk_usbhost20_phy_clk48mohci"};
 441 PNAME(mout_phyclk_usbdrd30_pipe_pclk_user_p) = {"fin_pll",
 442                         "phyclk_usbdrd30_udrd30_pipe_pclk"};
 443 PNAME(mout_phyclk_usbdrd30_phyclock_user_p) = {"fin_pll",
 444                         "phyclk_usbdrd30_udrd30_phyclock"};
 445
 446 static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
 447         MUX(FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER,
 448                         "mout_phyclk_usbdrd30_phyclock_user",
 449                         mout_phyclk_usbdrd30_phyclock_user_p,
 450                         MUX_SEL_FSYS1, 0, 1),
 451         MUX(FSYS_MOUT_PHYCLK_USBDRD30_PIPE_PCLK_USER,
 452                         "mout_phyclk_usbdrd30_pipe_pclk_user",
 453                         mout_phyclk_usbdrd30_pipe_pclk_user_p,
 454                         MUX_SEL_FSYS1, 4, 1),
 455         MUX(FSYS_MOUT_PHYCLK_USBHOST20_CLK48MOHCI_USER,
 456                         "mout_phyclk_usbhost20_clk48mohci_user",
 457                         mout_phyclk_usbhost20_clk48mohci_user_p,
 458                         MUX_SEL_FSYS1, 8, 1),
 459         MUX(FSYS_MOUT_PHYCLK_USBHOST20_FREECLK_USER,
 460                         "mout_phyclk_usbhost20_freeclk_user",
 461                         mout_phyclk_usbhost20_freeclk_user_p,
 462                         MUX_SEL_FSYS1, 12, 1),
 463         MUX(FSYS_MOUT_PHYCLK_USBHOST20_PHYCLK_USER,
 464                         "mout_phyclk_usbhost20_phyclk_user",
 465                         mout_phyclk_usbhost20_phyclk_user_p,
 466                         MUX_SEL_FSYS1, 16, 1),
 467 };
 468
 469 static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
 470         GATE(FSYS_PHYCLK_USBHOST20, "phyclk_usbhost20_phyclock",
 471                         "mout_phyclk_usbdrd30_phyclock_user",
 472                         EN_SCLK_FSYS, 1, 0, 0),
 473         GATE(FSYS_PHYCLK_USBDRD30, "phyclk_usbdrd30_udrd30_phyclock_g",
 474                         "mout_phyclk_usbdrd30_phyclock_user",
 475                         EN_SCLK_FSYS, 7, 0, 0),
 476
 477         GATE(FSYS_CLK_MMC0, "clk_mmc0", "dout_aclk_fsys_200",
 478                         EN_IP_FSYS, 6, 0, 0),
 479         GATE(FSYS_CLK_MMC1, "clk_mmc1", "dout_aclk_fsys_200",
 480                         EN_IP_FSYS, 7, 0, 0),
 481         GATE(FSYS_CLK_MMC2, "clk_mmc2", "dout_aclk_fsys_200",
 482                         EN_IP_FSYS, 8, 0, 0),
 483         GATE(FSYS_CLK_PDMA, "clk_pdma", "dout_aclk_fsys_200",
 484                         EN_IP_FSYS, 9, 0, 0),
 485         GATE(FSYS_CLK_SROMC, "clk_sromc", "dout_aclk_fsys_200",
 486                         EN_IP_FSYS, 13, 0, 0),
 487         GATE(FSYS_CLK_USBDRD30, "clk_usbdrd30", "dout_aclk_fsys_200",
 488                         EN_IP_FSYS, 14, 0, 0),
 489         GATE(FSYS_CLK_USBHOST20, "clk_usbhost20", "dout_aclk_fsys_200",
 490                         EN_IP_FSYS, 15, 0, 0),
 491         GATE(FSYS_CLK_USBLINK, "clk_usblink", "dout_aclk_fsys_200",
 492                         EN_IP_FSYS, 18, 0, 0),
 493         GATE(FSYS_CLK_TSI, "clk_tsi", "dout_aclk_fsys_200",
 494                         EN_IP_FSYS, 20, 0, 0),
 495
 496         GATE(FSYS_CLK_RTIC, "clk_rtic", "dout_aclk_fsys_200",
 497                         EN_IP_FSYS_SECURE_RTIC, 11, 0, 0),
 498         GATE(FSYS_CLK_SMMU_RTIC, "clk_smmu_rtic", "dout_aclk_fsys_200",
 499                         EN_IP_FSYS_SECURE_SMMU_RTIC, 12, 0, 0),
 500 };
 501
 502 static const struct samsung_cmu_info fsys_cmu __initconst = {
 503         .mux_clks       = fsys_mux_clks,
 504         .nr_mux_clks    = ARRAY_SIZE(fsys_mux_clks),
 505         .gate_clks      = fsys_gate_clks,
 506         .nr_gate_clks   = ARRAY_SIZE(fsys_gate_clks),
 507         .nr_clk_ids     = CLKS_NR_FSYS,
 508         .clk_regs       = fsys_clk_regs,
 509         .nr_clk_regs    = ARRAY_SIZE(fsys_clk_regs),
 510 };
 511
 512 static void __init exynos5260_clk_fsys_init(struct device_node *np)
 513 {
 514         samsung_cmu_register_one(np, &fsys_cmu);
 515 }
 516
 517 CLK_OF_DECLARE(exynos5260_clk_fsys, "samsung,exynos5260-clock-fsys",
 518                 exynos5260_clk_fsys_init);
 519
 520
 521 /* CMU_G2D */
 522
 523 static const unsigned long g2d_clk_regs[] __initconst = {
 524         MUX_SEL_G2D,
 525         MUX_STAT_G2D,
 526         DIV_G2D,
 527         EN_ACLK_G2D,
 528         EN_ACLK_G2D_SECURE_SSS,
 529         EN_ACLK_G2D_SECURE_SLIM_SSS,
 530         EN_ACLK_G2D_SECURE_SMMU_SLIM_SSS,
 531         EN_ACLK_G2D_SECURE_SMMU_SSS,
 532         EN_ACLK_G2D_SECURE_SMMU_MDMA,
 533         EN_ACLK_G2D_SECURE_SMMU_G2D,
 534         EN_PCLK_G2D,
 535         EN_PCLK_G2D_SECURE_SMMU_SLIM_SSS,
 536         EN_PCLK_G2D_SECURE_SMMU_SSS,
 537         EN_PCLK_G2D_SECURE_SMMU_MDMA,
 538         EN_PCLK_G2D_SECURE_SMMU_G2D,
 539         EN_IP_G2D,
 540         EN_IP_G2D_SECURE_SSS,
 541         EN_IP_G2D_SECURE_SLIM_SSS,
 542         EN_IP_G2D_SECURE_SMMU_SLIM_SSS,
 543         EN_IP_G2D_SECURE_SMMU_SSS,
 544         EN_IP_G2D_SECURE_SMMU_MDMA,
 545         EN_IP_G2D_SECURE_SMMU_G2D,
 546 };
 547
 548 PNAME(mout_aclk_g2d_333_user_p) = {"fin_pll", "dout_aclk_g2d_333"};
 549
 550 static const struct samsung_mux_clock g2d_mux_clks[] __initconst = {
 551         MUX(G2D_MOUT_ACLK_G2D_333_USER, "mout_aclk_g2d_333_user",
 552                         mout_aclk_g2d_333_user_p,
 553                         MUX_SEL_G2D, 0, 1),
 554 };
 555
 556 static const struct samsung_div_clock g2d_div_clks[] __initconst = {
 557         DIV(G2D_DOUT_PCLK_G2D_83, "dout_pclk_g2d_83", "mout_aclk_g2d_333_user",
 558                         DIV_G2D, 0, 3),
 559 };
 560
 561 static const struct samsung_gate_clock g2d_gate_clks[] __initconst = {
 562         GATE(G2D_CLK_G2D, "clk_g2d", "mout_aclk_g2d_333_user",
 563                         EN_IP_G2D, 4, 0, 0),
 564         GATE(G2D_CLK_JPEG, "clk_jpeg", "mout_aclk_g2d_333_user",
 565                         EN_IP_G2D, 5, 0, 0),
 566         GATE(G2D_CLK_MDMA, "clk_mdma", "mout_aclk_g2d_333_user",
 567                         EN_IP_G2D, 6, 0, 0),
 568         GATE(G2D_CLK_SMMU3_JPEG, "clk_smmu3_jpeg", "mout_aclk_g2d_333_user",
 569                         EN_IP_G2D, 16, 0, 0),
 570
 571         GATE(G2D_CLK_SSS, "clk_sss", "mout_aclk_g2d_333_user",
 572                         EN_IP_G2D_SECURE_SSS, 17, 0, 0),
 573
 574         GATE(G2D_CLK_SLIM_SSS, "clk_slim_sss", "mout_aclk_g2d_333_user",
 575                         EN_IP_G2D_SECURE_SLIM_SSS, 11, 0, 0),
 576
 577         GATE(G2D_CLK_SMMU_SLIM_SSS, "clk_smmu_slim_sss",
 578                         "mout_aclk_g2d_333_user",
 579                         EN_IP_G2D_SECURE_SMMU_SLIM_SSS, 13, 0, 0),
 580
 581         GATE(G2D_CLK_SMMU_SSS, "clk_smmu_sss", "mout_aclk_g2d_333_user",
 582                         EN_IP_G2D_SECURE_SMMU_SSS, 14, 0, 0),
 583
 584         GATE(G2D_CLK_SMMU_MDMA, "clk_smmu_mdma", "mout_aclk_g2d_333_user",
 585                         EN_IP_G2D_SECURE_SMMU_MDMA, 12, 0, 0),
 586
 587         GATE(G2D_CLK_SMMU3_G2D, "clk_smmu3_g2d", "mout_aclk_g2d_333_user",
 588                         EN_IP_G2D_SECURE_SMMU_G2D, 15, 0, 0),
 589 };
 590
 591 static const struct samsung_cmu_info g2d_cmu __initconst = {
 592         .mux_clks       = g2d_mux_clks,
 593         .nr_mux_clks    = ARRAY_SIZE(g2d_mux_clks),
 594         .div_clks       = g2d_div_clks,
 595         .nr_div_clks    = ARRAY_SIZE(g2d_div_clks),
 596         .gate_clks      = g2d_gate_clks,
 597         .nr_gate_clks   = ARRAY_SIZE(g2d_gate_clks),
 598         .nr_clk_ids     = CLKS_NR_G2D,
 599         .clk_regs       = g2d_clk_regs,
 600         .nr_clk_regs    = ARRAY_SIZE(g2d_clk_regs),
 601 };
 602
 603 static void __init exynos5260_clk_g2d_init(struct device_node *np)
 604 {
 605         samsung_cmu_register_one(np, &g2d_cmu);
 606 }
 607
 608 CLK_OF_DECLARE(exynos5260_clk_g2d, "samsung,exynos5260-clock-g2d",
 609                 exynos5260_clk_g2d_init);
 610
 611
 612 /* CMU_G3D */
 613
 614 static const unsigned long g3d_clk_regs[] __initconst = {
 615         G3D_PLL_LOCK,
 616         G3D_PLL_CON0,
 617         G3D_PLL_CON1,
 618         G3D_PLL_FDET,
 619         MUX_SEL_G3D,
 620         DIV_G3D,
 621         DIV_G3D_PLL_FDET,
 622         EN_ACLK_G3D,
 623         EN_PCLK_G3D,
 624         EN_SCLK_G3D,
 625         EN_IP_G3D,
 626 };
 627
 628 PNAME(mout_g3d_pll_p) = {"fin_pll", "fout_g3d_pll"};
 629
 630 static const struct samsung_mux_clock g3d_mux_clks[] __initconst = {
 631         MUX(G3D_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
 632                         MUX_SEL_G3D, 0, 1),
 633 };
 634
 635 static const struct samsung_div_clock g3d_div_clks[] __initconst = {
 636         DIV(G3D_DOUT_PCLK_G3D, "dout_pclk_g3d", "dout_aclk_g3d", DIV_G3D, 0, 3),
 637         DIV(G3D_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_g3d_pll", DIV_G3D, 4, 3),
 638 };
 639
 640 static const struct samsung_gate_clock g3d_gate_clks[] __initconst = {
 641         GATE(G3D_CLK_G3D, "clk_g3d", "dout_aclk_g3d", EN_IP_G3D, 2, 0, 0),
 642         GATE(G3D_CLK_G3D_HPM, "clk_g3d_hpm", "dout_aclk_g3d",
 643                         EN_IP_G3D, 3, 0, 0),
 644 };
 645
 646 static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {
 647         PLL(pll_2550, G3D_FOUT_G3D_PLL, "fout_g3d_pll", "fin_pll",
 648                 G3D_PLL_LOCK, G3D_PLL_CON0,
 649                 pll2550_24mhz_tbl),
 650 };
 651
 652 static const struct samsung_cmu_info g3d_cmu __initconst = {
 653         .pll_clks       = g3d_pll_clks,
 654         .nr_pll_clks    = ARRAY_SIZE(g3d_pll_clks),
 655         .mux_clks       = g3d_mux_clks,
 656         .nr_mux_clks    = ARRAY_SIZE(g3d_mux_clks),
 657         .div_clks       = g3d_div_clks,
 658         .nr_div_clks    = ARRAY_SIZE(g3d_div_clks),
 659         .gate_clks      = g3d_gate_clks,
 660         .nr_gate_clks   = ARRAY_SIZE(g3d_gate_clks),
 661         .nr_clk_ids     = CLKS_NR_G3D,
 662         .clk_regs       = g3d_clk_regs,
 663         .nr_clk_regs    = ARRAY_SIZE(g3d_clk_regs),
 664 };
 665
 666 static void __init exynos5260_clk_g3d_init(struct device_node *np)
 667 {
 668         samsung_cmu_register_one(np, &g3d_cmu);
 669 }
 670
 671 CLK_OF_DECLARE(exynos5260_clk_g3d, "samsung,exynos5260-clock-g3d",
 672                 exynos5260_clk_g3d_init);
 673
 674
 675 /* CMU_GSCL */
 676
 677 static const unsigned long gscl_clk_regs[] __initconst = {
 678         MUX_SEL_GSCL,
 679         DIV_GSCL,
 680         EN_ACLK_GSCL,
 681         EN_ACLK_GSCL_FIMC,
 682         EN_ACLK_GSCL_SECURE_SMMU_GSCL0,
 683         EN_ACLK_GSCL_SECURE_SMMU_GSCL1,
 684         EN_ACLK_GSCL_SECURE_SMMU_MSCL0,
 685         EN_ACLK_GSCL_SECURE_SMMU_MSCL1,
 686         EN_PCLK_GSCL,
 687         EN_PCLK_GSCL_FIMC,
 688         EN_PCLK_GSCL_SECURE_SMMU_GSCL0,
 689         EN_PCLK_GSCL_SECURE_SMMU_GSCL1,
 690         EN_PCLK_GSCL_SECURE_SMMU_MSCL0,
 691         EN_PCLK_GSCL_SECURE_SMMU_MSCL1,
 692         EN_SCLK_GSCL,
 693         EN_SCLK_GSCL_FIMC,
 694         EN_IP_GSCL,
 695         EN_IP_GSCL_FIMC,
 696         EN_IP_GSCL_SECURE_SMMU_GSCL0,
 697         EN_IP_GSCL_SECURE_SMMU_GSCL1,
 698         EN_IP_GSCL_SECURE_SMMU_MSCL0,
 699         EN_IP_GSCL_SECURE_SMMU_MSCL1,
 700 };
 701
 702 PNAME(mout_aclk_gscl_333_user_p) = {"fin_pll", "dout_aclk_gscl_333"};
 703 PNAME(mout_aclk_m2m_400_user_p) = {"fin_pll", "dout_aclk_gscl_400"};
 704 PNAME(mout_aclk_gscl_fimc_user_p) = {"fin_pll", "dout_aclk_gscl_400"};
 705 PNAME(mout_aclk_csis_p) = {"dout_aclk_csis_200", "mout_aclk_gscl_fimc_user"};
 706
 707 static const struct samsung_mux_clock gscl_mux_clks[] __initconst = {
 708         MUX(GSCL_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user",
 709                         mout_aclk_gscl_333_user_p,
 710                         MUX_SEL_GSCL, 0, 1),
 711         MUX(GSCL_MOUT_ACLK_M2M_400_USER, "mout_aclk_m2m_400_user",
 712                         mout_aclk_m2m_400_user_p,
 713                         MUX_SEL_GSCL, 4, 1),
 714         MUX(GSCL_MOUT_ACLK_GSCL_FIMC_USER, "mout_aclk_gscl_fimc_user",
 715                         mout_aclk_gscl_fimc_user_p,
 716                         MUX_SEL_GSCL, 8, 1),
 717         MUX(GSCL_MOUT_ACLK_CSIS, "mout_aclk_csis", mout_aclk_csis_p,
 718                         MUX_SEL_GSCL, 24, 1),
 719 };
 720
 721 static const struct samsung_div_clock gscl_div_clks[] __initconst = {
 722         DIV(GSCL_DOUT_PCLK_M2M_100, "dout_pclk_m2m_100",
 723                         "mout_aclk_m2m_400_user",
 724                         DIV_GSCL, 0, 3),
 725         DIV(GSCL_DOUT_ACLK_CSIS_200, "dout_aclk_csis_200",
 726                         "mout_aclk_m2m_400_user",
 727                         DIV_GSCL, 4, 3),
 728 };
 729
 730 static const struct samsung_gate_clock gscl_gate_clks[] __initconst = {
 731         GATE(GSCL_SCLK_CSIS0_WRAP, "sclk_csis0_wrap", "dout_aclk_csis_200",
 732                         EN_SCLK_GSCL_FIMC, 0, CLK_SET_RATE_PARENT, 0),
 733         GATE(GSCL_SCLK_CSIS1_WRAP, "sclk_csis1_wrap", "dout_aclk_csis_200",
 734                         EN_SCLK_GSCL_FIMC, 1, CLK_SET_RATE_PARENT, 0),
 735
 736         GATE(GSCL_CLK_GSCL0, "clk_gscl0", "mout_aclk_gscl_333_user",
 737                         EN_IP_GSCL, 2, 0, 0),
 738         GATE(GSCL_CLK_GSCL1, "clk_gscl1", "mout_aclk_gscl_333_user",
 739                         EN_IP_GSCL, 3, 0, 0),
 740         GATE(GSCL_CLK_MSCL0, "clk_mscl0", "mout_aclk_gscl_333_user",
 741                         EN_IP_GSCL, 4, 0, 0),
 742         GATE(GSCL_CLK_MSCL1, "clk_mscl1", "mout_aclk_gscl_333_user",
 743                         EN_IP_GSCL, 5, 0, 0),
 744         GATE(GSCL_CLK_PIXEL_GSCL0, "clk_pixel_gscl0",
 745                         "mout_aclk_gscl_333_user",
 746                         EN_IP_GSCL, 8, 0, 0),
 747         GATE(GSCL_CLK_PIXEL_GSCL1, "clk_pixel_gscl1",
 748                         "mout_aclk_gscl_333_user",
 749                         EN_IP_GSCL, 9, 0, 0),
 750
 751         GATE(GSCL_CLK_SMMU3_LITE_A, "clk_smmu3_lite_a",
 752                         "mout_aclk_gscl_fimc_user",
 753                         EN_IP_GSCL_FIMC, 5, 0, 0),
 754         GATE(GSCL_CLK_SMMU3_LITE_B, "clk_smmu3_lite_b",
 755                         "mout_aclk_gscl_fimc_user",
 756                         EN_IP_GSCL_FIMC, 6, 0, 0),
 757         GATE(GSCL_CLK_SMMU3_LITE_D, "clk_smmu3_lite_d",
 758                         "mout_aclk_gscl_fimc_user",
 759                         EN_IP_GSCL_FIMC, 7, 0, 0),
 760         GATE(GSCL_CLK_CSIS0, "clk_csis0", "mout_aclk_gscl_fimc_user",
 761                         EN_IP_GSCL_FIMC, 8, 0, 0),
 762         GATE(GSCL_CLK_CSIS1, "clk_csis1", "mout_aclk_gscl_fimc_user",
 763                         EN_IP_GSCL_FIMC, 9, 0, 0),
 764         GATE(GSCL_CLK_FIMC_LITE_A, "clk_fimc_lite_a",
 765                         "mout_aclk_gscl_fimc_user",
 766                         EN_IP_GSCL_FIMC, 10, 0, 0),
 767         GATE(GSCL_CLK_FIMC_LITE_B, "clk_fimc_lite_b",
 768                         "mout_aclk_gscl_fimc_user",
 769                         EN_IP_GSCL_FIMC, 11, 0, 0),
 770         GATE(GSCL_CLK_FIMC_LITE_D, "clk_fimc_lite_d",
 771                         "mout_aclk_gscl_fimc_user",
 772                         EN_IP_GSCL_FIMC, 12, 0, 0),
 773
 774         GATE(GSCL_CLK_SMMU3_GSCL0, "clk_smmu3_gscl0",
 775                         "mout_aclk_gscl_333_user",
 776                         EN_IP_GSCL_SECURE_SMMU_GSCL0, 17, 0, 0),
 777         GATE(GSCL_CLK_SMMU3_GSCL1, "clk_smmu3_gscl1", "mout_aclk_gscl_333_user",
 778                         EN_IP_GSCL_SECURE_SMMU_GSCL1, 18, 0, 0),
 779         GATE(GSCL_CLK_SMMU3_MSCL0, "clk_smmu3_mscl0",
 780                         "mout_aclk_m2m_400_user",
 781                         EN_IP_GSCL_SECURE_SMMU_MSCL0, 19, 0, 0),
 782         GATE(GSCL_CLK_SMMU3_MSCL1, "clk_smmu3_mscl1",
 783                         "mout_aclk_m2m_400_user",
 784                         EN_IP_GSCL_SECURE_SMMU_MSCL1, 20, 0, 0),
 785 };
 786
 787 static const struct samsung_cmu_info gscl_cmu __initconst = {
 788         .mux_clks       = gscl_mux_clks,
 789         .nr_mux_clks    = ARRAY_SIZE(gscl_mux_clks),
 790         .div_clks       = gscl_div_clks,
 791         .nr_div_clks    = ARRAY_SIZE(gscl_div_clks),
 792         .gate_clks      = gscl_gate_clks,
 793         .nr_gate_clks   = ARRAY_SIZE(gscl_gate_clks),
 794         .nr_clk_ids     = CLKS_NR_GSCL,
 795         .clk_regs       = gscl_clk_regs,
 796         .nr_clk_regs    = ARRAY_SIZE(gscl_clk_regs),
 797 };
 798
 799 static void __init exynos5260_clk_gscl_init(struct device_node *np)
 800 {
 801         samsung_cmu_register_one(np, &gscl_cmu);
 802 }
 803
 804 CLK_OF_DECLARE(exynos5260_clk_gscl, "samsung,exynos5260-clock-gscl",
 805                 exynos5260_clk_gscl_init);
 806
 807
 808 /* CMU_ISP */
 809
 810 static const unsigned long isp_clk_regs[] __initconst = {
 811         MUX_SEL_ISP0,
 812         MUX_SEL_ISP1,
 813         DIV_ISP,
 814         EN_ACLK_ISP0,
 815         EN_ACLK_ISP1,
 816         EN_PCLK_ISP0,
 817         EN_PCLK_ISP1,
 818         EN_SCLK_ISP,
 819         EN_IP_ISP0,
 820         EN_IP_ISP1,
 821 };
 822
 823 PNAME(mout_isp_400_user_p) = {"fin_pll", "dout_aclk_isp1_400"};
 824 PNAME(mout_isp_266_user_p)       = {"fin_pll", "dout_aclk_isp1_266"};
 825
 826 static const struct samsung_mux_clock isp_mux_clks[] __initconst = {
 827         MUX(ISP_MOUT_ISP_266_USER, "mout_isp_266_user", mout_isp_266_user_p,
 828                         MUX_SEL_ISP0, 0, 1),
 829         MUX(ISP_MOUT_ISP_400_USER, "mout_isp_400_user", mout_isp_400_user_p,
 830                         MUX_SEL_ISP0, 4, 1),
 831 };
 832
 833 static const struct samsung_div_clock isp_div_clks[] __initconst = {
 834         DIV(ISP_DOUT_PCLK_ISP_66, "dout_pclk_isp_66", "mout_kfc",
 835                         DIV_ISP, 0, 3),
 836         DIV(ISP_DOUT_PCLK_ISP_133, "dout_pclk_isp_133", "mout_kfc",
 837                         DIV_ISP, 4, 4),
 838         DIV(ISP_DOUT_CA5_ATCLKIN, "dout_ca5_atclkin", "mout_kfc",
 839                         DIV_ISP, 12, 3),
 840         DIV(ISP_DOUT_CA5_PCLKDBG, "dout_ca5_pclkdbg", "mout_kfc",
 841                         DIV_ISP, 16, 4),
 842         DIV(ISP_DOUT_SCLK_MPWM, "dout_sclk_mpwm", "mout_kfc", DIV_ISP, 20, 2),
 843 };
 844
 845 static const struct samsung_gate_clock isp_gate_clks[] __initconst = {
 846         GATE(ISP_CLK_GIC, "clk_isp_gic", "mout_aclk_isp1_266",
 847                         EN_IP_ISP0, 15, 0, 0),
 848
 849         GATE(ISP_CLK_CA5, "clk_isp_ca5", "mout_aclk_isp1_266",
 850                         EN_IP_ISP1, 1, 0, 0),
 851         GATE(ISP_CLK_FIMC_DRC, "clk_isp_fimc_drc", "mout_aclk_isp1_266",
 852                         EN_IP_ISP1, 2, 0, 0),
 853         GATE(ISP_CLK_FIMC_FD, "clk_isp_fimc_fd", "mout_aclk_isp1_266",
 854                         EN_IP_ISP1, 3, 0, 0),
 855         GATE(ISP_CLK_FIMC, "clk_isp_fimc", "mout_aclk_isp1_266",
 856                         EN_IP_ISP1, 4, 0, 0),
 857         GATE(ISP_CLK_FIMC_SCALERC, "clk_isp_fimc_scalerc",
 858                         "mout_aclk_isp1_266",
 859                         EN_IP_ISP1, 5, 0, 0),
 860         GATE(ISP_CLK_FIMC_SCALERP, "clk_isp_fimc_scalerp",
 861                         "mout_aclk_isp1_266",
 862                         EN_IP_ISP1, 6, 0, 0),
 863         GATE(ISP_CLK_I2C0, "clk_isp_i2c0", "mout_aclk_isp1_266",
 864                         EN_IP_ISP1, 7, 0, 0),
 865         GATE(ISP_CLK_I2C1, "clk_isp_i2c1", "mout_aclk_isp1_266",
 866                         EN_IP_ISP1, 8, 0, 0),
 867         GATE(ISP_CLK_MCUCTL, "clk_isp_mcuctl", "mout_aclk_isp1_266",
 868                         EN_IP_ISP1, 9, 0, 0),
 869         GATE(ISP_CLK_MPWM, "clk_isp_mpwm", "mout_aclk_isp1_266",
 870                         EN_IP_ISP1, 10, 0, 0),
 871         GATE(ISP_CLK_MTCADC, "clk_isp_mtcadc", "mout_aclk_isp1_266",
 872                         EN_IP_ISP1, 11, 0, 0),
 873         GATE(ISP_CLK_PWM, "clk_isp_pwm", "mout_aclk_isp1_266",
 874                         EN_IP_ISP1, 14, 0, 0),
 875         GATE(ISP_CLK_SMMU_DRC, "clk_smmu_drc", "mout_aclk_isp1_266",
 876                         EN_IP_ISP1, 21, 0, 0),
 877         GATE(ISP_CLK_SMMU_FD, "clk_smmu_fd", "mout_aclk_isp1_266",
 878                         EN_IP_ISP1, 22, 0, 0),
 879         GATE(ISP_CLK_SMMU_ISP, "clk_smmu_isp", "mout_aclk_isp1_266",
 880                         EN_IP_ISP1, 23, 0, 0),
 881         GATE(ISP_CLK_SMMU_ISPCX, "clk_smmu_ispcx", "mout_aclk_isp1_266",
 882                         EN_IP_ISP1, 24, 0, 0),
 883         GATE(ISP_CLK_SMMU_SCALERC, "clk_isp_smmu_scalerc",
 884                         "mout_aclk_isp1_266",
 885                         EN_IP_ISP1, 25, 0, 0),
 886         GATE(ISP_CLK_SMMU_SCALERP, "clk_isp_smmu_scalerp",
 887                         "mout_aclk_isp1_266",
 888                         EN_IP_ISP1, 26, 0, 0),
 889         GATE(ISP_CLK_SPI0, "clk_isp_spi0", "mout_aclk_isp1_266",
 890                         EN_IP_ISP1, 27, 0, 0),
 891         GATE(ISP_CLK_SPI1, "clk_isp_spi1", "mout_aclk_isp1_266",
 892                         EN_IP_ISP1, 28, 0, 0),
 893         GATE(ISP_CLK_WDT, "clk_isp_wdt", "mout_aclk_isp1_266",
 894                         EN_IP_ISP1, 31, 0, 0),
 895         GATE(ISP_CLK_UART, "clk_isp_uart", "mout_aclk_isp1_266",
 896                         EN_IP_ISP1, 30, 0, 0),
 897
 898         GATE(ISP_SCLK_UART_EXT, "sclk_isp_uart_ext", "fin_pll",
 899                         EN_SCLK_ISP, 7, CLK_SET_RATE_PARENT, 0),
 900         GATE(ISP_SCLK_SPI1_EXT, "sclk_isp_spi1_ext", "fin_pll",
 901                         EN_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
 902         GATE(ISP_SCLK_SPI0_EXT, "sclk_isp_spi0_ext", "fin_pll",
 903                         EN_SCLK_ISP, 9, CLK_SET_RATE_PARENT, 0),
 904 };
 905
 906 static const struct samsung_cmu_info isp_cmu __initconst = {
 907         .mux_clks       = isp_mux_clks,
 908         .nr_mux_clks    = ARRAY_SIZE(isp_mux_clks),
 909         .div_clks       = isp_div_clks,
 910         .nr_div_clks    = ARRAY_SIZE(isp_div_clks),
 911         .gate_clks      = isp_gate_clks,
 912         .nr_gate_clks   = ARRAY_SIZE(isp_gate_clks),
 913         .nr_clk_ids     = CLKS_NR_ISP,
 914         .clk_regs       = isp_clk_regs,
 915         .nr_clk_regs    = ARRAY_SIZE(isp_clk_regs),
 916 };
 917
 918 static void __init exynos5260_clk_isp_init(struct device_node *np)
 919 {
 920         samsung_cmu_register_one(np, &isp_cmu);
 921 }
 922
 923 CLK_OF_DECLARE(exynos5260_clk_isp, "samsung,exynos5260-clock-isp",
 924                 exynos5260_clk_isp_init);
 925
 926
 927 /* CMU_KFC */
 928
 929 static const unsigned long kfc_clk_regs[] __initconst = {
 930         KFC_PLL_LOCK,
 931         KFC_PLL_CON0,
 932         KFC_PLL_CON1,
 933         KFC_PLL_FDET,
 934         MUX_SEL_KFC0,
 935         MUX_SEL_KFC2,
 936         DIV_KFC,
 937         DIV_KFC_PLL_FDET,
 938         EN_ACLK_KFC,
 939         EN_PCLK_KFC,
 940         EN_SCLK_KFC,
 941         EN_IP_KFC,
 942 };
 943
 944 PNAME(mout_kfc_pll_p) = {"fin_pll", "fout_kfc_pll"};
 945 PNAME(mout_kfc_p)        = {"mout_kfc_pll", "dout_media_pll"};
 946
 947 static const struct samsung_mux_clock kfc_mux_clks[] __initconst = {
 948         MUX(KFC_MOUT_KFC_PLL, "mout_kfc_pll", mout_kfc_pll_p,
 949                         MUX_SEL_KFC0, 0, 1),
 950         MUX(KFC_MOUT_KFC, "mout_kfc", mout_kfc_p, MUX_SEL_KFC2, 0, 1),
 951 };
 952
 953 static const struct samsung_div_clock kfc_div_clks[] __initconst = {
 954         DIV(KFC_DOUT_KFC1, "dout_kfc1", "mout_kfc", DIV_KFC, 0, 3),
 955         DIV(KFC_DOUT_KFC2, "dout_kfc2", "dout_kfc1", DIV_KFC, 4, 3),
 956         DIV(KFC_DOUT_KFC_ATCLK, "dout_kfc_atclk", "dout_kfc2", DIV_KFC, 8, 3),
 957         DIV(KFC_DOUT_KFC_PCLK_DBG, "dout_kfc_pclk_dbg", "dout_kfc2",
 958                         DIV_KFC, 12, 3),
 959         DIV(KFC_DOUT_ACLK_KFC, "dout_aclk_kfc", "dout_kfc2", DIV_KFC, 16, 3),
 960         DIV(KFC_DOUT_PCLK_KFC, "dout_pclk_kfc", "dout_kfc2", DIV_KFC, 20, 3),
 961         DIV(KFC_DOUT_KFC_PLL, "dout_kfc_pll", "mout_kfc", DIV_KFC, 24, 3),
 962 };
 963
 964 static const struct samsung_pll_clock kfc_pll_clks[] __initconst = {
 965         PLL(pll_2550xx, KFC_FOUT_KFC_PLL, "fout_kfc_pll", "fin_pll",
 966                 KFC_PLL_LOCK, KFC_PLL_CON0,
 967                 pll2550_24mhz_tbl),
 968 };
 969
 970 static const struct samsung_cmu_info kfc_cmu __initconst = {
 971         .pll_clks       = kfc_pll_clks,
 972         .nr_pll_clks    = ARRAY_SIZE(kfc_pll_clks),
 973         .mux_clks       = kfc_mux_clks,
 974         .nr_mux_clks    = ARRAY_SIZE(kfc_mux_clks),
 975         .div_clks       = kfc_div_clks,
 976         .nr_div_clks    = ARRAY_SIZE(kfc_div_clks),
 977         .nr_clk_ids     = CLKS_NR_KFC,
 978         .clk_regs       = kfc_clk_regs,
 979         .nr_clk_regs    = ARRAY_SIZE(kfc_clk_regs),
 980 };
 981
 982 static void __init exynos5260_clk_kfc_init(struct device_node *np)
 983 {
 984         samsung_cmu_register_one(np, &kfc_cmu);
 985 }
 986
 987 CLK_OF_DECLARE(exynos5260_clk_kfc, "samsung,exynos5260-clock-kfc",
 988                 exynos5260_clk_kfc_init);
 989
 990
 991 /* CMU_MFC */
 992
 993 static const unsigned long mfc_clk_regs[] __initconst = {
 994         MUX_SEL_MFC,
 995         DIV_MFC,
 996         EN_ACLK_MFC,
 997         EN_ACLK_SECURE_SMMU2_MFC,
 998         EN_PCLK_MFC,
 999         EN_PCLK_SECURE_SMMU2_MFC,
1000         EN_IP_MFC,
1001         EN_IP_MFC_SECURE_SMMU2_MFC,
1002 };
1003
1004 PNAME(mout_aclk_mfc_333_user_p) = {"fin_pll", "dout_aclk_mfc_333"};
1005
1006 static const struct samsung_mux_clock mfc_mux_clks[] __initconst = {
1007         MUX(MFC_MOUT_ACLK_MFC_333_USER, "mout_aclk_mfc_333_user",
1008                         mout_aclk_mfc_333_user_p,
1009                         MUX_SEL_MFC, 0, 1),
1010 };
1011
1012 static const struct samsung_div_clock mfc_div_clks[] __initconst = {
1013         DIV(MFC_DOUT_PCLK_MFC_83, "dout_pclk_mfc_83", "mout_aclk_mfc_333_user",
1014                         DIV_MFC, 0, 3),
1015 };
1016
1017 static const struct samsung_gate_clock mfc_gate_clks[] __initconst = {
1018         GATE(MFC_CLK_MFC, "clk_mfc", "mout_aclk_mfc_333_user",
1019                         EN_IP_MFC, 1, 0, 0),
1020         GATE(MFC_CLK_SMMU2_MFCM0, "clk_smmu2_mfcm0", "mout_aclk_mfc_333_user",
1021                         EN_IP_MFC_SECURE_SMMU2_MFC, 6, 0, 0),
1022         GATE(MFC_CLK_SMMU2_MFCM1, "clk_smmu2_mfcm1", "mout_aclk_mfc_333_user",
1023                         EN_IP_MFC_SECURE_SMMU2_MFC, 7, 0, 0),
1024 };
1025
1026 static const struct samsung_cmu_info mfc_cmu __initconst = {
1027         .mux_clks       = mfc_mux_clks,
1028         .nr_mux_clks    = ARRAY_SIZE(mfc_mux_clks),
1029         .div_clks       = mfc_div_clks,
1030         .nr_div_clks    = ARRAY_SIZE(mfc_div_clks),
1031         .gate_clks      = mfc_gate_clks,
1032         .nr_gate_clks   = ARRAY_SIZE(mfc_gate_clks),
1033         .nr_clk_ids     = CLKS_NR_MFC,
1034         .clk_regs       = mfc_clk_regs,
1035         .nr_clk_regs    = ARRAY_SIZE(mfc_clk_regs),
1036 };
1037
1038 static void __init exynos5260_clk_mfc_init(struct device_node *np)
1039 {
1040         samsung_cmu_register_one(np, &mfc_cmu);
1041 }
1042
1043 CLK_OF_DECLARE(exynos5260_clk_mfc, "samsung,exynos5260-clock-mfc",
1044                 exynos5260_clk_mfc_init);
1045
1046
1047 /* CMU_MIF */
1048
1049 static const unsigned long mif_clk_regs[] __initconst = {
1050         MEM_PLL_LOCK,
1051         BUS_PLL_LOCK,
1052         MEDIA_PLL_LOCK,
1053         MEM_PLL_CON0,
1054         MEM_PLL_CON1,
1055         MEM_PLL_FDET,
1056         BUS_PLL_CON0,
1057         BUS_PLL_CON1,
1058         BUS_PLL_FDET,
1059         MEDIA_PLL_CON0,
1060         MEDIA_PLL_CON1,
1061         MEDIA_PLL_FDET,
1062         MUX_SEL_MIF,
1063         DIV_MIF,
1064         DIV_MIF_PLL_FDET,
1065         EN_ACLK_MIF,
1066         EN_ACLK_MIF_SECURE_DREX1_TZ,
1067         EN_ACLK_MIF_SECURE_DREX0_TZ,
1068         EN_ACLK_MIF_SECURE_INTMEM,
1069         EN_PCLK_MIF,
1070         EN_PCLK_MIF_SECURE_MONOCNT,
1071         EN_PCLK_MIF_SECURE_RTC_APBIF,
1072         EN_PCLK_MIF_SECURE_DREX1_TZ,
1073         EN_PCLK_MIF_SECURE_DREX0_TZ,
1074         EN_SCLK_MIF,
1075         EN_IP_MIF,
1076         EN_IP_MIF_SECURE_MONOCNT,
1077         EN_IP_MIF_SECURE_RTC_APBIF,
1078         EN_IP_MIF_SECURE_DREX1_TZ,
1079         EN_IP_MIF_SECURE_DREX0_TZ,
1080         EN_IP_MIF_SECURE_INTEMEM,
1081 };
1082
1083 PNAME(mout_mem_pll_p) = {"fin_pll", "fout_mem_pll"};
1084 PNAME(mout_bus_pll_p) = {"fin_pll", "fout_bus_pll"};
1085 PNAME(mout_media_pll_p) = {"fin_pll", "fout_media_pll"};
1086 PNAME(mout_mif_drex_p) = {"dout_mem_pll", "dout_bus_pll"};
1087 PNAME(mout_mif_drex2x_p) = {"dout_mem_pll", "dout_bus_pll"};
1088 PNAME(mout_clkm_phy_p) = {"mout_mif_drex", "dout_media_pll"};
1089 PNAME(mout_clk2x_phy_p) = {"mout_mif_drex2x", "dout_media_pll"};
1090
1091 static const struct samsung_mux_clock mif_mux_clks[] __initconst = {
1092         MUX(MIF_MOUT_MEM_PLL, "mout_mem_pll", mout_mem_pll_p,
1093                         MUX_SEL_MIF, 0, 1),
1094         MUX(MIF_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p,
1095                         MUX_SEL_MIF, 4, 1),
1096         MUX(MIF_MOUT_MEDIA_PLL, "mout_media_pll", mout_media_pll_p,
1097                         MUX_SEL_MIF, 8, 1),
1098         MUX(MIF_MOUT_MIF_DREX, "mout_mif_drex", mout_mif_drex_p,
1099                         MUX_SEL_MIF, 12, 1),
1100         MUX(MIF_MOUT_CLKM_PHY, "mout_clkm_phy", mout_clkm_phy_p,
1101                         MUX_SEL_MIF, 16, 1),
1102         MUX(MIF_MOUT_MIF_DREX2X, "mout_mif_drex2x", mout_mif_drex2x_p,
1103                         MUX_SEL_MIF, 20, 1),
1104         MUX(MIF_MOUT_CLK2X_PHY, "mout_clk2x_phy", mout_clk2x_phy_p,
1105                         MUX_SEL_MIF, 24, 1),
1106 };
1107
1108 static const struct samsung_div_clock mif_div_clks[] __initconst = {
1109         DIV(MIF_DOUT_MEDIA_PLL, "dout_media_pll", "mout_media_pll",
1110                         DIV_MIF, 0, 3),
1111         DIV(MIF_DOUT_MEM_PLL, "dout_mem_pll", "mout_mem_pll",
1112                         DIV_MIF, 4, 3),
1113         DIV(MIF_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll",
1114                         DIV_MIF, 8, 3),
1115         DIV(MIF_DOUT_CLKM_PHY, "dout_clkm_phy", "mout_clkm_phy",
1116                         DIV_MIF, 12, 3),
1117         DIV(MIF_DOUT_CLK2X_PHY, "dout_clk2x_phy", "mout_clk2x_phy",
1118                         DIV_MIF, 16, 4),
1119         DIV(MIF_DOUT_ACLK_MIF_466, "dout_aclk_mif_466", "dout_clk2x_phy",
1120                         DIV_MIF, 20, 3),
1121         DIV(MIF_DOUT_ACLK_BUS_200, "dout_aclk_bus_200", "dout_bus_pll",
1122                         DIV_MIF, 24, 3),
1123         DIV(MIF_DOUT_ACLK_BUS_100, "dout_aclk_bus_100", "dout_bus_pll",
1124                         DIV_MIF, 28, 4),
1125 };
1126
1127 static const struct samsung_gate_clock mif_gate_clks[] __initconst = {
1128         GATE(MIF_CLK_LPDDR3PHY_WRAP0, "clk_lpddr3phy_wrap0", "dout_clk2x_phy",
1129                         EN_IP_MIF, 12, CLK_IGNORE_UNUSED, 0),
1130         GATE(MIF_CLK_LPDDR3PHY_WRAP1, "clk_lpddr3phy_wrap1", "dout_clk2x_phy",
1131                         EN_IP_MIF, 13, CLK_IGNORE_UNUSED, 0),
1132
1133         GATE(MIF_CLK_MONOCNT, "clk_monocnt", "dout_aclk_bus_100",
1134                         EN_IP_MIF_SECURE_MONOCNT, 22,
1135                         CLK_IGNORE_UNUSED, 0),
1136
1137         GATE(MIF_CLK_MIF_RTC, "clk_mif_rtc", "dout_aclk_bus_100",
1138                         EN_IP_MIF_SECURE_RTC_APBIF, 23,
1139                         CLK_IGNORE_UNUSED, 0),
1140
1141         GATE(MIF_CLK_DREX1, "clk_drex1", "dout_aclk_mif_466",
1142                         EN_IP_MIF_SECURE_DREX1_TZ, 9,
1143                         CLK_IGNORE_UNUSED, 0),
1144
1145         GATE(MIF_CLK_DREX0, "clk_drex0", "dout_aclk_mif_466",
1146                         EN_IP_MIF_SECURE_DREX0_TZ, 9,
1147                         CLK_IGNORE_UNUSED, 0),
1148
1149         GATE(MIF_CLK_INTMEM, "clk_intmem", "dout_aclk_bus_200",
1150                         EN_IP_MIF_SECURE_INTEMEM, 11,
1151                         CLK_IGNORE_UNUSED, 0),
1152
1153         GATE(MIF_SCLK_LPDDR3PHY_WRAP_U0, "sclk_lpddr3phy_wrap_u0",
1154                         "dout_clkm_phy", EN_SCLK_MIF, 0,
1155                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1156         GATE(MIF_SCLK_LPDDR3PHY_WRAP_U1, "sclk_lpddr3phy_wrap_u1",
1157                         "dout_clkm_phy", EN_SCLK_MIF, 1,
1158                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1159 };
1160
1161 static const struct samsung_pll_clock mif_pll_clks[] __initconst = {
1162         PLL(pll_2550xx, MIF_FOUT_MEM_PLL, "fout_mem_pll", "fin_pll",
1163                 MEM_PLL_LOCK, MEM_PLL_CON0,
1164                 pll2550_24mhz_tbl),
1165         PLL(pll_2550xx, MIF_FOUT_BUS_PLL, "fout_bus_pll", "fin_pll",
1166                 BUS_PLL_LOCK, BUS_PLL_CON0,
1167                 pll2550_24mhz_tbl),
1168         PLL(pll_2550xx, MIF_FOUT_MEDIA_PLL, "fout_media_pll", "fin_pll",
1169                 MEDIA_PLL_LOCK, MEDIA_PLL_CON0,
1170                 pll2550_24mhz_tbl),
1171 };
1172
1173 static const struct samsung_cmu_info mif_cmu __initconst = {
1174         .pll_clks       = mif_pll_clks,
1175         .nr_pll_clks    = ARRAY_SIZE(mif_pll_clks),
1176         .mux_clks       = mif_mux_clks,
1177         .nr_mux_clks    = ARRAY_SIZE(mif_mux_clks),
1178         .div_clks       = mif_div_clks,
1179         .nr_div_clks    = ARRAY_SIZE(mif_div_clks),
1180         .gate_clks      = mif_gate_clks,
1181         .nr_gate_clks   = ARRAY_SIZE(mif_gate_clks),
1182         .nr_clk_ids     = CLKS_NR_MIF,
1183         .clk_regs       = mif_clk_regs,
1184         .nr_clk_regs    = ARRAY_SIZE(mif_clk_regs),
1185 };
1186
1187 static void __init exynos5260_clk_mif_init(struct device_node *np)
1188 {
1189         samsung_cmu_register_one(np, &mif_cmu);
1190 }
1191
1192 CLK_OF_DECLARE(exynos5260_clk_mif, "samsung,exynos5260-clock-mif",
1193                 exynos5260_clk_mif_init);
1194
1195
1196 /* CMU_PERI */
1197
1198 static const unsigned long peri_clk_regs[] __initconst = {
1199         MUX_SEL_PERI,
1200         MUX_SEL_PERI1,
1201         DIV_PERI,
1202         EN_PCLK_PERI0,
1203         EN_PCLK_PERI1,
1204         EN_PCLK_PERI2,
1205         EN_PCLK_PERI3,
1206         EN_PCLK_PERI_SECURE_CHIPID,
1207         EN_PCLK_PERI_SECURE_PROVKEY0,
1208         EN_PCLK_PERI_SECURE_PROVKEY1,
1209         EN_PCLK_PERI_SECURE_SECKEY,
1210         EN_PCLK_PERI_SECURE_ANTIRBKCNT,
1211         EN_PCLK_PERI_SECURE_TOP_RTC,
1212         EN_PCLK_PERI_SECURE_TZPC,
1213         EN_SCLK_PERI,
1214         EN_SCLK_PERI_SECURE_TOP_RTC,
1215         EN_IP_PERI0,
1216         EN_IP_PERI1,
1217         EN_IP_PERI2,
1218         EN_IP_PERI_SECURE_CHIPID,
1219         EN_IP_PERI_SECURE_PROVKEY0,
1220         EN_IP_PERI_SECURE_PROVKEY1,
1221         EN_IP_PERI_SECURE_SECKEY,
1222         EN_IP_PERI_SECURE_ANTIRBKCNT,
1223         EN_IP_PERI_SECURE_TOP_RTC,
1224         EN_IP_PERI_SECURE_TZPC,
1225 };
1226
1227 PNAME(mout_sclk_pcm_p) = {"ioclk_pcm_extclk", "fin_pll", "dout_aclk_peri_aud",
1228                         "phyclk_hdmi_phy_ref_cko"};
1229 PNAME(mout_sclk_i2scod_p) = {"ioclk_i2s_cdclk", "fin_pll", "dout_aclk_peri_aud",
1230                         "phyclk_hdmi_phy_ref_cko"};
1231 PNAME(mout_sclk_spdif_p) = {"ioclk_spdif_extclk", "fin_pll",
1232                         "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"};
1233
1234 static const struct samsung_mux_clock peri_mux_clks[] __initconst = {
1235         MUX(PERI_MOUT_SCLK_PCM, "mout_sclk_pcm", mout_sclk_pcm_p,
1236                         MUX_SEL_PERI1, 4, 2),
1237         MUX(PERI_MOUT_SCLK_I2SCOD, "mout_sclk_i2scod", mout_sclk_i2scod_p,
1238                         MUX_SEL_PERI1, 12, 2),
1239         MUX(PERI_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p,
1240                         MUX_SEL_PERI1, 20, 2),
1241 };
1242
1243 static const struct samsung_div_clock peri_div_clks[] __initconst = {
1244         DIV(PERI_DOUT_PCM, "dout_pcm", "mout_sclk_pcm", DIV_PERI, 0, 8),
1245         DIV(PERI_DOUT_I2S, "dout_i2s", "mout_sclk_i2scod", DIV_PERI, 8, 6),
1246 };
1247
1248 static const struct samsung_gate_clock peri_gate_clks[] __initconst = {
1249         GATE(PERI_SCLK_PCM1, "sclk_pcm1", "dout_pcm", EN_SCLK_PERI, 0,
1250                         CLK_SET_RATE_PARENT, 0),
1251         GATE(PERI_SCLK_I2S, "sclk_i2s", "dout_i2s", EN_SCLK_PERI, 1,
1252                         CLK_SET_RATE_PARENT, 0),
1253         GATE(PERI_SCLK_SPDIF, "sclk_spdif", "dout_sclk_peri_spi0_b",
1254                         EN_SCLK_PERI, 2, CLK_SET_RATE_PARENT, 0),
1255         GATE(PERI_SCLK_SPI0, "sclk_spi0", "dout_sclk_peri_spi0_b",
1256                         EN_SCLK_PERI, 7, CLK_SET_RATE_PARENT, 0),
1257         GATE(PERI_SCLK_SPI1, "sclk_spi1", "dout_sclk_peri_spi1_b",
1258                         EN_SCLK_PERI, 8, CLK_SET_RATE_PARENT, 0),
1259         GATE(PERI_SCLK_SPI2, "sclk_spi2", "dout_sclk_peri_spi2_b",
1260                         EN_SCLK_PERI, 9, CLK_SET_RATE_PARENT, 0),
1261         GATE(PERI_SCLK_UART0, "sclk_uart0", "dout_sclk_peri_uart0",
1262                         EN_SCLK_PERI, 10, CLK_SET_RATE_PARENT, 0),
1263         GATE(PERI_SCLK_UART1, "sclk_uart1", "dout_sclk_peri_uart1",
1264                         EN_SCLK_PERI, 11, CLK_SET_RATE_PARENT, 0),
1265         GATE(PERI_SCLK_UART2, "sclk_uart2", "dout_sclk_peri_uart2",
1266                         EN_SCLK_PERI, 12, CLK_SET_RATE_PARENT, 0),
1267
1268         GATE(PERI_CLK_ABB, "clk_abb", "dout_aclk_peri_66",
1269                 EN_IP_PERI0, 1, 0, 0),
1270         GATE(PERI_CLK_EFUSE_WRITER, "clk_efuse_writer", "dout_aclk_peri_66",
1271                 EN_IP_PERI0, 5, 0, 0),
1272         GATE(PERI_CLK_HDMICEC, "clk_hdmicec", "dout_aclk_peri_66",
1273                 EN_IP_PERI0, 6, 0, 0),
1274         GATE(PERI_CLK_I2C10, "clk_i2c10", "dout_aclk_peri_66",
1275                 EN_IP_PERI0, 7, 0, 0),
1276         GATE(PERI_CLK_I2C11, "clk_i2c11", "dout_aclk_peri_66",
1277                 EN_IP_PERI0, 8, 0, 0),
1278         GATE(PERI_CLK_I2C8, "clk_i2c8", "dout_aclk_peri_66",
1279                 EN_IP_PERI0, 9, 0, 0),
1280         GATE(PERI_CLK_I2C9, "clk_i2c9", "dout_aclk_peri_66",
1281                 EN_IP_PERI0, 10, 0, 0),
1282         GATE(PERI_CLK_I2C4, "clk_i2c4", "dout_aclk_peri_66",
1283                 EN_IP_PERI0, 11, 0, 0),
1284         GATE(PERI_CLK_I2C5, "clk_i2c5", "dout_aclk_peri_66",
1285                 EN_IP_PERI0, 12, 0, 0),
1286         GATE(PERI_CLK_I2C6, "clk_i2c6", "dout_aclk_peri_66",
1287                 EN_IP_PERI0, 13, 0, 0),
1288         GATE(PERI_CLK_I2C7, "clk_i2c7", "dout_aclk_peri_66",
1289                 EN_IP_PERI0, 14, 0, 0),
1290         GATE(PERI_CLK_I2CHDMI, "clk_i2chdmi", "dout_aclk_peri_66",
1291                 EN_IP_PERI0, 15, 0, 0),
1292         GATE(PERI_CLK_I2S, "clk_peri_i2s", "dout_aclk_peri_66",
1293                 EN_IP_PERI0, 16, 0, 0),
1294         GATE(PERI_CLK_MCT, "clk_mct", "dout_aclk_peri_66",
1295                 EN_IP_PERI0, 17, 0, 0),
1296         GATE(PERI_CLK_PCM, "clk_peri_pcm", "dout_aclk_peri_66",
1297                 EN_IP_PERI0, 18, 0, 0),
1298         GATE(PERI_CLK_HSIC0, "clk_hsic0", "dout_aclk_peri_66",
1299                 EN_IP_PERI0, 20, 0, 0),
1300         GATE(PERI_CLK_HSIC1, "clk_hsic1", "dout_aclk_peri_66",
1301                 EN_IP_PERI0, 21, 0, 0),
1302         GATE(PERI_CLK_HSIC2, "clk_hsic2", "dout_aclk_peri_66",
1303                 EN_IP_PERI0, 22, 0, 0),
1304         GATE(PERI_CLK_HSIC3, "clk_hsic3", "dout_aclk_peri_66",
1305                 EN_IP_PERI0, 23, 0, 0),
1306         GATE(PERI_CLK_WDT_EGL, "clk_wdt_egl", "dout_aclk_peri_66",
1307                 EN_IP_PERI0, 24, 0, 0),
1308         GATE(PERI_CLK_WDT_KFC, "clk_wdt_kfc", "dout_aclk_peri_66",
1309                 EN_IP_PERI0, 25, 0, 0),
1310
1311         GATE(PERI_CLK_UART4, "clk_uart4", "dout_aclk_peri_66",
1312                 EN_IP_PERI2, 0, 0, 0),
1313         GATE(PERI_CLK_PWM, "clk_pwm", "dout_aclk_peri_66",
1314                 EN_IP_PERI2, 3, 0, 0),
1315         GATE(PERI_CLK_SPDIF, "clk_spdif", "dout_aclk_peri_66",
1316                 EN_IP_PERI2, 6, 0, 0),
1317         GATE(PERI_CLK_SPI0, "clk_spi0", "dout_aclk_peri_66",
1318                 EN_IP_PERI2, 7, 0, 0),
1319         GATE(PERI_CLK_SPI1, "clk_spi1", "dout_aclk_peri_66",
1320                 EN_IP_PERI2, 8, 0, 0),
1321         GATE(PERI_CLK_SPI2, "clk_spi2", "dout_aclk_peri_66",
1322                 EN_IP_PERI2, 9, 0, 0),
1323         GATE(PERI_CLK_TMU0, "clk_tmu0", "dout_aclk_peri_66",
1324                 EN_IP_PERI2, 10, 0, 0),
1325         GATE(PERI_CLK_TMU1, "clk_tmu1", "dout_aclk_peri_66",
1326                 EN_IP_PERI2, 11, 0, 0),
1327         GATE(PERI_CLK_TMU2, "clk_tmu2", "dout_aclk_peri_66",
1328                 EN_IP_PERI2, 12, 0, 0),
1329         GATE(PERI_CLK_TMU3, "clk_tmu3", "dout_aclk_peri_66",
1330                 EN_IP_PERI2, 13, 0, 0),
1331         GATE(PERI_CLK_TMU4, "clk_tmu4", "dout_aclk_peri_66",
1332                 EN_IP_PERI2, 14, 0, 0),
1333         GATE(PERI_CLK_ADC, "clk_adc", "dout_aclk_peri_66",
1334                 EN_IP_PERI2, 18, 0, 0),
1335         GATE(PERI_CLK_UART0, "clk_uart0", "dout_aclk_peri_66",
1336                 EN_IP_PERI2, 19, 0, 0),
1337         GATE(PERI_CLK_UART1, "clk_uart1", "dout_aclk_peri_66",
1338                 EN_IP_PERI2, 20, 0, 0),
1339         GATE(PERI_CLK_UART2, "clk_uart2", "dout_aclk_peri_66",
1340                 EN_IP_PERI2, 21, 0, 0),
1341
1342         GATE(PERI_CLK_CHIPID, "clk_chipid", "dout_aclk_peri_66",
1343                 EN_IP_PERI_SECURE_CHIPID, 2, 0, 0),
1344
1345         GATE(PERI_CLK_PROVKEY0, "clk_provkey0", "dout_aclk_peri_66",
1346                 EN_IP_PERI_SECURE_PROVKEY0, 1, 0, 0),
1347
1348         GATE(PERI_CLK_PROVKEY1, "clk_provkey1", "dout_aclk_peri_66",
1349                 EN_IP_PERI_SECURE_PROVKEY1, 2, 0, 0),
1350
1351         GATE(PERI_CLK_SECKEY, "clk_seckey", "dout_aclk_peri_66",
1352                 EN_IP_PERI_SECURE_SECKEY, 5, 0, 0),
1353
1354         GATE(PERI_CLK_TOP_RTC, "clk_top_rtc", "dout_aclk_peri_66",
1355                 EN_IP_PERI_SECURE_TOP_RTC, 5, 0, 0),
1356
1357         GATE(PERI_CLK_TZPC0, "clk_tzpc0", "dout_aclk_peri_66",
1358                 EN_IP_PERI_SECURE_TZPC, 10, 0, 0),
1359         GATE(PERI_CLK_TZPC1, "clk_tzpc1", "dout_aclk_peri_66",
1360                 EN_IP_PERI_SECURE_TZPC, 11, 0, 0),
1361         GATE(PERI_CLK_TZPC2, "clk_tzpc2", "dout_aclk_peri_66",
1362                 EN_IP_PERI_SECURE_TZPC, 12, 0, 0),
1363         GATE(PERI_CLK_TZPC3, "clk_tzpc3", "dout_aclk_peri_66",
1364                 EN_IP_PERI_SECURE_TZPC, 13, 0, 0),
1365         GATE(PERI_CLK_TZPC4, "clk_tzpc4", "dout_aclk_peri_66",
1366                 EN_IP_PERI_SECURE_TZPC, 14, 0, 0),
1367         GATE(PERI_CLK_TZPC5, "clk_tzpc5", "dout_aclk_peri_66",
1368                 EN_IP_PERI_SECURE_TZPC, 15, 0, 0),
1369         GATE(PERI_CLK_TZPC6, "clk_tzpc6", "dout_aclk_peri_66",
1370                 EN_IP_PERI_SECURE_TZPC, 16, 0, 0),
1371         GATE(PERI_CLK_TZPC7, "clk_tzpc7", "dout_aclk_peri_66",
1372                 EN_IP_PERI_SECURE_TZPC, 17, 0, 0),
1373         GATE(PERI_CLK_TZPC8, "clk_tzpc8", "dout_aclk_peri_66",
1374                 EN_IP_PERI_SECURE_TZPC, 18, 0, 0),
1375         GATE(PERI_CLK_TZPC9, "clk_tzpc9", "dout_aclk_peri_66",
1376                 EN_IP_PERI_SECURE_TZPC, 19, 0, 0),
1377         GATE(PERI_CLK_TZPC10, "clk_tzpc10", "dout_aclk_peri_66",
1378                 EN_IP_PERI_SECURE_TZPC, 20, 0, 0),
1379 };
1380
1381 static const struct samsung_cmu_info peri_cmu __initconst = {
1382         .mux_clks       = peri_mux_clks,
1383         .nr_mux_clks    = ARRAY_SIZE(peri_mux_clks),
1384         .div_clks       = peri_div_clks,
1385         .nr_div_clks    = ARRAY_SIZE(peri_div_clks),
1386         .gate_clks      = peri_gate_clks,
1387         .nr_gate_clks   = ARRAY_SIZE(peri_gate_clks),
1388         .nr_clk_ids     = CLKS_NR_PERI,
1389         .clk_regs       = peri_clk_regs,
1390         .nr_clk_regs    = ARRAY_SIZE(peri_clk_regs),
1391 };
1392
1393 static void __init exynos5260_clk_peri_init(struct device_node *np)
1394 {
1395         samsung_cmu_register_one(np, &peri_cmu);
1396 }
1397
1398 CLK_OF_DECLARE(exynos5260_clk_peri, "samsung,exynos5260-clock-peri",
1399                 exynos5260_clk_peri_init);
1400
1401
1402 /* CMU_TOP */
1403
1404 static const unsigned long top_clk_regs[] __initconst = {
1405         DISP_PLL_LOCK,
1406         AUD_PLL_LOCK,
1407         DISP_PLL_CON0,
1408         DISP_PLL_CON1,
1409         DISP_PLL_FDET,
1410         AUD_PLL_CON0,
1411         AUD_PLL_CON1,
1412         AUD_PLL_CON2,
1413         AUD_PLL_FDET,
1414         MUX_SEL_TOP_PLL0,
1415         MUX_SEL_TOP_MFC,
1416         MUX_SEL_TOP_G2D,
1417         MUX_SEL_TOP_GSCL,
1418         MUX_SEL_TOP_ISP10,
1419         MUX_SEL_TOP_ISP11,
1420         MUX_SEL_TOP_DISP0,
1421         MUX_SEL_TOP_DISP1,
1422         MUX_SEL_TOP_BUS,
1423         MUX_SEL_TOP_PERI0,
1424         MUX_SEL_TOP_PERI1,
1425         MUX_SEL_TOP_FSYS,
1426         DIV_TOP_G2D_MFC,
1427         DIV_TOP_GSCL_ISP0,
1428         DIV_TOP_ISP10,
1429         DIV_TOP_ISP11,
1430         DIV_TOP_DISP,
1431         DIV_TOP_BUS,
1432         DIV_TOP_PERI0,
1433         DIV_TOP_PERI1,
1434         DIV_TOP_PERI2,
1435         DIV_TOP_FSYS0,
1436         DIV_TOP_FSYS1,
1437         DIV_TOP_HPM,
1438         DIV_TOP_PLL_FDET,
1439         EN_ACLK_TOP,
1440         EN_SCLK_TOP,
1441         EN_IP_TOP,
1442 };
1443
1444 /* fixed rate clocks generated inside the soc */
1445 static const struct samsung_fixed_rate_clock fixed_rate_clks[] __initconst = {
1446         FRATE(PHYCLK_DPTX_PHY_CH3_TXD_CLK, "phyclk_dptx_phy_ch3_txd_clk", NULL,
1447                         0, 270000000),
1448         FRATE(PHYCLK_DPTX_PHY_CH2_TXD_CLK, "phyclk_dptx_phy_ch2_txd_clk", NULL,
1449                         0, 270000000),
1450         FRATE(PHYCLK_DPTX_PHY_CH1_TXD_CLK, "phyclk_dptx_phy_ch1_txd_clk", NULL,
1451                         0, 270000000),
1452         FRATE(PHYCLK_DPTX_PHY_CH0_TXD_CLK, "phyclk_dptx_phy_ch0_txd_clk", NULL,
1453                         0, 270000000),
1454         FRATE(phyclk_hdmi_phy_tmds_clko, "phyclk_hdmi_phy_tmds_clko", NULL,
1455                         0, 250000000),
1456         FRATE(PHYCLK_HDMI_PHY_PIXEL_CLKO, "phyclk_hdmi_phy_pixel_clko", NULL,
1457                         0, 1660000000),
1458         FRATE(PHYCLK_HDMI_LINK_O_TMDS_CLKHI, "phyclk_hdmi_link_o_tmds_clkhi",
1459                         NULL, 0, 125000000),
1460         FRATE(PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS,
1461                         "phyclk_mipi_dphy_4l_m_txbyte_clkhs" , NULL,
1462                         0, 187500000),
1463         FRATE(PHYCLK_DPTX_PHY_O_REF_CLK_24M, "phyclk_dptx_phy_o_ref_clk_24m",
1464                         NULL, 0, 24000000),
1465         FRATE(PHYCLK_DPTX_PHY_CLK_DIV2, "phyclk_dptx_phy_clk_div2", NULL,
1466                         0, 135000000),
1467         FRATE(PHYCLK_MIPI_DPHY_4L_M_RXCLKESC0,
1468                         "phyclk_mipi_dphy_4l_m_rxclkesc0", NULL, 0, 20000000),
1469         FRATE(PHYCLK_USBHOST20_PHY_PHYCLOCK, "phyclk_usbhost20_phy_phyclock",
1470                         NULL, 0, 60000000),
1471         FRATE(PHYCLK_USBHOST20_PHY_FREECLK, "phyclk_usbhost20_phy_freeclk",
1472                         NULL, 0, 60000000),
1473         FRATE(PHYCLK_USBHOST20_PHY_CLK48MOHCI,
1474                         "phyclk_usbhost20_phy_clk48mohci", NULL, 0, 48000000),
1475         FRATE(PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,
1476                         "phyclk_usbdrd30_udrd30_pipe_pclk", NULL, 0, 125000000),
1477         FRATE(PHYCLK_USBDRD30_UDRD30_PHYCLOCK,
1478                         "phyclk_usbdrd30_udrd30_phyclock", NULL, 0, 60000000),
1479 };
1480
1481 PNAME(mout_memtop_pll_user_p) = {"fin_pll", "dout_mem_pll"};
1482 PNAME(mout_bustop_pll_user_p) = {"fin_pll", "dout_bus_pll"};
1483 PNAME(mout_mediatop_pll_user_p) = {"fin_pll", "dout_media_pll"};
1484 PNAME(mout_audtop_pll_user_p) = {"fin_pll", "mout_aud_pll"};
1485 PNAME(mout_aud_pll_p) = {"fin_pll", "fout_aud_pll"};
1486 PNAME(mout_disp_pll_p) = {"fin_pll", "fout_disp_pll"};
1487 PNAME(mout_mfc_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
1488 PNAME(mout_aclk_mfc_333_p) = {"mout_mediatop_pll_user", "mout_mfc_bustop_333"};
1489 PNAME(mout_g2d_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
1490 PNAME(mout_aclk_g2d_333_p) = {"mout_mediatop_pll_user", "mout_g2d_bustop_333"};
1491 PNAME(mout_gscl_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
1492 PNAME(mout_aclk_gscl_333_p) = {"mout_mediatop_pll_user",
1493                         "mout_gscl_bustop_333"};
1494 PNAME(mout_m2m_mediatop_400_p) = {"mout_mediatop_pll_user", "mout_disp_pll"};
1495 PNAME(mout_aclk_gscl_400_p) = {"mout_bustop_pll_user",
1496                         "mout_m2m_mediatop_400"};
1497 PNAME(mout_gscl_bustop_fimc_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
1498 PNAME(mout_aclk_gscl_fimc_p) = {"mout_mediatop_pll_user",
1499                         "mout_gscl_bustop_fimc"};
1500 PNAME(mout_isp1_media_266_p) = {"mout_mediatop_pll_user",
1501                         "mout_memtop_pll_user"};
1502 PNAME(mout_aclk_isp1_266_p) = {"mout_bustop_pll_user", "mout_isp1_media_266"};
1503 PNAME(mout_isp1_media_400_p) = {"mout_mediatop_pll_user", "mout_disp_pll"};
1504 PNAME(mout_aclk_isp1_400_p) = {"mout_bustop_pll_user", "mout_isp1_media_400"};
1505 PNAME(mout_sclk_isp_spi_p) = {"fin_pll", "mout_bustop_pll_user"};
1506 PNAME(mout_sclk_isp_uart_p) = {"fin_pll", "mout_bustop_pll_user"};
1507 PNAME(mout_sclk_isp_sensor_p) = {"fin_pll", "mout_bustop_pll_user"};
1508 PNAME(mout_disp_disp_333_p) = {"mout_disp_pll", "mout_bustop_pll_user"};
1509 PNAME(mout_aclk_disp_333_p) = {"mout_mediatop_pll_user", "mout_disp_disp_333"};
1510 PNAME(mout_disp_disp_222_p) = {"mout_disp_pll", "mout_bustop_pll_user"};
1511 PNAME(mout_aclk_disp_222_p) = {"mout_mediatop_pll_user", "mout_disp_disp_222"};
1512 PNAME(mout_disp_media_pixel_p) = {"mout_mediatop_pll_user",
1513                         "mout_bustop_pll_user"};
1514 PNAME(mout_sclk_disp_pixel_p) = {"mout_disp_pll", "mout_disp_media_pixel"};
1515 PNAME(mout_bus_bustop_400_p) = {"mout_bustop_pll_user", "mout_memtop_pll_user"};
1516 PNAME(mout_bus_bustop_100_p) = {"mout_bustop_pll_user", "mout_memtop_pll_user"};
1517 PNAME(mout_sclk_peri_spi_clk_p) = {"fin_pll", "mout_bustop_pll_user"};
1518 PNAME(mout_sclk_peri_uart_uclk_p) = {"fin_pll", "mout_bustop_pll_user"};
1519 PNAME(mout_sclk_fsys_usb_p) = {"fin_pll", "mout_bustop_pll_user"};
1520 PNAME(mout_sclk_fsys_mmc_sdclkin_a_p) = {"fin_pll", "mout_bustop_pll_user"};
1521 PNAME(mout_sclk_fsys_mmc0_sdclkin_b_p) = {"mout_sclk_fsys_mmc0_sdclkin_a",
1522                         "mout_mediatop_pll_user"};
1523 PNAME(mout_sclk_fsys_mmc1_sdclkin_b_p) = {"mout_sclk_fsys_mmc1_sdclkin_a",
1524                         "mout_mediatop_pll_user"};
1525 PNAME(mout_sclk_fsys_mmc2_sdclkin_b_p) = {"mout_sclk_fsys_mmc2_sdclkin_a",
1526                         "mout_mediatop_pll_user"};
1527
1528 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
1529         MUX(TOP_MOUT_MEDIATOP_PLL_USER, "mout_mediatop_pll_user",
1530                         mout_mediatop_pll_user_p,
1531                         MUX_SEL_TOP_PLL0, 0, 1),
1532         MUX(TOP_MOUT_MEMTOP_PLL_USER, "mout_memtop_pll_user",
1533                         mout_memtop_pll_user_p,
1534                         MUX_SEL_TOP_PLL0, 4, 1),
1535         MUX(TOP_MOUT_BUSTOP_PLL_USER, "mout_bustop_pll_user",
1536                         mout_bustop_pll_user_p,
1537                         MUX_SEL_TOP_PLL0, 8, 1),
1538         MUX(TOP_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p,
1539                         MUX_SEL_TOP_PLL0, 12, 1),
1540         MUX(TOP_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p,
1541                         MUX_SEL_TOP_PLL0, 16, 1),
1542         MUX(TOP_MOUT_AUDTOP_PLL_USER, "mout_audtop_pll_user",
1543                         mout_audtop_pll_user_p,
1544                         MUX_SEL_TOP_PLL0, 24, 1),
1545
1546         MUX(TOP_MOUT_DISP_DISP_333, "mout_disp_disp_333", mout_disp_disp_333_p,
1547                         MUX_SEL_TOP_DISP0, 0, 1),
1548         MUX(TOP_MOUT_ACLK_DISP_333, "mout_aclk_disp_333", mout_aclk_disp_333_p,
1549                         MUX_SEL_TOP_DISP0, 8, 1),
1550         MUX(TOP_MOUT_DISP_DISP_222, "mout_disp_disp_222", mout_disp_disp_222_p,
1551                         MUX_SEL_TOP_DISP0, 12, 1),
1552         MUX(TOP_MOUT_ACLK_DISP_222, "mout_aclk_disp_222", mout_aclk_disp_222_p,
1553                         MUX_SEL_TOP_DISP0, 20, 1),
1554
1555         MUX(TOP_MOUT_FIMD1, "mout_sclk_disp_pixel", mout_sclk_disp_pixel_p,
1556                         MUX_SEL_TOP_DISP1, 0, 1),
1557         MUX(TOP_MOUT_DISP_MEDIA_PIXEL, "mout_disp_media_pixel",
1558                         mout_disp_media_pixel_p,
1559                         MUX_SEL_TOP_DISP1, 8, 1),
1560
1561         MUX(TOP_MOUT_SCLK_PERI_SPI2_CLK, "mout_sclk_peri_spi2_clk",
1562                         mout_sclk_peri_spi_clk_p,
1563                         MUX_SEL_TOP_PERI1, 0, 1),
1564         MUX(TOP_MOUT_SCLK_PERI_SPI1_CLK, "mout_sclk_peri_spi1_clk",
1565                         mout_sclk_peri_spi_clk_p,
1566                         MUX_SEL_TOP_PERI1, 4, 1),
1567         MUX(TOP_MOUT_SCLK_PERI_SPI0_CLK, "mout_sclk_peri_spi0_clk",
1568                         mout_sclk_peri_spi_clk_p,
1569                         MUX_SEL_TOP_PERI1, 8, 1),
1570         MUX(TOP_MOUT_SCLK_PERI_UART1_UCLK, "mout_sclk_peri_uart1_uclk",
1571                         mout_sclk_peri_uart_uclk_p,
1572                         MUX_SEL_TOP_PERI1, 12, 1),
1573         MUX(TOP_MOUT_SCLK_PERI_UART2_UCLK, "mout_sclk_peri_uart2_uclk",
1574                         mout_sclk_peri_uart_uclk_p,
1575                         MUX_SEL_TOP_PERI1, 16, 1),
1576         MUX(TOP_MOUT_SCLK_PERI_UART0_UCLK, "mout_sclk_peri_uart0_uclk",
1577                         mout_sclk_peri_uart_uclk_p,
1578                         MUX_SEL_TOP_PERI1, 20, 1),
1579
1580
1581         MUX(TOP_MOUT_BUS1_BUSTOP_400, "mout_bus1_bustop_400",
1582                         mout_bus_bustop_400_p,
1583                         MUX_SEL_TOP_BUS, 0, 1),
1584         MUX(TOP_MOUT_BUS1_BUSTOP_100, "mout_bus1_bustop_100",
1585                         mout_bus_bustop_100_p,
1586                         MUX_SEL_TOP_BUS, 4, 1),
1587         MUX(TOP_MOUT_BUS2_BUSTOP_100, "mout_bus2_bustop_100",
1588                         mout_bus_bustop_100_p,
1589                         MUX_SEL_TOP_BUS, 8, 1),
1590         MUX(TOP_MOUT_BUS2_BUSTOP_400, "mout_bus2_bustop_400",
1591                         mout_bus_bustop_400_p,
1592                         MUX_SEL_TOP_BUS, 12, 1),
1593         MUX(TOP_MOUT_BUS3_BUSTOP_400, "mout_bus3_bustop_400",
1594                         mout_bus_bustop_400_p,
1595                         MUX_SEL_TOP_BUS, 16, 1),
1596         MUX(TOP_MOUT_BUS3_BUSTOP_100, "mout_bus3_bustop_100",
1597                         mout_bus_bustop_100_p,
1598                         MUX_SEL_TOP_BUS, 20, 1),
1599         MUX(TOP_MOUT_BUS4_BUSTOP_400, "mout_bus4_bustop_400",
1600                         mout_bus_bustop_400_p,
1601                         MUX_SEL_TOP_BUS, 24, 1),
1602         MUX(TOP_MOUT_BUS4_BUSTOP_100, "mout_bus4_bustop_100",
1603                         mout_bus_bustop_100_p,
1604                         MUX_SEL_TOP_BUS, 28, 1),
1605
1606         MUX(TOP_MOUT_SCLK_FSYS_USB, "mout_sclk_fsys_usb",
1607                         mout_sclk_fsys_usb_p,
1608                         MUX_SEL_TOP_FSYS, 0, 1),
1609         MUX(TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A, "mout_sclk_fsys_mmc2_sdclkin_a",
1610                         mout_sclk_fsys_mmc_sdclkin_a_p,
1611                         MUX_SEL_TOP_FSYS, 4, 1),
1612         MUX(TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B, "mout_sclk_fsys_mmc2_sdclkin_b",
1613                         mout_sclk_fsys_mmc2_sdclkin_b_p,
1614                         MUX_SEL_TOP_FSYS, 8, 1),
1615         MUX(TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A, "mout_sclk_fsys_mmc1_sdclkin_a",
1616                         mout_sclk_fsys_mmc_sdclkin_a_p,
1617                         MUX_SEL_TOP_FSYS, 12, 1),
1618         MUX(TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B, "mout_sclk_fsys_mmc1_sdclkin_b",
1619                         mout_sclk_fsys_mmc1_sdclkin_b_p,
1620                         MUX_SEL_TOP_FSYS, 16, 1),
1621         MUX(TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A, "mout_sclk_fsys_mmc0_sdclkin_a",
1622                         mout_sclk_fsys_mmc_sdclkin_a_p,
1623                         MUX_SEL_TOP_FSYS, 20, 1),
1624         MUX(TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B, "mout_sclk_fsys_mmc0_sdclkin_b",
1625                         mout_sclk_fsys_mmc0_sdclkin_b_p,
1626                         MUX_SEL_TOP_FSYS, 24, 1),
1627
1628         MUX(TOP_MOUT_ISP1_MEDIA_400, "mout_isp1_media_400",
1629                         mout_isp1_media_400_p,
1630                         MUX_SEL_TOP_ISP10, 4, 1),
1631         MUX(TOP_MOUT_ACLK_ISP1_400, "mout_aclk_isp1_400", mout_aclk_isp1_400_p,
1632                         MUX_SEL_TOP_ISP10, 8 , 1),
1633         MUX(TOP_MOUT_ISP1_MEDIA_266, "mout_isp1_media_266",
1634                         mout_isp1_media_266_p,
1635                         MUX_SEL_TOP_ISP10, 16, 1),
1636         MUX(TOP_MOUT_ACLK_ISP1_266, "mout_aclk_isp1_266", mout_aclk_isp1_266_p,
1637                         MUX_SEL_TOP_ISP10, 20, 1),
1638
1639         MUX(TOP_MOUT_SCLK_ISP1_SPI0, "mout_sclk_isp1_spi0", mout_sclk_isp_spi_p,
1640                         MUX_SEL_TOP_ISP11, 4, 1),
1641         MUX(TOP_MOUT_SCLK_ISP1_SPI1, "mout_sclk_isp1_spi1", mout_sclk_isp_spi_p,
1642                         MUX_SEL_TOP_ISP11, 8, 1),
1643         MUX(TOP_MOUT_SCLK_ISP1_UART, "mout_sclk_isp1_uart",
1644                         mout_sclk_isp_uart_p,
1645                         MUX_SEL_TOP_ISP11, 12, 1),
1646         MUX(TOP_MOUT_SCLK_ISP1_SENSOR0, "mout_sclk_isp1_sensor0",
1647                         mout_sclk_isp_sensor_p,
1648                         MUX_SEL_TOP_ISP11, 16, 1),
1649         MUX(TOP_MOUT_SCLK_ISP1_SENSOR1, "mout_sclk_isp1_sensor1",
1650                         mout_sclk_isp_sensor_p,
1651                         MUX_SEL_TOP_ISP11, 20, 1),
1652         MUX(TOP_MOUT_SCLK_ISP1_SENSOR2, "mout_sclk_isp1_sensor2",
1653                         mout_sclk_isp_sensor_p,
1654                         MUX_SEL_TOP_ISP11, 24, 1),
1655
1656         MUX(TOP_MOUT_MFC_BUSTOP_333, "mout_mfc_bustop_333",
1657                         mout_mfc_bustop_333_p,
1658                         MUX_SEL_TOP_MFC, 4, 1),
1659         MUX(TOP_MOUT_ACLK_MFC_333, "mout_aclk_mfc_333", mout_aclk_mfc_333_p,
1660                         MUX_SEL_TOP_MFC, 8, 1),
1661
1662         MUX(TOP_MOUT_G2D_BUSTOP_333, "mout_g2d_bustop_333",
1663                         mout_g2d_bustop_333_p,
1664                         MUX_SEL_TOP_G2D, 4, 1),
1665         MUX(TOP_MOUT_ACLK_G2D_333, "mout_aclk_g2d_333", mout_aclk_g2d_333_p,
1666                         MUX_SEL_TOP_G2D, 8, 1),
1667
1668         MUX(TOP_MOUT_M2M_MEDIATOP_400, "mout_m2m_mediatop_400",
1669                         mout_m2m_mediatop_400_p,
1670                         MUX_SEL_TOP_GSCL, 0, 1),
1671         MUX(TOP_MOUT_ACLK_GSCL_400, "mout_aclk_gscl_400",
1672                         mout_aclk_gscl_400_p,
1673                         MUX_SEL_TOP_GSCL, 4, 1),
1674         MUX(TOP_MOUT_GSCL_BUSTOP_333, "mout_gscl_bustop_333",
1675                         mout_gscl_bustop_333_p,
1676                         MUX_SEL_TOP_GSCL, 8, 1),
1677         MUX(TOP_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333",
1678                         mout_aclk_gscl_333_p,
1679                         MUX_SEL_TOP_GSCL, 12, 1),
1680         MUX(TOP_MOUT_GSCL_BUSTOP_FIMC, "mout_gscl_bustop_fimc",
1681                         mout_gscl_bustop_fimc_p,
1682                         MUX_SEL_TOP_GSCL, 16, 1),
1683         MUX(TOP_MOUT_ACLK_GSCL_FIMC, "mout_aclk_gscl_fimc",
1684                         mout_aclk_gscl_fimc_p,
1685                         MUX_SEL_TOP_GSCL, 20, 1),
1686 };
1687
1688 static const struct samsung_div_clock top_div_clks[] __initconst = {
1689         DIV(TOP_DOUT_ACLK_G2D_333, "dout_aclk_g2d_333", "mout_aclk_g2d_333",
1690                         DIV_TOP_G2D_MFC, 0, 3),
1691         DIV(TOP_DOUT_ACLK_MFC_333, "dout_aclk_mfc_333", "mout_aclk_mfc_333",
1692                         DIV_TOP_G2D_MFC, 4, 3),
1693
1694         DIV(TOP_DOUT_ACLK_GSCL_333, "dout_aclk_gscl_333", "mout_aclk_gscl_333",
1695                         DIV_TOP_GSCL_ISP0, 0, 3),
1696         DIV(TOP_DOUT_ACLK_GSCL_400, "dout_aclk_gscl_400", "mout_aclk_gscl_400",
1697                         DIV_TOP_GSCL_ISP0, 4, 3),
1698         DIV(TOP_DOUT_ACLK_GSCL_FIMC, "dout_aclk_gscl_fimc",
1699                         "mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0, 8, 3),
1700         DIV(TOP_DOUT_SCLK_ISP1_SENSOR0_A, "dout_sclk_isp1_sensor0_a",
1701                         "mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0, 16, 4),
1702         DIV(TOP_DOUT_SCLK_ISP1_SENSOR1_A, "dout_sclk_isp1_sensor1_a",
1703                         "mout_aclk_gscl_400", DIV_TOP_GSCL_ISP0, 20, 4),
1704         DIV(TOP_DOUT_SCLK_ISP1_SENSOR2_A, "dout_sclk_isp1_sensor2_a",
1705                         "mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0, 24, 4),
1706
1707         DIV(TOP_DOUT_ACLK_ISP1_266, "dout_aclk_isp1_266", "mout_aclk_isp1_266",
1708                         DIV_TOP_ISP10, 0, 3),
1709         DIV(TOP_DOUT_ACLK_ISP1_400, "dout_aclk_isp1_400", "mout_aclk_isp1_400",
1710                         DIV_TOP_ISP10, 4, 3),
1711         DIV(TOP_DOUT_SCLK_ISP1_SPI0_A, "dout_sclk_isp1_spi0_a",
1712                         "mout_sclk_isp1_spi0", DIV_TOP_ISP10, 12, 4),
1713         DIV(TOP_DOUT_SCLK_ISP1_SPI0_B, "dout_sclk_isp1_spi0_b",
1714                         "dout_sclk_isp1_spi0_a", DIV_TOP_ISP10, 16, 8),
1715
1716         DIV(TOP_DOUT_SCLK_ISP1_SPI1_A, "dout_sclk_isp1_spi1_a",
1717                         "mout_sclk_isp1_spi1", DIV_TOP_ISP11, 0, 4),
1718         DIV(TOP_DOUT_SCLK_ISP1_SPI1_B, "dout_sclk_isp1_spi1_b",
1719                         "dout_sclk_isp1_spi1_a", DIV_TOP_ISP11, 4, 8),
1720         DIV(TOP_DOUT_SCLK_ISP1_UART, "dout_sclk_isp1_uart",
1721                         "mout_sclk_isp1_uart", DIV_TOP_ISP11, 12, 4),
1722         DIV(TOP_DOUT_SCLK_ISP1_SENSOR0_B, "dout_sclk_isp1_sensor0_b",
1723                         "dout_sclk_isp1_sensor0_a", DIV_TOP_ISP11, 16, 4),
1724         DIV(TOP_DOUT_SCLK_ISP1_SENSOR1_B, "dout_sclk_isp1_sensor1_b",
1725                         "dout_sclk_isp1_sensor1_a", DIV_TOP_ISP11, 20, 4),
1726         DIV(TOP_DOUT_SCLK_ISP1_SENSOR2_B, "dout_sclk_isp1_sensor2_b",
1727                         "dout_sclk_isp1_sensor2_a", DIV_TOP_ISP11, 24, 4),
1728
1729         DIV(TOP_DOUTTOP__SCLK_HPM_TARGETCLK, "dout_sclk_hpm_targetclk",
1730                         "mout_bustop_pll_user", DIV_TOP_HPM, 0, 3),
1731
1732         DIV(TOP_DOUT_ACLK_DISP_333, "dout_aclk_disp_333", "mout_aclk_disp_333",
1733                         DIV_TOP_DISP, 0, 3),
1734         DIV(TOP_DOUT_ACLK_DISP_222, "dout_aclk_disp_222", "mout_aclk_disp_222",
1735                         DIV_TOP_DISP, 4, 3),
1736         DIV(TOP_DOUT_SCLK_DISP_PIXEL, "dout_sclk_disp_pixel",
1737                         "mout_sclk_disp_pixel", DIV_TOP_DISP, 8, 3),
1738
1739         DIV(TOP_DOUT_ACLK_BUS1_400, "dout_aclk_bus1_400",
1740                         "mout_bus1_bustop_400", DIV_TOP_BUS, 0, 3),
1741         DIV(TOP_DOUT_ACLK_BUS1_100, "dout_aclk_bus1_100",
1742                         "mout_bus1_bustop_100", DIV_TOP_BUS, 4, 4),
1743         DIV(TOP_DOUT_ACLK_BUS2_400, "dout_aclk_bus2_400",
1744                         "mout_bus2_bustop_400", DIV_TOP_BUS, 8, 3),
1745         DIV(TOP_DOUT_ACLK_BUS2_100, "dout_aclk_bus2_100",
1746                         "mout_bus2_bustop_100", DIV_TOP_BUS, 12, 4),
1747         DIV(TOP_DOUT_ACLK_BUS3_400, "dout_aclk_bus3_400",
1748                         "mout_bus3_bustop_400", DIV_TOP_BUS, 16, 3),
1749         DIV(TOP_DOUT_ACLK_BUS3_100, "dout_aclk_bus3_100",
1750                         "mout_bus3_bustop_100", DIV_TOP_BUS, 20, 4),
1751         DIV(TOP_DOUT_ACLK_BUS4_400, "dout_aclk_bus4_400",
1752                         "mout_bus4_bustop_400", DIV_TOP_BUS, 24, 3),
1753         DIV(TOP_DOUT_ACLK_BUS4_100, "dout_aclk_bus4_100",
1754                         "mout_bus4_bustop_100", DIV_TOP_BUS, 28, 4),
1755
1756         DIV(TOP_DOUT_SCLK_PERI_SPI0_A, "dout_sclk_peri_spi0_a",
1757                         "mout_sclk_peri_spi0_clk", DIV_TOP_PERI0, 4, 4),
1758         DIV(TOP_DOUT_SCLK_PERI_SPI0_B, "dout_sclk_peri_spi0_b",
1759                         "dout_sclk_peri_spi0_a", DIV_TOP_PERI0, 8, 8),
1760         DIV(TOP_DOUT_SCLK_PERI_SPI1_A, "dout_sclk_peri_spi1_a",
1761                         "mout_sclk_peri_spi1_clk", DIV_TOP_PERI0, 16, 4),
1762         DIV(TOP_DOUT_SCLK_PERI_SPI1_B, "dout_sclk_peri_spi1_b",
1763                         "dout_sclk_peri_spi1_a", DIV_TOP_PERI0, 20, 8),
1764
1765         DIV(TOP_DOUT_SCLK_PERI_SPI2_A, "dout_sclk_peri_spi2_a",
1766                         "mout_sclk_peri_spi2_clk", DIV_TOP_PERI1, 0, 4),
1767         DIV(TOP_DOUT_SCLK_PERI_SPI2_B, "dout_sclk_peri_spi2_b",
1768                         "dout_sclk_peri_spi2_a", DIV_TOP_PERI1, 4, 8),
1769         DIV(TOP_DOUT_SCLK_PERI_UART1, "dout_sclk_peri_uart1",
1770                         "mout_sclk_peri_uart1_uclk", DIV_TOP_PERI1, 16, 4),
1771         DIV(TOP_DOUT_SCLK_PERI_UART2, "dout_sclk_peri_uart2",
1772                         "mout_sclk_peri_uart2_uclk", DIV_TOP_PERI1, 20, 4),
1773         DIV(TOP_DOUT_SCLK_PERI_UART0, "dout_sclk_peri_uart0",
1774                         "mout_sclk_peri_uart0_uclk", DIV_TOP_PERI1, 24, 4),
1775
1776         DIV(TOP_DOUT_ACLK_PERI_66, "dout_aclk_peri_66", "mout_bustop_pll_user",
1777                         DIV_TOP_PERI2, 20, 4),
1778         DIV(TOP_DOUT_ACLK_PERI_AUD, "dout_aclk_peri_aud",
1779                         "mout_audtop_pll_user", DIV_TOP_PERI2, 24, 3),
1780
1781         DIV(TOP_DOUT_ACLK_FSYS_200, "dout_aclk_fsys_200",
1782                         "mout_bustop_pll_user", DIV_TOP_FSYS0, 0, 3),
1783         DIV(TOP_DOUT_SCLK_FSYS_USBDRD30_SUSPEND_CLK,
1784                         "dout_sclk_fsys_usbdrd30_suspend_clk",
1785                         "mout_sclk_fsys_usb", DIV_TOP_FSYS0, 4, 4),
1786         DIV(TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_A, "dout_sclk_fsys_mmc0_sdclkin_a",
1787                         "mout_sclk_fsys_mmc0_sdclkin_b",
1788                         DIV_TOP_FSYS0, 12, 4),
1789         DIV(TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_B, "dout_sclk_fsys_mmc0_sdclkin_b",
1790                         "dout_sclk_fsys_mmc0_sdclkin_a",
1791                         DIV_TOP_FSYS0, 16, 8),
1792
1793
1794         DIV(TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_A, "dout_sclk_fsys_mmc1_sdclkin_a",
1795                         "mout_sclk_fsys_mmc1_sdclkin_b",
1796                         DIV_TOP_FSYS1, 0, 4),
1797         DIV(TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_B, "dout_sclk_fsys_mmc1_sdclkin_b",
1798                         "dout_sclk_fsys_mmc1_sdclkin_a",
1799                         DIV_TOP_FSYS1, 4, 8),
1800         DIV(TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_A, "dout_sclk_fsys_mmc2_sdclkin_a",
1801                         "mout_sclk_fsys_mmc2_sdclkin_b",
1802                         DIV_TOP_FSYS1, 12, 4),
1803         DIV(TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_B, "dout_sclk_fsys_mmc2_sdclkin_b",
1804                         "dout_sclk_fsys_mmc2_sdclkin_a",
1805                         DIV_TOP_FSYS1, 16, 8),
1806
1807 };
1808
1809 static const struct samsung_gate_clock top_gate_clks[] __initconst = {
1810         GATE(TOP_SCLK_MMC0, "sclk_fsys_mmc0_sdclkin",
1811                         "dout_sclk_fsys_mmc0_sdclkin_b",
1812                         EN_SCLK_TOP, 7, CLK_SET_RATE_PARENT, 0),
1813         GATE(TOP_SCLK_MMC1, "sclk_fsys_mmc1_sdclkin",
1814                         "dout_sclk_fsys_mmc1_sdclkin_b",
1815                         EN_SCLK_TOP, 8, CLK_SET_RATE_PARENT, 0),
1816         GATE(TOP_SCLK_MMC2, "sclk_fsys_mmc2_sdclkin",
1817                         "dout_sclk_fsys_mmc2_sdclkin_b",
1818                         EN_SCLK_TOP, 9, CLK_SET_RATE_PARENT, 0),
1819         GATE(TOP_SCLK_FIMD1, "sclk_disp_pixel", "dout_sclk_disp_pixel",
1820                         EN_ACLK_TOP, 10, CLK_IGNORE_UNUSED |
1821                         CLK_SET_RATE_PARENT, 0),
1822 };
1823
1824 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
1825         PLL(pll_2550xx, TOP_FOUT_DISP_PLL, "fout_disp_pll", "fin_pll",
1826                 DISP_PLL_LOCK, DISP_PLL_CON0,
1827                 pll2550_24mhz_tbl),
1828         PLL(pll_2650xx, TOP_FOUT_AUD_PLL, "fout_aud_pll", "fin_pll",
1829                 AUD_PLL_LOCK, AUD_PLL_CON0,
1830                 pll2650_24mhz_tbl),
1831 };
1832
1833 static const struct samsung_cmu_info top_cmu __initconst = {
1834         .pll_clks       = top_pll_clks,
1835         .nr_pll_clks    = ARRAY_SIZE(top_pll_clks),
1836         .mux_clks       = top_mux_clks,
1837         .nr_mux_clks    = ARRAY_SIZE(top_mux_clks),
1838         .div_clks       = top_div_clks,
1839         .nr_div_clks    = ARRAY_SIZE(top_div_clks),
1840         .gate_clks      = top_gate_clks,
1841         .nr_gate_clks   = ARRAY_SIZE(top_gate_clks),
1842         .fixed_clks     = fixed_rate_clks,
1843         .nr_fixed_clks  = ARRAY_SIZE(fixed_rate_clks),
1844         .nr_clk_ids     = CLKS_NR_TOP,
1845         .clk_regs       = top_clk_regs,
1846         .nr_clk_regs    = ARRAY_SIZE(top_clk_regs),
1847 };
1848
1849 static void __init exynos5260_clk_top_init(struct device_node *np)
1850 {
1851         samsung_cmu_register_one(np, &top_cmu);
1852 }
1853
1854 CLK_OF_DECLARE(exynos5260_clk_top, "samsung,exynos5260-clock-top",
1855                 exynos5260_clk_top_init);