drivers/clk/samsung/clk-exynos-audss.c

   1 /*
   2  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   3  * Author: Padmavathi Venna <padma.v@samsung.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * Common Clock Framework support for Audio Subsystem Clock Controller.
  10 */
  11
  12 #include <linux/slab.h>
  13 #include <linux/io.h>
  14 #include <linux/clk.h>
  15 #include <linux/clk-provider.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_device.h>
  18 #include <linux/syscore_ops.h>
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21
  22 #include <dt-bindings/clock/exynos-audss-clk.h>
  23
  24 static DEFINE_SPINLOCK(lock);
  25 static void __iomem *reg_base;
  26 static struct clk_hw_onecell_data *clk_data;
  27 /*
  28  * On Exynos5420 this will be a clock which has to be enabled before any
  29  * access to audss registers. Typically a child of EPLL.
  30  *
  31  * On other platforms this will be -ENODEV.
  32  */
  33 static struct clk *epll;
  34
  35 #define ASS_CLK_SRC 0x0
  36 #define ASS_CLK_DIV 0x4
  37 #define ASS_CLK_GATE 0x8
  38
  39 #ifdef CONFIG_PM_SLEEP
  40 static unsigned long reg_save[][2] = {
  41         { ASS_CLK_SRC,  0 },
  42         { ASS_CLK_DIV,  0 },
  43         { ASS_CLK_GATE, 0 },
  44 };
  45
  46 static int exynos_audss_clk_suspend(struct device *dev)
  47 {
  48         int i;
  49
  50         for (i = 0; i < ARRAY_SIZE(reg_save); i++)
  51                 reg_save[i][1] = readl(reg_base + reg_save[i][0]);
  52
  53         return 0;
  54 }
  55
  56 static int exynos_audss_clk_resume(struct device *dev)
  57 {
  58         int i;
  59
  60         for (i = 0; i < ARRAY_SIZE(reg_save); i++)
  61                 writel(reg_save[i][1], reg_base + reg_save[i][0]);
  62
  63         return 0;
  64 }
  65 #endif /* CONFIG_PM_SLEEP */
  66
  67 struct exynos_audss_clk_drvdata {
  68         unsigned int has_adma_clk:1;
  69         unsigned int has_mst_clk:1;
  70         unsigned int enable_epll:1;
  71         unsigned int num_clks;
  72 };
  73
  74 static const struct exynos_audss_clk_drvdata exynos4210_drvdata = {
  75         .num_clks       = EXYNOS_AUDSS_MAX_CLKS - 1,
  76         .enable_epll    = 1,
  77 };
  78
  79 static const struct exynos_audss_clk_drvdata exynos5410_drvdata = {
  80         .num_clks       = EXYNOS_AUDSS_MAX_CLKS - 1,
  81         .has_mst_clk    = 1,
  82 };
  83
  84 static const struct exynos_audss_clk_drvdata exynos5420_drvdata = {
  85         .num_clks       = EXYNOS_AUDSS_MAX_CLKS,
  86         .has_adma_clk   = 1,
  87         .enable_epll    = 1,
  88 };
  89
  90 static const struct of_device_id exynos_audss_clk_of_match[] = {
  91         {
  92                 .compatible     = "samsung,exynos4210-audss-clock",
  93                 .data           = &exynos4210_drvdata,
  94         }, {
  95                 .compatible     = "samsung,exynos5250-audss-clock",
  96                 .data           = &exynos4210_drvdata,
  97         }, {
  98                 .compatible     = "samsung,exynos5410-audss-clock",
  99                 .data           = &exynos5410_drvdata,
 100         }, {
 101                 .compatible     = "samsung,exynos5420-audss-clock",
 102                 .data           = &exynos5420_drvdata,
 103         },
 104         { },
 105 };
 106 MODULE_DEVICE_TABLE(of, exynos_audss_clk_of_match);
 107
 108 static void exynos_audss_clk_teardown(void)
 109 {
 110         int i;
 111
 112         for (i = EXYNOS_MOUT_AUDSS; i < EXYNOS_DOUT_SRP; i++) {
 113                 if (!IS_ERR(clk_data->hws[i]))
 114                         clk_hw_unregister_mux(clk_data->hws[i]);
 115         }
 116
 117         for (; i < EXYNOS_SRP_CLK; i++) {
 118                 if (!IS_ERR(clk_data->hws[i]))
 119                         clk_hw_unregister_divider(clk_data->hws[i]);
 120         }
 121
 122         for (; i < clk_data->num; i++) {
 123                 if (!IS_ERR(clk_data->hws[i]))
 124                         clk_hw_unregister_gate(clk_data->hws[i]);
 125         }
 126 }
 127
 128 /* register exynos_audss clocks */
 129 static int exynos_audss_clk_probe(struct platform_device *pdev)
 130 {
 131         const char *mout_audss_p[] = {"fin_pll", "fout_epll"};
 132         const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"};
 133         const char *sclk_pcm_p = "sclk_pcm0";
 134         struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
 135         const struct exynos_audss_clk_drvdata *variant;
 136         struct clk_hw **clk_table;
 137         struct resource *res;
 138         int i, ret = 0;
 139
 140         variant = of_device_get_match_data(&pdev->dev);
 141         if (!variant)
 142                 return -EINVAL;
 143
 144         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 145         reg_base = devm_ioremap_resource(&pdev->dev, res);
 146         if (IS_ERR(reg_base)) {
 147                 dev_err(&pdev->dev, "failed to map audss registers\n");
 148                 return PTR_ERR(reg_base);
 149         }
 150
 151         epll = ERR_PTR(-ENODEV);
 152
 153         clk_data = devm_kzalloc(&pdev->dev,
 154                                 sizeof(*clk_data) +
 155                                 sizeof(*clk_data->hws) * EXYNOS_AUDSS_MAX_CLKS,
 156                                 GFP_KERNEL);
 157         if (!clk_data)
 158                 return -ENOMEM;
 159
 160         clk_data->num = variant->num_clks;
 161         clk_table = clk_data->hws;
 162
 163         pll_ref = devm_clk_get(&pdev->dev, "pll_ref");
 164         pll_in = devm_clk_get(&pdev->dev, "pll_in");
 165         if (!IS_ERR(pll_ref))
 166                 mout_audss_p[0] = __clk_get_name(pll_ref);
 167         if (!IS_ERR(pll_in)) {
 168                 mout_audss_p[1] = __clk_get_name(pll_in);
 169
 170                 if (variant->enable_epll) {
 171                         epll = pll_in;
 172
 173                         ret = clk_prepare_enable(epll);
 174                         if (ret) {
 175                                 dev_err(&pdev->dev,
 176                                         "failed to prepare the epll clock\n");
 177                                 return ret;
 178                         }
 179                 }
 180         }
 181         clk_table[EXYNOS_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss",
 182                                 mout_audss_p, ARRAY_SIZE(mout_audss_p),
 183                                 CLK_SET_RATE_NO_REPARENT,
 184                                 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
 185
 186         cdclk = devm_clk_get(&pdev->dev, "cdclk");
 187         sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio");
 188         if (!IS_ERR(cdclk))
 189                 mout_i2s_p[1] = __clk_get_name(cdclk);
 190         if (!IS_ERR(sclk_audio))
 191                 mout_i2s_p[2] = __clk_get_name(sclk_audio);
 192         clk_table[EXYNOS_MOUT_I2S] = clk_hw_register_mux(NULL, "mout_i2s",
 193                                 mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
 194                                 CLK_SET_RATE_NO_REPARENT,
 195                                 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
 196
 197         clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(NULL, "dout_srp",
 198                                 "mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4,
 199                                 0, &lock);
 200
 201         clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(NULL,
 202                                 "dout_aud_bus", "dout_srp", 0,
 203                                 reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
 204
 205         clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(NULL, "dout_i2s",
 206                                 "mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
 207                                 &lock);
 208
 209         clk_table[EXYNOS_SRP_CLK] = clk_hw_register_gate(NULL, "srp_clk",
 210                                 "dout_srp", CLK_SET_RATE_PARENT,
 211                                 reg_base + ASS_CLK_GATE, 0, 0, &lock);
 212
 213         clk_table[EXYNOS_I2S_BUS] = clk_hw_register_gate(NULL, "i2s_bus",
 214                                 "dout_aud_bus", CLK_SET_RATE_PARENT,
 215                                 reg_base + ASS_CLK_GATE, 2, 0, &lock);
 216
 217         clk_table[EXYNOS_SCLK_I2S] = clk_hw_register_gate(NULL, "sclk_i2s",
 218                                 "dout_i2s", CLK_SET_RATE_PARENT,
 219                                 reg_base + ASS_CLK_GATE, 3, 0, &lock);
 220
 221         clk_table[EXYNOS_PCM_BUS] = clk_hw_register_gate(NULL, "pcm_bus",
 222                                  "sclk_pcm", CLK_SET_RATE_PARENT,
 223                                 reg_base + ASS_CLK_GATE, 4, 0, &lock);
 224
 225         sclk_pcm_in = devm_clk_get(&pdev->dev, "sclk_pcm_in");
 226         if (!IS_ERR(sclk_pcm_in))
 227                 sclk_pcm_p = __clk_get_name(sclk_pcm_in);
 228         clk_table[EXYNOS_SCLK_PCM] = clk_hw_register_gate(NULL, "sclk_pcm",
 229                                 sclk_pcm_p, CLK_SET_RATE_PARENT,
 230                                 reg_base + ASS_CLK_GATE, 5, 0, &lock);
 231
 232         if (variant->has_adma_clk) {
 233                 clk_table[EXYNOS_ADMA] = clk_hw_register_gate(NULL, "adma",
 234                                 "dout_srp", CLK_SET_RATE_PARENT,
 235                                 reg_base + ASS_CLK_GATE, 9, 0, &lock);
 236         }
 237
 238         for (i = 0; i < clk_data->num; i++) {
 239                 if (IS_ERR(clk_table[i])) {
 240                         dev_err(&pdev->dev, "failed to register clock %d\n", i);
 241                         ret = PTR_ERR(clk_table[i]);
 242                         goto unregister;
 243                 }
 244         }
 245
 246         ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
 247                                      clk_data);
 248         if (ret) {
 249                 dev_err(&pdev->dev, "failed to add clock provider\n");
 250                 goto unregister;
 251         }
 252
 253         return 0;
 254
 255 unregister:
 256         exynos_audss_clk_teardown();
 257
 258         if (!IS_ERR(epll))
 259                 clk_disable_unprepare(epll);
 260
 261         return ret;
 262 }
 263
 264 static int exynos_audss_clk_remove(struct platform_device *pdev)
 265 {
 266         of_clk_del_provider(pdev->dev.of_node);
 267
 268         exynos_audss_clk_teardown();
 269
 270         if (!IS_ERR(epll))
 271                 clk_disable_unprepare(epll);
 272
 273         return 0;
 274 }
 275
 276 static const struct dev_pm_ops exynos_audss_clk_pm_ops = {
 277         SET_LATE_SYSTEM_SLEEP_PM_OPS(exynos_audss_clk_suspend,
 278                                      exynos_audss_clk_resume)
 279 };
 280
 281 static struct platform_driver exynos_audss_clk_driver = {
 282         .driver = {
 283                 .name = "exynos-audss-clk",
 284                 .of_match_table = exynos_audss_clk_of_match,
 285                 .pm = &exynos_audss_clk_pm_ops,
 286         },
 287         .probe = exynos_audss_clk_probe,
 288         .remove = exynos_audss_clk_remove,
 289 };
 290
 291 module_platform_driver(exynos_audss_clk_driver);
 292
 293 MODULE_AUTHOR("Padmavathi Venna <padma.v@samsung.com>");
 294 MODULE_DESCRIPTION("Exynos Audio Subsystem Clock Controller");
 295 MODULE_LICENSE("GPL v2");
 296 MODULE_ALIAS("platform:exynos-audss-clk");