1 // SPDX-License-Identifier: GPL-2.0
3 * (C) Copyright 2015 Google, Inc
4 * (C) 2017 Theobroma Systems Design und Consulting GmbH
8 #include <clk-uclass.h>
10 #include <dt-structs.h>
16 #include <asm/arch-rockchip/clock.h>
17 #include <asm/arch-rockchip/cru_rk3399.h>
18 #include <asm/arch-rockchip/hardware.h>
20 #include <dt-bindings/clock/rk3399-cru.h>
22 #if CONFIG_IS_ENABLED(OF_PLATDATA)
23 struct rk3399_clk_plat {
24 struct dtd_rockchip_rk3399_cru dtd;
27 struct rk3399_pmuclk_plat {
28 struct dtd_rockchip_rk3399_pmucru dtd;
40 #define RATE_TO_DIV(input_rate, output_rate) \
41 ((input_rate) / (output_rate) - 1)
42 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
44 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
46 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
47 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
49 #if defined(CONFIG_SPL_BUILD)
50 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
51 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
53 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
56 static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600 * MHz, 3, 1, 1);
57 static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
59 static const struct pll_div *apll_l_cfgs[] = {
60 [APLL_L_1600_MHZ] = &apll_l_1600_cfg,
61 [APLL_L_600_MHZ] = &apll_l_600_cfg,
64 static const struct pll_div apll_b_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
65 static const struct pll_div *apll_b_cfgs[] = {
66 [APLL_B_600_MHZ] = &apll_b_600_cfg,
71 PLL_FBDIV_MASK = 0xfff,
75 PLL_POSTDIV2_SHIFT = 12,
76 PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT,
77 PLL_POSTDIV1_SHIFT = 8,
78 PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT,
79 PLL_REFDIV_MASK = 0x3f,
83 PLL_LOCK_STATUS_SHIFT = 31,
84 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
85 PLL_FRACDIV_MASK = 0xffffff,
86 PLL_FRACDIV_SHIFT = 0,
90 PLL_MODE_MASK = 3 << PLL_MODE_SHIFT,
95 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
98 /* PMUCRU_CLKSEL_CON0 */
99 PMU_PCLK_DIV_CON_MASK = 0x1f,
100 PMU_PCLK_DIV_CON_SHIFT = 0,
102 /* PMUCRU_CLKSEL_CON1 */
103 SPI3_PLL_SEL_SHIFT = 7,
104 SPI3_PLL_SEL_MASK = 1 << SPI3_PLL_SEL_SHIFT,
105 SPI3_PLL_SEL_24M = 0,
106 SPI3_PLL_SEL_PPLL = 1,
107 SPI3_DIV_CON_SHIFT = 0x0,
108 SPI3_DIV_CON_MASK = 0x7f,
110 /* PMUCRU_CLKSEL_CON2 */
111 I2C_DIV_CON_MASK = 0x7f,
112 CLK_I2C8_DIV_CON_SHIFT = 8,
113 CLK_I2C0_DIV_CON_SHIFT = 0,
115 /* PMUCRU_CLKSEL_CON3 */
116 CLK_I2C4_DIV_CON_SHIFT = 0,
119 ACLKM_CORE_L_DIV_CON_SHIFT = 8,
120 ACLKM_CORE_L_DIV_CON_MASK = 0x1f << ACLKM_CORE_L_DIV_CON_SHIFT,
121 CLK_CORE_L_PLL_SEL_SHIFT = 6,
122 CLK_CORE_L_PLL_SEL_MASK = 3 << CLK_CORE_L_PLL_SEL_SHIFT,
123 CLK_CORE_L_PLL_SEL_ALPLL = 0x0,
124 CLK_CORE_L_PLL_SEL_ABPLL = 0x1,
125 CLK_CORE_L_PLL_SEL_DPLL = 0x10,
126 CLK_CORE_L_PLL_SEL_GPLL = 0x11,
127 CLK_CORE_L_DIV_MASK = 0x1f,
128 CLK_CORE_L_DIV_SHIFT = 0,
131 PCLK_DBG_L_DIV_SHIFT = 0x8,
132 PCLK_DBG_L_DIV_MASK = 0x1f << PCLK_DBG_L_DIV_SHIFT,
133 ATCLK_CORE_L_DIV_SHIFT = 0,
134 ATCLK_CORE_L_DIV_MASK = 0x1f << ATCLK_CORE_L_DIV_SHIFT,
137 ACLKM_CORE_B_DIV_CON_SHIFT = 8,
138 ACLKM_CORE_B_DIV_CON_MASK = 0x1f << ACLKM_CORE_B_DIV_CON_SHIFT,
139 CLK_CORE_B_PLL_SEL_SHIFT = 6,
140 CLK_CORE_B_PLL_SEL_MASK = 3 << CLK_CORE_B_PLL_SEL_SHIFT,
141 CLK_CORE_B_PLL_SEL_ALPLL = 0x0,
142 CLK_CORE_B_PLL_SEL_ABPLL = 0x1,
143 CLK_CORE_B_PLL_SEL_DPLL = 0x10,
144 CLK_CORE_B_PLL_SEL_GPLL = 0x11,
145 CLK_CORE_B_DIV_MASK = 0x1f,
146 CLK_CORE_B_DIV_SHIFT = 0,
149 PCLK_DBG_B_DIV_SHIFT = 0x8,
150 PCLK_DBG_B_DIV_MASK = 0x1f << PCLK_DBG_B_DIV_SHIFT,
151 ATCLK_CORE_B_DIV_SHIFT = 0,
152 ATCLK_CORE_B_DIV_MASK = 0x1f << ATCLK_CORE_B_DIV_SHIFT,
155 PCLK_PERIHP_DIV_CON_SHIFT = 12,
156 PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT,
157 HCLK_PERIHP_DIV_CON_SHIFT = 8,
158 HCLK_PERIHP_DIV_CON_MASK = 3 << HCLK_PERIHP_DIV_CON_SHIFT,
159 ACLK_PERIHP_PLL_SEL_SHIFT = 7,
160 ACLK_PERIHP_PLL_SEL_MASK = 1 << ACLK_PERIHP_PLL_SEL_SHIFT,
161 ACLK_PERIHP_PLL_SEL_CPLL = 0,
162 ACLK_PERIHP_PLL_SEL_GPLL = 1,
163 ACLK_PERIHP_DIV_CON_SHIFT = 0,
164 ACLK_PERIHP_DIV_CON_MASK = 0x1f,
167 ACLK_EMMC_PLL_SEL_SHIFT = 7,
168 ACLK_EMMC_PLL_SEL_MASK = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT,
169 ACLK_EMMC_PLL_SEL_GPLL = 0x1,
170 ACLK_EMMC_DIV_CON_SHIFT = 0,
171 ACLK_EMMC_DIV_CON_MASK = 0x1f,
174 CLK_EMMC_PLL_SHIFT = 8,
175 CLK_EMMC_PLL_MASK = 0x7 << CLK_EMMC_PLL_SHIFT,
176 CLK_EMMC_PLL_SEL_GPLL = 0x1,
177 CLK_EMMC_PLL_SEL_24M = 0x5,
178 CLK_EMMC_DIV_CON_SHIFT = 0,
179 CLK_EMMC_DIV_CON_MASK = 0x7f << CLK_EMMC_DIV_CON_SHIFT,
182 PCLK_PERILP0_DIV_CON_SHIFT = 12,
183 PCLK_PERILP0_DIV_CON_MASK = 0x7 << PCLK_PERILP0_DIV_CON_SHIFT,
184 HCLK_PERILP0_DIV_CON_SHIFT = 8,
185 HCLK_PERILP0_DIV_CON_MASK = 3 << HCLK_PERILP0_DIV_CON_SHIFT,
186 ACLK_PERILP0_PLL_SEL_SHIFT = 7,
187 ACLK_PERILP0_PLL_SEL_MASK = 1 << ACLK_PERILP0_PLL_SEL_SHIFT,
188 ACLK_PERILP0_PLL_SEL_CPLL = 0,
189 ACLK_PERILP0_PLL_SEL_GPLL = 1,
190 ACLK_PERILP0_DIV_CON_SHIFT = 0,
191 ACLK_PERILP0_DIV_CON_MASK = 0x1f,
194 PCLK_PERILP1_DIV_CON_SHIFT = 8,
195 PCLK_PERILP1_DIV_CON_MASK = 0x7 << PCLK_PERILP1_DIV_CON_SHIFT,
196 HCLK_PERILP1_PLL_SEL_SHIFT = 7,
197 HCLK_PERILP1_PLL_SEL_MASK = 1 << HCLK_PERILP1_PLL_SEL_SHIFT,
198 HCLK_PERILP1_PLL_SEL_CPLL = 0,
199 HCLK_PERILP1_PLL_SEL_GPLL = 1,
200 HCLK_PERILP1_DIV_CON_SHIFT = 0,
201 HCLK_PERILP1_DIV_CON_MASK = 0x1f,
204 CLK_SARADC_DIV_CON_SHIFT = 8,
205 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8),
206 CLK_SARADC_DIV_CON_WIDTH = 8,
209 CLK_TSADC_SEL_X24M = 0x0,
210 CLK_TSADC_SEL_SHIFT = 15,
211 CLK_TSADC_SEL_MASK = 1 << CLK_TSADC_SEL_SHIFT,
212 CLK_TSADC_DIV_CON_SHIFT = 0,
213 CLK_TSADC_DIV_CON_MASK = 0x3ff,
215 /* CLKSEL_CON47 & CLKSEL_CON48 */
216 ACLK_VOP_PLL_SEL_SHIFT = 6,
217 ACLK_VOP_PLL_SEL_MASK = 0x3 << ACLK_VOP_PLL_SEL_SHIFT,
218 ACLK_VOP_PLL_SEL_CPLL = 0x1,
219 ACLK_VOP_DIV_CON_SHIFT = 0,
220 ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT,
222 /* CLKSEL_CON49 & CLKSEL_CON50 */
223 DCLK_VOP_DCLK_SEL_SHIFT = 11,
224 DCLK_VOP_DCLK_SEL_MASK = 1 << DCLK_VOP_DCLK_SEL_SHIFT,
225 DCLK_VOP_DCLK_SEL_DIVOUT = 0,
226 DCLK_VOP_PLL_SEL_SHIFT = 8,
227 DCLK_VOP_PLL_SEL_MASK = 3 << DCLK_VOP_PLL_SEL_SHIFT,
228 DCLK_VOP_PLL_SEL_VPLL = 0,
229 DCLK_VOP_DIV_CON_MASK = 0xff,
230 DCLK_VOP_DIV_CON_SHIFT = 0,
233 CLK_SPI_PLL_SEL_WIDTH = 1,
234 CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1),
235 CLK_SPI_PLL_SEL_CPLL = 0,
236 CLK_SPI_PLL_SEL_GPLL = 1,
237 CLK_SPI_PLL_DIV_CON_WIDTH = 7,
238 CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1),
240 CLK_SPI5_PLL_DIV_CON_SHIFT = 8,
241 CLK_SPI5_PLL_SEL_SHIFT = 15,
244 CLK_SPI1_PLL_SEL_SHIFT = 15,
245 CLK_SPI1_PLL_DIV_CON_SHIFT = 8,
246 CLK_SPI0_PLL_SEL_SHIFT = 7,
247 CLK_SPI0_PLL_DIV_CON_SHIFT = 0,
250 CLK_SPI4_PLL_SEL_SHIFT = 15,
251 CLK_SPI4_PLL_DIV_CON_SHIFT = 8,
252 CLK_SPI2_PLL_SEL_SHIFT = 7,
253 CLK_SPI2_PLL_DIV_CON_SHIFT = 0,
256 CLK_I2C_PLL_SEL_MASK = 1,
257 CLK_I2C_PLL_SEL_CPLL = 0,
258 CLK_I2C_PLL_SEL_GPLL = 1,
259 CLK_I2C5_PLL_SEL_SHIFT = 15,
260 CLK_I2C5_DIV_CON_SHIFT = 8,
261 CLK_I2C1_PLL_SEL_SHIFT = 7,
262 CLK_I2C1_DIV_CON_SHIFT = 0,
265 CLK_I2C6_PLL_SEL_SHIFT = 15,
266 CLK_I2C6_DIV_CON_SHIFT = 8,
267 CLK_I2C2_PLL_SEL_SHIFT = 7,
268 CLK_I2C2_DIV_CON_SHIFT = 0,
271 CLK_I2C7_PLL_SEL_SHIFT = 15,
272 CLK_I2C7_DIV_CON_SHIFT = 8,
273 CLK_I2C3_PLL_SEL_SHIFT = 7,
274 CLK_I2C3_DIV_CON_SHIFT = 0,
276 /* CRU_SOFTRST_CON4 */
277 RESETN_DDR0_REQ_SHIFT = 8,
278 RESETN_DDR0_REQ_MASK = 1 << RESETN_DDR0_REQ_SHIFT,
279 RESETN_DDRPHY0_REQ_SHIFT = 9,
280 RESETN_DDRPHY0_REQ_MASK = 1 << RESETN_DDRPHY0_REQ_SHIFT,
281 RESETN_DDR1_REQ_SHIFT = 12,
282 RESETN_DDR1_REQ_MASK = 1 << RESETN_DDR1_REQ_SHIFT,
283 RESETN_DDRPHY1_REQ_SHIFT = 13,
284 RESETN_DDRPHY1_REQ_MASK = 1 << RESETN_DDRPHY1_REQ_SHIFT,
287 #define VCO_MAX_KHZ (3200 * (MHz / KHz))
288 #define VCO_MIN_KHZ (800 * (MHz / KHz))
289 #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz))
290 #define OUTPUT_MIN_KHZ (16 * (MHz / KHz))
293 * the div restructions of pll in integer mode, these are defined in
294 * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0
296 #define PLL_DIV_MIN 16
297 #define PLL_DIV_MAX 3200
300 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
301 * Formulas also embedded within the Fractional PLL Verilog model:
302 * If DSMPD = 1 (DSM is disabled, "integer mode")
303 * FOUTVCO = FREF / REFDIV * FBDIV
304 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
306 * FOUTVCO = Fractional PLL non-divided output frequency
307 * FOUTPOSTDIV = Fractional PLL divided output frequency
308 * (output of second post divider)
309 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
310 * REFDIV = Fractional PLL input reference clock divider
311 * FBDIV = Integer value programmed into feedback divide
314 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div)
316 /* All 8 PLLs have same VCO and output frequency range restrictions. */
317 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv;
318 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
320 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, "
321 "postdiv2=%d, vco=%u khz, output=%u khz\n",
322 pll_con, div->fbdiv, div->refdiv, div->postdiv1,
323 div->postdiv2, vco_khz, output_khz);
324 assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
325 output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ &&
326 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX);
329 * When power on or changing PLL setting,
330 * we must force PLL into slow mode to ensure output stable clock.
332 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
333 PLL_MODE_SLOW << PLL_MODE_SHIFT);
335 /* use integer mode */
336 rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK,
337 PLL_INTEGER_MODE << PLL_DSMPD_SHIFT);
339 rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK,
340 div->fbdiv << PLL_FBDIV_SHIFT);
341 rk_clrsetreg(&pll_con[1],
342 PLL_POSTDIV2_MASK | PLL_POSTDIV1_MASK |
343 PLL_REFDIV_MASK | PLL_REFDIV_SHIFT,
344 (div->postdiv2 << PLL_POSTDIV2_SHIFT) |
345 (div->postdiv1 << PLL_POSTDIV1_SHIFT) |
346 (div->refdiv << PLL_REFDIV_SHIFT));
348 /* waiting for pll lock */
349 while (!(readl(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT)))
352 /* pll enter normal mode */
353 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
354 PLL_MODE_NORM << PLL_MODE_SHIFT);
357 static int pll_para_config(u32 freq_hz, struct pll_div *div)
359 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0;
360 u32 postdiv1, postdiv2 = 1;
362 u32 diff_khz, best_diff_khz;
363 const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16;
364 const u32 max_postdiv1 = 7, max_postdiv2 = 7;
366 u32 freq_khz = freq_hz / KHz;
369 printf("%s: the frequency can't be 0 Hz\n", __func__);
373 postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
374 if (postdiv1 > max_postdiv1) {
375 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1);
376 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2);
379 vco_khz = freq_khz * postdiv1 * postdiv2;
381 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ ||
382 postdiv2 > max_postdiv2) {
383 printf("%s: Cannot find out a supported VCO"
384 " for Frequency (%uHz).\n", __func__, freq_hz);
388 div->postdiv1 = postdiv1;
389 div->postdiv2 = postdiv2;
391 best_diff_khz = vco_khz;
392 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) {
393 fref_khz = ref_khz / refdiv;
395 fbdiv = vco_khz / fref_khz;
396 if (fbdiv >= max_fbdiv || fbdiv <= min_fbdiv)
398 diff_khz = vco_khz - fbdiv * fref_khz;
399 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) {
401 diff_khz = fref_khz - diff_khz;
404 if (diff_khz >= best_diff_khz)
407 best_diff_khz = diff_khz;
408 div->refdiv = refdiv;
412 if (best_diff_khz > 4 * (MHz / KHz)) {
413 printf("%s: Failed to match output frequency %u, "
414 "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz,
415 best_diff_khz * KHz);
421 void rk3399_configure_cpu_l(struct rk3399_cru *cru,
422 enum apll_l_frequencies apll_l_freq)
428 /* Setup cluster L */
429 rkclk_set_pll(&cru->apll_l_con[0], apll_l_cfgs[apll_l_freq]);
431 aclkm_div = LPLL_HZ / ACLKM_CORE_L_HZ - 1;
432 assert((aclkm_div + 1) * ACLKM_CORE_L_HZ == LPLL_HZ &&
435 pclk_dbg_div = LPLL_HZ / PCLK_DBG_L_HZ - 1;
436 assert((pclk_dbg_div + 1) * PCLK_DBG_L_HZ == LPLL_HZ &&
437 pclk_dbg_div < 0x1f);
439 atclk_div = LPLL_HZ / ATCLK_CORE_L_HZ - 1;
440 assert((atclk_div + 1) * ATCLK_CORE_L_HZ == LPLL_HZ &&
443 rk_clrsetreg(&cru->clksel_con[0],
444 ACLKM_CORE_L_DIV_CON_MASK | CLK_CORE_L_PLL_SEL_MASK |
446 aclkm_div << ACLKM_CORE_L_DIV_CON_SHIFT |
447 CLK_CORE_L_PLL_SEL_ALPLL << CLK_CORE_L_PLL_SEL_SHIFT |
448 0 << CLK_CORE_L_DIV_SHIFT);
450 rk_clrsetreg(&cru->clksel_con[1],
451 PCLK_DBG_L_DIV_MASK | ATCLK_CORE_L_DIV_MASK,
452 pclk_dbg_div << PCLK_DBG_L_DIV_SHIFT |
453 atclk_div << ATCLK_CORE_L_DIV_SHIFT);
456 void rk3399_configure_cpu_b(struct rk3399_cru *cru,
457 enum apll_b_frequencies apll_b_freq)
463 /* Setup cluster B */
464 rkclk_set_pll(&cru->apll_b_con[0], apll_b_cfgs[apll_b_freq]);
466 aclkm_div = BPLL_HZ / ACLKM_CORE_B_HZ - 1;
467 assert((aclkm_div + 1) * ACLKM_CORE_B_HZ == BPLL_HZ &&
470 pclk_dbg_div = BPLL_HZ / PCLK_DBG_B_HZ - 1;
471 assert((pclk_dbg_div + 1) * PCLK_DBG_B_HZ == BPLL_HZ &&
472 pclk_dbg_div < 0x1f);
474 atclk_div = BPLL_HZ / ATCLK_CORE_B_HZ - 1;
475 assert((atclk_div + 1) * ATCLK_CORE_B_HZ == BPLL_HZ &&
478 rk_clrsetreg(&cru->clksel_con[2],
479 ACLKM_CORE_B_DIV_CON_MASK | CLK_CORE_B_PLL_SEL_MASK |
481 aclkm_div << ACLKM_CORE_B_DIV_CON_SHIFT |
482 CLK_CORE_B_PLL_SEL_ABPLL << CLK_CORE_B_PLL_SEL_SHIFT |
483 0 << CLK_CORE_B_DIV_SHIFT);
485 rk_clrsetreg(&cru->clksel_con[3],
486 PCLK_DBG_B_DIV_MASK | ATCLK_CORE_B_DIV_MASK,
487 pclk_dbg_div << PCLK_DBG_B_DIV_SHIFT |
488 atclk_div << ATCLK_CORE_B_DIV_SHIFT);
491 #define I2C_CLK_REG_MASK(bus) \
492 (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT | \
493 CLK_I2C_PLL_SEL_MASK << CLK_I2C ##bus## _PLL_SEL_SHIFT)
495 #define I2C_CLK_REG_VALUE(bus, clk_div) \
496 ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT | \
497 CLK_I2C_PLL_SEL_GPLL << CLK_I2C ##bus## _PLL_SEL_SHIFT)
499 #define I2C_CLK_DIV_VALUE(con, bus) \
500 ((con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & I2C_DIV_CON_MASK)
502 #define I2C_PMUCLK_REG_MASK(bus) \
503 (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT)
505 #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \
506 ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT)
508 static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id)
514 con = readl(&cru->clksel_con[61]);
515 div = I2C_CLK_DIV_VALUE(con, 1);
518 con = readl(&cru->clksel_con[62]);
519 div = I2C_CLK_DIV_VALUE(con, 2);
522 con = readl(&cru->clksel_con[63]);
523 div = I2C_CLK_DIV_VALUE(con, 3);
526 con = readl(&cru->clksel_con[61]);
527 div = I2C_CLK_DIV_VALUE(con, 5);
530 con = readl(&cru->clksel_con[62]);
531 div = I2C_CLK_DIV_VALUE(con, 6);
534 con = readl(&cru->clksel_con[63]);
535 div = I2C_CLK_DIV_VALUE(con, 7);
538 printf("do not support this i2c bus\n");
542 return DIV_TO_RATE(GPLL_HZ, div);
545 static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
549 /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/
550 src_clk_div = GPLL_HZ / hz;
551 assert(src_clk_div - 1 < 127);
555 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1),
556 I2C_CLK_REG_VALUE(1, src_clk_div));
559 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2),
560 I2C_CLK_REG_VALUE(2, src_clk_div));
563 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3),
564 I2C_CLK_REG_VALUE(3, src_clk_div));
567 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(5),
568 I2C_CLK_REG_VALUE(5, src_clk_div));
571 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(6),
572 I2C_CLK_REG_VALUE(6, src_clk_div));
575 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(7),
576 I2C_CLK_REG_VALUE(7, src_clk_div));
579 printf("do not support this i2c bus\n");
583 return rk3399_i2c_get_clk(cru, clk_id);
587 * RK3399 SPI clocks have a common divider-width (7 bits) and a single bit
588 * to select either CPLL or GPLL as the clock-parent. The location within
589 * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable.
593 u8 reg; /* CLKSEL_CON[reg] register in CRU */
599 * The entries are numbered relative to their offset from SCLK_SPI0.
601 * Note that SCLK_SPI3 (which is configured via PMUCRU and requires different
602 * logic is not supported).
604 static const struct spi_clkreg spi_clkregs[] = {
606 .div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT,
607 .sel_shift = CLK_SPI0_PLL_SEL_SHIFT, },
609 .div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT,
610 .sel_shift = CLK_SPI1_PLL_SEL_SHIFT, },
612 .div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT,
613 .sel_shift = CLK_SPI2_PLL_SEL_SHIFT, },
615 .div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT,
616 .sel_shift = CLK_SPI4_PLL_SEL_SHIFT, },
618 .div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT,
619 .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, },
622 static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id)
624 const struct spi_clkreg *spiclk = NULL;
628 case SCLK_SPI0 ... SCLK_SPI5:
629 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
633 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
637 val = readl(&cru->clksel_con[spiclk->reg]);
638 div = bitfield_extract(val, spiclk->div_shift,
639 CLK_SPI_PLL_DIV_CON_WIDTH);
641 return DIV_TO_RATE(GPLL_HZ, div);
644 static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
646 const struct spi_clkreg *spiclk = NULL;
649 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
650 assert(src_clk_div < 128);
653 case SCLK_SPI1 ... SCLK_SPI5:
654 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
658 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
662 rk_clrsetreg(&cru->clksel_con[spiclk->reg],
663 ((CLK_SPI_PLL_DIV_CON_MASK << spiclk->div_shift) |
664 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)),
665 ((src_clk_div << spiclk->div_shift) |
666 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)));
668 return rk3399_spi_get_clk(cru, clk_id);
671 static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)
673 struct pll_div vpll_config = {0};
674 int aclk_vop = 198 * MHz;
675 void *aclkreg_addr, *dclkreg_addr;
680 aclkreg_addr = &cru->clksel_con[47];
681 dclkreg_addr = &cru->clksel_con[49];
684 aclkreg_addr = &cru->clksel_con[48];
685 dclkreg_addr = &cru->clksel_con[50];
690 /* vop aclk source clk: cpll */
691 div = CPLL_HZ / aclk_vop;
692 assert(div - 1 < 32);
694 rk_clrsetreg(aclkreg_addr,
695 ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK,
696 ACLK_VOP_PLL_SEL_CPLL << ACLK_VOP_PLL_SEL_SHIFT |
697 (div - 1) << ACLK_VOP_DIV_CON_SHIFT);
699 /* vop dclk source from vpll, and equals to vpll(means div == 1) */
700 if (pll_para_config(hz, &vpll_config))
703 rkclk_set_pll(&cru->vpll_con[0], &vpll_config);
705 rk_clrsetreg(dclkreg_addr,
706 DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK |
707 DCLK_VOP_DIV_CON_MASK,
708 DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT |
709 DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT |
710 (1 - 1) << DCLK_VOP_DIV_CON_SHIFT);
715 static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id)
722 con = readl(&cru->clksel_con[16]);
723 /* dwmmc controller have internal div 2 */
727 con = readl(&cru->clksel_con[21]);
734 div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
735 if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
736 == CLK_EMMC_PLL_SEL_24M)
737 return DIV_TO_RATE(OSC_HZ, div);
739 return DIV_TO_RATE(GPLL_HZ, div);
742 static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
743 ulong clk_id, ulong set_rate)
746 int aclk_emmc = 198 * MHz;
751 /* Select clk_sdmmc source from GPLL by default */
752 /* mmc clock defaulg div 2 internal, provide double in cru */
753 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);
755 if (src_clk_div > 128) {
756 /* use 24MHz source for 400KHz clock */
757 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
758 assert(src_clk_div - 1 < 128);
759 rk_clrsetreg(&cru->clksel_con[16],
760 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
761 CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
762 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
764 rk_clrsetreg(&cru->clksel_con[16],
765 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
766 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
767 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
771 /* Select aclk_emmc source from GPLL */
772 src_clk_div = DIV_ROUND_UP(GPLL_HZ, aclk_emmc);
773 assert(src_clk_div - 1 < 32);
775 rk_clrsetreg(&cru->clksel_con[21],
776 ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK,
777 ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT |
778 (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT);
780 /* Select clk_emmc source from GPLL too */
781 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate);
782 assert(src_clk_div - 1 < 128);
784 rk_clrsetreg(&cru->clksel_con[22],
785 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
786 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
787 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
792 return rk3399_mmc_get_clk(cru, clk_id);
795 static ulong rk3399_gmac_set_clk(struct rk3399_cru *cru, ulong rate)
800 * The RGMII CLK can be derived either from an external "clkin"
801 * or can be generated from internally by a divider from SCLK_MAC.
803 if (readl(&cru->clksel_con[19]) & BIT(4)) {
804 /* An external clock will always generate the right rate... */
808 * No platform uses an internal clock to date.
809 * Implement this once it becomes necessary and print an error
810 * if someone tries to use it (while it remains unimplemented).
812 pr_err("%s: internal clock is UNIMPLEMENTED\n", __func__);
819 #define PMUSGRF_DDR_RGN_CON16 0xff330040
820 static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
823 struct pll_div dpll_cfg;
825 /* IC ECO bug, need to set this register */
826 writel(0xc000c000, PMUSGRF_DDR_RGN_CON16);
828 /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
831 dpll_cfg = (struct pll_div)
832 {.refdiv = 1, .fbdiv = 12, .postdiv1 = 3, .postdiv2 = 2};
835 dpll_cfg = (struct pll_div)
836 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1};
839 dpll_cfg = (struct pll_div)
840 {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1};
843 dpll_cfg = (struct pll_div)
844 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
847 dpll_cfg = (struct pll_div)
848 {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1};
851 dpll_cfg = (struct pll_div)
852 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
855 dpll_cfg = (struct pll_div)
856 {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1};
859 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate);
861 rkclk_set_pll(&cru->dpll_con[0], &dpll_cfg);
866 static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru)
870 val = readl(&cru->clksel_con[26]);
871 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
872 CLK_SARADC_DIV_CON_WIDTH);
874 return DIV_TO_RATE(OSC_HZ, div);
877 static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz)
881 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
882 assert(src_clk_div < 128);
884 rk_clrsetreg(&cru->clksel_con[26],
885 CLK_SARADC_DIV_CON_MASK,
886 src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
888 return rk3399_saradc_get_clk(cru);
891 static ulong rk3399_clk_get_rate(struct clk *clk)
893 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
902 rate = rk3399_mmc_get_clk(priv->cru, clk->id);
910 rate = rk3399_i2c_get_clk(priv->cru, clk->id);
912 case SCLK_SPI0...SCLK_SPI5:
913 rate = rk3399_spi_get_clk(priv->cru, clk->id);
925 case PCLK_EFUSE1024NS:
928 rate = rk3399_saradc_get_clk(priv->cru);
936 log_debug("Unknown clock %lu\n", clk->id);
943 static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
945 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
972 ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate);
975 ret = rk3399_gmac_set_clk(priv->cru, rate);
983 ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate);
985 case SCLK_SPI0...SCLK_SPI5:
986 ret = rk3399_spi_set_clk(priv->cru, clk->id, rate);
990 /* the PCLK gates for video are enabled by default */
994 ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);
997 ret = rk3399_ddr_set_clk(priv->cru, rate);
999 case PCLK_EFUSE1024NS:
1002 ret = rk3399_saradc_set_clk(priv->cru, rate);
1010 log_debug("Unknown clock %lu\n", clk->id);
1017 static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk,
1020 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
1021 const char *clock_output_name;
1025 * If the requested parent is in the same clock-controller and
1026 * the id is SCLK_MAC ("clk_gmac"), switch to the internal clock.
1028 if (parent->dev == clk->dev && parent->id == SCLK_MAC) {
1029 debug("%s: switching RGMII to SCLK_MAC\n", __func__);
1030 rk_clrreg(&priv->cru->clksel_con[19], BIT(4));
1035 * Otherwise, we need to check the clock-output-names of the
1036 * requested parent to see if the requested id is "clkin_gmac".
1038 ret = dev_read_string_index(parent->dev, "clock-output-names",
1039 parent->id, &clock_output_name);
1043 /* If this is "clkin_gmac", switch to the external clock input */
1044 if (!strcmp(clock_output_name, "clkin_gmac")) {
1045 debug("%s: switching RGMII to CLKIN\n", __func__);
1046 rk_setreg(&priv->cru->clksel_con[19], BIT(4));
1053 static int __maybe_unused rk3399_clk_set_parent(struct clk *clk,
1058 return rk3399_gmac_set_parent(clk, parent);
1061 debug("%s: unsupported clk %ld\n", __func__, clk->id);
1065 static struct clk_ops rk3399_clk_ops = {
1066 .get_rate = rk3399_clk_get_rate,
1067 .set_rate = rk3399_clk_set_rate,
1068 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1069 .set_parent = rk3399_clk_set_parent,
1073 #ifdef CONFIG_SPL_BUILD
1074 static void rkclk_init(struct rk3399_cru *cru)
1080 rk3399_configure_cpu_l(cru, APLL_L_600_MHZ);
1081 rk3399_configure_cpu_b(cru, APLL_B_600_MHZ);
1083 * some cru registers changed by bootrom, we'd better reset them to
1084 * reset/default values described in TRM to avoid confusion in kernel.
1085 * Please consider these three lines as a fix of bootrom bug.
1087 rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101);
1088 rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f);
1089 rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003);
1091 /* configure gpll cpll */
1092 rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg);
1093 rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg);
1095 /* configure perihp aclk, hclk, pclk */
1096 aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
1097 assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
1099 hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
1100 assert((hclk_div + 1) * PERIHP_HCLK_HZ ==
1101 PERIHP_ACLK_HZ && (hclk_div < 0x4));
1103 pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
1104 assert((pclk_div + 1) * PERIHP_PCLK_HZ ==
1105 PERIHP_ACLK_HZ && (pclk_div < 0x7));
1107 rk_clrsetreg(&cru->clksel_con[14],
1108 PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK |
1109 ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK,
1110 pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
1111 hclk_div << HCLK_PERIHP_DIV_CON_SHIFT |
1112 ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT |
1113 aclk_div << ACLK_PERIHP_DIV_CON_SHIFT);
1115 /* configure perilp0 aclk, hclk, pclk */
1116 aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1;
1117 assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
1119 hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1;
1120 assert((hclk_div + 1) * PERILP0_HCLK_HZ ==
1121 PERILP0_ACLK_HZ && (hclk_div < 0x4));
1123 pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1;
1124 assert((pclk_div + 1) * PERILP0_PCLK_HZ ==
1125 PERILP0_ACLK_HZ && (pclk_div < 0x7));
1127 rk_clrsetreg(&cru->clksel_con[23],
1128 PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK |
1129 ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK,
1130 pclk_div << PCLK_PERILP0_DIV_CON_SHIFT |
1131 hclk_div << HCLK_PERILP0_DIV_CON_SHIFT |
1132 ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT |
1133 aclk_div << ACLK_PERILP0_DIV_CON_SHIFT);
1135 /* perilp1 hclk select gpll as source */
1136 hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1;
1137 assert((hclk_div + 1) * PERILP1_HCLK_HZ ==
1138 GPLL_HZ && (hclk_div < 0x1f));
1140 pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1;
1141 assert((pclk_div + 1) * PERILP1_HCLK_HZ ==
1142 PERILP1_HCLK_HZ && (hclk_div < 0x7));
1144 rk_clrsetreg(&cru->clksel_con[25],
1145 PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK |
1146 HCLK_PERILP1_PLL_SEL_MASK,
1147 pclk_div << PCLK_PERILP1_DIV_CON_SHIFT |
1148 hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
1149 HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
1153 static int rk3399_clk_probe(struct udevice *dev)
1155 #ifdef CONFIG_SPL_BUILD
1156 struct rk3399_clk_priv *priv = dev_get_priv(dev);
1158 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1159 struct rk3399_clk_plat *plat = dev_get_platdata(dev);
1161 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
1163 rkclk_init(priv->cru);
1168 static int rk3399_clk_ofdata_to_platdata(struct udevice *dev)
1170 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1171 struct rk3399_clk_priv *priv = dev_get_priv(dev);
1173 priv->cru = dev_read_addr_ptr(dev);
1178 static int rk3399_clk_bind(struct udevice *dev)
1181 struct udevice *sys_child;
1182 struct sysreset_reg *priv;
1184 /* The reset driver does not have a device node, so bind it here */
1185 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
1188 debug("Warning: No sysreset driver: ret=%d\n", ret);
1190 priv = malloc(sizeof(struct sysreset_reg));
1191 priv->glb_srst_fst_value = offsetof(struct rk3399_cru,
1192 glb_srst_fst_value);
1193 priv->glb_srst_snd_value = offsetof(struct rk3399_cru,
1194 glb_srst_snd_value);
1195 sys_child->priv = priv;
1198 #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
1199 ret = offsetof(struct rk3399_cru, softrst_con[0]);
1200 ret = rockchip_reset_bind(dev, ret, 21);
1202 debug("Warning: software reset driver bind faile\n");
1208 static const struct udevice_id rk3399_clk_ids[] = {
1209 { .compatible = "rockchip,rk3399-cru" },
1213 U_BOOT_DRIVER(clk_rk3399) = {
1214 .name = "rockchip_rk3399_cru",
1216 .of_match = rk3399_clk_ids,
1217 .priv_auto_alloc_size = sizeof(struct rk3399_clk_priv),
1218 .ofdata_to_platdata = rk3399_clk_ofdata_to_platdata,
1219 .ops = &rk3399_clk_ops,
1220 .bind = rk3399_clk_bind,
1221 .probe = rk3399_clk_probe,
1222 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1223 .platdata_auto_alloc_size = sizeof(struct rk3399_clk_plat),
1227 static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id)
1233 con = readl(&pmucru->pmucru_clksel[2]);
1234 div = I2C_CLK_DIV_VALUE(con, 0);
1237 con = readl(&pmucru->pmucru_clksel[3]);
1238 div = I2C_CLK_DIV_VALUE(con, 4);
1241 con = readl(&pmucru->pmucru_clksel[2]);
1242 div = I2C_CLK_DIV_VALUE(con, 8);
1245 printf("do not support this i2c bus\n");
1249 return DIV_TO_RATE(PPLL_HZ, div);
1252 static ulong rk3399_i2c_set_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id,
1257 src_clk_div = PPLL_HZ / hz;
1258 assert(src_clk_div - 1 < 127);
1262 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(0),
1263 I2C_PMUCLK_REG_VALUE(0, src_clk_div));
1266 rk_clrsetreg(&pmucru->pmucru_clksel[3], I2C_PMUCLK_REG_MASK(4),
1267 I2C_PMUCLK_REG_VALUE(4, src_clk_div));
1270 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(8),
1271 I2C_PMUCLK_REG_VALUE(8, src_clk_div));
1274 printf("do not support this i2c bus\n");
1278 return DIV_TO_RATE(PPLL_HZ, src_clk_div);
1281 static ulong rk3399_pwm_get_clk(struct rk3399_pmucru *pmucru)
1285 /* PWM closk rate is same as pclk_pmu */
1286 con = readl(&pmucru->pmucru_clksel[0]);
1287 div = con & PMU_PCLK_DIV_CON_MASK;
1289 return DIV_TO_RATE(PPLL_HZ, div);
1292 static ulong rk3399_pmuclk_get_rate(struct clk *clk)
1294 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
1300 case PCLK_RKPWM_PMU:
1301 rate = rk3399_pwm_get_clk(priv->pmucru);
1306 rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id);
1315 static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate)
1317 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
1323 * This has already been set up and we don't want/need
1324 * to change it here. Accept the request though, as the
1325 * device-tree has this in an 'assigned-clocks' list.
1331 ret = rk3399_i2c_set_pmuclk(priv->pmucru, clk->id, rate);
1340 static struct clk_ops rk3399_pmuclk_ops = {
1341 .get_rate = rk3399_pmuclk_get_rate,
1342 .set_rate = rk3399_pmuclk_set_rate,
1345 #ifndef CONFIG_SPL_BUILD
1346 static void pmuclk_init(struct rk3399_pmucru *pmucru)
1350 /* configure pmu pll(ppll) */
1351 rkclk_set_pll(&pmucru->ppll_con[0], &ppll_init_cfg);
1353 /* configure pmu pclk */
1354 pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1;
1355 rk_clrsetreg(&pmucru->pmucru_clksel[0],
1356 PMU_PCLK_DIV_CON_MASK,
1357 pclk_div << PMU_PCLK_DIV_CON_SHIFT);
1361 static int rk3399_pmuclk_probe(struct udevice *dev)
1363 #if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD)
1364 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
1367 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1368 struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev);
1370 priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
1373 #ifndef CONFIG_SPL_BUILD
1374 pmuclk_init(priv->pmucru);
1379 static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev)
1381 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1382 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
1384 priv->pmucru = dev_read_addr_ptr(dev);
1389 static int rk3399_pmuclk_bind(struct udevice *dev)
1391 #if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
1394 ret = offsetof(struct rk3399_pmucru, pmucru_softrst_con[0]);
1395 ret = rockchip_reset_bind(dev, ret, 2);
1397 debug("Warning: software reset driver bind faile\n");
1402 static const struct udevice_id rk3399_pmuclk_ids[] = {
1403 { .compatible = "rockchip,rk3399-pmucru" },
1407 U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = {
1408 .name = "rockchip_rk3399_pmucru",
1410 .of_match = rk3399_pmuclk_ids,
1411 .priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv),
1412 .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata,
1413 .ops = &rk3399_pmuclk_ops,
1414 .probe = rk3399_pmuclk_probe,
1415 .bind = rk3399_pmuclk_bind,
1416 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1417 .platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat),