drivers/clk/rockchip/clk_rk3399.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * (C) Copyright 2015 Google, Inc
   4  * (C) 2017 Theobroma Systems Design und Consulting GmbH
   5  */
   6
   7 #include <common.h>
   8 #include <clk-uclass.h>
   9 #include <dm.h>
  10 #include <dt-structs.h>
  11 #include <errno.h>
  12 #include <log.h>
  13 #include <malloc.h>
  14 #include <mapmem.h>
  15 #include <syscon.h>
  16 #include <bitfield.h>
  17 #include <asm/io.h>
  18 #include <asm/arch-rockchip/clock.h>
  19 #include <asm/arch-rockchip/cru.h>
  20 #include <asm/arch-rockchip/hardware.h>
  21 #include <dm/lists.h>
  22 #include <dt-bindings/clock/rk3399-cru.h>
  23 #include <linux/bitops.h>
  24 #include <linux/delay.h>
  25
  26 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  27 struct rk3399_clk_plat {
  28         struct dtd_rockchip_rk3399_cru dtd;
  29 };
  30
  31 struct rk3399_pmuclk_plat {
  32         struct dtd_rockchip_rk3399_pmucru dtd;
  33 };
  34 #endif
  35
  36 struct pll_div {
  37         u32 refdiv;
  38         u32 fbdiv;
  39         u32 postdiv1;
  40         u32 postdiv2;
  41         u32 frac;
  42 };
  43
  44 #define RATE_TO_DIV(input_rate, output_rate) \
  45         ((input_rate) / (output_rate) - 1)
  46 #define DIV_TO_RATE(input_rate, div)            ((input_rate) / ((div) + 1))
  47
  48 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
  49         .refdiv = _refdiv,\
  50         .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
  51         .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
  52
  53 #if defined(CONFIG_SPL_BUILD)
  54 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
  55 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
  56 #else
  57 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
  58 #endif
  59
  60 static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600 * MHz, 3, 1, 1);
  61 static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
  62
  63 static const struct pll_div *apll_l_cfgs[] = {
  64         [APLL_L_1600_MHZ] = &apll_l_1600_cfg,
  65         [APLL_L_600_MHZ] = &apll_l_600_cfg,
  66 };
  67
  68 static const struct pll_div apll_b_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
  69 static const struct pll_div *apll_b_cfgs[] = {
  70         [APLL_B_600_MHZ] = &apll_b_600_cfg,
  71 };
  72
  73 enum {
  74         /* PLL_CON0 */
  75         PLL_FBDIV_MASK                  = 0xfff,
  76         PLL_FBDIV_SHIFT                 = 0,
  77
  78         /* PLL_CON1 */
  79         PLL_POSTDIV2_SHIFT              = 12,
  80         PLL_POSTDIV2_MASK               = 0x7 << PLL_POSTDIV2_SHIFT,
  81         PLL_POSTDIV1_SHIFT              = 8,
  82         PLL_POSTDIV1_MASK               = 0x7 << PLL_POSTDIV1_SHIFT,
  83         PLL_REFDIV_MASK                 = 0x3f,
  84         PLL_REFDIV_SHIFT                = 0,
  85
  86         /* PLL_CON2 */
  87         PLL_LOCK_STATUS_SHIFT           = 31,
  88         PLL_LOCK_STATUS_MASK            = 1 << PLL_LOCK_STATUS_SHIFT,
  89         PLL_FRACDIV_MASK                = 0xffffff,
  90         PLL_FRACDIV_SHIFT               = 0,
  91
  92         /* PLL_CON3 */
  93         PLL_MODE_SHIFT                  = 8,
  94         PLL_MODE_MASK                   = 3 << PLL_MODE_SHIFT,
  95         PLL_MODE_SLOW                   = 0,
  96         PLL_MODE_NORM,
  97         PLL_MODE_DEEP,
  98         PLL_DSMPD_SHIFT                 = 3,
  99         PLL_DSMPD_MASK                  = 1 << PLL_DSMPD_SHIFT,
 100         PLL_INTEGER_MODE                = 1,
 101
 102         /* PMUCRU_CLKSEL_CON0 */
 103         PMU_PCLK_DIV_CON_MASK           = 0x1f,
 104         PMU_PCLK_DIV_CON_SHIFT          = 0,
 105
 106         /* PMUCRU_CLKSEL_CON1 */
 107         SPI3_PLL_SEL_SHIFT              = 7,
 108         SPI3_PLL_SEL_MASK               = 1 << SPI3_PLL_SEL_SHIFT,
 109         SPI3_PLL_SEL_24M                = 0,
 110         SPI3_PLL_SEL_PPLL               = 1,
 111         SPI3_DIV_CON_SHIFT              = 0x0,
 112         SPI3_DIV_CON_MASK               = 0x7f,
 113
 114         /* PMUCRU_CLKSEL_CON2 */
 115         I2C_DIV_CON_MASK                = 0x7f,
 116         CLK_I2C8_DIV_CON_SHIFT          = 8,
 117         CLK_I2C0_DIV_CON_SHIFT          = 0,
 118
 119         /* PMUCRU_CLKSEL_CON3 */
 120         CLK_I2C4_DIV_CON_SHIFT          = 0,
 121
 122         /* CLKSEL_CON0 */
 123         ACLKM_CORE_L_DIV_CON_SHIFT      = 8,
 124         ACLKM_CORE_L_DIV_CON_MASK       = 0x1f << ACLKM_CORE_L_DIV_CON_SHIFT,
 125         CLK_CORE_L_PLL_SEL_SHIFT        = 6,
 126         CLK_CORE_L_PLL_SEL_MASK         = 3 << CLK_CORE_L_PLL_SEL_SHIFT,
 127         CLK_CORE_L_PLL_SEL_ALPLL        = 0x0,
 128         CLK_CORE_L_PLL_SEL_ABPLL        = 0x1,
 129         CLK_CORE_L_PLL_SEL_DPLL         = 0x10,
 130         CLK_CORE_L_PLL_SEL_GPLL         = 0x11,
 131         CLK_CORE_L_DIV_MASK             = 0x1f,
 132         CLK_CORE_L_DIV_SHIFT            = 0,
 133
 134         /* CLKSEL_CON1 */
 135         PCLK_DBG_L_DIV_SHIFT            = 0x8,
 136         PCLK_DBG_L_DIV_MASK             = 0x1f << PCLK_DBG_L_DIV_SHIFT,
 137         ATCLK_CORE_L_DIV_SHIFT          = 0,
 138         ATCLK_CORE_L_DIV_MASK           = 0x1f << ATCLK_CORE_L_DIV_SHIFT,
 139
 140         /* CLKSEL_CON2 */
 141         ACLKM_CORE_B_DIV_CON_SHIFT      = 8,
 142         ACLKM_CORE_B_DIV_CON_MASK       = 0x1f << ACLKM_CORE_B_DIV_CON_SHIFT,
 143         CLK_CORE_B_PLL_SEL_SHIFT        = 6,
 144         CLK_CORE_B_PLL_SEL_MASK         = 3 << CLK_CORE_B_PLL_SEL_SHIFT,
 145         CLK_CORE_B_PLL_SEL_ALPLL        = 0x0,
 146         CLK_CORE_B_PLL_SEL_ABPLL        = 0x1,
 147         CLK_CORE_B_PLL_SEL_DPLL         = 0x10,
 148         CLK_CORE_B_PLL_SEL_GPLL         = 0x11,
 149         CLK_CORE_B_DIV_MASK             = 0x1f,
 150         CLK_CORE_B_DIV_SHIFT            = 0,
 151
 152         /* CLKSEL_CON3 */
 153         PCLK_DBG_B_DIV_SHIFT            = 0x8,
 154         PCLK_DBG_B_DIV_MASK             = 0x1f << PCLK_DBG_B_DIV_SHIFT,
 155         ATCLK_CORE_B_DIV_SHIFT          = 0,
 156         ATCLK_CORE_B_DIV_MASK           = 0x1f << ATCLK_CORE_B_DIV_SHIFT,
 157
 158         /* CLKSEL_CON14 */
 159         PCLK_PERIHP_DIV_CON_SHIFT       = 12,
 160         PCLK_PERIHP_DIV_CON_MASK        = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT,
 161         HCLK_PERIHP_DIV_CON_SHIFT       = 8,
 162         HCLK_PERIHP_DIV_CON_MASK        = 3 << HCLK_PERIHP_DIV_CON_SHIFT,
 163         ACLK_PERIHP_PLL_SEL_SHIFT       = 7,
 164         ACLK_PERIHP_PLL_SEL_MASK        = 1 << ACLK_PERIHP_PLL_SEL_SHIFT,
 165         ACLK_PERIHP_PLL_SEL_CPLL        = 0,
 166         ACLK_PERIHP_PLL_SEL_GPLL        = 1,
 167         ACLK_PERIHP_DIV_CON_SHIFT       = 0,
 168         ACLK_PERIHP_DIV_CON_MASK        = 0x1f,
 169
 170         /* CLKSEL_CON21 */
 171         ACLK_EMMC_PLL_SEL_SHIFT         = 7,
 172         ACLK_EMMC_PLL_SEL_MASK          = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT,
 173         ACLK_EMMC_PLL_SEL_GPLL          = 0x1,
 174         ACLK_EMMC_DIV_CON_SHIFT         = 0,
 175         ACLK_EMMC_DIV_CON_MASK          = 0x1f,
 176
 177         /* CLKSEL_CON22 */
 178         CLK_EMMC_PLL_SHIFT              = 8,
 179         CLK_EMMC_PLL_MASK               = 0x7 << CLK_EMMC_PLL_SHIFT,
 180         CLK_EMMC_PLL_SEL_GPLL           = 0x1,
 181         CLK_EMMC_PLL_SEL_24M            = 0x5,
 182         CLK_EMMC_DIV_CON_SHIFT          = 0,
 183         CLK_EMMC_DIV_CON_MASK           = 0x7f << CLK_EMMC_DIV_CON_SHIFT,
 184
 185         /* CLKSEL_CON23 */
 186         PCLK_PERILP0_DIV_CON_SHIFT      = 12,
 187         PCLK_PERILP0_DIV_CON_MASK       = 0x7 << PCLK_PERILP0_DIV_CON_SHIFT,
 188         HCLK_PERILP0_DIV_CON_SHIFT      = 8,
 189         HCLK_PERILP0_DIV_CON_MASK       = 3 << HCLK_PERILP0_DIV_CON_SHIFT,
 190         ACLK_PERILP0_PLL_SEL_SHIFT      = 7,
 191         ACLK_PERILP0_PLL_SEL_MASK       = 1 << ACLK_PERILP0_PLL_SEL_SHIFT,
 192         ACLK_PERILP0_PLL_SEL_CPLL       = 0,
 193         ACLK_PERILP0_PLL_SEL_GPLL       = 1,
 194         ACLK_PERILP0_DIV_CON_SHIFT      = 0,
 195         ACLK_PERILP0_DIV_CON_MASK       = 0x1f,
 196
 197         /* CLKSEL_CON25 */
 198         PCLK_PERILP1_DIV_CON_SHIFT      = 8,
 199         PCLK_PERILP1_DIV_CON_MASK       = 0x7 << PCLK_PERILP1_DIV_CON_SHIFT,
 200         HCLK_PERILP1_PLL_SEL_SHIFT      = 7,
 201         HCLK_PERILP1_PLL_SEL_MASK       = 1 << HCLK_PERILP1_PLL_SEL_SHIFT,
 202         HCLK_PERILP1_PLL_SEL_CPLL       = 0,
 203         HCLK_PERILP1_PLL_SEL_GPLL       = 1,
 204         HCLK_PERILP1_DIV_CON_SHIFT      = 0,
 205         HCLK_PERILP1_DIV_CON_MASK       = 0x1f,
 206
 207         /* CLKSEL_CON26 */
 208         CLK_SARADC_DIV_CON_SHIFT        = 8,
 209         CLK_SARADC_DIV_CON_MASK         = GENMASK(15, 8),
 210         CLK_SARADC_DIV_CON_WIDTH        = 8,
 211
 212         /* CLKSEL_CON27 */
 213         CLK_TSADC_SEL_X24M              = 0x0,
 214         CLK_TSADC_SEL_SHIFT             = 15,
 215         CLK_TSADC_SEL_MASK              = 1 << CLK_TSADC_SEL_SHIFT,
 216         CLK_TSADC_DIV_CON_SHIFT         = 0,
 217         CLK_TSADC_DIV_CON_MASK          = 0x3ff,
 218
 219         /* CLKSEL_CON47 & CLKSEL_CON48 */
 220         ACLK_VOP_PLL_SEL_SHIFT          = 6,
 221         ACLK_VOP_PLL_SEL_MASK           = 0x3 << ACLK_VOP_PLL_SEL_SHIFT,
 222         ACLK_VOP_PLL_SEL_CPLL           = 0x1,
 223         ACLK_VOP_DIV_CON_SHIFT          = 0,
 224         ACLK_VOP_DIV_CON_MASK           = 0x1f << ACLK_VOP_DIV_CON_SHIFT,
 225
 226         /* CLKSEL_CON49 & CLKSEL_CON50 */
 227         DCLK_VOP_DCLK_SEL_SHIFT         = 11,
 228         DCLK_VOP_DCLK_SEL_MASK          = 1 << DCLK_VOP_DCLK_SEL_SHIFT,
 229         DCLK_VOP_DCLK_SEL_DIVOUT        = 0,
 230         DCLK_VOP_PLL_SEL_SHIFT          = 8,
 231         DCLK_VOP_PLL_SEL_MASK           = 3 << DCLK_VOP_PLL_SEL_SHIFT,
 232         DCLK_VOP_PLL_SEL_VPLL           = 0,
 233         DCLK_VOP_DIV_CON_MASK           = 0xff,
 234         DCLK_VOP_DIV_CON_SHIFT          = 0,
 235
 236         /* CLKSEL_CON58 */
 237         CLK_SPI_PLL_SEL_WIDTH = 1,
 238         CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1),
 239         CLK_SPI_PLL_SEL_CPLL = 0,
 240         CLK_SPI_PLL_SEL_GPLL = 1,
 241         CLK_SPI_PLL_DIV_CON_WIDTH = 7,
 242         CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1),
 243
 244         CLK_SPI5_PLL_DIV_CON_SHIFT      = 8,
 245         CLK_SPI5_PLL_SEL_SHIFT          = 15,
 246
 247         /* CLKSEL_CON59 */
 248         CLK_SPI1_PLL_SEL_SHIFT          = 15,
 249         CLK_SPI1_PLL_DIV_CON_SHIFT      = 8,
 250         CLK_SPI0_PLL_SEL_SHIFT          = 7,
 251         CLK_SPI0_PLL_DIV_CON_SHIFT      = 0,
 252
 253         /* CLKSEL_CON60 */
 254         CLK_SPI4_PLL_SEL_SHIFT          = 15,
 255         CLK_SPI4_PLL_DIV_CON_SHIFT      = 8,
 256         CLK_SPI2_PLL_SEL_SHIFT          = 7,
 257         CLK_SPI2_PLL_DIV_CON_SHIFT      = 0,
 258
 259         /* CLKSEL_CON61 */
 260         CLK_I2C_PLL_SEL_MASK            = 1,
 261         CLK_I2C_PLL_SEL_CPLL            = 0,
 262         CLK_I2C_PLL_SEL_GPLL            = 1,
 263         CLK_I2C5_PLL_SEL_SHIFT          = 15,
 264         CLK_I2C5_DIV_CON_SHIFT          = 8,
 265         CLK_I2C1_PLL_SEL_SHIFT          = 7,
 266         CLK_I2C1_DIV_CON_SHIFT          = 0,
 267
 268         /* CLKSEL_CON62 */
 269         CLK_I2C6_PLL_SEL_SHIFT          = 15,
 270         CLK_I2C6_DIV_CON_SHIFT          = 8,
 271         CLK_I2C2_PLL_SEL_SHIFT          = 7,
 272         CLK_I2C2_DIV_CON_SHIFT          = 0,
 273
 274         /* CLKSEL_CON63 */
 275         CLK_I2C7_PLL_SEL_SHIFT          = 15,
 276         CLK_I2C7_DIV_CON_SHIFT          = 8,
 277         CLK_I2C3_PLL_SEL_SHIFT          = 7,
 278         CLK_I2C3_DIV_CON_SHIFT          = 0,
 279
 280         /* CRU_SOFTRST_CON4 */
 281         RESETN_DDR0_REQ_SHIFT           = 8,
 282         RESETN_DDR0_REQ_MASK            = 1 << RESETN_DDR0_REQ_SHIFT,
 283         RESETN_DDRPHY0_REQ_SHIFT        = 9,
 284         RESETN_DDRPHY0_REQ_MASK         = 1 << RESETN_DDRPHY0_REQ_SHIFT,
 285         RESETN_DDR1_REQ_SHIFT           = 12,
 286         RESETN_DDR1_REQ_MASK            = 1 << RESETN_DDR1_REQ_SHIFT,
 287         RESETN_DDRPHY1_REQ_SHIFT        = 13,
 288         RESETN_DDRPHY1_REQ_MASK         = 1 << RESETN_DDRPHY1_REQ_SHIFT,
 289 };
 290
 291 #define VCO_MAX_KHZ     (3200 * (MHz / KHz))
 292 #define VCO_MIN_KHZ     (800 * (MHz / KHz))
 293 #define OUTPUT_MAX_KHZ  (3200 * (MHz / KHz))
 294 #define OUTPUT_MIN_KHZ  (16 * (MHz / KHz))
 295
 296 /*
 297  *  the div restructions of pll in integer mode, these are defined in
 298  *  * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0
 299  */
 300 #define PLL_DIV_MIN     16
 301 #define PLL_DIV_MAX     3200
 302
 303 /*
 304  * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
 305  * Formulas also embedded within the Fractional PLL Verilog model:
 306  * If DSMPD = 1 (DSM is disabled, "integer mode")
 307  * FOUTVCO = FREF / REFDIV * FBDIV
 308  * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
 309  * Where:
 310  * FOUTVCO = Fractional PLL non-divided output frequency
 311  * FOUTPOSTDIV = Fractional PLL divided output frequency
 312  *               (output of second post divider)
 313  * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
 314  * REFDIV = Fractional PLL input reference clock divider
 315  * FBDIV = Integer value programmed into feedback divide
 316  *
 317  */
 318 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div)
 319 {
 320         /* All 8 PLLs have same VCO and output frequency range restrictions. */
 321         u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv;
 322         u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
 323
 324         debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, "
 325                            "postdiv2=%d, vco=%u khz, output=%u khz\n",
 326                            pll_con, div->fbdiv, div->refdiv, div->postdiv1,
 327                            div->postdiv2, vco_khz, output_khz);
 328         assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
 329                output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ &&
 330                div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX);
 331
 332         /*
 333          * When power on or changing PLL setting,
 334          * we must force PLL into slow mode to ensure output stable clock.
 335          */
 336         rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
 337                      PLL_MODE_SLOW << PLL_MODE_SHIFT);
 338
 339         /* use integer mode */
 340         rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK,
 341                      PLL_INTEGER_MODE << PLL_DSMPD_SHIFT);
 342
 343         rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK,
 344                      div->fbdiv << PLL_FBDIV_SHIFT);
 345         rk_clrsetreg(&pll_con[1],
 346                      PLL_POSTDIV2_MASK | PLL_POSTDIV1_MASK |
 347                      PLL_REFDIV_MASK | PLL_REFDIV_SHIFT,
 348                      (div->postdiv2 << PLL_POSTDIV2_SHIFT) |
 349                      (div->postdiv1 << PLL_POSTDIV1_SHIFT) |
 350                      (div->refdiv << PLL_REFDIV_SHIFT));
 351
 352         /* waiting for pll lock */
 353         while (!(readl(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT)))
 354                 udelay(1);
 355
 356         /* pll enter normal mode */
 357         rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
 358                      PLL_MODE_NORM << PLL_MODE_SHIFT);
 359 }
 360
 361 static int pll_para_config(u32 freq_hz, struct pll_div *div)
 362 {
 363         u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0;
 364         u32 postdiv1, postdiv2 = 1;
 365         u32 fref_khz;
 366         u32 diff_khz, best_diff_khz;
 367         const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16;
 368         const u32 max_postdiv1 = 7, max_postdiv2 = 7;
 369         u32 vco_khz;
 370         u32 freq_khz = freq_hz / KHz;
 371
 372         if (!freq_hz) {
 373                 printf("%s: the frequency can't be 0 Hz\n", __func__);
 374                 return -1;
 375         }
 376
 377         postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
 378         if (postdiv1 > max_postdiv1) {
 379                 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1);
 380                 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2);
 381         }
 382
 383         vco_khz = freq_khz * postdiv1 * postdiv2;
 384
 385         if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ ||
 386             postdiv2 > max_postdiv2) {
 387                 printf("%s: Cannot find out a supported VCO"
 388                        " for Frequency (%uHz).\n", __func__, freq_hz);
 389                 return -1;
 390         }
 391
 392         div->postdiv1 = postdiv1;
 393         div->postdiv2 = postdiv2;
 394
 395         best_diff_khz = vco_khz;
 396         for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) {
 397                 fref_khz = ref_khz / refdiv;
 398
 399                 fbdiv = vco_khz / fref_khz;
 400                 if (fbdiv >= max_fbdiv || fbdiv <= min_fbdiv)
 401                         continue;
 402                 diff_khz = vco_khz - fbdiv * fref_khz;
 403                 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) {
 404                         fbdiv++;
 405                         diff_khz = fref_khz - diff_khz;
 406                 }
 407
 408                 if (diff_khz >= best_diff_khz)
 409                         continue;
 410
 411                 best_diff_khz = diff_khz;
 412                 div->refdiv = refdiv;
 413                 div->fbdiv = fbdiv;
 414         }
 415
 416         if (best_diff_khz > 4 * (MHz / KHz)) {
 417                 printf("%s: Failed to match output frequency %u, "
 418                        "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz,
 419                        best_diff_khz * KHz);
 420                 return -1;
 421         }
 422         return 0;
 423 }
 424
 425 void rk3399_configure_cpu_l(struct rockchip_cru *cru,
 426                             enum apll_l_frequencies apll_l_freq)
 427 {
 428         u32 aclkm_div;
 429         u32 pclk_dbg_div;
 430         u32 atclk_div;
 431
 432         /* Setup cluster L */
 433         rkclk_set_pll(&cru->apll_l_con[0], apll_l_cfgs[apll_l_freq]);
 434
 435         aclkm_div = LPLL_HZ / ACLKM_CORE_L_HZ - 1;
 436         assert((aclkm_div + 1) * ACLKM_CORE_L_HZ == LPLL_HZ &&
 437                aclkm_div < 0x1f);
 438
 439         pclk_dbg_div = LPLL_HZ / PCLK_DBG_L_HZ - 1;
 440         assert((pclk_dbg_div + 1) * PCLK_DBG_L_HZ == LPLL_HZ &&
 441                pclk_dbg_div < 0x1f);
 442
 443         atclk_div = LPLL_HZ / ATCLK_CORE_L_HZ - 1;
 444         assert((atclk_div + 1) * ATCLK_CORE_L_HZ == LPLL_HZ &&
 445                atclk_div < 0x1f);
 446
 447         rk_clrsetreg(&cru->clksel_con[0],
 448                      ACLKM_CORE_L_DIV_CON_MASK | CLK_CORE_L_PLL_SEL_MASK |
 449                      CLK_CORE_L_DIV_MASK,
 450                      aclkm_div << ACLKM_CORE_L_DIV_CON_SHIFT |
 451                      CLK_CORE_L_PLL_SEL_ALPLL << CLK_CORE_L_PLL_SEL_SHIFT |
 452                      0 << CLK_CORE_L_DIV_SHIFT);
 453
 454         rk_clrsetreg(&cru->clksel_con[1],
 455                      PCLK_DBG_L_DIV_MASK | ATCLK_CORE_L_DIV_MASK,
 456                      pclk_dbg_div << PCLK_DBG_L_DIV_SHIFT |
 457                      atclk_div << ATCLK_CORE_L_DIV_SHIFT);
 458 }
 459
 460 void rk3399_configure_cpu_b(struct rockchip_cru *cru,
 461                             enum apll_b_frequencies apll_b_freq)
 462 {
 463         u32 aclkm_div;
 464         u32 pclk_dbg_div;
 465         u32 atclk_div;
 466
 467         /* Setup cluster B */
 468         rkclk_set_pll(&cru->apll_b_con[0], apll_b_cfgs[apll_b_freq]);
 469
 470         aclkm_div = BPLL_HZ / ACLKM_CORE_B_HZ - 1;
 471         assert((aclkm_div + 1) * ACLKM_CORE_B_HZ == BPLL_HZ &&
 472                aclkm_div < 0x1f);
 473
 474         pclk_dbg_div = BPLL_HZ / PCLK_DBG_B_HZ - 1;
 475         assert((pclk_dbg_div + 1) * PCLK_DBG_B_HZ == BPLL_HZ &&
 476                pclk_dbg_div < 0x1f);
 477
 478         atclk_div = BPLL_HZ / ATCLK_CORE_B_HZ - 1;
 479         assert((atclk_div + 1) * ATCLK_CORE_B_HZ == BPLL_HZ &&
 480                atclk_div < 0x1f);
 481
 482         rk_clrsetreg(&cru->clksel_con[2],
 483                      ACLKM_CORE_B_DIV_CON_MASK | CLK_CORE_B_PLL_SEL_MASK |
 484                      CLK_CORE_B_DIV_MASK,
 485                      aclkm_div << ACLKM_CORE_B_DIV_CON_SHIFT |
 486                      CLK_CORE_B_PLL_SEL_ABPLL << CLK_CORE_B_PLL_SEL_SHIFT |
 487                      0 << CLK_CORE_B_DIV_SHIFT);
 488
 489         rk_clrsetreg(&cru->clksel_con[3],
 490                      PCLK_DBG_B_DIV_MASK | ATCLK_CORE_B_DIV_MASK,
 491                      pclk_dbg_div << PCLK_DBG_B_DIV_SHIFT |
 492                      atclk_div << ATCLK_CORE_B_DIV_SHIFT);
 493 }
 494
 495 #define I2C_CLK_REG_MASK(bus) \
 496         (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT | \
 497          CLK_I2C_PLL_SEL_MASK << CLK_I2C ##bus## _PLL_SEL_SHIFT)
 498
 499 #define I2C_CLK_REG_VALUE(bus, clk_div) \
 500         ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT | \
 501          CLK_I2C_PLL_SEL_GPLL << CLK_I2C ##bus## _PLL_SEL_SHIFT)
 502
 503 #define I2C_CLK_DIV_VALUE(con, bus) \
 504         ((con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & I2C_DIV_CON_MASK)
 505
 506 #define I2C_PMUCLK_REG_MASK(bus) \
 507         (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT)
 508
 509 #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \
 510         ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT)
 511
 512 static ulong rk3399_i2c_get_clk(struct rockchip_cru *cru, ulong clk_id)
 513 {
 514         u32 div, con;
 515
 516         switch (clk_id) {
 517         case SCLK_I2C1:
 518                 con = readl(&cru->clksel_con[61]);
 519                 div = I2C_CLK_DIV_VALUE(con, 1);
 520                 break;
 521         case SCLK_I2C2:
 522                 con = readl(&cru->clksel_con[62]);
 523                 div = I2C_CLK_DIV_VALUE(con, 2);
 524                 break;
 525         case SCLK_I2C3:
 526                 con = readl(&cru->clksel_con[63]);
 527                 div = I2C_CLK_DIV_VALUE(con, 3);
 528                 break;
 529         case SCLK_I2C5:
 530                 con = readl(&cru->clksel_con[61]);
 531                 div = I2C_CLK_DIV_VALUE(con, 5);
 532                 break;
 533         case SCLK_I2C6:
 534                 con = readl(&cru->clksel_con[62]);
 535                 div = I2C_CLK_DIV_VALUE(con, 6);
 536                 break;
 537         case SCLK_I2C7:
 538                 con = readl(&cru->clksel_con[63]);
 539                 div = I2C_CLK_DIV_VALUE(con, 7);
 540                 break;
 541         default:
 542                 printf("do not support this i2c bus\n");
 543                 return -EINVAL;
 544         }
 545
 546         return DIV_TO_RATE(GPLL_HZ, div);
 547 }
 548
 549 static ulong rk3399_i2c_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
 550 {
 551         int src_clk_div;
 552
 553         /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/
 554         src_clk_div = GPLL_HZ / hz;
 555         assert(src_clk_div - 1 < 127);
 556
 557         switch (clk_id) {
 558         case SCLK_I2C1:
 559                 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1),
 560                              I2C_CLK_REG_VALUE(1, src_clk_div));
 561                 break;
 562         case SCLK_I2C2:
 563                 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2),
 564                              I2C_CLK_REG_VALUE(2, src_clk_div));
 565                 break;
 566         case SCLK_I2C3:
 567                 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3),
 568                              I2C_CLK_REG_VALUE(3, src_clk_div));
 569                 break;
 570         case SCLK_I2C5:
 571                 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(5),
 572                              I2C_CLK_REG_VALUE(5, src_clk_div));
 573                 break;
 574         case SCLK_I2C6:
 575                 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(6),
 576                              I2C_CLK_REG_VALUE(6, src_clk_div));
 577                 break;
 578         case SCLK_I2C7:
 579                 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(7),
 580                              I2C_CLK_REG_VALUE(7, src_clk_div));
 581                 break;
 582         default:
 583                 printf("do not support this i2c bus\n");
 584                 return -EINVAL;
 585         }
 586
 587         return rk3399_i2c_get_clk(cru, clk_id);
 588 }
 589
 590 /*
 591  * RK3399 SPI clocks have a common divider-width (7 bits) and a single bit
 592  * to select either CPLL or GPLL as the clock-parent. The location within
 593  * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable.
 594  */
 595
 596 struct spi_clkreg {
 597         u8 reg;  /* CLKSEL_CON[reg] register in CRU */
 598         u8 div_shift;
 599         u8 sel_shift;
 600 };
 601
 602 /*
 603  * The entries are numbered relative to their offset from SCLK_SPI0.
 604  *
 605  * Note that SCLK_SPI3 (which is configured via PMUCRU and requires different
 606  * logic is not supported).
 607  */
 608 static const struct spi_clkreg spi_clkregs[] = {
 609         [0] = { .reg = 59,
 610                 .div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT,
 611                 .sel_shift = CLK_SPI0_PLL_SEL_SHIFT, },
 612         [1] = { .reg = 59,
 613                 .div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT,
 614                 .sel_shift = CLK_SPI1_PLL_SEL_SHIFT, },
 615         [2] = { .reg = 60,
 616                 .div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT,
 617                 .sel_shift = CLK_SPI2_PLL_SEL_SHIFT, },
 618         [3] = { .reg = 60,
 619                 .div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT,
 620                 .sel_shift = CLK_SPI4_PLL_SEL_SHIFT, },
 621         [4] = { .reg = 58,
 622                 .div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT,
 623                 .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, },
 624 };
 625
 626 static ulong rk3399_spi_get_clk(struct rockchip_cru *cru, ulong clk_id)
 627 {
 628         const struct spi_clkreg *spiclk = NULL;
 629         u32 div, val;
 630
 631         switch (clk_id) {
 632         case SCLK_SPI0 ... SCLK_SPI5:
 633                 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
 634                 break;
 635
 636         default:
 637                 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
 638                 return -EINVAL;
 639         }
 640
 641         val = readl(&cru->clksel_con[spiclk->reg]);
 642         div = bitfield_extract(val, spiclk->div_shift,
 643                                CLK_SPI_PLL_DIV_CON_WIDTH);
 644
 645         return DIV_TO_RATE(GPLL_HZ, div);
 646 }
 647
 648 static ulong rk3399_spi_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
 649 {
 650         const struct spi_clkreg *spiclk = NULL;
 651         int src_clk_div;
 652
 653         src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
 654         assert(src_clk_div < 128);
 655
 656         switch (clk_id) {
 657         case SCLK_SPI1 ... SCLK_SPI5:
 658                 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
 659                 break;
 660
 661         default:
 662                 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
 663                 return -EINVAL;
 664         }
 665
 666         rk_clrsetreg(&cru->clksel_con[spiclk->reg],
 667                      ((CLK_SPI_PLL_DIV_CON_MASK << spiclk->div_shift) |
 668                        (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)),
 669                      ((src_clk_div << spiclk->div_shift) |
 670                       (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)));
 671
 672         return rk3399_spi_get_clk(cru, clk_id);
 673 }
 674
 675 static ulong rk3399_vop_set_clk(struct rockchip_cru *cru, ulong clk_id, u32 hz)
 676 {
 677         struct pll_div vpll_config = {0};
 678         int aclk_vop = 198 * MHz;
 679         void *aclkreg_addr, *dclkreg_addr;
 680         u32 div;
 681
 682         switch (clk_id) {
 683         case DCLK_VOP0:
 684                 aclkreg_addr = &cru->clksel_con[47];
 685                 dclkreg_addr = &cru->clksel_con[49];
 686                 break;
 687         case DCLK_VOP1:
 688                 aclkreg_addr = &cru->clksel_con[48];
 689                 dclkreg_addr = &cru->clksel_con[50];
 690                 break;
 691         default:
 692                 return -EINVAL;
 693         }
 694         /* vop aclk source clk: cpll */
 695         div = CPLL_HZ / aclk_vop;
 696         assert(div - 1 < 32);
 697
 698         rk_clrsetreg(aclkreg_addr,
 699                      ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK,
 700                      ACLK_VOP_PLL_SEL_CPLL << ACLK_VOP_PLL_SEL_SHIFT |
 701                      (div - 1) << ACLK_VOP_DIV_CON_SHIFT);
 702
 703         /* vop dclk source from vpll, and equals to vpll(means div == 1) */
 704         if (pll_para_config(hz, &vpll_config))
 705                 return -1;
 706
 707         rkclk_set_pll(&cru->vpll_con[0], &vpll_config);
 708
 709         rk_clrsetreg(dclkreg_addr,
 710                      DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK |
 711                      DCLK_VOP_DIV_CON_MASK,
 712                      DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT |
 713                      DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT |
 714                      (1 - 1) << DCLK_VOP_DIV_CON_SHIFT);
 715
 716         return hz;
 717 }
 718
 719 static ulong rk3399_mmc_get_clk(struct rockchip_cru *cru, uint clk_id)
 720 {
 721         u32 div, con;
 722
 723         switch (clk_id) {
 724         case HCLK_SDMMC:
 725         case SCLK_SDMMC:
 726                 con = readl(&cru->clksel_con[16]);
 727                 /* dwmmc controller have internal div 2 */
 728                 div = 2;
 729                 break;
 730         case SCLK_EMMC:
 731                 con = readl(&cru->clksel_con[21]);
 732                 div = 1;
 733                 break;
 734         default:
 735                 return -EINVAL;
 736         }
 737
 738         div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
 739         if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
 740                         == CLK_EMMC_PLL_SEL_24M)
 741                 return DIV_TO_RATE(OSC_HZ, div);
 742         else
 743                 return DIV_TO_RATE(GPLL_HZ, div);
 744 }
 745
 746 static ulong rk3399_mmc_set_clk(struct rockchip_cru *cru,
 747                                 ulong clk_id, ulong set_rate)
 748 {
 749         int src_clk_div;
 750         int aclk_emmc = 198 * MHz;
 751
 752         switch (clk_id) {
 753         case HCLK_SDMMC:
 754         case SCLK_SDMMC:
 755                 /* Select clk_sdmmc source from GPLL by default */
 756                 /* mmc clock defaulg div 2 internal, provide double in cru */
 757                 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);
 758
 759                 if (src_clk_div > 128) {
 760                         /* use 24MHz source for 400KHz clock */
 761                         src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
 762                         assert(src_clk_div - 1 < 128);
 763                         rk_clrsetreg(&cru->clksel_con[16],
 764                                      CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
 765                                      CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
 766                                      (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
 767                 } else {
 768                         rk_clrsetreg(&cru->clksel_con[16],
 769                                      CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
 770                                      CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
 771                                      (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
 772                 }
 773                 break;
 774         case SCLK_EMMC:
 775                 /* Select aclk_emmc source from GPLL */
 776                 src_clk_div = DIV_ROUND_UP(GPLL_HZ, aclk_emmc);
 777                 assert(src_clk_div - 1 < 32);
 778
 779                 rk_clrsetreg(&cru->clksel_con[21],
 780                              ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK,
 781                              ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT |
 782                              (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT);
 783
 784                 /* Select clk_emmc source from GPLL too */
 785                 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate);
 786                 assert(src_clk_div - 1 < 128);
 787
 788                 rk_clrsetreg(&cru->clksel_con[22],
 789                              CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
 790                              CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
 791                              (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
 792                 break;
 793         default:
 794                 return -EINVAL;
 795         }
 796         return rk3399_mmc_get_clk(cru, clk_id);
 797 }
 798
 799 static ulong rk3399_gmac_set_clk(struct rockchip_cru *cru, ulong rate)
 800 {
 801         ulong ret;
 802
 803         /*
 804          * The RGMII CLK can be derived either from an external "clkin"
 805          * or can be generated from internally by a divider from SCLK_MAC.
 806          */
 807         if (readl(&cru->clksel_con[19]) & BIT(4)) {
 808                 /* An external clock will always generate the right rate... */
 809                 ret = rate;
 810         } else {
 811                 /*
 812                  * No platform uses an internal clock to date.
 813                  * Implement this once it becomes necessary and print an error
 814                  * if someone tries to use it (while it remains unimplemented).
 815                  */
 816                 pr_err("%s: internal clock is UNIMPLEMENTED\n", __func__);
 817                 ret = 0;
 818         }
 819
 820         return ret;
 821 }
 822
 823 #define PMUSGRF_DDR_RGN_CON16 0xff330040
 824 static ulong rk3399_ddr_set_clk(struct rockchip_cru *cru,
 825                                 ulong set_rate)
 826 {
 827         struct pll_div dpll_cfg;
 828
 829         /*  IC ECO bug, need to set this register */
 830         writel(0xc000c000, PMUSGRF_DDR_RGN_CON16);
 831
 832         /*  clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
 833         switch (set_rate) {
 834         case 50 * MHz:
 835                 dpll_cfg = (struct pll_div)
 836                 {.refdiv = 1, .fbdiv = 12, .postdiv1 = 3, .postdiv2 = 2};
 837                 break;
 838         case 200 * MHz:
 839                 dpll_cfg = (struct pll_div)
 840                 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1};
 841                 break;
 842         case 300 * MHz:
 843                 dpll_cfg = (struct pll_div)
 844                 {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1};
 845                 break;
 846         case 400 * MHz:
 847                 dpll_cfg = (struct pll_div)
 848                 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
 849                 break;
 850         case 666 * MHz:
 851                 dpll_cfg = (struct pll_div)
 852                 {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1};
 853                 break;
 854         case 800 * MHz:
 855                 dpll_cfg = (struct pll_div)
 856                 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
 857                 break;
 858         case 933 * MHz:
 859                 dpll_cfg = (struct pll_div)
 860                 {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1};
 861                 break;
 862         default:
 863                 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate);
 864         }
 865         rkclk_set_pll(&cru->dpll_con[0], &dpll_cfg);
 866
 867         return set_rate;
 868 }
 869
 870 static ulong rk3399_saradc_get_clk(struct rockchip_cru *cru)
 871 {
 872         u32 div, val;
 873
 874         val = readl(&cru->clksel_con[26]);
 875         div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
 876                                CLK_SARADC_DIV_CON_WIDTH);
 877
 878         return DIV_TO_RATE(OSC_HZ, div);
 879 }
 880
 881 static ulong rk3399_saradc_set_clk(struct rockchip_cru *cru, uint hz)
 882 {
 883         int src_clk_div;
 884
 885         src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
 886         assert(src_clk_div < 128);
 887
 888         rk_clrsetreg(&cru->clksel_con[26],
 889                      CLK_SARADC_DIV_CON_MASK,
 890                      src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
 891
 892         return rk3399_saradc_get_clk(cru);
 893 }
 894
 895 static ulong rk3399_clk_get_rate(struct clk *clk)
 896 {
 897         struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
 898         ulong rate = 0;
 899
 900         switch (clk->id) {
 901         case 0 ... 63:
 902                 return 0;
 903         case HCLK_SDMMC:
 904         case SCLK_SDMMC:
 905         case SCLK_EMMC:
 906                 rate = rk3399_mmc_get_clk(priv->cru, clk->id);
 907                 break;
 908         case SCLK_I2C1:
 909         case SCLK_I2C2:
 910         case SCLK_I2C3:
 911         case SCLK_I2C5:
 912         case SCLK_I2C6:
 913         case SCLK_I2C7:
 914                 rate = rk3399_i2c_get_clk(priv->cru, clk->id);
 915                 break;
 916         case SCLK_SPI0...SCLK_SPI5:
 917                 rate = rk3399_spi_get_clk(priv->cru, clk->id);
 918                 break;
 919         case SCLK_UART0:
 920         case SCLK_UART1:
 921         case SCLK_UART2:
 922         case SCLK_UART3:
 923                 return 24000000;
 924         case PCLK_HDMI_CTRL:
 925                 break;
 926         case DCLK_VOP0:
 927         case DCLK_VOP1:
 928                 break;
 929         case PCLK_EFUSE1024NS:
 930                 break;
 931         case SCLK_SARADC:
 932                 rate = rk3399_saradc_get_clk(priv->cru);
 933                 break;
 934         case ACLK_VIO:
 935         case ACLK_HDCP:
 936         case ACLK_GIC_PRE:
 937         case PCLK_DDR:
 938                 break;
 939         default:
 940                 log_debug("Unknown clock %lu\n", clk->id);
 941                 return -ENOENT;
 942         }
 943
 944         return rate;
 945 }
 946
 947 static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
 948 {
 949         struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
 950         ulong ret = 0;
 951
 952         switch (clk->id) {
 953         case 0 ... 63:
 954                 return 0;
 955
 956         case ACLK_PERIHP:
 957         case HCLK_PERIHP:
 958         case PCLK_PERIHP:
 959                 return 0;
 960
 961         case ACLK_PERILP0:
 962         case HCLK_PERILP0:
 963         case PCLK_PERILP0:
 964                 return 0;
 965
 966         case ACLK_CCI:
 967                 return 0;
 968
 969         case HCLK_PERILP1:
 970         case PCLK_PERILP1:
 971                 return 0;
 972
 973         case HCLK_SDMMC:
 974         case SCLK_SDMMC:
 975         case SCLK_EMMC:
 976                 ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate);
 977                 break;
 978         case SCLK_MAC:
 979                 ret = rk3399_gmac_set_clk(priv->cru, rate);
 980                 break;
 981         case SCLK_I2C1:
 982         case SCLK_I2C2:
 983         case SCLK_I2C3:
 984         case SCLK_I2C5:
 985         case SCLK_I2C6:
 986         case SCLK_I2C7:
 987                 ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate);
 988                 break;
 989         case SCLK_SPI0...SCLK_SPI5:
 990                 ret = rk3399_spi_set_clk(priv->cru, clk->id, rate);
 991                 break;
 992         case PCLK_HDMI_CTRL:
 993         case PCLK_VIO_GRF:
 994                 /* the PCLK gates for video are enabled by default */
 995                 break;
 996         case DCLK_VOP0:
 997         case DCLK_VOP1:
 998                 ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);
 999                 break;
1000         case ACLK_VOP1:
1001         case HCLK_VOP1:
1002         case HCLK_SD:
1003                 /**
1004                  * assigned-clocks handling won't require for vopl, so
1005                  * return 0 to satisfy clk_set_defaults during device probe.
1006                  */
1007                 return 0;
1008         case SCLK_DDRCLK:
1009                 ret = rk3399_ddr_set_clk(priv->cru, rate);
1010                 break;
1011         case PCLK_EFUSE1024NS:
1012                 break;
1013         case SCLK_SARADC:
1014                 ret = rk3399_saradc_set_clk(priv->cru, rate);
1015                 break;
1016         case ACLK_VIO:
1017         case ACLK_HDCP:
1018         case ACLK_GIC_PRE:
1019         case PCLK_DDR:
1020                 return 0;
1021         default:
1022                 log_debug("Unknown clock %lu\n", clk->id);
1023                 return -ENOENT;
1024         }
1025
1026         return ret;
1027 }
1028
1029 static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk,
1030                                                  struct clk *parent)
1031 {
1032         struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
1033         const char *clock_output_name;
1034         int ret;
1035
1036         /*
1037          * If the requested parent is in the same clock-controller and
1038          * the id is SCLK_MAC ("clk_gmac"), switch to the internal clock.
1039          */
1040         if (parent->dev == clk->dev && parent->id == SCLK_MAC) {
1041                 debug("%s: switching RGMII to SCLK_MAC\n", __func__);
1042                 rk_clrreg(&priv->cru->clksel_con[19], BIT(4));
1043                 return 0;
1044         }
1045
1046         /*
1047          * Otherwise, we need to check the clock-output-names of the
1048          * requested parent to see if the requested id is "clkin_gmac".
1049          */
1050         ret = dev_read_string_index(parent->dev, "clock-output-names",
1051                                     parent->id, &clock_output_name);
1052         if (ret < 0)
1053                 return -ENODATA;
1054
1055         /* If this is "clkin_gmac", switch to the external clock input */
1056         if (!strcmp(clock_output_name, "clkin_gmac")) {
1057                 debug("%s: switching RGMII to CLKIN\n", __func__);
1058                 rk_setreg(&priv->cru->clksel_con[19], BIT(4));
1059                 return 0;
1060         }
1061
1062         return -EINVAL;
1063 }
1064
1065 static int __maybe_unused rk3399_clk_set_parent(struct clk *clk,
1066                                                 struct clk *parent)
1067 {
1068         switch (clk->id) {
1069         case SCLK_RMII_SRC:
1070                 return rk3399_gmac_set_parent(clk, parent);
1071         }
1072
1073         debug("%s: unsupported clk %ld\n", __func__, clk->id);
1074         return -ENOENT;
1075 }
1076
1077 static struct clk_ops rk3399_clk_ops = {
1078         .get_rate = rk3399_clk_get_rate,
1079         .set_rate = rk3399_clk_set_rate,
1080 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1081         .set_parent = rk3399_clk_set_parent,
1082 #endif
1083 };
1084
1085 #ifdef CONFIG_SPL_BUILD
1086 static void rkclk_init(struct rockchip_cru *cru)
1087 {
1088         u32 aclk_div;
1089         u32 hclk_div;
1090         u32 pclk_div;
1091
1092         rk3399_configure_cpu_l(cru, APLL_L_600_MHZ);
1093         rk3399_configure_cpu_b(cru, APLL_B_600_MHZ);
1094         /*
1095          * some cru registers changed by bootrom, we'd better reset them to
1096          * reset/default values described in TRM to avoid confusion in kernel.
1097          * Please consider these three lines as a fix of bootrom bug.
1098          */
1099         rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101);
1100         rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f);
1101         rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003);
1102
1103         /* configure gpll cpll */
1104         rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg);
1105         rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg);
1106
1107         /* configure perihp aclk, hclk, pclk */
1108         aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
1109         assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
1110
1111         hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
1112         assert((hclk_div + 1) * PERIHP_HCLK_HZ ==
1113                PERIHP_ACLK_HZ && (hclk_div < 0x4));
1114
1115         pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
1116         assert((pclk_div + 1) * PERIHP_PCLK_HZ ==
1117                PERIHP_ACLK_HZ && (pclk_div < 0x7));
1118
1119         rk_clrsetreg(&cru->clksel_con[14],
1120                      PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK |
1121                      ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK,
1122                      pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
1123                      hclk_div << HCLK_PERIHP_DIV_CON_SHIFT |
1124                      ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT |
1125                      aclk_div << ACLK_PERIHP_DIV_CON_SHIFT);
1126
1127         /* configure perilp0 aclk, hclk, pclk */
1128         aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1;
1129         assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
1130
1131         hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1;
1132         assert((hclk_div + 1) * PERILP0_HCLK_HZ ==
1133                PERILP0_ACLK_HZ && (hclk_div < 0x4));
1134
1135         pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1;
1136         assert((pclk_div + 1) * PERILP0_PCLK_HZ ==
1137                PERILP0_ACLK_HZ && (pclk_div < 0x7));
1138
1139         rk_clrsetreg(&cru->clksel_con[23],
1140                      PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK |
1141                      ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK,
1142                      pclk_div << PCLK_PERILP0_DIV_CON_SHIFT |
1143                      hclk_div << HCLK_PERILP0_DIV_CON_SHIFT |
1144                      ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT |
1145                      aclk_div << ACLK_PERILP0_DIV_CON_SHIFT);
1146
1147         /* perilp1 hclk select gpll as source */
1148         hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1;
1149         assert((hclk_div + 1) * PERILP1_HCLK_HZ ==
1150                GPLL_HZ && (hclk_div < 0x1f));
1151
1152         pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1;
1153         assert((pclk_div + 1) * PERILP1_HCLK_HZ ==
1154                PERILP1_HCLK_HZ && (hclk_div < 0x7));
1155
1156         rk_clrsetreg(&cru->clksel_con[25],
1157                      PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK |
1158                      HCLK_PERILP1_PLL_SEL_MASK,
1159                      pclk_div << PCLK_PERILP1_DIV_CON_SHIFT |
1160                      hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
1161                      HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
1162 }
1163 #endif
1164
1165 static int rk3399_clk_probe(struct udevice *dev)
1166 {
1167 #ifdef CONFIG_SPL_BUILD
1168         struct rk3399_clk_priv *priv = dev_get_priv(dev);
1169
1170 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1171         struct rk3399_clk_plat *plat = dev_get_platdata(dev);
1172
1173         priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
1174 #endif
1175         rkclk_init(priv->cru);
1176 #endif
1177         return 0;
1178 }
1179
1180 static int rk3399_clk_ofdata_to_platdata(struct udevice *dev)
1181 {
1182 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1183         struct rk3399_clk_priv *priv = dev_get_priv(dev);
1184
1185         priv->cru = dev_read_addr_ptr(dev);
1186 #endif
1187         return 0;
1188 }
1189
1190 static int rk3399_clk_bind(struct udevice *dev)
1191 {
1192         int ret;
1193         struct udevice *sys_child;
1194         struct sysreset_reg *priv;
1195
1196         /* The reset driver does not have a device node, so bind it here */
1197         ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
1198                                  &sys_child);
1199         if (ret) {
1200                 debug("Warning: No sysreset driver: ret=%d\n", ret);
1201         } else {
1202                 priv = malloc(sizeof(struct sysreset_reg));
1203                 priv->glb_srst_fst_value = offsetof(struct rockchip_cru,
1204                                                     glb_srst_fst_value);
1205                 priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
1206                                                     glb_srst_snd_value);
1207                 sys_child->priv = priv;
1208         }
1209
1210 #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
1211         ret = offsetof(struct rockchip_cru, softrst_con[0]);
1212         ret = rockchip_reset_bind(dev, ret, 21);
1213         if (ret)
1214                 debug("Warning: software reset driver bind faile\n");
1215 #endif
1216
1217         return 0;
1218 }
1219
1220 static const struct udevice_id rk3399_clk_ids[] = {
1221         { .compatible = "rockchip,rk3399-cru" },
1222         { }
1223 };
1224
1225 U_BOOT_DRIVER(clk_rk3399) = {
1226         .name           = "rockchip_rk3399_cru",
1227         .id             = UCLASS_CLK,
1228         .of_match       = rk3399_clk_ids,
1229         .priv_auto_alloc_size = sizeof(struct rk3399_clk_priv),
1230         .ofdata_to_platdata = rk3399_clk_ofdata_to_platdata,
1231         .ops            = &rk3399_clk_ops,
1232         .bind           = rk3399_clk_bind,
1233         .probe          = rk3399_clk_probe,
1234 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1235         .platdata_auto_alloc_size = sizeof(struct rk3399_clk_plat),
1236 #endif
1237 };
1238
1239 static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id)
1240 {
1241         u32 div, con;
1242
1243         switch (clk_id) {
1244         case SCLK_I2C0_PMU:
1245                 con = readl(&pmucru->pmucru_clksel[2]);
1246                 div = I2C_CLK_DIV_VALUE(con, 0);
1247                 break;
1248         case SCLK_I2C4_PMU:
1249                 con = readl(&pmucru->pmucru_clksel[3]);
1250                 div = I2C_CLK_DIV_VALUE(con, 4);
1251                 break;
1252         case SCLK_I2C8_PMU:
1253                 con = readl(&pmucru->pmucru_clksel[2]);
1254                 div = I2C_CLK_DIV_VALUE(con, 8);
1255                 break;
1256         default:
1257                 printf("do not support this i2c bus\n");
1258                 return -EINVAL;
1259         }
1260
1261         return DIV_TO_RATE(PPLL_HZ, div);
1262 }
1263
1264 static ulong rk3399_i2c_set_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id,
1265                                    uint hz)
1266 {
1267         int src_clk_div;
1268
1269         src_clk_div = PPLL_HZ / hz;
1270         assert(src_clk_div - 1 < 127);
1271
1272         switch (clk_id) {
1273         case SCLK_I2C0_PMU:
1274                 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(0),
1275                              I2C_PMUCLK_REG_VALUE(0, src_clk_div));
1276                 break;
1277         case SCLK_I2C4_PMU:
1278                 rk_clrsetreg(&pmucru->pmucru_clksel[3], I2C_PMUCLK_REG_MASK(4),
1279                              I2C_PMUCLK_REG_VALUE(4, src_clk_div));
1280                 break;
1281         case SCLK_I2C8_PMU:
1282                 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(8),
1283                              I2C_PMUCLK_REG_VALUE(8, src_clk_div));
1284                 break;
1285         default:
1286                 printf("do not support this i2c bus\n");
1287                 return -EINVAL;
1288         }
1289
1290         return DIV_TO_RATE(PPLL_HZ, src_clk_div);
1291 }
1292
1293 static ulong rk3399_pwm_get_clk(struct rk3399_pmucru *pmucru)
1294 {
1295         u32 div, con;
1296
1297         /* PWM closk rate is same as pclk_pmu */
1298         con = readl(&pmucru->pmucru_clksel[0]);
1299         div = con & PMU_PCLK_DIV_CON_MASK;
1300
1301         return DIV_TO_RATE(PPLL_HZ, div);
1302 }
1303
1304 static ulong rk3399_pmuclk_get_rate(struct clk *clk)
1305 {
1306         struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
1307         ulong rate = 0;
1308
1309         switch (clk->id) {
1310         case PLL_PPLL:
1311                 return PPLL_HZ;
1312         case PCLK_RKPWM_PMU:
1313                 rate = rk3399_pwm_get_clk(priv->pmucru);
1314                 break;
1315         case SCLK_I2C0_PMU:
1316         case SCLK_I2C4_PMU:
1317         case SCLK_I2C8_PMU:
1318                 rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id);
1319                 break;
1320         default:
1321                 return -ENOENT;
1322         }
1323
1324         return rate;
1325 }
1326
1327 static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate)
1328 {
1329         struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
1330         ulong ret = 0;
1331
1332         switch (clk->id) {
1333         case PLL_PPLL:
1334                 /*
1335                  * This has already been set up and we don't want/need
1336                  * to change it here.  Accept the request though, as the
1337                  * device-tree has this in an 'assigned-clocks' list.
1338                  */
1339                 return PPLL_HZ;
1340         case SCLK_I2C0_PMU:
1341         case SCLK_I2C4_PMU:
1342         case SCLK_I2C8_PMU:
1343                 ret = rk3399_i2c_set_pmuclk(priv->pmucru, clk->id, rate);
1344                 break;
1345         default:
1346                 return -ENOENT;
1347         }
1348
1349         return ret;
1350 }
1351
1352 static struct clk_ops rk3399_pmuclk_ops = {
1353         .get_rate = rk3399_pmuclk_get_rate,
1354         .set_rate = rk3399_pmuclk_set_rate,
1355 };
1356
1357 #ifndef CONFIG_SPL_BUILD
1358 static void pmuclk_init(struct rk3399_pmucru *pmucru)
1359 {
1360         u32 pclk_div;
1361
1362         /*  configure pmu pll(ppll) */
1363         rkclk_set_pll(&pmucru->ppll_con[0], &ppll_init_cfg);
1364
1365         /*  configure pmu pclk */
1366         pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1;
1367         rk_clrsetreg(&pmucru->pmucru_clksel[0],
1368                      PMU_PCLK_DIV_CON_MASK,
1369                      pclk_div << PMU_PCLK_DIV_CON_SHIFT);
1370 }
1371 #endif
1372
1373 static int rk3399_pmuclk_probe(struct udevice *dev)
1374 {
1375 #if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD)
1376         struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
1377 #endif
1378
1379 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1380         struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev);
1381
1382         priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
1383 #endif
1384
1385 #ifndef CONFIG_SPL_BUILD
1386         pmuclk_init(priv->pmucru);
1387 #endif
1388         return 0;
1389 }
1390
1391 static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev)
1392 {
1393 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1394         struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
1395
1396         priv->pmucru = dev_read_addr_ptr(dev);
1397 #endif
1398         return 0;
1399 }
1400
1401 static int rk3399_pmuclk_bind(struct udevice *dev)
1402 {
1403 #if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
1404         int ret;
1405
1406         ret = offsetof(struct rk3399_pmucru, pmucru_softrst_con[0]);
1407         ret = rockchip_reset_bind(dev, ret, 2);
1408         if (ret)
1409                 debug("Warning: software reset driver bind faile\n");
1410 #endif
1411         return 0;
1412 }
1413
1414 static const struct udevice_id rk3399_pmuclk_ids[] = {
1415         { .compatible = "rockchip,rk3399-pmucru" },
1416         { }
1417 };
1418
1419 U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = {
1420         .name           = "rockchip_rk3399_pmucru",
1421         .id             = UCLASS_CLK,
1422         .of_match       = rk3399_pmuclk_ids,
1423         .priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv),
1424         .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata,
1425         .ops            = &rk3399_pmuclk_ops,
1426         .probe          = rk3399_pmuclk_probe,
1427         .bind           = rk3399_pmuclk_bind,
1428 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1429         .platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat),
1430 #endif
1431 };