1 // SPDX-License-Identifier: GPL-2.0
3 * (C) Copyright 2015 Google, Inc
4 * (C) 2017 Theobroma Systems Design und Consulting GmbH
8 #include <clk-uclass.h>
10 #include <dt-structs.h>
18 #include <asm/arch-rockchip/clock.h>
19 #include <asm/arch-rockchip/cru.h>
20 #include <asm/arch-rockchip/hardware.h>
22 #include <dt-bindings/clock/rk3399-cru.h>
23 #include <linux/bitops.h>
24 #include <linux/delay.h>
26 #if CONFIG_IS_ENABLED(OF_PLATDATA)
27 struct rk3399_clk_plat {
28 struct dtd_rockchip_rk3399_cru dtd;
31 struct rk3399_pmuclk_plat {
32 struct dtd_rockchip_rk3399_pmucru dtd;
44 #define RATE_TO_DIV(input_rate, output_rate) \
45 ((input_rate) / (output_rate) - 1)
46 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
48 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
50 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
51 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
53 #if defined(CONFIG_SPL_BUILD)
54 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
55 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
57 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
60 static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600 * MHz, 3, 1, 1);
61 static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
63 static const struct pll_div *apll_l_cfgs[] = {
64 [APLL_L_1600_MHZ] = &apll_l_1600_cfg,
65 [APLL_L_600_MHZ] = &apll_l_600_cfg,
68 static const struct pll_div apll_b_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
69 static const struct pll_div *apll_b_cfgs[] = {
70 [APLL_B_600_MHZ] = &apll_b_600_cfg,
75 PLL_FBDIV_MASK = 0xfff,
79 PLL_POSTDIV2_SHIFT = 12,
80 PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT,
81 PLL_POSTDIV1_SHIFT = 8,
82 PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT,
83 PLL_REFDIV_MASK = 0x3f,
87 PLL_LOCK_STATUS_SHIFT = 31,
88 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
89 PLL_FRACDIV_MASK = 0xffffff,
90 PLL_FRACDIV_SHIFT = 0,
94 PLL_MODE_MASK = 3 << PLL_MODE_SHIFT,
99 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
100 PLL_INTEGER_MODE = 1,
102 /* PMUCRU_CLKSEL_CON0 */
103 PMU_PCLK_DIV_CON_MASK = 0x1f,
104 PMU_PCLK_DIV_CON_SHIFT = 0,
106 /* PMUCRU_CLKSEL_CON1 */
107 SPI3_PLL_SEL_SHIFT = 7,
108 SPI3_PLL_SEL_MASK = 1 << SPI3_PLL_SEL_SHIFT,
109 SPI3_PLL_SEL_24M = 0,
110 SPI3_PLL_SEL_PPLL = 1,
111 SPI3_DIV_CON_SHIFT = 0x0,
112 SPI3_DIV_CON_MASK = 0x7f,
114 /* PMUCRU_CLKSEL_CON2 */
115 I2C_DIV_CON_MASK = 0x7f,
116 CLK_I2C8_DIV_CON_SHIFT = 8,
117 CLK_I2C0_DIV_CON_SHIFT = 0,
119 /* PMUCRU_CLKSEL_CON3 */
120 CLK_I2C4_DIV_CON_SHIFT = 0,
123 ACLKM_CORE_L_DIV_CON_SHIFT = 8,
124 ACLKM_CORE_L_DIV_CON_MASK = 0x1f << ACLKM_CORE_L_DIV_CON_SHIFT,
125 CLK_CORE_L_PLL_SEL_SHIFT = 6,
126 CLK_CORE_L_PLL_SEL_MASK = 3 << CLK_CORE_L_PLL_SEL_SHIFT,
127 CLK_CORE_L_PLL_SEL_ALPLL = 0x0,
128 CLK_CORE_L_PLL_SEL_ABPLL = 0x1,
129 CLK_CORE_L_PLL_SEL_DPLL = 0x10,
130 CLK_CORE_L_PLL_SEL_GPLL = 0x11,
131 CLK_CORE_L_DIV_MASK = 0x1f,
132 CLK_CORE_L_DIV_SHIFT = 0,
135 PCLK_DBG_L_DIV_SHIFT = 0x8,
136 PCLK_DBG_L_DIV_MASK = 0x1f << PCLK_DBG_L_DIV_SHIFT,
137 ATCLK_CORE_L_DIV_SHIFT = 0,
138 ATCLK_CORE_L_DIV_MASK = 0x1f << ATCLK_CORE_L_DIV_SHIFT,
141 ACLKM_CORE_B_DIV_CON_SHIFT = 8,
142 ACLKM_CORE_B_DIV_CON_MASK = 0x1f << ACLKM_CORE_B_DIV_CON_SHIFT,
143 CLK_CORE_B_PLL_SEL_SHIFT = 6,
144 CLK_CORE_B_PLL_SEL_MASK = 3 << CLK_CORE_B_PLL_SEL_SHIFT,
145 CLK_CORE_B_PLL_SEL_ALPLL = 0x0,
146 CLK_CORE_B_PLL_SEL_ABPLL = 0x1,
147 CLK_CORE_B_PLL_SEL_DPLL = 0x10,
148 CLK_CORE_B_PLL_SEL_GPLL = 0x11,
149 CLK_CORE_B_DIV_MASK = 0x1f,
150 CLK_CORE_B_DIV_SHIFT = 0,
153 PCLK_DBG_B_DIV_SHIFT = 0x8,
154 PCLK_DBG_B_DIV_MASK = 0x1f << PCLK_DBG_B_DIV_SHIFT,
155 ATCLK_CORE_B_DIV_SHIFT = 0,
156 ATCLK_CORE_B_DIV_MASK = 0x1f << ATCLK_CORE_B_DIV_SHIFT,
159 PCLK_PERIHP_DIV_CON_SHIFT = 12,
160 PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT,
161 HCLK_PERIHP_DIV_CON_SHIFT = 8,
162 HCLK_PERIHP_DIV_CON_MASK = 3 << HCLK_PERIHP_DIV_CON_SHIFT,
163 ACLK_PERIHP_PLL_SEL_SHIFT = 7,
164 ACLK_PERIHP_PLL_SEL_MASK = 1 << ACLK_PERIHP_PLL_SEL_SHIFT,
165 ACLK_PERIHP_PLL_SEL_CPLL = 0,
166 ACLK_PERIHP_PLL_SEL_GPLL = 1,
167 ACLK_PERIHP_DIV_CON_SHIFT = 0,
168 ACLK_PERIHP_DIV_CON_MASK = 0x1f,
171 ACLK_EMMC_PLL_SEL_SHIFT = 7,
172 ACLK_EMMC_PLL_SEL_MASK = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT,
173 ACLK_EMMC_PLL_SEL_GPLL = 0x1,
174 ACLK_EMMC_DIV_CON_SHIFT = 0,
175 ACLK_EMMC_DIV_CON_MASK = 0x1f,
178 CLK_EMMC_PLL_SHIFT = 8,
179 CLK_EMMC_PLL_MASK = 0x7 << CLK_EMMC_PLL_SHIFT,
180 CLK_EMMC_PLL_SEL_GPLL = 0x1,
181 CLK_EMMC_PLL_SEL_24M = 0x5,
182 CLK_EMMC_DIV_CON_SHIFT = 0,
183 CLK_EMMC_DIV_CON_MASK = 0x7f << CLK_EMMC_DIV_CON_SHIFT,
186 PCLK_PERILP0_DIV_CON_SHIFT = 12,
187 PCLK_PERILP0_DIV_CON_MASK = 0x7 << PCLK_PERILP0_DIV_CON_SHIFT,
188 HCLK_PERILP0_DIV_CON_SHIFT = 8,
189 HCLK_PERILP0_DIV_CON_MASK = 3 << HCLK_PERILP0_DIV_CON_SHIFT,
190 ACLK_PERILP0_PLL_SEL_SHIFT = 7,
191 ACLK_PERILP0_PLL_SEL_MASK = 1 << ACLK_PERILP0_PLL_SEL_SHIFT,
192 ACLK_PERILP0_PLL_SEL_CPLL = 0,
193 ACLK_PERILP0_PLL_SEL_GPLL = 1,
194 ACLK_PERILP0_DIV_CON_SHIFT = 0,
195 ACLK_PERILP0_DIV_CON_MASK = 0x1f,
198 PCLK_PERILP1_DIV_CON_SHIFT = 8,
199 PCLK_PERILP1_DIV_CON_MASK = 0x7 << PCLK_PERILP1_DIV_CON_SHIFT,
200 HCLK_PERILP1_PLL_SEL_SHIFT = 7,
201 HCLK_PERILP1_PLL_SEL_MASK = 1 << HCLK_PERILP1_PLL_SEL_SHIFT,
202 HCLK_PERILP1_PLL_SEL_CPLL = 0,
203 HCLK_PERILP1_PLL_SEL_GPLL = 1,
204 HCLK_PERILP1_DIV_CON_SHIFT = 0,
205 HCLK_PERILP1_DIV_CON_MASK = 0x1f,
208 CLK_SARADC_DIV_CON_SHIFT = 8,
209 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8),
210 CLK_SARADC_DIV_CON_WIDTH = 8,
213 CLK_TSADC_SEL_X24M = 0x0,
214 CLK_TSADC_SEL_SHIFT = 15,
215 CLK_TSADC_SEL_MASK = 1 << CLK_TSADC_SEL_SHIFT,
216 CLK_TSADC_DIV_CON_SHIFT = 0,
217 CLK_TSADC_DIV_CON_MASK = 0x3ff,
219 /* CLKSEL_CON47 & CLKSEL_CON48 */
220 ACLK_VOP_PLL_SEL_SHIFT = 6,
221 ACLK_VOP_PLL_SEL_MASK = 0x3 << ACLK_VOP_PLL_SEL_SHIFT,
222 ACLK_VOP_PLL_SEL_CPLL = 0x1,
223 ACLK_VOP_DIV_CON_SHIFT = 0,
224 ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT,
226 /* CLKSEL_CON49 & CLKSEL_CON50 */
227 DCLK_VOP_DCLK_SEL_SHIFT = 11,
228 DCLK_VOP_DCLK_SEL_MASK = 1 << DCLK_VOP_DCLK_SEL_SHIFT,
229 DCLK_VOP_DCLK_SEL_DIVOUT = 0,
230 DCLK_VOP_PLL_SEL_SHIFT = 8,
231 DCLK_VOP_PLL_SEL_MASK = 3 << DCLK_VOP_PLL_SEL_SHIFT,
232 DCLK_VOP_PLL_SEL_VPLL = 0,
233 DCLK_VOP_DIV_CON_MASK = 0xff,
234 DCLK_VOP_DIV_CON_SHIFT = 0,
237 CLK_SPI_PLL_SEL_WIDTH = 1,
238 CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1),
239 CLK_SPI_PLL_SEL_CPLL = 0,
240 CLK_SPI_PLL_SEL_GPLL = 1,
241 CLK_SPI_PLL_DIV_CON_WIDTH = 7,
242 CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1),
244 CLK_SPI5_PLL_DIV_CON_SHIFT = 8,
245 CLK_SPI5_PLL_SEL_SHIFT = 15,
248 CLK_SPI1_PLL_SEL_SHIFT = 15,
249 CLK_SPI1_PLL_DIV_CON_SHIFT = 8,
250 CLK_SPI0_PLL_SEL_SHIFT = 7,
251 CLK_SPI0_PLL_DIV_CON_SHIFT = 0,
254 CLK_SPI4_PLL_SEL_SHIFT = 15,
255 CLK_SPI4_PLL_DIV_CON_SHIFT = 8,
256 CLK_SPI2_PLL_SEL_SHIFT = 7,
257 CLK_SPI2_PLL_DIV_CON_SHIFT = 0,
260 CLK_I2C_PLL_SEL_MASK = 1,
261 CLK_I2C_PLL_SEL_CPLL = 0,
262 CLK_I2C_PLL_SEL_GPLL = 1,
263 CLK_I2C5_PLL_SEL_SHIFT = 15,
264 CLK_I2C5_DIV_CON_SHIFT = 8,
265 CLK_I2C1_PLL_SEL_SHIFT = 7,
266 CLK_I2C1_DIV_CON_SHIFT = 0,
269 CLK_I2C6_PLL_SEL_SHIFT = 15,
270 CLK_I2C6_DIV_CON_SHIFT = 8,
271 CLK_I2C2_PLL_SEL_SHIFT = 7,
272 CLK_I2C2_DIV_CON_SHIFT = 0,
275 CLK_I2C7_PLL_SEL_SHIFT = 15,
276 CLK_I2C7_DIV_CON_SHIFT = 8,
277 CLK_I2C3_PLL_SEL_SHIFT = 7,
278 CLK_I2C3_DIV_CON_SHIFT = 0,
280 /* CRU_SOFTRST_CON4 */
281 RESETN_DDR0_REQ_SHIFT = 8,
282 RESETN_DDR0_REQ_MASK = 1 << RESETN_DDR0_REQ_SHIFT,
283 RESETN_DDRPHY0_REQ_SHIFT = 9,
284 RESETN_DDRPHY0_REQ_MASK = 1 << RESETN_DDRPHY0_REQ_SHIFT,
285 RESETN_DDR1_REQ_SHIFT = 12,
286 RESETN_DDR1_REQ_MASK = 1 << RESETN_DDR1_REQ_SHIFT,
287 RESETN_DDRPHY1_REQ_SHIFT = 13,
288 RESETN_DDRPHY1_REQ_MASK = 1 << RESETN_DDRPHY1_REQ_SHIFT,
291 #define VCO_MAX_KHZ (3200 * (MHz / KHz))
292 #define VCO_MIN_KHZ (800 * (MHz / KHz))
293 #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz))
294 #define OUTPUT_MIN_KHZ (16 * (MHz / KHz))
297 * the div restructions of pll in integer mode, these are defined in
298 * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0
300 #define PLL_DIV_MIN 16
301 #define PLL_DIV_MAX 3200
304 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
305 * Formulas also embedded within the Fractional PLL Verilog model:
306 * If DSMPD = 1 (DSM is disabled, "integer mode")
307 * FOUTVCO = FREF / REFDIV * FBDIV
308 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
310 * FOUTVCO = Fractional PLL non-divided output frequency
311 * FOUTPOSTDIV = Fractional PLL divided output frequency
312 * (output of second post divider)
313 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
314 * REFDIV = Fractional PLL input reference clock divider
315 * FBDIV = Integer value programmed into feedback divide
318 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div)
320 /* All 8 PLLs have same VCO and output frequency range restrictions. */
321 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv;
322 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
324 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, "
325 "postdiv2=%d, vco=%u khz, output=%u khz\n",
326 pll_con, div->fbdiv, div->refdiv, div->postdiv1,
327 div->postdiv2, vco_khz, output_khz);
328 assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
329 output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ &&
330 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX);
333 * When power on or changing PLL setting,
334 * we must force PLL into slow mode to ensure output stable clock.
336 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
337 PLL_MODE_SLOW << PLL_MODE_SHIFT);
339 /* use integer mode */
340 rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK,
341 PLL_INTEGER_MODE << PLL_DSMPD_SHIFT);
343 rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK,
344 div->fbdiv << PLL_FBDIV_SHIFT);
345 rk_clrsetreg(&pll_con[1],
346 PLL_POSTDIV2_MASK | PLL_POSTDIV1_MASK |
347 PLL_REFDIV_MASK | PLL_REFDIV_SHIFT,
348 (div->postdiv2 << PLL_POSTDIV2_SHIFT) |
349 (div->postdiv1 << PLL_POSTDIV1_SHIFT) |
350 (div->refdiv << PLL_REFDIV_SHIFT));
352 /* waiting for pll lock */
353 while (!(readl(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT)))
356 /* pll enter normal mode */
357 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
358 PLL_MODE_NORM << PLL_MODE_SHIFT);
361 static int pll_para_config(u32 freq_hz, struct pll_div *div)
363 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0;
364 u32 postdiv1, postdiv2 = 1;
366 u32 diff_khz, best_diff_khz;
367 const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16;
368 const u32 max_postdiv1 = 7, max_postdiv2 = 7;
370 u32 freq_khz = freq_hz / KHz;
373 printf("%s: the frequency can't be 0 Hz\n", __func__);
377 postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
378 if (postdiv1 > max_postdiv1) {
379 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1);
380 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2);
383 vco_khz = freq_khz * postdiv1 * postdiv2;
385 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ ||
386 postdiv2 > max_postdiv2) {
387 printf("%s: Cannot find out a supported VCO"
388 " for Frequency (%uHz).\n", __func__, freq_hz);
392 div->postdiv1 = postdiv1;
393 div->postdiv2 = postdiv2;
395 best_diff_khz = vco_khz;
396 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) {
397 fref_khz = ref_khz / refdiv;
399 fbdiv = vco_khz / fref_khz;
400 if (fbdiv >= max_fbdiv || fbdiv <= min_fbdiv)
402 diff_khz = vco_khz - fbdiv * fref_khz;
403 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) {
405 diff_khz = fref_khz - diff_khz;
408 if (diff_khz >= best_diff_khz)
411 best_diff_khz = diff_khz;
412 div->refdiv = refdiv;
416 if (best_diff_khz > 4 * (MHz / KHz)) {
417 printf("%s: Failed to match output frequency %u, "
418 "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz,
419 best_diff_khz * KHz);
425 void rk3399_configure_cpu_l(struct rockchip_cru *cru,
426 enum apll_l_frequencies apll_l_freq)
432 /* Setup cluster L */
433 rkclk_set_pll(&cru->apll_l_con[0], apll_l_cfgs[apll_l_freq]);
435 aclkm_div = LPLL_HZ / ACLKM_CORE_L_HZ - 1;
436 assert((aclkm_div + 1) * ACLKM_CORE_L_HZ == LPLL_HZ &&
439 pclk_dbg_div = LPLL_HZ / PCLK_DBG_L_HZ - 1;
440 assert((pclk_dbg_div + 1) * PCLK_DBG_L_HZ == LPLL_HZ &&
441 pclk_dbg_div < 0x1f);
443 atclk_div = LPLL_HZ / ATCLK_CORE_L_HZ - 1;
444 assert((atclk_div + 1) * ATCLK_CORE_L_HZ == LPLL_HZ &&
447 rk_clrsetreg(&cru->clksel_con[0],
448 ACLKM_CORE_L_DIV_CON_MASK | CLK_CORE_L_PLL_SEL_MASK |
450 aclkm_div << ACLKM_CORE_L_DIV_CON_SHIFT |
451 CLK_CORE_L_PLL_SEL_ALPLL << CLK_CORE_L_PLL_SEL_SHIFT |
452 0 << CLK_CORE_L_DIV_SHIFT);
454 rk_clrsetreg(&cru->clksel_con[1],
455 PCLK_DBG_L_DIV_MASK | ATCLK_CORE_L_DIV_MASK,
456 pclk_dbg_div << PCLK_DBG_L_DIV_SHIFT |
457 atclk_div << ATCLK_CORE_L_DIV_SHIFT);
460 void rk3399_configure_cpu_b(struct rockchip_cru *cru,
461 enum apll_b_frequencies apll_b_freq)
467 /* Setup cluster B */
468 rkclk_set_pll(&cru->apll_b_con[0], apll_b_cfgs[apll_b_freq]);
470 aclkm_div = BPLL_HZ / ACLKM_CORE_B_HZ - 1;
471 assert((aclkm_div + 1) * ACLKM_CORE_B_HZ == BPLL_HZ &&
474 pclk_dbg_div = BPLL_HZ / PCLK_DBG_B_HZ - 1;
475 assert((pclk_dbg_div + 1) * PCLK_DBG_B_HZ == BPLL_HZ &&
476 pclk_dbg_div < 0x1f);
478 atclk_div = BPLL_HZ / ATCLK_CORE_B_HZ - 1;
479 assert((atclk_div + 1) * ATCLK_CORE_B_HZ == BPLL_HZ &&
482 rk_clrsetreg(&cru->clksel_con[2],
483 ACLKM_CORE_B_DIV_CON_MASK | CLK_CORE_B_PLL_SEL_MASK |
485 aclkm_div << ACLKM_CORE_B_DIV_CON_SHIFT |
486 CLK_CORE_B_PLL_SEL_ABPLL << CLK_CORE_B_PLL_SEL_SHIFT |
487 0 << CLK_CORE_B_DIV_SHIFT);
489 rk_clrsetreg(&cru->clksel_con[3],
490 PCLK_DBG_B_DIV_MASK | ATCLK_CORE_B_DIV_MASK,
491 pclk_dbg_div << PCLK_DBG_B_DIV_SHIFT |
492 atclk_div << ATCLK_CORE_B_DIV_SHIFT);
495 #define I2C_CLK_REG_MASK(bus) \
496 (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT | \
497 CLK_I2C_PLL_SEL_MASK << CLK_I2C ##bus## _PLL_SEL_SHIFT)
499 #define I2C_CLK_REG_VALUE(bus, clk_div) \
500 ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT | \
501 CLK_I2C_PLL_SEL_GPLL << CLK_I2C ##bus## _PLL_SEL_SHIFT)
503 #define I2C_CLK_DIV_VALUE(con, bus) \
504 ((con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & I2C_DIV_CON_MASK)
506 #define I2C_PMUCLK_REG_MASK(bus) \
507 (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT)
509 #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \
510 ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT)
512 static ulong rk3399_i2c_get_clk(struct rockchip_cru *cru, ulong clk_id)
518 con = readl(&cru->clksel_con[61]);
519 div = I2C_CLK_DIV_VALUE(con, 1);
522 con = readl(&cru->clksel_con[62]);
523 div = I2C_CLK_DIV_VALUE(con, 2);
526 con = readl(&cru->clksel_con[63]);
527 div = I2C_CLK_DIV_VALUE(con, 3);
530 con = readl(&cru->clksel_con[61]);
531 div = I2C_CLK_DIV_VALUE(con, 5);
534 con = readl(&cru->clksel_con[62]);
535 div = I2C_CLK_DIV_VALUE(con, 6);
538 con = readl(&cru->clksel_con[63]);
539 div = I2C_CLK_DIV_VALUE(con, 7);
542 printf("do not support this i2c bus\n");
546 return DIV_TO_RATE(GPLL_HZ, div);
549 static ulong rk3399_i2c_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
553 /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/
554 src_clk_div = GPLL_HZ / hz;
555 assert(src_clk_div - 1 < 127);
559 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1),
560 I2C_CLK_REG_VALUE(1, src_clk_div));
563 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2),
564 I2C_CLK_REG_VALUE(2, src_clk_div));
567 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3),
568 I2C_CLK_REG_VALUE(3, src_clk_div));
571 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(5),
572 I2C_CLK_REG_VALUE(5, src_clk_div));
575 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(6),
576 I2C_CLK_REG_VALUE(6, src_clk_div));
579 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(7),
580 I2C_CLK_REG_VALUE(7, src_clk_div));
583 printf("do not support this i2c bus\n");
587 return rk3399_i2c_get_clk(cru, clk_id);
591 * RK3399 SPI clocks have a common divider-width (7 bits) and a single bit
592 * to select either CPLL or GPLL as the clock-parent. The location within
593 * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable.
597 u8 reg; /* CLKSEL_CON[reg] register in CRU */
603 * The entries are numbered relative to their offset from SCLK_SPI0.
605 * Note that SCLK_SPI3 (which is configured via PMUCRU and requires different
606 * logic is not supported).
608 static const struct spi_clkreg spi_clkregs[] = {
610 .div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT,
611 .sel_shift = CLK_SPI0_PLL_SEL_SHIFT, },
613 .div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT,
614 .sel_shift = CLK_SPI1_PLL_SEL_SHIFT, },
616 .div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT,
617 .sel_shift = CLK_SPI2_PLL_SEL_SHIFT, },
619 .div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT,
620 .sel_shift = CLK_SPI4_PLL_SEL_SHIFT, },
622 .div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT,
623 .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, },
626 static ulong rk3399_spi_get_clk(struct rockchip_cru *cru, ulong clk_id)
628 const struct spi_clkreg *spiclk = NULL;
632 case SCLK_SPI0 ... SCLK_SPI5:
633 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
637 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
641 val = readl(&cru->clksel_con[spiclk->reg]);
642 div = bitfield_extract(val, spiclk->div_shift,
643 CLK_SPI_PLL_DIV_CON_WIDTH);
645 return DIV_TO_RATE(GPLL_HZ, div);
648 static ulong rk3399_spi_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
650 const struct spi_clkreg *spiclk = NULL;
653 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
654 assert(src_clk_div < 128);
657 case SCLK_SPI1 ... SCLK_SPI5:
658 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
662 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
666 rk_clrsetreg(&cru->clksel_con[spiclk->reg],
667 ((CLK_SPI_PLL_DIV_CON_MASK << spiclk->div_shift) |
668 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)),
669 ((src_clk_div << spiclk->div_shift) |
670 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)));
672 return rk3399_spi_get_clk(cru, clk_id);
675 static ulong rk3399_vop_set_clk(struct rockchip_cru *cru, ulong clk_id, u32 hz)
677 struct pll_div vpll_config = {0};
678 int aclk_vop = 198 * MHz;
679 void *aclkreg_addr, *dclkreg_addr;
684 aclkreg_addr = &cru->clksel_con[47];
685 dclkreg_addr = &cru->clksel_con[49];
688 aclkreg_addr = &cru->clksel_con[48];
689 dclkreg_addr = &cru->clksel_con[50];
694 /* vop aclk source clk: cpll */
695 div = CPLL_HZ / aclk_vop;
696 assert(div - 1 < 32);
698 rk_clrsetreg(aclkreg_addr,
699 ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK,
700 ACLK_VOP_PLL_SEL_CPLL << ACLK_VOP_PLL_SEL_SHIFT |
701 (div - 1) << ACLK_VOP_DIV_CON_SHIFT);
703 /* vop dclk source from vpll, and equals to vpll(means div == 1) */
704 if (pll_para_config(hz, &vpll_config))
707 rkclk_set_pll(&cru->vpll_con[0], &vpll_config);
709 rk_clrsetreg(dclkreg_addr,
710 DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK |
711 DCLK_VOP_DIV_CON_MASK,
712 DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT |
713 DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT |
714 (1 - 1) << DCLK_VOP_DIV_CON_SHIFT);
719 static ulong rk3399_mmc_get_clk(struct rockchip_cru *cru, uint clk_id)
726 con = readl(&cru->clksel_con[16]);
727 /* dwmmc controller have internal div 2 */
731 con = readl(&cru->clksel_con[21]);
738 div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
739 if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
740 == CLK_EMMC_PLL_SEL_24M)
741 return DIV_TO_RATE(OSC_HZ, div);
743 return DIV_TO_RATE(GPLL_HZ, div);
746 static ulong rk3399_mmc_set_clk(struct rockchip_cru *cru,
747 ulong clk_id, ulong set_rate)
750 int aclk_emmc = 198 * MHz;
755 /* Select clk_sdmmc source from GPLL by default */
756 /* mmc clock defaulg div 2 internal, provide double in cru */
757 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);
759 if (src_clk_div > 128) {
760 /* use 24MHz source for 400KHz clock */
761 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
762 assert(src_clk_div - 1 < 128);
763 rk_clrsetreg(&cru->clksel_con[16],
764 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
765 CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
766 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
768 rk_clrsetreg(&cru->clksel_con[16],
769 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
770 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
771 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
775 /* Select aclk_emmc source from GPLL */
776 src_clk_div = DIV_ROUND_UP(GPLL_HZ, aclk_emmc);
777 assert(src_clk_div - 1 < 32);
779 rk_clrsetreg(&cru->clksel_con[21],
780 ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK,
781 ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT |
782 (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT);
784 /* Select clk_emmc source from GPLL too */
785 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate);
786 assert(src_clk_div - 1 < 128);
788 rk_clrsetreg(&cru->clksel_con[22],
789 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
790 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
791 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
796 return rk3399_mmc_get_clk(cru, clk_id);
799 static ulong rk3399_gmac_set_clk(struct rockchip_cru *cru, ulong rate)
804 * The RGMII CLK can be derived either from an external "clkin"
805 * or can be generated from internally by a divider from SCLK_MAC.
807 if (readl(&cru->clksel_con[19]) & BIT(4)) {
808 /* An external clock will always generate the right rate... */
812 * No platform uses an internal clock to date.
813 * Implement this once it becomes necessary and print an error
814 * if someone tries to use it (while it remains unimplemented).
816 pr_err("%s: internal clock is UNIMPLEMENTED\n", __func__);
823 #define PMUSGRF_DDR_RGN_CON16 0xff330040
824 static ulong rk3399_ddr_set_clk(struct rockchip_cru *cru,
827 struct pll_div dpll_cfg;
829 /* IC ECO bug, need to set this register */
830 writel(0xc000c000, PMUSGRF_DDR_RGN_CON16);
832 /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
835 dpll_cfg = (struct pll_div)
836 {.refdiv = 1, .fbdiv = 12, .postdiv1 = 3, .postdiv2 = 2};
839 dpll_cfg = (struct pll_div)
840 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1};
843 dpll_cfg = (struct pll_div)
844 {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1};
847 dpll_cfg = (struct pll_div)
848 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
851 dpll_cfg = (struct pll_div)
852 {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1};
855 dpll_cfg = (struct pll_div)
856 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
859 dpll_cfg = (struct pll_div)
860 {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1};
863 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate);
865 rkclk_set_pll(&cru->dpll_con[0], &dpll_cfg);
870 static ulong rk3399_saradc_get_clk(struct rockchip_cru *cru)
874 val = readl(&cru->clksel_con[26]);
875 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
876 CLK_SARADC_DIV_CON_WIDTH);
878 return DIV_TO_RATE(OSC_HZ, div);
881 static ulong rk3399_saradc_set_clk(struct rockchip_cru *cru, uint hz)
885 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
886 assert(src_clk_div < 128);
888 rk_clrsetreg(&cru->clksel_con[26],
889 CLK_SARADC_DIV_CON_MASK,
890 src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
892 return rk3399_saradc_get_clk(cru);
895 static ulong rk3399_clk_get_rate(struct clk *clk)
897 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
906 rate = rk3399_mmc_get_clk(priv->cru, clk->id);
914 rate = rk3399_i2c_get_clk(priv->cru, clk->id);
916 case SCLK_SPI0...SCLK_SPI5:
917 rate = rk3399_spi_get_clk(priv->cru, clk->id);
929 case PCLK_EFUSE1024NS:
932 rate = rk3399_saradc_get_clk(priv->cru);
940 log_debug("Unknown clock %lu\n", clk->id);
947 static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
949 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
976 ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate);
979 ret = rk3399_gmac_set_clk(priv->cru, rate);
987 ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate);
989 case SCLK_SPI0...SCLK_SPI5:
990 ret = rk3399_spi_set_clk(priv->cru, clk->id, rate);
994 /* the PCLK gates for video are enabled by default */
998 ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);
1004 * assigned-clocks handling won't require for vopl, so
1005 * return 0 to satisfy clk_set_defaults during device probe.
1009 ret = rk3399_ddr_set_clk(priv->cru, rate);
1011 case PCLK_EFUSE1024NS:
1014 ret = rk3399_saradc_set_clk(priv->cru, rate);
1022 log_debug("Unknown clock %lu\n", clk->id);
1029 static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk,
1032 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
1033 const char *clock_output_name;
1037 * If the requested parent is in the same clock-controller and
1038 * the id is SCLK_MAC ("clk_gmac"), switch to the internal clock.
1040 if (parent->dev == clk->dev && parent->id == SCLK_MAC) {
1041 debug("%s: switching RGMII to SCLK_MAC\n", __func__);
1042 rk_clrreg(&priv->cru->clksel_con[19], BIT(4));
1047 * Otherwise, we need to check the clock-output-names of the
1048 * requested parent to see if the requested id is "clkin_gmac".
1050 ret = dev_read_string_index(parent->dev, "clock-output-names",
1051 parent->id, &clock_output_name);
1055 /* If this is "clkin_gmac", switch to the external clock input */
1056 if (!strcmp(clock_output_name, "clkin_gmac")) {
1057 debug("%s: switching RGMII to CLKIN\n", __func__);
1058 rk_setreg(&priv->cru->clksel_con[19], BIT(4));
1065 static int __maybe_unused rk3399_clk_set_parent(struct clk *clk,
1070 return rk3399_gmac_set_parent(clk, parent);
1073 debug("%s: unsupported clk %ld\n", __func__, clk->id);
1077 static int rk3399_clk_enable(struct clk *clk)
1079 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
1083 rk_clrreg(&priv->cru->clkgate_con[5], BIT(5));
1086 rk_clrreg(&priv->cru->clkgate_con[5], BIT(8));
1089 rk_clrreg(&priv->cru->clkgate_con[5], BIT(9));
1092 rk_clrreg(&priv->cru->clkgate_con[5], BIT(7));
1094 case SCLK_MACREF_OUT:
1095 rk_clrreg(&priv->cru->clkgate_con[5], BIT(6));
1098 rk_clrreg(&priv->cru->clkgate_con[32], BIT(0));
1101 rk_clrreg(&priv->cru->clkgate_con[32], BIT(2));
1103 case SCLK_USB3OTG0_REF:
1104 rk_clrreg(&priv->cru->clkgate_con[12], BIT(1));
1106 case SCLK_USB3OTG1_REF:
1107 rk_clrreg(&priv->cru->clkgate_con[12], BIT(2));
1109 case SCLK_USB3OTG0_SUSPEND:
1110 rk_clrreg(&priv->cru->clkgate_con[12], BIT(3));
1112 case SCLK_USB3OTG1_SUSPEND:
1113 rk_clrreg(&priv->cru->clkgate_con[12], BIT(4));
1116 rk_clrreg(&priv->cru->clkgate_con[30], BIT(1));
1119 rk_clrreg(&priv->cru->clkgate_con[30], BIT(2));
1121 case ACLK_USB3_RKSOC_AXI_PERF:
1122 rk_clrreg(&priv->cru->clkgate_con[30], BIT(3));
1125 rk_clrreg(&priv->cru->clkgate_con[12], BIT(0));
1128 rk_clrreg(&priv->cru->clkgate_con[30], BIT(4));
1131 rk_clrreg(&priv->cru->clksel_con[20], BIT(5));
1133 case HCLK_HOST0_ARB:
1134 rk_clrreg(&priv->cru->clksel_con[20], BIT(6));
1137 rk_clrreg(&priv->cru->clksel_con[20], BIT(7));
1139 case HCLK_HOST1_ARB:
1140 rk_clrreg(&priv->cru->clksel_con[20], BIT(8));
1142 case SCLK_PCIEPHY_REF:
1143 rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
1146 debug("%s: unsupported clk %ld\n", __func__, clk->id);
1153 static int rk3399_clk_disable(struct clk *clk)
1155 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
1159 rk_setreg(&priv->cru->clkgate_con[5], BIT(5));
1162 rk_setreg(&priv->cru->clkgate_con[5], BIT(8));
1165 rk_setreg(&priv->cru->clkgate_con[5], BIT(9));
1168 rk_setreg(&priv->cru->clkgate_con[5], BIT(7));
1170 case SCLK_MACREF_OUT:
1171 rk_setreg(&priv->cru->clkgate_con[5], BIT(6));
1174 rk_setreg(&priv->cru->clkgate_con[32], BIT(0));
1177 rk_setreg(&priv->cru->clkgate_con[32], BIT(2));
1179 case SCLK_USB3OTG0_REF:
1180 rk_setreg(&priv->cru->clkgate_con[12], BIT(1));
1182 case SCLK_USB3OTG1_REF:
1183 rk_setreg(&priv->cru->clkgate_con[12], BIT(2));
1185 case SCLK_USB3OTG0_SUSPEND:
1186 rk_setreg(&priv->cru->clkgate_con[12], BIT(3));
1188 case SCLK_USB3OTG1_SUSPEND:
1189 rk_setreg(&priv->cru->clkgate_con[12], BIT(4));
1192 rk_setreg(&priv->cru->clkgate_con[30], BIT(1));
1195 rk_setreg(&priv->cru->clkgate_con[30], BIT(2));
1197 case ACLK_USB3_RKSOC_AXI_PERF:
1198 rk_setreg(&priv->cru->clkgate_con[30], BIT(3));
1201 rk_setreg(&priv->cru->clkgate_con[12], BIT(0));
1204 rk_setreg(&priv->cru->clkgate_con[30], BIT(4));
1207 rk_setreg(&priv->cru->clksel_con[20], BIT(5));
1209 case HCLK_HOST0_ARB:
1210 rk_setreg(&priv->cru->clksel_con[20], BIT(6));
1213 rk_setreg(&priv->cru->clksel_con[20], BIT(7));
1215 case HCLK_HOST1_ARB:
1216 rk_setreg(&priv->cru->clksel_con[20], BIT(8));
1218 case SCLK_PCIEPHY_REF:
1219 rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
1222 debug("%s: unsupported clk %ld\n", __func__, clk->id);
1229 static struct clk_ops rk3399_clk_ops = {
1230 .get_rate = rk3399_clk_get_rate,
1231 .set_rate = rk3399_clk_set_rate,
1232 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1233 .set_parent = rk3399_clk_set_parent,
1235 .enable = rk3399_clk_enable,
1236 .disable = rk3399_clk_disable,
1239 #ifdef CONFIG_SPL_BUILD
1240 static void rkclk_init(struct rockchip_cru *cru)
1246 rk3399_configure_cpu_l(cru, APLL_L_600_MHZ);
1247 rk3399_configure_cpu_b(cru, APLL_B_600_MHZ);
1249 * some cru registers changed by bootrom, we'd better reset them to
1250 * reset/default values described in TRM to avoid confusion in kernel.
1251 * Please consider these three lines as a fix of bootrom bug.
1253 rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101);
1254 rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f);
1255 rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003);
1257 /* configure gpll cpll */
1258 rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg);
1259 rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg);
1261 /* configure perihp aclk, hclk, pclk */
1262 aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
1263 assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
1265 hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
1266 assert((hclk_div + 1) * PERIHP_HCLK_HZ ==
1267 PERIHP_ACLK_HZ && (hclk_div < 0x4));
1269 pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
1270 assert((pclk_div + 1) * PERIHP_PCLK_HZ ==
1271 PERIHP_ACLK_HZ && (pclk_div < 0x7));
1273 rk_clrsetreg(&cru->clksel_con[14],
1274 PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK |
1275 ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK,
1276 pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
1277 hclk_div << HCLK_PERIHP_DIV_CON_SHIFT |
1278 ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT |
1279 aclk_div << ACLK_PERIHP_DIV_CON_SHIFT);
1281 /* configure perilp0 aclk, hclk, pclk */
1282 aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1;
1283 assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
1285 hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1;
1286 assert((hclk_div + 1) * PERILP0_HCLK_HZ ==
1287 PERILP0_ACLK_HZ && (hclk_div < 0x4));
1289 pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1;
1290 assert((pclk_div + 1) * PERILP0_PCLK_HZ ==
1291 PERILP0_ACLK_HZ && (pclk_div < 0x7));
1293 rk_clrsetreg(&cru->clksel_con[23],
1294 PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK |
1295 ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK,
1296 pclk_div << PCLK_PERILP0_DIV_CON_SHIFT |
1297 hclk_div << HCLK_PERILP0_DIV_CON_SHIFT |
1298 ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT |
1299 aclk_div << ACLK_PERILP0_DIV_CON_SHIFT);
1301 /* perilp1 hclk select gpll as source */
1302 hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1;
1303 assert((hclk_div + 1) * PERILP1_HCLK_HZ ==
1304 GPLL_HZ && (hclk_div < 0x1f));
1306 pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1;
1307 assert((pclk_div + 1) * PERILP1_HCLK_HZ ==
1308 PERILP1_HCLK_HZ && (hclk_div < 0x7));
1310 rk_clrsetreg(&cru->clksel_con[25],
1311 PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK |
1312 HCLK_PERILP1_PLL_SEL_MASK,
1313 pclk_div << PCLK_PERILP1_DIV_CON_SHIFT |
1314 hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
1315 HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
1319 static int rk3399_clk_probe(struct udevice *dev)
1321 #ifdef CONFIG_SPL_BUILD
1322 struct rk3399_clk_priv *priv = dev_get_priv(dev);
1324 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1325 struct rk3399_clk_plat *plat = dev_get_platdata(dev);
1327 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
1329 rkclk_init(priv->cru);
1334 static int rk3399_clk_ofdata_to_platdata(struct udevice *dev)
1336 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1337 struct rk3399_clk_priv *priv = dev_get_priv(dev);
1339 priv->cru = dev_read_addr_ptr(dev);
1344 static int rk3399_clk_bind(struct udevice *dev)
1347 struct udevice *sys_child;
1348 struct sysreset_reg *priv;
1350 /* The reset driver does not have a device node, so bind it here */
1351 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
1354 debug("Warning: No sysreset driver: ret=%d\n", ret);
1356 priv = malloc(sizeof(struct sysreset_reg));
1357 priv->glb_srst_fst_value = offsetof(struct rockchip_cru,
1358 glb_srst_fst_value);
1359 priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
1360 glb_srst_snd_value);
1361 sys_child->priv = priv;
1364 #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
1365 ret = offsetof(struct rockchip_cru, softrst_con[0]);
1366 ret = rockchip_reset_bind(dev, ret, 21);
1368 debug("Warning: software reset driver bind faile\n");
1374 static const struct udevice_id rk3399_clk_ids[] = {
1375 { .compatible = "rockchip,rk3399-cru" },
1379 U_BOOT_DRIVER(clk_rk3399) = {
1380 .name = "rockchip_rk3399_cru",
1382 .of_match = rk3399_clk_ids,
1383 .priv_auto_alloc_size = sizeof(struct rk3399_clk_priv),
1384 .ofdata_to_platdata = rk3399_clk_ofdata_to_platdata,
1385 .ops = &rk3399_clk_ops,
1386 .bind = rk3399_clk_bind,
1387 .probe = rk3399_clk_probe,
1388 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1389 .platdata_auto_alloc_size = sizeof(struct rk3399_clk_plat),
1393 static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id)
1399 con = readl(&pmucru->pmucru_clksel[2]);
1400 div = I2C_CLK_DIV_VALUE(con, 0);
1403 con = readl(&pmucru->pmucru_clksel[3]);
1404 div = I2C_CLK_DIV_VALUE(con, 4);
1407 con = readl(&pmucru->pmucru_clksel[2]);
1408 div = I2C_CLK_DIV_VALUE(con, 8);
1411 printf("do not support this i2c bus\n");
1415 return DIV_TO_RATE(PPLL_HZ, div);
1418 static ulong rk3399_i2c_set_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id,
1423 src_clk_div = PPLL_HZ / hz;
1424 assert(src_clk_div - 1 < 127);
1428 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(0),
1429 I2C_PMUCLK_REG_VALUE(0, src_clk_div));
1432 rk_clrsetreg(&pmucru->pmucru_clksel[3], I2C_PMUCLK_REG_MASK(4),
1433 I2C_PMUCLK_REG_VALUE(4, src_clk_div));
1436 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(8),
1437 I2C_PMUCLK_REG_VALUE(8, src_clk_div));
1440 printf("do not support this i2c bus\n");
1444 return DIV_TO_RATE(PPLL_HZ, src_clk_div);
1447 static ulong rk3399_pwm_get_clk(struct rk3399_pmucru *pmucru)
1451 /* PWM closk rate is same as pclk_pmu */
1452 con = readl(&pmucru->pmucru_clksel[0]);
1453 div = con & PMU_PCLK_DIV_CON_MASK;
1455 return DIV_TO_RATE(PPLL_HZ, div);
1458 static ulong rk3399_pmuclk_get_rate(struct clk *clk)
1460 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
1466 case PCLK_RKPWM_PMU:
1467 rate = rk3399_pwm_get_clk(priv->pmucru);
1472 rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id);
1481 static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate)
1483 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
1489 * This has already been set up and we don't want/need
1490 * to change it here. Accept the request though, as the
1491 * device-tree has this in an 'assigned-clocks' list.
1497 ret = rk3399_i2c_set_pmuclk(priv->pmucru, clk->id, rate);
1506 static struct clk_ops rk3399_pmuclk_ops = {
1507 .get_rate = rk3399_pmuclk_get_rate,
1508 .set_rate = rk3399_pmuclk_set_rate,
1511 #ifndef CONFIG_SPL_BUILD
1512 static void pmuclk_init(struct rk3399_pmucru *pmucru)
1516 /* configure pmu pll(ppll) */
1517 rkclk_set_pll(&pmucru->ppll_con[0], &ppll_init_cfg);
1519 /* configure pmu pclk */
1520 pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1;
1521 rk_clrsetreg(&pmucru->pmucru_clksel[0],
1522 PMU_PCLK_DIV_CON_MASK,
1523 pclk_div << PMU_PCLK_DIV_CON_SHIFT);
1527 static int rk3399_pmuclk_probe(struct udevice *dev)
1529 #if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD)
1530 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
1533 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1534 struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev);
1536 priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
1539 #ifndef CONFIG_SPL_BUILD
1540 pmuclk_init(priv->pmucru);
1545 static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev)
1547 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1548 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
1550 priv->pmucru = dev_read_addr_ptr(dev);
1555 static int rk3399_pmuclk_bind(struct udevice *dev)
1557 #if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
1560 ret = offsetof(struct rk3399_pmucru, pmucru_softrst_con[0]);
1561 ret = rockchip_reset_bind(dev, ret, 2);
1563 debug("Warning: software reset driver bind faile\n");
1568 static const struct udevice_id rk3399_pmuclk_ids[] = {
1569 { .compatible = "rockchip,rk3399-pmucru" },
1573 U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = {
1574 .name = "rockchip_rk3399_pmucru",
1576 .of_match = rk3399_pmuclk_ids,
1577 .priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv),
1578 .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata,
1579 .ops = &rk3399_pmuclk_ops,
1580 .probe = rk3399_pmuclk_probe,
1581 .bind = rk3399_pmuclk_bind,
1582 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1583 .platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat),