drivers/clk/rockchip/clk_rk3399.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * (C) Copyright 2015 Google, Inc
   4  * (C) 2017 Theobroma Systems Design und Consulting GmbH
   5  */
   6
   7 #include <common.h>
   8 #include <clk-uclass.h>
   9 #include <dm.h>
  10 #include <dt-structs.h>
  11 #include <errno.h>
  12 #include <log.h>
  13 #include <malloc.h>
  14 #include <mapmem.h>
  15 #include <syscon.h>
  16 #include <bitfield.h>
  17 #include <asm/io.h>
  18 #include <asm/arch-rockchip/clock.h>
  19 #include <asm/arch-rockchip/cru.h>
  20 #include <asm/arch-rockchip/hardware.h>
  21 #include <asm/global_data.h>
  22 #include <dm/device-internal.h>
  23 #include <dm/lists.h>
  24 #include <dt-bindings/clock/rk3399-cru.h>
  25 #include <linux/bitops.h>
  26 #include <linux/delay.h>
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  31 struct rk3399_clk_plat {
  32         struct dtd_rockchip_rk3399_cru dtd;
  33 };
  34
  35 struct rk3399_pmuclk_plat {
  36         struct dtd_rockchip_rk3399_pmucru dtd;
  37 };
  38 #endif
  39
  40 struct pll_div {
  41         u32 refdiv;
  42         u32 fbdiv;
  43         u32 postdiv1;
  44         u32 postdiv2;
  45         u32 frac;
  46 };
  47
  48 #define RATE_TO_DIV(input_rate, output_rate) \
  49         ((input_rate) / (output_rate) - 1)
  50 #define DIV_TO_RATE(input_rate, div)            ((input_rate) / ((div) + 1))
  51
  52 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
  53         .refdiv = _refdiv,\
  54         .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
  55         .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
  56
  57 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
  58 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
  59 #if !defined(CONFIG_SPL_BUILD)
  60 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
  61 #endif
  62
  63 static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600 * MHz, 3, 1, 1);
  64 static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
  65
  66 static const struct pll_div *apll_l_cfgs[] = {
  67         [APLL_L_1600_MHZ] = &apll_l_1600_cfg,
  68         [APLL_L_600_MHZ] = &apll_l_600_cfg,
  69 };
  70
  71 static const struct pll_div apll_b_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
  72 static const struct pll_div *apll_b_cfgs[] = {
  73         [APLL_B_600_MHZ] = &apll_b_600_cfg,
  74 };
  75
  76 enum {
  77         /* PLL_CON0 */
  78         PLL_FBDIV_MASK                  = 0xfff,
  79         PLL_FBDIV_SHIFT                 = 0,
  80
  81         /* PLL_CON1 */
  82         PLL_POSTDIV2_SHIFT              = 12,
  83         PLL_POSTDIV2_MASK               = 0x7 << PLL_POSTDIV2_SHIFT,
  84         PLL_POSTDIV1_SHIFT              = 8,
  85         PLL_POSTDIV1_MASK               = 0x7 << PLL_POSTDIV1_SHIFT,
  86         PLL_REFDIV_MASK                 = 0x3f,
  87         PLL_REFDIV_SHIFT                = 0,
  88
  89         /* PLL_CON2 */
  90         PLL_LOCK_STATUS_SHIFT           = 31,
  91         PLL_LOCK_STATUS_MASK            = 1 << PLL_LOCK_STATUS_SHIFT,
  92         PLL_FRACDIV_MASK                = 0xffffff,
  93         PLL_FRACDIV_SHIFT               = 0,
  94
  95         /* PLL_CON3 */
  96         PLL_MODE_SHIFT                  = 8,
  97         PLL_MODE_MASK                   = 3 << PLL_MODE_SHIFT,
  98         PLL_MODE_SLOW                   = 0,
  99         PLL_MODE_NORM,
 100         PLL_MODE_DEEP,
 101         PLL_DSMPD_SHIFT                 = 3,
 102         PLL_DSMPD_MASK                  = 1 << PLL_DSMPD_SHIFT,
 103         PLL_INTEGER_MODE                = 1,
 104
 105         /* PMUCRU_CLKSEL_CON0 */
 106         PMU_PCLK_DIV_CON_MASK           = 0x1f,
 107         PMU_PCLK_DIV_CON_SHIFT          = 0,
 108
 109         /* PMUCRU_CLKSEL_CON1 */
 110         SPI3_PLL_SEL_SHIFT              = 7,
 111         SPI3_PLL_SEL_MASK               = 1 << SPI3_PLL_SEL_SHIFT,
 112         SPI3_PLL_SEL_24M                = 0,
 113         SPI3_PLL_SEL_PPLL               = 1,
 114         SPI3_DIV_CON_SHIFT              = 0x0,
 115         SPI3_DIV_CON_MASK               = 0x7f,
 116
 117         /* PMUCRU_CLKSEL_CON2 */
 118         I2C_DIV_CON_MASK                = 0x7f,
 119         CLK_I2C8_DIV_CON_SHIFT          = 8,
 120         CLK_I2C0_DIV_CON_SHIFT          = 0,
 121
 122         /* PMUCRU_CLKSEL_CON3 */
 123         CLK_I2C4_DIV_CON_SHIFT          = 0,
 124
 125         /* CLKSEL_CON0 */
 126         ACLKM_CORE_L_DIV_CON_SHIFT      = 8,
 127         ACLKM_CORE_L_DIV_CON_MASK       = 0x1f << ACLKM_CORE_L_DIV_CON_SHIFT,
 128         CLK_CORE_L_PLL_SEL_SHIFT        = 6,
 129         CLK_CORE_L_PLL_SEL_MASK         = 3 << CLK_CORE_L_PLL_SEL_SHIFT,
 130         CLK_CORE_L_PLL_SEL_ALPLL        = 0x0,
 131         CLK_CORE_L_PLL_SEL_ABPLL        = 0x1,
 132         CLK_CORE_L_PLL_SEL_DPLL         = 0x10,
 133         CLK_CORE_L_PLL_SEL_GPLL         = 0x11,
 134         CLK_CORE_L_DIV_MASK             = 0x1f,
 135         CLK_CORE_L_DIV_SHIFT            = 0,
 136
 137         /* CLKSEL_CON1 */
 138         PCLK_DBG_L_DIV_SHIFT            = 0x8,
 139         PCLK_DBG_L_DIV_MASK             = 0x1f << PCLK_DBG_L_DIV_SHIFT,
 140         ATCLK_CORE_L_DIV_SHIFT          = 0,
 141         ATCLK_CORE_L_DIV_MASK           = 0x1f << ATCLK_CORE_L_DIV_SHIFT,
 142
 143         /* CLKSEL_CON2 */
 144         ACLKM_CORE_B_DIV_CON_SHIFT      = 8,
 145         ACLKM_CORE_B_DIV_CON_MASK       = 0x1f << ACLKM_CORE_B_DIV_CON_SHIFT,
 146         CLK_CORE_B_PLL_SEL_SHIFT        = 6,
 147         CLK_CORE_B_PLL_SEL_MASK         = 3 << CLK_CORE_B_PLL_SEL_SHIFT,
 148         CLK_CORE_B_PLL_SEL_ALPLL        = 0x0,
 149         CLK_CORE_B_PLL_SEL_ABPLL        = 0x1,
 150         CLK_CORE_B_PLL_SEL_DPLL         = 0x10,
 151         CLK_CORE_B_PLL_SEL_GPLL         = 0x11,
 152         CLK_CORE_B_DIV_MASK             = 0x1f,
 153         CLK_CORE_B_DIV_SHIFT            = 0,
 154
 155         /* CLKSEL_CON3 */
 156         PCLK_DBG_B_DIV_SHIFT            = 0x8,
 157         PCLK_DBG_B_DIV_MASK             = 0x1f << PCLK_DBG_B_DIV_SHIFT,
 158         ATCLK_CORE_B_DIV_SHIFT          = 0,
 159         ATCLK_CORE_B_DIV_MASK           = 0x1f << ATCLK_CORE_B_DIV_SHIFT,
 160
 161         /* CLKSEL_CON14 */
 162         PCLK_PERIHP_DIV_CON_SHIFT       = 12,
 163         PCLK_PERIHP_DIV_CON_MASK        = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT,
 164         HCLK_PERIHP_DIV_CON_SHIFT       = 8,
 165         HCLK_PERIHP_DIV_CON_MASK        = 3 << HCLK_PERIHP_DIV_CON_SHIFT,
 166         ACLK_PERIHP_PLL_SEL_SHIFT       = 7,
 167         ACLK_PERIHP_PLL_SEL_MASK        = 1 << ACLK_PERIHP_PLL_SEL_SHIFT,
 168         ACLK_PERIHP_PLL_SEL_CPLL        = 0,
 169         ACLK_PERIHP_PLL_SEL_GPLL        = 1,
 170         ACLK_PERIHP_DIV_CON_SHIFT       = 0,
 171         ACLK_PERIHP_DIV_CON_MASK        = 0x1f,
 172
 173         /* CLKSEL_CON21 */
 174         ACLK_EMMC_PLL_SEL_SHIFT         = 7,
 175         ACLK_EMMC_PLL_SEL_MASK          = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT,
 176         ACLK_EMMC_PLL_SEL_GPLL          = 0x1,
 177         ACLK_EMMC_DIV_CON_SHIFT         = 0,
 178         ACLK_EMMC_DIV_CON_MASK          = 0x1f,
 179
 180         /* CLKSEL_CON22 */
 181         CLK_EMMC_PLL_SHIFT              = 8,
 182         CLK_EMMC_PLL_MASK               = 0x7 << CLK_EMMC_PLL_SHIFT,
 183         CLK_EMMC_PLL_SEL_GPLL           = 0x1,
 184         CLK_EMMC_PLL_SEL_24M            = 0x5,
 185         CLK_EMMC_DIV_CON_SHIFT          = 0,
 186         CLK_EMMC_DIV_CON_MASK           = 0x7f << CLK_EMMC_DIV_CON_SHIFT,
 187
 188         /* CLKSEL_CON23 */
 189         PCLK_PERILP0_DIV_CON_SHIFT      = 12,
 190         PCLK_PERILP0_DIV_CON_MASK       = 0x7 << PCLK_PERILP0_DIV_CON_SHIFT,
 191         HCLK_PERILP0_DIV_CON_SHIFT      = 8,
 192         HCLK_PERILP0_DIV_CON_MASK       = 3 << HCLK_PERILP0_DIV_CON_SHIFT,
 193         ACLK_PERILP0_PLL_SEL_SHIFT      = 7,
 194         ACLK_PERILP0_PLL_SEL_MASK       = 1 << ACLK_PERILP0_PLL_SEL_SHIFT,
 195         ACLK_PERILP0_PLL_SEL_CPLL       = 0,
 196         ACLK_PERILP0_PLL_SEL_GPLL       = 1,
 197         ACLK_PERILP0_DIV_CON_SHIFT      = 0,
 198         ACLK_PERILP0_DIV_CON_MASK       = 0x1f,
 199
 200         /* CLKSEL_CON25 */
 201         PCLK_PERILP1_DIV_CON_SHIFT      = 8,
 202         PCLK_PERILP1_DIV_CON_MASK       = 0x7 << PCLK_PERILP1_DIV_CON_SHIFT,
 203         HCLK_PERILP1_PLL_SEL_SHIFT      = 7,
 204         HCLK_PERILP1_PLL_SEL_MASK       = 1 << HCLK_PERILP1_PLL_SEL_SHIFT,
 205         HCLK_PERILP1_PLL_SEL_CPLL       = 0,
 206         HCLK_PERILP1_PLL_SEL_GPLL       = 1,
 207         HCLK_PERILP1_DIV_CON_SHIFT      = 0,
 208         HCLK_PERILP1_DIV_CON_MASK       = 0x1f,
 209
 210         /* CLKSEL_CON26 */
 211         CLK_SARADC_DIV_CON_SHIFT        = 8,
 212         CLK_SARADC_DIV_CON_MASK         = GENMASK(15, 8),
 213         CLK_SARADC_DIV_CON_WIDTH        = 8,
 214
 215         /* CLKSEL_CON27 */
 216         CLK_TSADC_SEL_X24M              = 0x0,
 217         CLK_TSADC_SEL_SHIFT             = 15,
 218         CLK_TSADC_SEL_MASK              = 1 << CLK_TSADC_SEL_SHIFT,
 219         CLK_TSADC_DIV_CON_SHIFT         = 0,
 220         CLK_TSADC_DIV_CON_MASK          = 0x3ff,
 221
 222         /* CLKSEL_CON47 & CLKSEL_CON48 */
 223         ACLK_VOP_PLL_SEL_SHIFT          = 6,
 224         ACLK_VOP_PLL_SEL_MASK           = 0x3 << ACLK_VOP_PLL_SEL_SHIFT,
 225         ACLK_VOP_PLL_SEL_CPLL           = 0x1,
 226         ACLK_VOP_DIV_CON_SHIFT          = 0,
 227         ACLK_VOP_DIV_CON_MASK           = 0x1f << ACLK_VOP_DIV_CON_SHIFT,
 228
 229         /* CLKSEL_CON49 & CLKSEL_CON50 */
 230         DCLK_VOP_DCLK_SEL_SHIFT         = 11,
 231         DCLK_VOP_DCLK_SEL_MASK          = 1 << DCLK_VOP_DCLK_SEL_SHIFT,
 232         DCLK_VOP_DCLK_SEL_DIVOUT        = 0,
 233         DCLK_VOP_PLL_SEL_SHIFT          = 8,
 234         DCLK_VOP_PLL_SEL_MASK           = 3 << DCLK_VOP_PLL_SEL_SHIFT,
 235         DCLK_VOP_PLL_SEL_VPLL           = 0,
 236         DCLK_VOP_DIV_CON_MASK           = 0xff,
 237         DCLK_VOP_DIV_CON_SHIFT          = 0,
 238
 239         /* CLKSEL_CON57 */
 240         PCLK_ALIVE_DIV_CON_SHIFT        = 0,
 241         PCLK_ALIVE_DIV_CON_MASK         = 0x1f << PCLK_ALIVE_DIV_CON_SHIFT,
 242
 243         /* CLKSEL_CON58 */
 244         CLK_SPI_PLL_SEL_WIDTH = 1,
 245         CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1),
 246         CLK_SPI_PLL_SEL_CPLL = 0,
 247         CLK_SPI_PLL_SEL_GPLL = 1,
 248         CLK_SPI_PLL_DIV_CON_WIDTH = 7,
 249         CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1),
 250
 251         CLK_SPI5_PLL_DIV_CON_SHIFT      = 8,
 252         CLK_SPI5_PLL_SEL_SHIFT          = 15,
 253
 254         /* CLKSEL_CON59 */
 255         CLK_SPI1_PLL_SEL_SHIFT          = 15,
 256         CLK_SPI1_PLL_DIV_CON_SHIFT      = 8,
 257         CLK_SPI0_PLL_SEL_SHIFT          = 7,
 258         CLK_SPI0_PLL_DIV_CON_SHIFT      = 0,
 259
 260         /* CLKSEL_CON60 */
 261         CLK_SPI4_PLL_SEL_SHIFT          = 15,
 262         CLK_SPI4_PLL_DIV_CON_SHIFT      = 8,
 263         CLK_SPI2_PLL_SEL_SHIFT          = 7,
 264         CLK_SPI2_PLL_DIV_CON_SHIFT      = 0,
 265
 266         /* CLKSEL_CON61 */
 267         CLK_I2C_PLL_SEL_MASK            = 1,
 268         CLK_I2C_PLL_SEL_CPLL            = 0,
 269         CLK_I2C_PLL_SEL_GPLL            = 1,
 270         CLK_I2C5_PLL_SEL_SHIFT          = 15,
 271         CLK_I2C5_DIV_CON_SHIFT          = 8,
 272         CLK_I2C1_PLL_SEL_SHIFT          = 7,
 273         CLK_I2C1_DIV_CON_SHIFT          = 0,
 274
 275         /* CLKSEL_CON62 */
 276         CLK_I2C6_PLL_SEL_SHIFT          = 15,
 277         CLK_I2C6_DIV_CON_SHIFT          = 8,
 278         CLK_I2C2_PLL_SEL_SHIFT          = 7,
 279         CLK_I2C2_DIV_CON_SHIFT          = 0,
 280
 281         /* CLKSEL_CON63 */
 282         CLK_I2C7_PLL_SEL_SHIFT          = 15,
 283         CLK_I2C7_DIV_CON_SHIFT          = 8,
 284         CLK_I2C3_PLL_SEL_SHIFT          = 7,
 285         CLK_I2C3_DIV_CON_SHIFT          = 0,
 286
 287         /* CRU_SOFTRST_CON4 */
 288         RESETN_DDR0_REQ_SHIFT           = 8,
 289         RESETN_DDR0_REQ_MASK            = 1 << RESETN_DDR0_REQ_SHIFT,
 290         RESETN_DDRPHY0_REQ_SHIFT        = 9,
 291         RESETN_DDRPHY0_REQ_MASK         = 1 << RESETN_DDRPHY0_REQ_SHIFT,
 292         RESETN_DDR1_REQ_SHIFT           = 12,
 293         RESETN_DDR1_REQ_MASK            = 1 << RESETN_DDR1_REQ_SHIFT,
 294         RESETN_DDRPHY1_REQ_SHIFT        = 13,
 295         RESETN_DDRPHY1_REQ_MASK         = 1 << RESETN_DDRPHY1_REQ_SHIFT,
 296 };
 297
 298 #define VCO_MAX_KHZ     (3200 * (MHz / KHz))
 299 #define VCO_MIN_KHZ     (800 * (MHz / KHz))
 300 #define OUTPUT_MAX_KHZ  (3200 * (MHz / KHz))
 301 #define OUTPUT_MIN_KHZ  (16 * (MHz / KHz))
 302
 303 /*
 304  *  the div restructions of pll in integer mode, these are defined in
 305  *  * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0
 306  */
 307 #define PLL_DIV_MIN     16
 308 #define PLL_DIV_MAX     3200
 309
 310 /*
 311  * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
 312  * Formulas also embedded within the Fractional PLL Verilog model:
 313  * If DSMPD = 1 (DSM is disabled, "integer mode")
 314  * FOUTVCO = FREF / REFDIV * FBDIV
 315  * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
 316  * Where:
 317  * FOUTVCO = Fractional PLL non-divided output frequency
 318  * FOUTPOSTDIV = Fractional PLL divided output frequency
 319  *               (output of second post divider)
 320  * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
 321  * REFDIV = Fractional PLL input reference clock divider
 322  * FBDIV = Integer value programmed into feedback divide
 323  *
 324  */
 325 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div)
 326 {
 327         /* All 8 PLLs have same VCO and output frequency range restrictions. */
 328         u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv;
 329         u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
 330
 331         debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, "
 332                            "postdiv2=%d, vco=%u khz, output=%u khz\n",
 333                            pll_con, div->fbdiv, div->refdiv, div->postdiv1,
 334                            div->postdiv2, vco_khz, output_khz);
 335         assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
 336                output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ &&
 337                div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX);
 338
 339         /*
 340          * When power on or changing PLL setting,
 341          * we must force PLL into slow mode to ensure output stable clock.
 342          */
 343         rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
 344                      PLL_MODE_SLOW << PLL_MODE_SHIFT);
 345
 346         /* use integer mode */
 347         rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK,
 348                      PLL_INTEGER_MODE << PLL_DSMPD_SHIFT);
 349
 350         rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK,
 351                      div->fbdiv << PLL_FBDIV_SHIFT);
 352         rk_clrsetreg(&pll_con[1],
 353                      PLL_POSTDIV2_MASK | PLL_POSTDIV1_MASK |
 354                      PLL_REFDIV_MASK | PLL_REFDIV_SHIFT,
 355                      (div->postdiv2 << PLL_POSTDIV2_SHIFT) |
 356                      (div->postdiv1 << PLL_POSTDIV1_SHIFT) |
 357                      (div->refdiv << PLL_REFDIV_SHIFT));
 358
 359         /* waiting for pll lock */
 360         while (!(readl(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT)))
 361                 udelay(1);
 362
 363         /* pll enter normal mode */
 364         rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
 365                      PLL_MODE_NORM << PLL_MODE_SHIFT);
 366 }
 367
 368 static int pll_para_config(u32 freq_hz, struct pll_div *div)
 369 {
 370         u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0;
 371         u32 postdiv1, postdiv2 = 1;
 372         u32 fref_khz;
 373         u32 diff_khz, best_diff_khz;
 374         const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16;
 375         const u32 max_postdiv1 = 7, max_postdiv2 = 7;
 376         u32 vco_khz;
 377         u32 freq_khz = freq_hz / KHz;
 378
 379         if (!freq_hz) {
 380                 printf("%s: the frequency can't be 0 Hz\n", __func__);
 381                 return -1;
 382         }
 383
 384         postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
 385         if (postdiv1 > max_postdiv1) {
 386                 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1);
 387                 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2);
 388         }
 389
 390         vco_khz = freq_khz * postdiv1 * postdiv2;
 391
 392         if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ ||
 393             postdiv2 > max_postdiv2) {
 394                 printf("%s: Cannot find out a supported VCO"
 395                        " for Frequency (%uHz).\n", __func__, freq_hz);
 396                 return -1;
 397         }
 398
 399         div->postdiv1 = postdiv1;
 400         div->postdiv2 = postdiv2;
 401
 402         best_diff_khz = vco_khz;
 403         for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) {
 404                 fref_khz = ref_khz / refdiv;
 405
 406                 fbdiv = vco_khz / fref_khz;
 407                 if (fbdiv >= max_fbdiv || fbdiv <= min_fbdiv)
 408                         continue;
 409                 diff_khz = vco_khz - fbdiv * fref_khz;
 410                 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) {
 411                         fbdiv++;
 412                         diff_khz = fref_khz - diff_khz;
 413                 }
 414
 415                 if (diff_khz >= best_diff_khz)
 416                         continue;
 417
 418                 best_diff_khz = diff_khz;
 419                 div->refdiv = refdiv;
 420                 div->fbdiv = fbdiv;
 421         }
 422
 423         if (best_diff_khz > 4 * (MHz / KHz)) {
 424                 printf("%s: Failed to match output frequency %u, "
 425                        "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz,
 426                        best_diff_khz * KHz);
 427                 return -1;
 428         }
 429         return 0;
 430 }
 431
 432 void rk3399_configure_cpu_l(struct rockchip_cru *cru,
 433                             enum apll_l_frequencies apll_l_freq)
 434 {
 435         u32 aclkm_div;
 436         u32 pclk_dbg_div;
 437         u32 atclk_div;
 438
 439         /* Setup cluster L */
 440         rkclk_set_pll(&cru->apll_l_con[0], apll_l_cfgs[apll_l_freq]);
 441
 442         aclkm_div = LPLL_HZ / ACLKM_CORE_L_HZ - 1;
 443         assert((aclkm_div + 1) * ACLKM_CORE_L_HZ == LPLL_HZ &&
 444                aclkm_div < 0x1f);
 445
 446         pclk_dbg_div = LPLL_HZ / PCLK_DBG_L_HZ - 1;
 447         assert((pclk_dbg_div + 1) * PCLK_DBG_L_HZ == LPLL_HZ &&
 448                pclk_dbg_div < 0x1f);
 449
 450         atclk_div = LPLL_HZ / ATCLK_CORE_L_HZ - 1;
 451         assert((atclk_div + 1) * ATCLK_CORE_L_HZ == LPLL_HZ &&
 452                atclk_div < 0x1f);
 453
 454         rk_clrsetreg(&cru->clksel_con[0],
 455                      ACLKM_CORE_L_DIV_CON_MASK | CLK_CORE_L_PLL_SEL_MASK |
 456                      CLK_CORE_L_DIV_MASK,
 457                      aclkm_div << ACLKM_CORE_L_DIV_CON_SHIFT |
 458                      CLK_CORE_L_PLL_SEL_ALPLL << CLK_CORE_L_PLL_SEL_SHIFT |
 459                      0 << CLK_CORE_L_DIV_SHIFT);
 460
 461         rk_clrsetreg(&cru->clksel_con[1],
 462                      PCLK_DBG_L_DIV_MASK | ATCLK_CORE_L_DIV_MASK,
 463                      pclk_dbg_div << PCLK_DBG_L_DIV_SHIFT |
 464                      atclk_div << ATCLK_CORE_L_DIV_SHIFT);
 465 }
 466
 467 void rk3399_configure_cpu_b(struct rockchip_cru *cru,
 468                             enum apll_b_frequencies apll_b_freq)
 469 {
 470         u32 aclkm_div;
 471         u32 pclk_dbg_div;
 472         u32 atclk_div;
 473
 474         /* Setup cluster B */
 475         rkclk_set_pll(&cru->apll_b_con[0], apll_b_cfgs[apll_b_freq]);
 476
 477         aclkm_div = BPLL_HZ / ACLKM_CORE_B_HZ - 1;
 478         assert((aclkm_div + 1) * ACLKM_CORE_B_HZ == BPLL_HZ &&
 479                aclkm_div < 0x1f);
 480
 481         pclk_dbg_div = BPLL_HZ / PCLK_DBG_B_HZ - 1;
 482         assert((pclk_dbg_div + 1) * PCLK_DBG_B_HZ == BPLL_HZ &&
 483                pclk_dbg_div < 0x1f);
 484
 485         atclk_div = BPLL_HZ / ATCLK_CORE_B_HZ - 1;
 486         assert((atclk_div + 1) * ATCLK_CORE_B_HZ == BPLL_HZ &&
 487                atclk_div < 0x1f);
 488
 489         rk_clrsetreg(&cru->clksel_con[2],
 490                      ACLKM_CORE_B_DIV_CON_MASK | CLK_CORE_B_PLL_SEL_MASK |
 491                      CLK_CORE_B_DIV_MASK,
 492                      aclkm_div << ACLKM_CORE_B_DIV_CON_SHIFT |
 493                      CLK_CORE_B_PLL_SEL_ABPLL << CLK_CORE_B_PLL_SEL_SHIFT |
 494                      0 << CLK_CORE_B_DIV_SHIFT);
 495
 496         rk_clrsetreg(&cru->clksel_con[3],
 497                      PCLK_DBG_B_DIV_MASK | ATCLK_CORE_B_DIV_MASK,
 498                      pclk_dbg_div << PCLK_DBG_B_DIV_SHIFT |
 499                      atclk_div << ATCLK_CORE_B_DIV_SHIFT);
 500 }
 501
 502 #define I2C_CLK_REG_MASK(bus) \
 503         (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT | \
 504          CLK_I2C_PLL_SEL_MASK << CLK_I2C ##bus## _PLL_SEL_SHIFT)
 505
 506 #define I2C_CLK_REG_VALUE(bus, clk_div) \
 507         ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT | \
 508          CLK_I2C_PLL_SEL_GPLL << CLK_I2C ##bus## _PLL_SEL_SHIFT)
 509
 510 #define I2C_CLK_DIV_VALUE(con, bus) \
 511         ((con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & I2C_DIV_CON_MASK)
 512
 513 #define I2C_PMUCLK_REG_MASK(bus) \
 514         (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT)
 515
 516 #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \
 517         ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT)
 518
 519 static ulong rk3399_i2c_get_clk(struct rockchip_cru *cru, ulong clk_id)
 520 {
 521         u32 div, con;
 522
 523         switch (clk_id) {
 524         case SCLK_I2C1:
 525                 con = readl(&cru->clksel_con[61]);
 526                 div = I2C_CLK_DIV_VALUE(con, 1);
 527                 break;
 528         case SCLK_I2C2:
 529                 con = readl(&cru->clksel_con[62]);
 530                 div = I2C_CLK_DIV_VALUE(con, 2);
 531                 break;
 532         case SCLK_I2C3:
 533                 con = readl(&cru->clksel_con[63]);
 534                 div = I2C_CLK_DIV_VALUE(con, 3);
 535                 break;
 536         case SCLK_I2C5:
 537                 con = readl(&cru->clksel_con[61]);
 538                 div = I2C_CLK_DIV_VALUE(con, 5);
 539                 break;
 540         case SCLK_I2C6:
 541                 con = readl(&cru->clksel_con[62]);
 542                 div = I2C_CLK_DIV_VALUE(con, 6);
 543                 break;
 544         case SCLK_I2C7:
 545                 con = readl(&cru->clksel_con[63]);
 546                 div = I2C_CLK_DIV_VALUE(con, 7);
 547                 break;
 548         default:
 549                 printf("do not support this i2c bus\n");
 550                 return -EINVAL;
 551         }
 552
 553         return DIV_TO_RATE(GPLL_HZ, div);
 554 }
 555
 556 static ulong rk3399_i2c_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
 557 {
 558         int src_clk_div;
 559
 560         /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/
 561         src_clk_div = GPLL_HZ / hz;
 562         assert(src_clk_div - 1 < 127);
 563
 564         switch (clk_id) {
 565         case SCLK_I2C1:
 566                 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1),
 567                              I2C_CLK_REG_VALUE(1, src_clk_div));
 568                 break;
 569         case SCLK_I2C2:
 570                 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2),
 571                              I2C_CLK_REG_VALUE(2, src_clk_div));
 572                 break;
 573         case SCLK_I2C3:
 574                 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3),
 575                              I2C_CLK_REG_VALUE(3, src_clk_div));
 576                 break;
 577         case SCLK_I2C5:
 578                 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(5),
 579                              I2C_CLK_REG_VALUE(5, src_clk_div));
 580                 break;
 581         case SCLK_I2C6:
 582                 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(6),
 583                              I2C_CLK_REG_VALUE(6, src_clk_div));
 584                 break;
 585         case SCLK_I2C7:
 586                 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(7),
 587                              I2C_CLK_REG_VALUE(7, src_clk_div));
 588                 break;
 589         default:
 590                 printf("do not support this i2c bus\n");
 591                 return -EINVAL;
 592         }
 593
 594         return rk3399_i2c_get_clk(cru, clk_id);
 595 }
 596
 597 /*
 598  * RK3399 SPI clocks have a common divider-width (7 bits) and a single bit
 599  * to select either CPLL or GPLL as the clock-parent. The location within
 600  * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable.
 601  */
 602
 603 struct spi_clkreg {
 604         u8 reg;  /* CLKSEL_CON[reg] register in CRU */
 605         u8 div_shift;
 606         u8 sel_shift;
 607 };
 608
 609 /*
 610  * The entries are numbered relative to their offset from SCLK_SPI0.
 611  *
 612  * Note that SCLK_SPI3 (which is configured via PMUCRU and requires different
 613  * logic is not supported).
 614  */
 615 static const struct spi_clkreg spi_clkregs[] = {
 616         [0] = { .reg = 59,
 617                 .div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT,
 618                 .sel_shift = CLK_SPI0_PLL_SEL_SHIFT, },
 619         [1] = { .reg = 59,
 620                 .div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT,
 621                 .sel_shift = CLK_SPI1_PLL_SEL_SHIFT, },
 622         [2] = { .reg = 60,
 623                 .div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT,
 624                 .sel_shift = CLK_SPI2_PLL_SEL_SHIFT, },
 625         [3] = { .reg = 60,
 626                 .div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT,
 627                 .sel_shift = CLK_SPI4_PLL_SEL_SHIFT, },
 628         [4] = { .reg = 58,
 629                 .div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT,
 630                 .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, },
 631 };
 632
 633 static ulong rk3399_spi_get_clk(struct rockchip_cru *cru, ulong clk_id)
 634 {
 635         const struct spi_clkreg *spiclk = NULL;
 636         u32 div, val;
 637
 638         switch (clk_id) {
 639         case SCLK_SPI0 ... SCLK_SPI5:
 640                 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
 641                 break;
 642
 643         default:
 644                 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
 645                 return -EINVAL;
 646         }
 647
 648         val = readl(&cru->clksel_con[spiclk->reg]);
 649         div = bitfield_extract(val, spiclk->div_shift,
 650                                CLK_SPI_PLL_DIV_CON_WIDTH);
 651
 652         return DIV_TO_RATE(GPLL_HZ, div);
 653 }
 654
 655 static ulong rk3399_spi_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
 656 {
 657         const struct spi_clkreg *spiclk = NULL;
 658         int src_clk_div;
 659
 660         src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
 661         assert(src_clk_div < 128);
 662
 663         switch (clk_id) {
 664         case SCLK_SPI1 ... SCLK_SPI5:
 665                 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
 666                 break;
 667
 668         default:
 669                 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
 670                 return -EINVAL;
 671         }
 672
 673         rk_clrsetreg(&cru->clksel_con[spiclk->reg],
 674                      ((CLK_SPI_PLL_DIV_CON_MASK << spiclk->div_shift) |
 675                        (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)),
 676                      ((src_clk_div << spiclk->div_shift) |
 677                       (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)));
 678
 679         return rk3399_spi_get_clk(cru, clk_id);
 680 }
 681
 682 static ulong rk3399_vop_set_clk(struct rockchip_cru *cru, ulong clk_id, u32 hz)
 683 {
 684         struct pll_div vpll_config = {0};
 685         int aclk_vop = 198 * MHz;
 686         void *aclkreg_addr, *dclkreg_addr;
 687         u32 div;
 688
 689         switch (clk_id) {
 690         case DCLK_VOP0:
 691                 aclkreg_addr = &cru->clksel_con[47];
 692                 dclkreg_addr = &cru->clksel_con[49];
 693                 break;
 694         case DCLK_VOP1:
 695                 aclkreg_addr = &cru->clksel_con[48];
 696                 dclkreg_addr = &cru->clksel_con[50];
 697                 break;
 698         default:
 699                 return -EINVAL;
 700         }
 701         /* vop aclk source clk: cpll */
 702         div = CPLL_HZ / aclk_vop;
 703         assert(div - 1 < 32);
 704
 705         rk_clrsetreg(aclkreg_addr,
 706                      ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK,
 707                      ACLK_VOP_PLL_SEL_CPLL << ACLK_VOP_PLL_SEL_SHIFT |
 708                      (div - 1) << ACLK_VOP_DIV_CON_SHIFT);
 709
 710         /* vop dclk source from vpll, and equals to vpll(means div == 1) */
 711         if (pll_para_config(hz, &vpll_config))
 712                 return -1;
 713
 714         rkclk_set_pll(&cru->vpll_con[0], &vpll_config);
 715
 716         rk_clrsetreg(dclkreg_addr,
 717                      DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK |
 718                      DCLK_VOP_DIV_CON_MASK,
 719                      DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT |
 720                      DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT |
 721                      (1 - 1) << DCLK_VOP_DIV_CON_SHIFT);
 722
 723         return hz;
 724 }
 725
 726 static ulong rk3399_mmc_get_clk(struct rockchip_cru *cru, uint clk_id)
 727 {
 728         u32 div, con;
 729
 730         switch (clk_id) {
 731         case HCLK_SDMMC:
 732         case SCLK_SDMMC:
 733                 con = readl(&cru->clksel_con[16]);
 734                 /* dwmmc controller have internal div 2 */
 735                 div = 2;
 736                 break;
 737         case SCLK_EMMC:
 738                 con = readl(&cru->clksel_con[22]);
 739                 div = 1;
 740                 break;
 741         default:
 742                 return -EINVAL;
 743         }
 744
 745         div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
 746         if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
 747                         == CLK_EMMC_PLL_SEL_24M)
 748                 return DIV_TO_RATE(OSC_HZ, div);
 749         else
 750                 return DIV_TO_RATE(GPLL_HZ, div);
 751 }
 752
 753 static ulong rk3399_mmc_set_clk(struct rockchip_cru *cru,
 754                                 ulong clk_id, ulong set_rate)
 755 {
 756         int src_clk_div;
 757         int aclk_emmc = 198 * MHz;
 758
 759         switch (clk_id) {
 760         case HCLK_SDMMC:
 761         case SCLK_SDMMC:
 762                 /* Select clk_sdmmc source from GPLL by default */
 763                 /* mmc clock defaulg div 2 internal, provide double in cru */
 764                 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);
 765
 766                 if (src_clk_div > 128) {
 767                         /* use 24MHz source for 400KHz clock */
 768                         src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
 769                         assert(src_clk_div - 1 < 128);
 770                         rk_clrsetreg(&cru->clksel_con[16],
 771                                      CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
 772                                      CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
 773                                      (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
 774                 } else {
 775                         rk_clrsetreg(&cru->clksel_con[16],
 776                                      CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
 777                                      CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
 778                                      (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
 779                 }
 780                 break;
 781         case SCLK_EMMC:
 782                 /* Select aclk_emmc source from GPLL */
 783                 src_clk_div = DIV_ROUND_UP(GPLL_HZ, aclk_emmc);
 784                 assert(src_clk_div - 1 < 32);
 785
 786                 rk_clrsetreg(&cru->clksel_con[21],
 787                              ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK,
 788                              ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT |
 789                              (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT);
 790
 791                 /* Select clk_emmc source from GPLL too */
 792                 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate);
 793                 assert(src_clk_div - 1 < 128);
 794
 795                 rk_clrsetreg(&cru->clksel_con[22],
 796                              CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
 797                              CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
 798                              (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
 799                 break;
 800         default:
 801                 return -EINVAL;
 802         }
 803         return rk3399_mmc_get_clk(cru, clk_id);
 804 }
 805
 806 static ulong rk3399_gmac_set_clk(struct rockchip_cru *cru, ulong rate)
 807 {
 808         ulong ret;
 809
 810         /*
 811          * The RGMII CLK can be derived either from an external "clkin"
 812          * or can be generated from internally by a divider from SCLK_MAC.
 813          */
 814         if (readl(&cru->clksel_con[19]) & BIT(4)) {
 815                 /* An external clock will always generate the right rate... */
 816                 ret = rate;
 817         } else {
 818                 /*
 819                  * No platform uses an internal clock to date.
 820                  * Implement this once it becomes necessary and print an error
 821                  * if someone tries to use it (while it remains unimplemented).
 822                  */
 823                 pr_err("%s: internal clock is UNIMPLEMENTED\n", __func__);
 824                 ret = 0;
 825         }
 826
 827         return ret;
 828 }
 829
 830 #define PMUSGRF_DDR_RGN_CON16 0xff330040
 831 static ulong rk3399_ddr_set_clk(struct rockchip_cru *cru,
 832                                 ulong set_rate)
 833 {
 834         struct pll_div dpll_cfg;
 835
 836         /*  IC ECO bug, need to set this register */
 837         writel(0xc000c000, PMUSGRF_DDR_RGN_CON16);
 838
 839         /*  clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
 840         switch (set_rate) {
 841         case 50 * MHz:
 842                 dpll_cfg = (struct pll_div)
 843                 {.refdiv = 1, .fbdiv = 12, .postdiv1 = 3, .postdiv2 = 2};
 844                 break;
 845         case 200 * MHz:
 846                 dpll_cfg = (struct pll_div)
 847                 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1};
 848                 break;
 849         case 300 * MHz:
 850                 dpll_cfg = (struct pll_div)
 851                 {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1};
 852                 break;
 853         case 400 * MHz:
 854                 dpll_cfg = (struct pll_div)
 855                 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
 856                 break;
 857         case 666 * MHz:
 858                 dpll_cfg = (struct pll_div)
 859                 {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1};
 860                 break;
 861         case 800 * MHz:
 862                 dpll_cfg = (struct pll_div)
 863                 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
 864                 break;
 865         case 933 * MHz:
 866                 dpll_cfg = (struct pll_div)
 867                 {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1};
 868                 break;
 869         default:
 870                 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate);
 871         }
 872         rkclk_set_pll(&cru->dpll_con[0], &dpll_cfg);
 873
 874         return set_rate;
 875 }
 876
 877 static ulong rk3399_alive_get_clk(struct rockchip_cru *cru)
 878 {
 879         u32 div, val;
 880
 881         val = readl(&cru->clksel_con[57]);
 882         div = (val & PCLK_ALIVE_DIV_CON_MASK) >>
 883                PCLK_ALIVE_DIV_CON_SHIFT;
 884
 885         return DIV_TO_RATE(GPLL_HZ, div);
 886 }
 887
 888 static ulong rk3399_saradc_get_clk(struct rockchip_cru *cru)
 889 {
 890         u32 div, val;
 891
 892         val = readl(&cru->clksel_con[26]);
 893         div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
 894                                CLK_SARADC_DIV_CON_WIDTH);
 895
 896         return DIV_TO_RATE(OSC_HZ, div);
 897 }
 898
 899 static ulong rk3399_saradc_set_clk(struct rockchip_cru *cru, uint hz)
 900 {
 901         int src_clk_div;
 902
 903         src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
 904         assert(src_clk_div < 128);
 905
 906         rk_clrsetreg(&cru->clksel_con[26],
 907                      CLK_SARADC_DIV_CON_MASK,
 908                      src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
 909
 910         return rk3399_saradc_get_clk(cru);
 911 }
 912
 913 static ulong rk3399_clk_get_rate(struct clk *clk)
 914 {
 915         struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
 916         ulong rate = 0;
 917
 918         switch (clk->id) {
 919         case 0 ... 63:
 920                 return 0;
 921         case HCLK_SDMMC:
 922         case SCLK_SDMMC:
 923         case SCLK_EMMC:
 924                 rate = rk3399_mmc_get_clk(priv->cru, clk->id);
 925                 break;
 926         case SCLK_I2C1:
 927         case SCLK_I2C2:
 928         case SCLK_I2C3:
 929         case SCLK_I2C5:
 930         case SCLK_I2C6:
 931         case SCLK_I2C7:
 932                 rate = rk3399_i2c_get_clk(priv->cru, clk->id);
 933                 break;
 934         case SCLK_SPI0...SCLK_SPI5:
 935                 rate = rk3399_spi_get_clk(priv->cru, clk->id);
 936                 break;
 937         case SCLK_UART0:
 938         case SCLK_UART1:
 939         case SCLK_UART2:
 940         case SCLK_UART3:
 941                 return 24000000;
 942         case PCLK_HDMI_CTRL:
 943                 break;
 944         case DCLK_VOP0:
 945         case DCLK_VOP1:
 946                 break;
 947         case PCLK_EFUSE1024NS:
 948                 break;
 949         case SCLK_SARADC:
 950                 rate = rk3399_saradc_get_clk(priv->cru);
 951                 break;
 952         case ACLK_VIO:
 953         case ACLK_HDCP:
 954         case ACLK_GIC_PRE:
 955         case PCLK_DDR:
 956                 break;
 957         case PCLK_ALIVE:
 958         case PCLK_WDT:
 959                 rate = rk3399_alive_get_clk(priv->cru);
 960                 break;
 961         default:
 962                 log_debug("Unknown clock %lu\n", clk->id);
 963                 return -ENOENT;
 964         }
 965
 966         return rate;
 967 }
 968
 969 static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
 970 {
 971         struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
 972         ulong ret = 0;
 973
 974         switch (clk->id) {
 975         case 0 ... 63:
 976                 return 0;
 977
 978         case ACLK_PERIHP:
 979         case HCLK_PERIHP:
 980         case PCLK_PERIHP:
 981                 return 0;
 982
 983         case ACLK_PERILP0:
 984         case HCLK_PERILP0:
 985         case PCLK_PERILP0:
 986                 return 0;
 987
 988         case ACLK_CCI:
 989                 return 0;
 990
 991         case HCLK_PERILP1:
 992         case PCLK_PERILP1:
 993                 return 0;
 994
 995         case HCLK_SDMMC:
 996         case SCLK_SDMMC:
 997         case SCLK_EMMC:
 998                 ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate);
 999                 break;
1000         case SCLK_MAC:
1001                 ret = rk3399_gmac_set_clk(priv->cru, rate);
1002                 break;
1003         case SCLK_I2C1:
1004         case SCLK_I2C2:
1005         case SCLK_I2C3:
1006         case SCLK_I2C5:
1007         case SCLK_I2C6:
1008         case SCLK_I2C7:
1009                 ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate);
1010                 break;
1011         case SCLK_SPI0...SCLK_SPI5:
1012                 ret = rk3399_spi_set_clk(priv->cru, clk->id, rate);
1013                 break;
1014         case PCLK_HDMI_CTRL:
1015         case PCLK_VIO_GRF:
1016                 /* the PCLK gates for video are enabled by default */
1017                 break;
1018         case DCLK_VOP0:
1019         case DCLK_VOP1:
1020                 ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);
1021                 break;
1022         case ACLK_VOP1:
1023         case HCLK_VOP1:
1024         case HCLK_SD:
1025         case SCLK_UPHY0_TCPDCORE:
1026         case SCLK_UPHY1_TCPDCORE:
1027                 /**
1028                  * assigned-clocks handling won't require for vopl, so
1029                  * return 0 to satisfy clk_set_defaults during device probe.
1030                  */
1031                 return 0;
1032         case SCLK_DDRCLK:
1033                 ret = rk3399_ddr_set_clk(priv->cru, rate);
1034                 break;
1035         case PCLK_EFUSE1024NS:
1036                 break;
1037         case SCLK_SARADC:
1038                 ret = rk3399_saradc_set_clk(priv->cru, rate);
1039                 break;
1040         case ACLK_VIO:
1041         case ACLK_HDCP:
1042         case ACLK_GIC_PRE:
1043         case PCLK_DDR:
1044                 return 0;
1045         default:
1046                 log_debug("Unknown clock %lu\n", clk->id);
1047                 return -ENOENT;
1048         }
1049
1050         return ret;
1051 }
1052
1053 static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk,
1054                                                  struct clk *parent)
1055 {
1056         struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
1057         const char *clock_output_name;
1058         int ret;
1059
1060         /*
1061          * If the requested parent is in the same clock-controller and
1062          * the id is SCLK_MAC ("clk_gmac"), switch to the internal clock.
1063          */
1064         if (parent->dev == clk->dev && parent->id == SCLK_MAC) {
1065                 debug("%s: switching RGMII to SCLK_MAC\n", __func__);
1066                 rk_clrreg(&priv->cru->clksel_con[19], BIT(4));
1067                 return 0;
1068         }
1069
1070         /*
1071          * Otherwise, we need to check the clock-output-names of the
1072          * requested parent to see if the requested id is "clkin_gmac".
1073          */
1074         ret = dev_read_string_index(parent->dev, "clock-output-names",
1075                                     parent->id, &clock_output_name);
1076         if (ret < 0)
1077                 return -ENODATA;
1078
1079         /* If this is "clkin_gmac", switch to the external clock input */
1080         if (!strcmp(clock_output_name, "clkin_gmac")) {
1081                 debug("%s: switching RGMII to CLKIN\n", __func__);
1082                 rk_setreg(&priv->cru->clksel_con[19], BIT(4));
1083                 return 0;
1084         }
1085
1086         return -EINVAL;
1087 }
1088
1089 static int __maybe_unused rk3399_clk_set_parent(struct clk *clk,
1090                                                 struct clk *parent)
1091 {
1092         switch (clk->id) {
1093         case SCLK_RMII_SRC:
1094                 return rk3399_gmac_set_parent(clk, parent);
1095         }
1096
1097         debug("%s: unsupported clk %ld\n", __func__, clk->id);
1098         return -ENOENT;
1099 }
1100
1101 static int rk3399_clk_enable(struct clk *clk)
1102 {
1103         struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
1104
1105         switch (clk->id) {
1106         case SCLK_MAC:
1107                 rk_clrreg(&priv->cru->clkgate_con[5], BIT(5));
1108                 break;
1109         case SCLK_MAC_RX:
1110                 rk_clrreg(&priv->cru->clkgate_con[5], BIT(8));
1111                 break;
1112         case SCLK_MAC_TX:
1113                 rk_clrreg(&priv->cru->clkgate_con[5], BIT(9));
1114                 break;
1115         case SCLK_MACREF:
1116                 rk_clrreg(&priv->cru->clkgate_con[5], BIT(7));
1117                 break;
1118         case SCLK_MACREF_OUT:
1119                 rk_clrreg(&priv->cru->clkgate_con[5], BIT(6));
1120                 break;
1121         case SCLK_USB2PHY0_REF:
1122                 rk_clrreg(&priv->cru->clkgate_con[6], BIT(5));
1123                 break;
1124         case SCLK_USB2PHY1_REF:
1125                 rk_clrreg(&priv->cru->clkgate_con[6], BIT(6));
1126                 break;
1127         case ACLK_GMAC:
1128                 rk_clrreg(&priv->cru->clkgate_con[32], BIT(0));
1129                 break;
1130         case PCLK_GMAC:
1131                 rk_clrreg(&priv->cru->clkgate_con[32], BIT(2));
1132                 break;
1133         case SCLK_USB3OTG0_REF:
1134                 rk_clrreg(&priv->cru->clkgate_con[12], BIT(1));
1135                 break;
1136         case SCLK_USB3OTG1_REF:
1137                 rk_clrreg(&priv->cru->clkgate_con[12], BIT(2));
1138                 break;
1139         case SCLK_USB3OTG0_SUSPEND:
1140                 rk_clrreg(&priv->cru->clkgate_con[12], BIT(3));
1141                 break;
1142         case SCLK_USB3OTG1_SUSPEND:
1143                 rk_clrreg(&priv->cru->clkgate_con[12], BIT(4));
1144                 break;
1145         case ACLK_USB3OTG0:
1146                 rk_clrreg(&priv->cru->clkgate_con[30], BIT(1));
1147                 break;
1148         case ACLK_USB3OTG1:
1149                 rk_clrreg(&priv->cru->clkgate_con[30], BIT(2));
1150                 break;
1151         case ACLK_USB3_RKSOC_AXI_PERF:
1152                 rk_clrreg(&priv->cru->clkgate_con[30], BIT(3));
1153                 break;
1154         case ACLK_USB3:
1155                 rk_clrreg(&priv->cru->clkgate_con[12], BIT(0));
1156                 break;
1157         case ACLK_USB3_GRF:
1158                 rk_clrreg(&priv->cru->clkgate_con[30], BIT(4));
1159                 break;
1160         case HCLK_HOST0:
1161                 rk_clrreg(&priv->cru->clksel_con[20], BIT(5));
1162                 break;
1163         case HCLK_HOST0_ARB:
1164                 rk_clrreg(&priv->cru->clksel_con[20], BIT(6));
1165                 break;
1166         case HCLK_HOST1:
1167                 rk_clrreg(&priv->cru->clksel_con[20], BIT(7));
1168                 break;
1169         case HCLK_HOST1_ARB:
1170                 rk_clrreg(&priv->cru->clksel_con[20], BIT(8));
1171                 break;
1172         case SCLK_UPHY0_TCPDPHY_REF:
1173                 rk_clrreg(&priv->cru->clkgate_con[13], BIT(4));
1174                 break;
1175         case SCLK_UPHY0_TCPDCORE:
1176                 rk_clrreg(&priv->cru->clkgate_con[13], BIT(5));
1177                 break;
1178         case SCLK_UPHY1_TCPDPHY_REF:
1179                 rk_clrreg(&priv->cru->clkgate_con[13], BIT(6));
1180                 break;
1181         case SCLK_UPHY1_TCPDCORE:
1182                 rk_clrreg(&priv->cru->clkgate_con[13], BIT(7));
1183                 break;
1184         case SCLK_PCIEPHY_REF:
1185                 rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
1186                 break;
1187         default:
1188                 debug("%s: unsupported clk %ld\n", __func__, clk->id);
1189                 return -ENOENT;
1190         }
1191
1192         return 0;
1193 }
1194
1195 static int rk3399_clk_disable(struct clk *clk)
1196 {
1197         struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
1198
1199         switch (clk->id) {
1200         case SCLK_MAC:
1201                 rk_setreg(&priv->cru->clkgate_con[5], BIT(5));
1202                 break;
1203         case SCLK_MAC_RX:
1204                 rk_setreg(&priv->cru->clkgate_con[5], BIT(8));
1205                 break;
1206         case SCLK_MAC_TX:
1207                 rk_setreg(&priv->cru->clkgate_con[5], BIT(9));
1208                 break;
1209         case SCLK_MACREF:
1210                 rk_setreg(&priv->cru->clkgate_con[5], BIT(7));
1211                 break;
1212         case SCLK_MACREF_OUT:
1213                 rk_setreg(&priv->cru->clkgate_con[5], BIT(6));
1214                 break;
1215         case SCLK_USB2PHY0_REF:
1216                 rk_setreg(&priv->cru->clkgate_con[6], BIT(5));
1217                 break;
1218         case SCLK_USB2PHY1_REF:
1219                 rk_setreg(&priv->cru->clkgate_con[6], BIT(6));
1220                 break;
1221         case ACLK_GMAC:
1222                 rk_setreg(&priv->cru->clkgate_con[32], BIT(0));
1223                 break;
1224         case PCLK_GMAC:
1225                 rk_setreg(&priv->cru->clkgate_con[32], BIT(2));
1226                 break;
1227         case SCLK_USB3OTG0_REF:
1228                 rk_setreg(&priv->cru->clkgate_con[12], BIT(1));
1229                 break;
1230         case SCLK_USB3OTG1_REF:
1231                 rk_setreg(&priv->cru->clkgate_con[12], BIT(2));
1232                 break;
1233         case SCLK_USB3OTG0_SUSPEND:
1234                 rk_setreg(&priv->cru->clkgate_con[12], BIT(3));
1235                 break;
1236         case SCLK_USB3OTG1_SUSPEND:
1237                 rk_setreg(&priv->cru->clkgate_con[12], BIT(4));
1238                 break;
1239         case ACLK_USB3OTG0:
1240                 rk_setreg(&priv->cru->clkgate_con[30], BIT(1));
1241                 break;
1242         case ACLK_USB3OTG1:
1243                 rk_setreg(&priv->cru->clkgate_con[30], BIT(2));
1244                 break;
1245         case ACLK_USB3_RKSOC_AXI_PERF:
1246                 rk_setreg(&priv->cru->clkgate_con[30], BIT(3));
1247                 break;
1248         case ACLK_USB3:
1249                 rk_setreg(&priv->cru->clkgate_con[12], BIT(0));
1250                 break;
1251         case ACLK_USB3_GRF:
1252                 rk_setreg(&priv->cru->clkgate_con[30], BIT(4));
1253                 break;
1254         case HCLK_HOST0:
1255                 rk_setreg(&priv->cru->clksel_con[20], BIT(5));
1256                 break;
1257         case HCLK_HOST0_ARB:
1258                 rk_setreg(&priv->cru->clksel_con[20], BIT(6));
1259                 break;
1260         case HCLK_HOST1:
1261                 rk_setreg(&priv->cru->clksel_con[20], BIT(7));
1262                 break;
1263         case HCLK_HOST1_ARB:
1264                 rk_setreg(&priv->cru->clksel_con[20], BIT(8));
1265                 break;
1266         case SCLK_UPHY0_TCPDPHY_REF:
1267                 rk_setreg(&priv->cru->clkgate_con[13], BIT(4));
1268                 break;
1269         case SCLK_UPHY0_TCPDCORE:
1270                 rk_setreg(&priv->cru->clkgate_con[13], BIT(5));
1271                 break;
1272         case SCLK_UPHY1_TCPDPHY_REF:
1273                 rk_setreg(&priv->cru->clkgate_con[13], BIT(6));
1274                 break;
1275         case SCLK_UPHY1_TCPDCORE:
1276                 rk_setreg(&priv->cru->clkgate_con[13], BIT(7));
1277                 break;
1278         case SCLK_PCIEPHY_REF:
1279                 rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
1280                 break;
1281         default:
1282                 debug("%s: unsupported clk %ld\n", __func__, clk->id);
1283                 return -ENOENT;
1284         }
1285
1286         return 0;
1287 }
1288
1289 static struct clk_ops rk3399_clk_ops = {
1290         .get_rate = rk3399_clk_get_rate,
1291         .set_rate = rk3399_clk_set_rate,
1292 #if CONFIG_IS_ENABLED(OF_REAL)
1293         .set_parent = rk3399_clk_set_parent,
1294 #endif
1295         .enable = rk3399_clk_enable,
1296         .disable = rk3399_clk_disable,
1297 };
1298
1299 static void rkclk_init(struct rockchip_cru *cru)
1300 {
1301         u32 aclk_div;
1302         u32 hclk_div;
1303         u32 pclk_div;
1304
1305         rk3399_configure_cpu_l(cru, APLL_L_600_MHZ);
1306         rk3399_configure_cpu_b(cru, APLL_B_600_MHZ);
1307         /*
1308          * some cru registers changed by bootrom, we'd better reset them to
1309          * reset/default values described in TRM to avoid confusion in kernel.
1310          * Please consider these three lines as a fix of bootrom bug.
1311          */
1312         rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101);
1313         rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f);
1314         rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003);
1315
1316         /* configure gpll cpll */
1317         rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg);
1318         rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg);
1319
1320         /* configure perihp aclk, hclk, pclk */
1321         aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
1322         assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
1323
1324         hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
1325         assert((hclk_div + 1) * PERIHP_HCLK_HZ ==
1326                PERIHP_ACLK_HZ && (hclk_div < 0x4));
1327
1328         pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
1329         assert((pclk_div + 1) * PERIHP_PCLK_HZ ==
1330                PERIHP_ACLK_HZ && (pclk_div < 0x7));
1331
1332         rk_clrsetreg(&cru->clksel_con[14],
1333                      PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK |
1334                      ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK,
1335                      pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
1336                      hclk_div << HCLK_PERIHP_DIV_CON_SHIFT |
1337                      ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT |
1338                      aclk_div << ACLK_PERIHP_DIV_CON_SHIFT);
1339
1340         /* configure perilp0 aclk, hclk, pclk */
1341         aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1;
1342         assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
1343
1344         hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1;
1345         assert((hclk_div + 1) * PERILP0_HCLK_HZ ==
1346                PERILP0_ACLK_HZ && (hclk_div < 0x4));
1347
1348         pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1;
1349         assert((pclk_div + 1) * PERILP0_PCLK_HZ ==
1350                PERILP0_ACLK_HZ && (pclk_div < 0x7));
1351
1352         rk_clrsetreg(&cru->clksel_con[23],
1353                      PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK |
1354                      ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK,
1355                      pclk_div << PCLK_PERILP0_DIV_CON_SHIFT |
1356                      hclk_div << HCLK_PERILP0_DIV_CON_SHIFT |
1357                      ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT |
1358                      aclk_div << ACLK_PERILP0_DIV_CON_SHIFT);
1359
1360         /* perilp1 hclk select gpll as source */
1361         hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1;
1362         assert((hclk_div + 1) * PERILP1_HCLK_HZ ==
1363                GPLL_HZ && (hclk_div < 0x1f));
1364
1365         pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1;
1366         assert((pclk_div + 1) * PERILP1_HCLK_HZ ==
1367                PERILP1_HCLK_HZ && (hclk_div < 0x7));
1368
1369         rk_clrsetreg(&cru->clksel_con[25],
1370                      PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK |
1371                      HCLK_PERILP1_PLL_SEL_MASK,
1372                      pclk_div << PCLK_PERILP1_DIV_CON_SHIFT |
1373                      hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
1374                      HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
1375 }
1376
1377 static int rk3399_clk_probe(struct udevice *dev)
1378 {
1379         struct rk3399_clk_priv *priv = dev_get_priv(dev);
1380         bool init_clocks = false;
1381
1382 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1383         struct rk3399_clk_plat *plat = dev_get_plat(dev);
1384
1385         priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
1386 #endif
1387
1388 #if defined(CONFIG_SPL_BUILD)
1389         init_clocks = true;
1390 #elif CONFIG_IS_ENABLED(HANDOFF)
1391         if (!(gd->flags & GD_FLG_RELOC)) {
1392                 if (!(gd->spl_handoff))
1393                         init_clocks = true;
1394         }
1395 #endif
1396
1397         if (init_clocks)
1398                 rkclk_init(priv->cru);
1399
1400         return 0;
1401 }
1402
1403 static int rk3399_clk_of_to_plat(struct udevice *dev)
1404 {
1405         if (CONFIG_IS_ENABLED(OF_REAL)) {
1406                 struct rk3399_clk_priv *priv = dev_get_priv(dev);
1407
1408                 priv->cru = dev_read_addr_ptr(dev);
1409         }
1410
1411         return 0;
1412 }
1413
1414 static int rk3399_clk_bind(struct udevice *dev)
1415 {
1416         int ret;
1417         struct udevice *sys_child;
1418         struct sysreset_reg *priv;
1419
1420         /* The reset driver does not have a device node, so bind it here */
1421         ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
1422                                  &sys_child);
1423         if (ret) {
1424                 debug("Warning: No sysreset driver: ret=%d\n", ret);
1425         } else {
1426                 priv = malloc(sizeof(struct sysreset_reg));
1427                 priv->glb_srst_fst_value = offsetof(struct rockchip_cru,
1428                                                     glb_srst_fst_value);
1429                 priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
1430                                                     glb_srst_snd_value);
1431                 dev_set_priv(sys_child, priv);
1432         }
1433
1434 #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
1435         ret = offsetof(struct rockchip_cru, softrst_con[0]);
1436         ret = rockchip_reset_bind(dev, ret, 21);
1437         if (ret)
1438                 debug("Warning: software reset driver bind faile\n");
1439 #endif
1440
1441         return 0;
1442 }
1443
1444 static const struct udevice_id rk3399_clk_ids[] = {
1445         { .compatible = "rockchip,rk3399-cru" },
1446         { }
1447 };
1448
1449 U_BOOT_DRIVER(clk_rk3399) = {
1450         .name           = "rockchip_rk3399_cru",
1451         .id             = UCLASS_CLK,
1452         .of_match       = rk3399_clk_ids,
1453         .priv_auto      = sizeof(struct rk3399_clk_priv),
1454         .of_to_plat = rk3399_clk_of_to_plat,
1455         .ops            = &rk3399_clk_ops,
1456         .bind           = rk3399_clk_bind,
1457         .probe          = rk3399_clk_probe,
1458 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1459         .plat_auto      = sizeof(struct rk3399_clk_plat),
1460 #endif
1461 };
1462
1463 static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id)
1464 {
1465         u32 div, con;
1466
1467         switch (clk_id) {
1468         case SCLK_I2C0_PMU:
1469                 con = readl(&pmucru->pmucru_clksel[2]);
1470                 div = I2C_CLK_DIV_VALUE(con, 0);
1471                 break;
1472         case SCLK_I2C4_PMU:
1473                 con = readl(&pmucru->pmucru_clksel[3]);
1474                 div = I2C_CLK_DIV_VALUE(con, 4);
1475                 break;
1476         case SCLK_I2C8_PMU:
1477                 con = readl(&pmucru->pmucru_clksel[2]);
1478                 div = I2C_CLK_DIV_VALUE(con, 8);
1479                 break;
1480         default:
1481                 printf("do not support this i2c bus\n");
1482                 return -EINVAL;
1483         }
1484
1485         return DIV_TO_RATE(PPLL_HZ, div);
1486 }
1487
1488 static ulong rk3399_i2c_set_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id,
1489                                    uint hz)
1490 {
1491         int src_clk_div;
1492
1493         src_clk_div = PPLL_HZ / hz;
1494         assert(src_clk_div - 1 < 127);
1495
1496         switch (clk_id) {
1497         case SCLK_I2C0_PMU:
1498                 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(0),
1499                              I2C_PMUCLK_REG_VALUE(0, src_clk_div));
1500                 break;
1501         case SCLK_I2C4_PMU:
1502                 rk_clrsetreg(&pmucru->pmucru_clksel[3], I2C_PMUCLK_REG_MASK(4),
1503                              I2C_PMUCLK_REG_VALUE(4, src_clk_div));
1504                 break;
1505         case SCLK_I2C8_PMU:
1506                 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(8),
1507                              I2C_PMUCLK_REG_VALUE(8, src_clk_div));
1508                 break;
1509         default:
1510                 printf("do not support this i2c bus\n");
1511                 return -EINVAL;
1512         }
1513
1514         return DIV_TO_RATE(PPLL_HZ, src_clk_div);
1515 }
1516
1517 static ulong rk3399_pwm_get_clk(struct rk3399_pmucru *pmucru)
1518 {
1519         u32 div, con;
1520
1521         /* PWM closk rate is same as pclk_pmu */
1522         con = readl(&pmucru->pmucru_clksel[0]);
1523         div = con & PMU_PCLK_DIV_CON_MASK;
1524
1525         return DIV_TO_RATE(PPLL_HZ, div);
1526 }
1527
1528 static ulong rk3399_pmuclk_get_rate(struct clk *clk)
1529 {
1530         struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
1531         ulong rate = 0;
1532
1533         switch (clk->id) {
1534         case PLL_PPLL:
1535                 return PPLL_HZ;
1536         case PCLK_RKPWM_PMU:
1537         case PCLK_WDT_M0_PMU:
1538                 rate = rk3399_pwm_get_clk(priv->pmucru);
1539                 break;
1540         case SCLK_I2C0_PMU:
1541         case SCLK_I2C4_PMU:
1542         case SCLK_I2C8_PMU:
1543                 rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id);
1544                 break;
1545         default:
1546                 return -ENOENT;
1547         }
1548
1549         return rate;
1550 }
1551
1552 static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate)
1553 {
1554         struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
1555         ulong ret = 0;
1556
1557         switch (clk->id) {
1558         case PLL_PPLL:
1559                 /*
1560                  * This has already been set up and we don't want/need
1561                  * to change it here.  Accept the request though, as the
1562                  * device-tree has this in an 'assigned-clocks' list.
1563                  */
1564                 return PPLL_HZ;
1565         case SCLK_I2C0_PMU:
1566         case SCLK_I2C4_PMU:
1567         case SCLK_I2C8_PMU:
1568                 ret = rk3399_i2c_set_pmuclk(priv->pmucru, clk->id, rate);
1569                 break;
1570         default:
1571                 return -ENOENT;
1572         }
1573
1574         return ret;
1575 }
1576
1577 static struct clk_ops rk3399_pmuclk_ops = {
1578         .get_rate = rk3399_pmuclk_get_rate,
1579         .set_rate = rk3399_pmuclk_set_rate,
1580 };
1581
1582 #ifndef CONFIG_SPL_BUILD
1583 static void pmuclk_init(struct rk3399_pmucru *pmucru)
1584 {
1585         u32 pclk_div;
1586
1587         /*  configure pmu pll(ppll) */
1588         rkclk_set_pll(&pmucru->ppll_con[0], &ppll_init_cfg);
1589
1590         /*  configure pmu pclk */
1591         pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1;
1592         rk_clrsetreg(&pmucru->pmucru_clksel[0],
1593                      PMU_PCLK_DIV_CON_MASK,
1594                      pclk_div << PMU_PCLK_DIV_CON_SHIFT);
1595 }
1596 #endif
1597
1598 static int rk3399_pmuclk_probe(struct udevice *dev)
1599 {
1600 #if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD)
1601         struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
1602 #endif
1603
1604 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1605         struct rk3399_pmuclk_plat *plat = dev_get_plat(dev);
1606
1607         priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
1608 #endif
1609
1610 #ifndef CONFIG_SPL_BUILD
1611         pmuclk_init(priv->pmucru);
1612 #endif
1613         return 0;
1614 }
1615
1616 static int rk3399_pmuclk_of_to_plat(struct udevice *dev)
1617 {
1618         if (CONFIG_IS_ENABLED(OF_REAL)) {
1619                 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
1620
1621                 priv->pmucru = dev_read_addr_ptr(dev);
1622         }
1623
1624         return 0;
1625 }
1626
1627 static int rk3399_pmuclk_bind(struct udevice *dev)
1628 {
1629 #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
1630         int ret;
1631
1632         ret = offsetof(struct rk3399_pmucru, pmucru_softrst_con[0]);
1633         ret = rockchip_reset_bind(dev, ret, 2);
1634         if (ret)
1635                 debug("Warning: software reset driver bind faile\n");
1636 #endif
1637         return 0;
1638 }
1639
1640 static const struct udevice_id rk3399_pmuclk_ids[] = {
1641         { .compatible = "rockchip,rk3399-pmucru" },
1642         { }
1643 };
1644
1645 U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = {
1646         .name           = "rockchip_rk3399_pmucru",
1647         .id             = UCLASS_CLK,
1648         .of_match       = rk3399_pmuclk_ids,
1649         .priv_auto      = sizeof(struct rk3399_pmuclk_priv),
1650         .of_to_plat = rk3399_pmuclk_of_to_plat,
1651         .ops            = &rk3399_pmuclk_ops,
1652         .probe          = rk3399_pmuclk_probe,
1653         .bind           = rk3399_pmuclk_bind,
1654 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1655         .plat_auto      = sizeof(struct rk3399_pmuclk_plat),
1656 #endif
1657 };