drivers/clk/rockchip/clk_rk3399.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * (C) Copyright 2015 Google, Inc
   4  * (C) 2017 Theobroma Systems Design und Consulting GmbH
   5  */
   6
   7 #include <common.h>
   8 #include <clk-uclass.h>
   9 #include <dm.h>
  10 #include <dt-structs.h>
  11 #include <errno.h>
  12 #include <log.h>
  13 #include <malloc.h>
  14 #include <mapmem.h>
  15 #include <syscon.h>
  16 #include <bitfield.h>
  17 #include <asm/io.h>
  18 #include <asm/arch-rockchip/clock.h>
  19 #include <asm/arch-rockchip/cru.h>
  20 #include <asm/arch-rockchip/hardware.h>
  21 #include <dm/lists.h>
  22 #include <dt-bindings/clock/rk3399-cru.h>
  23 #include <linux/bitops.h>
  24 #include <linux/delay.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  29 struct rk3399_clk_plat {
  30         struct dtd_rockchip_rk3399_cru dtd;
  31 };
  32
  33 struct rk3399_pmuclk_plat {
  34         struct dtd_rockchip_rk3399_pmucru dtd;
  35 };
  36 #endif
  37
  38 struct pll_div {
  39         u32 refdiv;
  40         u32 fbdiv;
  41         u32 postdiv1;
  42         u32 postdiv2;
  43         u32 frac;
  44 };
  45
  46 #define RATE_TO_DIV(input_rate, output_rate) \
  47         ((input_rate) / (output_rate) - 1)
  48 #define DIV_TO_RATE(input_rate, div)            ((input_rate) / ((div) + 1))
  49
  50 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
  51         .refdiv = _refdiv,\
  52         .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
  53         .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
  54
  55 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
  56 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
  57 #if !defined(CONFIG_SPL_BUILD)
  58 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
  59 #endif
  60
  61 static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600 * MHz, 3, 1, 1);
  62 static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
  63
  64 static const struct pll_div *apll_l_cfgs[] = {
  65         [APLL_L_1600_MHZ] = &apll_l_1600_cfg,
  66         [APLL_L_600_MHZ] = &apll_l_600_cfg,
  67 };
  68
  69 static const struct pll_div apll_b_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
  70 static const struct pll_div *apll_b_cfgs[] = {
  71         [APLL_B_600_MHZ] = &apll_b_600_cfg,
  72 };
  73
  74 enum {
  75         /* PLL_CON0 */
  76         PLL_FBDIV_MASK                  = 0xfff,
  77         PLL_FBDIV_SHIFT                 = 0,
  78
  79         /* PLL_CON1 */
  80         PLL_POSTDIV2_SHIFT              = 12,
  81         PLL_POSTDIV2_MASK               = 0x7 << PLL_POSTDIV2_SHIFT,
  82         PLL_POSTDIV1_SHIFT              = 8,
  83         PLL_POSTDIV1_MASK               = 0x7 << PLL_POSTDIV1_SHIFT,
  84         PLL_REFDIV_MASK                 = 0x3f,
  85         PLL_REFDIV_SHIFT                = 0,
  86
  87         /* PLL_CON2 */
  88         PLL_LOCK_STATUS_SHIFT           = 31,
  89         PLL_LOCK_STATUS_MASK            = 1 << PLL_LOCK_STATUS_SHIFT,
  90         PLL_FRACDIV_MASK                = 0xffffff,
  91         PLL_FRACDIV_SHIFT               = 0,
  92
  93         /* PLL_CON3 */
  94         PLL_MODE_SHIFT                  = 8,
  95         PLL_MODE_MASK                   = 3 << PLL_MODE_SHIFT,
  96         PLL_MODE_SLOW                   = 0,
  97         PLL_MODE_NORM,
  98         PLL_MODE_DEEP,
  99         PLL_DSMPD_SHIFT                 = 3,
 100         PLL_DSMPD_MASK                  = 1 << PLL_DSMPD_SHIFT,
 101         PLL_INTEGER_MODE                = 1,
 102
 103         /* PMUCRU_CLKSEL_CON0 */
 104         PMU_PCLK_DIV_CON_MASK           = 0x1f,
 105         PMU_PCLK_DIV_CON_SHIFT          = 0,
 106
 107         /* PMUCRU_CLKSEL_CON1 */
 108         SPI3_PLL_SEL_SHIFT              = 7,
 109         SPI3_PLL_SEL_MASK               = 1 << SPI3_PLL_SEL_SHIFT,
 110         SPI3_PLL_SEL_24M                = 0,
 111         SPI3_PLL_SEL_PPLL               = 1,
 112         SPI3_DIV_CON_SHIFT              = 0x0,
 113         SPI3_DIV_CON_MASK               = 0x7f,
 114
 115         /* PMUCRU_CLKSEL_CON2 */
 116         I2C_DIV_CON_MASK                = 0x7f,
 117         CLK_I2C8_DIV_CON_SHIFT          = 8,
 118         CLK_I2C0_DIV_CON_SHIFT          = 0,
 119
 120         /* PMUCRU_CLKSEL_CON3 */
 121         CLK_I2C4_DIV_CON_SHIFT          = 0,
 122
 123         /* CLKSEL_CON0 */
 124         ACLKM_CORE_L_DIV_CON_SHIFT      = 8,
 125         ACLKM_CORE_L_DIV_CON_MASK       = 0x1f << ACLKM_CORE_L_DIV_CON_SHIFT,
 126         CLK_CORE_L_PLL_SEL_SHIFT        = 6,
 127         CLK_CORE_L_PLL_SEL_MASK         = 3 << CLK_CORE_L_PLL_SEL_SHIFT,
 128         CLK_CORE_L_PLL_SEL_ALPLL        = 0x0,
 129         CLK_CORE_L_PLL_SEL_ABPLL        = 0x1,
 130         CLK_CORE_L_PLL_SEL_DPLL         = 0x10,
 131         CLK_CORE_L_PLL_SEL_GPLL         = 0x11,
 132         CLK_CORE_L_DIV_MASK             = 0x1f,
 133         CLK_CORE_L_DIV_SHIFT            = 0,
 134
 135         /* CLKSEL_CON1 */
 136         PCLK_DBG_L_DIV_SHIFT            = 0x8,
 137         PCLK_DBG_L_DIV_MASK             = 0x1f << PCLK_DBG_L_DIV_SHIFT,
 138         ATCLK_CORE_L_DIV_SHIFT          = 0,
 139         ATCLK_CORE_L_DIV_MASK           = 0x1f << ATCLK_CORE_L_DIV_SHIFT,
 140
 141         /* CLKSEL_CON2 */
 142         ACLKM_CORE_B_DIV_CON_SHIFT      = 8,
 143         ACLKM_CORE_B_DIV_CON_MASK       = 0x1f << ACLKM_CORE_B_DIV_CON_SHIFT,
 144         CLK_CORE_B_PLL_SEL_SHIFT        = 6,
 145         CLK_CORE_B_PLL_SEL_MASK         = 3 << CLK_CORE_B_PLL_SEL_SHIFT,
 146         CLK_CORE_B_PLL_SEL_ALPLL        = 0x0,
 147         CLK_CORE_B_PLL_SEL_ABPLL        = 0x1,
 148         CLK_CORE_B_PLL_SEL_DPLL         = 0x10,
 149         CLK_CORE_B_PLL_SEL_GPLL         = 0x11,
 150         CLK_CORE_B_DIV_MASK             = 0x1f,
 151         CLK_CORE_B_DIV_SHIFT            = 0,
 152
 153         /* CLKSEL_CON3 */
 154         PCLK_DBG_B_DIV_SHIFT            = 0x8,
 155         PCLK_DBG_B_DIV_MASK             = 0x1f << PCLK_DBG_B_DIV_SHIFT,
 156         ATCLK_CORE_B_DIV_SHIFT          = 0,
 157         ATCLK_CORE_B_DIV_MASK           = 0x1f << ATCLK_CORE_B_DIV_SHIFT,
 158
 159         /* CLKSEL_CON14 */
 160         PCLK_PERIHP_DIV_CON_SHIFT       = 12,
 161         PCLK_PERIHP_DIV_CON_MASK        = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT,
 162         HCLK_PERIHP_DIV_CON_SHIFT       = 8,
 163         HCLK_PERIHP_DIV_CON_MASK        = 3 << HCLK_PERIHP_DIV_CON_SHIFT,
 164         ACLK_PERIHP_PLL_SEL_SHIFT       = 7,
 165         ACLK_PERIHP_PLL_SEL_MASK        = 1 << ACLK_PERIHP_PLL_SEL_SHIFT,
 166         ACLK_PERIHP_PLL_SEL_CPLL        = 0,
 167         ACLK_PERIHP_PLL_SEL_GPLL        = 1,
 168         ACLK_PERIHP_DIV_CON_SHIFT       = 0,
 169         ACLK_PERIHP_DIV_CON_MASK        = 0x1f,
 170
 171         /* CLKSEL_CON21 */
 172         ACLK_EMMC_PLL_SEL_SHIFT         = 7,
 173         ACLK_EMMC_PLL_SEL_MASK          = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT,
 174         ACLK_EMMC_PLL_SEL_GPLL          = 0x1,
 175         ACLK_EMMC_DIV_CON_SHIFT         = 0,
 176         ACLK_EMMC_DIV_CON_MASK          = 0x1f,
 177
 178         /* CLKSEL_CON22 */
 179         CLK_EMMC_PLL_SHIFT              = 8,
 180         CLK_EMMC_PLL_MASK               = 0x7 << CLK_EMMC_PLL_SHIFT,
 181         CLK_EMMC_PLL_SEL_GPLL           = 0x1,
 182         CLK_EMMC_PLL_SEL_24M            = 0x5,
 183         CLK_EMMC_DIV_CON_SHIFT          = 0,
 184         CLK_EMMC_DIV_CON_MASK           = 0x7f << CLK_EMMC_DIV_CON_SHIFT,
 185
 186         /* CLKSEL_CON23 */
 187         PCLK_PERILP0_DIV_CON_SHIFT      = 12,
 188         PCLK_PERILP0_DIV_CON_MASK       = 0x7 << PCLK_PERILP0_DIV_CON_SHIFT,
 189         HCLK_PERILP0_DIV_CON_SHIFT      = 8,
 190         HCLK_PERILP0_DIV_CON_MASK       = 3 << HCLK_PERILP0_DIV_CON_SHIFT,
 191         ACLK_PERILP0_PLL_SEL_SHIFT      = 7,
 192         ACLK_PERILP0_PLL_SEL_MASK       = 1 << ACLK_PERILP0_PLL_SEL_SHIFT,
 193         ACLK_PERILP0_PLL_SEL_CPLL       = 0,
 194         ACLK_PERILP0_PLL_SEL_GPLL       = 1,
 195         ACLK_PERILP0_DIV_CON_SHIFT      = 0,
 196         ACLK_PERILP0_DIV_CON_MASK       = 0x1f,
 197
 198         /* CLKSEL_CON25 */
 199         PCLK_PERILP1_DIV_CON_SHIFT      = 8,
 200         PCLK_PERILP1_DIV_CON_MASK       = 0x7 << PCLK_PERILP1_DIV_CON_SHIFT,
 201         HCLK_PERILP1_PLL_SEL_SHIFT      = 7,
 202         HCLK_PERILP1_PLL_SEL_MASK       = 1 << HCLK_PERILP1_PLL_SEL_SHIFT,
 203         HCLK_PERILP1_PLL_SEL_CPLL       = 0,
 204         HCLK_PERILP1_PLL_SEL_GPLL       = 1,
 205         HCLK_PERILP1_DIV_CON_SHIFT      = 0,
 206         HCLK_PERILP1_DIV_CON_MASK       = 0x1f,
 207
 208         /* CLKSEL_CON26 */
 209         CLK_SARADC_DIV_CON_SHIFT        = 8,
 210         CLK_SARADC_DIV_CON_MASK         = GENMASK(15, 8),
 211         CLK_SARADC_DIV_CON_WIDTH        = 8,
 212
 213         /* CLKSEL_CON27 */
 214         CLK_TSADC_SEL_X24M              = 0x0,
 215         CLK_TSADC_SEL_SHIFT             = 15,
 216         CLK_TSADC_SEL_MASK              = 1 << CLK_TSADC_SEL_SHIFT,
 217         CLK_TSADC_DIV_CON_SHIFT         = 0,
 218         CLK_TSADC_DIV_CON_MASK          = 0x3ff,
 219
 220         /* CLKSEL_CON47 & CLKSEL_CON48 */
 221         ACLK_VOP_PLL_SEL_SHIFT          = 6,
 222         ACLK_VOP_PLL_SEL_MASK           = 0x3 << ACLK_VOP_PLL_SEL_SHIFT,
 223         ACLK_VOP_PLL_SEL_CPLL           = 0x1,
 224         ACLK_VOP_DIV_CON_SHIFT          = 0,
 225         ACLK_VOP_DIV_CON_MASK           = 0x1f << ACLK_VOP_DIV_CON_SHIFT,
 226
 227         /* CLKSEL_CON49 & CLKSEL_CON50 */
 228         DCLK_VOP_DCLK_SEL_SHIFT         = 11,
 229         DCLK_VOP_DCLK_SEL_MASK          = 1 << DCLK_VOP_DCLK_SEL_SHIFT,
 230         DCLK_VOP_DCLK_SEL_DIVOUT        = 0,
 231         DCLK_VOP_PLL_SEL_SHIFT          = 8,
 232         DCLK_VOP_PLL_SEL_MASK           = 3 << DCLK_VOP_PLL_SEL_SHIFT,
 233         DCLK_VOP_PLL_SEL_VPLL           = 0,
 234         DCLK_VOP_DIV_CON_MASK           = 0xff,
 235         DCLK_VOP_DIV_CON_SHIFT          = 0,
 236
 237         /* CLKSEL_CON57 */
 238         PCLK_ALIVE_DIV_CON_SHIFT        = 0,
 239         PCLK_ALIVE_DIV_CON_MASK         = 0x1f << PCLK_ALIVE_DIV_CON_SHIFT,
 240
 241         /* CLKSEL_CON58 */
 242         CLK_SPI_PLL_SEL_WIDTH = 1,
 243         CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1),
 244         CLK_SPI_PLL_SEL_CPLL = 0,
 245         CLK_SPI_PLL_SEL_GPLL = 1,
 246         CLK_SPI_PLL_DIV_CON_WIDTH = 7,
 247         CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1),
 248
 249         CLK_SPI5_PLL_DIV_CON_SHIFT      = 8,
 250         CLK_SPI5_PLL_SEL_SHIFT          = 15,
 251
 252         /* CLKSEL_CON59 */
 253         CLK_SPI1_PLL_SEL_SHIFT          = 15,
 254         CLK_SPI1_PLL_DIV_CON_SHIFT      = 8,
 255         CLK_SPI0_PLL_SEL_SHIFT          = 7,
 256         CLK_SPI0_PLL_DIV_CON_SHIFT      = 0,
 257
 258         /* CLKSEL_CON60 */
 259         CLK_SPI4_PLL_SEL_SHIFT          = 15,
 260         CLK_SPI4_PLL_DIV_CON_SHIFT      = 8,
 261         CLK_SPI2_PLL_SEL_SHIFT          = 7,
 262         CLK_SPI2_PLL_DIV_CON_SHIFT      = 0,
 263
 264         /* CLKSEL_CON61 */
 265         CLK_I2C_PLL_SEL_MASK            = 1,
 266         CLK_I2C_PLL_SEL_CPLL            = 0,
 267         CLK_I2C_PLL_SEL_GPLL            = 1,
 268         CLK_I2C5_PLL_SEL_SHIFT          = 15,
 269         CLK_I2C5_DIV_CON_SHIFT          = 8,
 270         CLK_I2C1_PLL_SEL_SHIFT          = 7,
 271         CLK_I2C1_DIV_CON_SHIFT          = 0,
 272
 273         /* CLKSEL_CON62 */
 274         CLK_I2C6_PLL_SEL_SHIFT          = 15,
 275         CLK_I2C6_DIV_CON_SHIFT          = 8,
 276         CLK_I2C2_PLL_SEL_SHIFT          = 7,
 277         CLK_I2C2_DIV_CON_SHIFT          = 0,
 278
 279         /* CLKSEL_CON63 */
 280         CLK_I2C7_PLL_SEL_SHIFT          = 15,
 281         CLK_I2C7_DIV_CON_SHIFT          = 8,
 282         CLK_I2C3_PLL_SEL_SHIFT          = 7,
 283         CLK_I2C3_DIV_CON_SHIFT          = 0,
 284
 285         /* CRU_SOFTRST_CON4 */
 286         RESETN_DDR0_REQ_SHIFT           = 8,
 287         RESETN_DDR0_REQ_MASK            = 1 << RESETN_DDR0_REQ_SHIFT,
 288         RESETN_DDRPHY0_REQ_SHIFT        = 9,
 289         RESETN_DDRPHY0_REQ_MASK         = 1 << RESETN_DDRPHY0_REQ_SHIFT,
 290         RESETN_DDR1_REQ_SHIFT           = 12,
 291         RESETN_DDR1_REQ_MASK            = 1 << RESETN_DDR1_REQ_SHIFT,
 292         RESETN_DDRPHY1_REQ_SHIFT        = 13,
 293         RESETN_DDRPHY1_REQ_MASK         = 1 << RESETN_DDRPHY1_REQ_SHIFT,
 294 };
 295
 296 #define VCO_MAX_KHZ     (3200 * (MHz / KHz))
 297 #define VCO_MIN_KHZ     (800 * (MHz / KHz))
 298 #define OUTPUT_MAX_KHZ  (3200 * (MHz / KHz))
 299 #define OUTPUT_MIN_KHZ  (16 * (MHz / KHz))
 300
 301 /*
 302  *  the div restructions of pll in integer mode, these are defined in
 303  *  * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0
 304  */
 305 #define PLL_DIV_MIN     16
 306 #define PLL_DIV_MAX     3200
 307
 308 /*
 309  * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
 310  * Formulas also embedded within the Fractional PLL Verilog model:
 311  * If DSMPD = 1 (DSM is disabled, "integer mode")
 312  * FOUTVCO = FREF / REFDIV * FBDIV
 313  * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
 314  * Where:
 315  * FOUTVCO = Fractional PLL non-divided output frequency
 316  * FOUTPOSTDIV = Fractional PLL divided output frequency
 317  *               (output of second post divider)
 318  * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
 319  * REFDIV = Fractional PLL input reference clock divider
 320  * FBDIV = Integer value programmed into feedback divide
 321  *
 322  */
 323 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div)
 324 {
 325         /* All 8 PLLs have same VCO and output frequency range restrictions. */
 326         u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv;
 327         u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
 328
 329         debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, "
 330                            "postdiv2=%d, vco=%u khz, output=%u khz\n",
 331                            pll_con, div->fbdiv, div->refdiv, div->postdiv1,
 332                            div->postdiv2, vco_khz, output_khz);
 333         assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
 334                output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ &&
 335                div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX);
 336
 337         /*
 338          * When power on or changing PLL setting,
 339          * we must force PLL into slow mode to ensure output stable clock.
 340          */
 341         rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
 342                      PLL_MODE_SLOW << PLL_MODE_SHIFT);
 343
 344         /* use integer mode */
 345         rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK,
 346                      PLL_INTEGER_MODE << PLL_DSMPD_SHIFT);
 347
 348         rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK,
 349                      div->fbdiv << PLL_FBDIV_SHIFT);
 350         rk_clrsetreg(&pll_con[1],
 351                      PLL_POSTDIV2_MASK | PLL_POSTDIV1_MASK |
 352                      PLL_REFDIV_MASK | PLL_REFDIV_SHIFT,
 353                      (div->postdiv2 << PLL_POSTDIV2_SHIFT) |
 354                      (div->postdiv1 << PLL_POSTDIV1_SHIFT) |
 355                      (div->refdiv << PLL_REFDIV_SHIFT));
 356
 357         /* waiting for pll lock */
 358         while (!(readl(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT)))
 359                 udelay(1);
 360
 361         /* pll enter normal mode */
 362         rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
 363                      PLL_MODE_NORM << PLL_MODE_SHIFT);
 364 }
 365
 366 static int pll_para_config(u32 freq_hz, struct pll_div *div)
 367 {
 368         u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0;
 369         u32 postdiv1, postdiv2 = 1;
 370         u32 fref_khz;
 371         u32 diff_khz, best_diff_khz;
 372         const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16;
 373         const u32 max_postdiv1 = 7, max_postdiv2 = 7;
 374         u32 vco_khz;
 375         u32 freq_khz = freq_hz / KHz;
 376
 377         if (!freq_hz) {
 378                 printf("%s: the frequency can't be 0 Hz\n", __func__);
 379                 return -1;
 380         }
 381
 382         postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
 383         if (postdiv1 > max_postdiv1) {
 384                 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1);
 385                 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2);
 386         }
 387
 388         vco_khz = freq_khz * postdiv1 * postdiv2;
 389
 390         if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ ||
 391             postdiv2 > max_postdiv2) {
 392                 printf("%s: Cannot find out a supported VCO"
 393                        " for Frequency (%uHz).\n", __func__, freq_hz);
 394                 return -1;
 395         }
 396
 397         div->postdiv1 = postdiv1;
 398         div->postdiv2 = postdiv2;
 399
 400         best_diff_khz = vco_khz;
 401         for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) {
 402                 fref_khz = ref_khz / refdiv;
 403
 404                 fbdiv = vco_khz / fref_khz;
 405                 if (fbdiv >= max_fbdiv || fbdiv <= min_fbdiv)
 406                         continue;
 407                 diff_khz = vco_khz - fbdiv * fref_khz;
 408                 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) {
 409                         fbdiv++;
 410                         diff_khz = fref_khz - diff_khz;
 411                 }
 412
 413                 if (diff_khz >= best_diff_khz)
 414                         continue;
 415
 416                 best_diff_khz = diff_khz;
 417                 div->refdiv = refdiv;
 418                 div->fbdiv = fbdiv;
 419         }
 420
 421         if (best_diff_khz > 4 * (MHz / KHz)) {
 422                 printf("%s: Failed to match output frequency %u, "
 423                        "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz,
 424                        best_diff_khz * KHz);
 425                 return -1;
 426         }
 427         return 0;
 428 }
 429
 430 void rk3399_configure_cpu_l(struct rockchip_cru *cru,
 431                             enum apll_l_frequencies apll_l_freq)
 432 {
 433         u32 aclkm_div;
 434         u32 pclk_dbg_div;
 435         u32 atclk_div;
 436
 437         /* Setup cluster L */
 438         rkclk_set_pll(&cru->apll_l_con[0], apll_l_cfgs[apll_l_freq]);
 439
 440         aclkm_div = LPLL_HZ / ACLKM_CORE_L_HZ - 1;
 441         assert((aclkm_div + 1) * ACLKM_CORE_L_HZ == LPLL_HZ &&
 442                aclkm_div < 0x1f);
 443
 444         pclk_dbg_div = LPLL_HZ / PCLK_DBG_L_HZ - 1;
 445         assert((pclk_dbg_div + 1) * PCLK_DBG_L_HZ == LPLL_HZ &&
 446                pclk_dbg_div < 0x1f);
 447
 448         atclk_div = LPLL_HZ / ATCLK_CORE_L_HZ - 1;
 449         assert((atclk_div + 1) * ATCLK_CORE_L_HZ == LPLL_HZ &&
 450                atclk_div < 0x1f);
 451
 452         rk_clrsetreg(&cru->clksel_con[0],
 453                      ACLKM_CORE_L_DIV_CON_MASK | CLK_CORE_L_PLL_SEL_MASK |
 454                      CLK_CORE_L_DIV_MASK,
 455                      aclkm_div << ACLKM_CORE_L_DIV_CON_SHIFT |
 456                      CLK_CORE_L_PLL_SEL_ALPLL << CLK_CORE_L_PLL_SEL_SHIFT |
 457                      0 << CLK_CORE_L_DIV_SHIFT);
 458
 459         rk_clrsetreg(&cru->clksel_con[1],
 460                      PCLK_DBG_L_DIV_MASK | ATCLK_CORE_L_DIV_MASK,
 461                      pclk_dbg_div << PCLK_DBG_L_DIV_SHIFT |
 462                      atclk_div << ATCLK_CORE_L_DIV_SHIFT);
 463 }
 464
 465 void rk3399_configure_cpu_b(struct rockchip_cru *cru,
 466                             enum apll_b_frequencies apll_b_freq)
 467 {
 468         u32 aclkm_div;
 469         u32 pclk_dbg_div;
 470         u32 atclk_div;
 471
 472         /* Setup cluster B */
 473         rkclk_set_pll(&cru->apll_b_con[0], apll_b_cfgs[apll_b_freq]);
 474
 475         aclkm_div = BPLL_HZ / ACLKM_CORE_B_HZ - 1;
 476         assert((aclkm_div + 1) * ACLKM_CORE_B_HZ == BPLL_HZ &&
 477                aclkm_div < 0x1f);
 478
 479         pclk_dbg_div = BPLL_HZ / PCLK_DBG_B_HZ - 1;
 480         assert((pclk_dbg_div + 1) * PCLK_DBG_B_HZ == BPLL_HZ &&
 481                pclk_dbg_div < 0x1f);
 482
 483         atclk_div = BPLL_HZ / ATCLK_CORE_B_HZ - 1;
 484         assert((atclk_div + 1) * ATCLK_CORE_B_HZ == BPLL_HZ &&
 485                atclk_div < 0x1f);
 486
 487         rk_clrsetreg(&cru->clksel_con[2],
 488                      ACLKM_CORE_B_DIV_CON_MASK | CLK_CORE_B_PLL_SEL_MASK |
 489                      CLK_CORE_B_DIV_MASK,
 490                      aclkm_div << ACLKM_CORE_B_DIV_CON_SHIFT |
 491                      CLK_CORE_B_PLL_SEL_ABPLL << CLK_CORE_B_PLL_SEL_SHIFT |
 492                      0 << CLK_CORE_B_DIV_SHIFT);
 493
 494         rk_clrsetreg(&cru->clksel_con[3],
 495                      PCLK_DBG_B_DIV_MASK | ATCLK_CORE_B_DIV_MASK,
 496                      pclk_dbg_div << PCLK_DBG_B_DIV_SHIFT |
 497                      atclk_div << ATCLK_CORE_B_DIV_SHIFT);
 498 }
 499
 500 #define I2C_CLK_REG_MASK(bus) \
 501         (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT | \
 502          CLK_I2C_PLL_SEL_MASK << CLK_I2C ##bus## _PLL_SEL_SHIFT)
 503
 504 #define I2C_CLK_REG_VALUE(bus, clk_div) \
 505         ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT | \
 506          CLK_I2C_PLL_SEL_GPLL << CLK_I2C ##bus## _PLL_SEL_SHIFT)
 507
 508 #define I2C_CLK_DIV_VALUE(con, bus) \
 509         ((con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & I2C_DIV_CON_MASK)
 510
 511 #define I2C_PMUCLK_REG_MASK(bus) \
 512         (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT)
 513
 514 #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \
 515         ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT)
 516
 517 static ulong rk3399_i2c_get_clk(struct rockchip_cru *cru, ulong clk_id)
 518 {
 519         u32 div, con;
 520
 521         switch (clk_id) {
 522         case SCLK_I2C1:
 523                 con = readl(&cru->clksel_con[61]);
 524                 div = I2C_CLK_DIV_VALUE(con, 1);
 525                 break;
 526         case SCLK_I2C2:
 527                 con = readl(&cru->clksel_con[62]);
 528                 div = I2C_CLK_DIV_VALUE(con, 2);
 529                 break;
 530         case SCLK_I2C3:
 531                 con = readl(&cru->clksel_con[63]);
 532                 div = I2C_CLK_DIV_VALUE(con, 3);
 533                 break;
 534         case SCLK_I2C5:
 535                 con = readl(&cru->clksel_con[61]);
 536                 div = I2C_CLK_DIV_VALUE(con, 5);
 537                 break;
 538         case SCLK_I2C6:
 539                 con = readl(&cru->clksel_con[62]);
 540                 div = I2C_CLK_DIV_VALUE(con, 6);
 541                 break;
 542         case SCLK_I2C7:
 543                 con = readl(&cru->clksel_con[63]);
 544                 div = I2C_CLK_DIV_VALUE(con, 7);
 545                 break;
 546         default:
 547                 printf("do not support this i2c bus\n");
 548                 return -EINVAL;
 549         }
 550
 551         return DIV_TO_RATE(GPLL_HZ, div);
 552 }
 553
 554 static ulong rk3399_i2c_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
 555 {
 556         int src_clk_div;
 557
 558         /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/
 559         src_clk_div = GPLL_HZ / hz;
 560         assert(src_clk_div - 1 < 127);
 561
 562         switch (clk_id) {
 563         case SCLK_I2C1:
 564                 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1),
 565                              I2C_CLK_REG_VALUE(1, src_clk_div));
 566                 break;
 567         case SCLK_I2C2:
 568                 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2),
 569                              I2C_CLK_REG_VALUE(2, src_clk_div));
 570                 break;
 571         case SCLK_I2C3:
 572                 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3),
 573                              I2C_CLK_REG_VALUE(3, src_clk_div));
 574                 break;
 575         case SCLK_I2C5:
 576                 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(5),
 577                              I2C_CLK_REG_VALUE(5, src_clk_div));
 578                 break;
 579         case SCLK_I2C6:
 580                 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(6),
 581                              I2C_CLK_REG_VALUE(6, src_clk_div));
 582                 break;
 583         case SCLK_I2C7:
 584                 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(7),
 585                              I2C_CLK_REG_VALUE(7, src_clk_div));
 586                 break;
 587         default:
 588                 printf("do not support this i2c bus\n");
 589                 return -EINVAL;
 590         }
 591
 592         return rk3399_i2c_get_clk(cru, clk_id);
 593 }
 594
 595 /*
 596  * RK3399 SPI clocks have a common divider-width (7 bits) and a single bit
 597  * to select either CPLL or GPLL as the clock-parent. The location within
 598  * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable.
 599  */
 600
 601 struct spi_clkreg {
 602         u8 reg;  /* CLKSEL_CON[reg] register in CRU */
 603         u8 div_shift;
 604         u8 sel_shift;
 605 };
 606
 607 /*
 608  * The entries are numbered relative to their offset from SCLK_SPI0.
 609  *
 610  * Note that SCLK_SPI3 (which is configured via PMUCRU and requires different
 611  * logic is not supported).
 612  */
 613 static const struct spi_clkreg spi_clkregs[] = {
 614         [0] = { .reg = 59,
 615                 .div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT,
 616                 .sel_shift = CLK_SPI0_PLL_SEL_SHIFT, },
 617         [1] = { .reg = 59,
 618                 .div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT,
 619                 .sel_shift = CLK_SPI1_PLL_SEL_SHIFT, },
 620         [2] = { .reg = 60,
 621                 .div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT,
 622                 .sel_shift = CLK_SPI2_PLL_SEL_SHIFT, },
 623         [3] = { .reg = 60,
 624                 .div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT,
 625                 .sel_shift = CLK_SPI4_PLL_SEL_SHIFT, },
 626         [4] = { .reg = 58,
 627                 .div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT,
 628                 .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, },
 629 };
 630
 631 static ulong rk3399_spi_get_clk(struct rockchip_cru *cru, ulong clk_id)
 632 {
 633         const struct spi_clkreg *spiclk = NULL;
 634         u32 div, val;
 635
 636         switch (clk_id) {
 637         case SCLK_SPI0 ... SCLK_SPI5:
 638                 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
 639                 break;
 640
 641         default:
 642                 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
 643                 return -EINVAL;
 644         }
 645
 646         val = readl(&cru->clksel_con[spiclk->reg]);
 647         div = bitfield_extract(val, spiclk->div_shift,
 648                                CLK_SPI_PLL_DIV_CON_WIDTH);
 649
 650         return DIV_TO_RATE(GPLL_HZ, div);
 651 }
 652
 653 static ulong rk3399_spi_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
 654 {
 655         const struct spi_clkreg *spiclk = NULL;
 656         int src_clk_div;
 657
 658         src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
 659         assert(src_clk_div < 128);
 660
 661         switch (clk_id) {
 662         case SCLK_SPI1 ... SCLK_SPI5:
 663                 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
 664                 break;
 665
 666         default:
 667                 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
 668                 return -EINVAL;
 669         }
 670
 671         rk_clrsetreg(&cru->clksel_con[spiclk->reg],
 672                      ((CLK_SPI_PLL_DIV_CON_MASK << spiclk->div_shift) |
 673                        (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)),
 674                      ((src_clk_div << spiclk->div_shift) |
 675                       (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)));
 676
 677         return rk3399_spi_get_clk(cru, clk_id);
 678 }
 679
 680 static ulong rk3399_vop_set_clk(struct rockchip_cru *cru, ulong clk_id, u32 hz)
 681 {
 682         struct pll_div vpll_config = {0};
 683         int aclk_vop = 198 * MHz;
 684         void *aclkreg_addr, *dclkreg_addr;
 685         u32 div;
 686
 687         switch (clk_id) {
 688         case DCLK_VOP0:
 689                 aclkreg_addr = &cru->clksel_con[47];
 690                 dclkreg_addr = &cru->clksel_con[49];
 691                 break;
 692         case DCLK_VOP1:
 693                 aclkreg_addr = &cru->clksel_con[48];
 694                 dclkreg_addr = &cru->clksel_con[50];
 695                 break;
 696         default:
 697                 return -EINVAL;
 698         }
 699         /* vop aclk source clk: cpll */
 700         div = CPLL_HZ / aclk_vop;
 701         assert(div - 1 < 32);
 702
 703         rk_clrsetreg(aclkreg_addr,
 704                      ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK,
 705                      ACLK_VOP_PLL_SEL_CPLL << ACLK_VOP_PLL_SEL_SHIFT |
 706                      (div - 1) << ACLK_VOP_DIV_CON_SHIFT);
 707
 708         /* vop dclk source from vpll, and equals to vpll(means div == 1) */
 709         if (pll_para_config(hz, &vpll_config))
 710                 return -1;
 711
 712         rkclk_set_pll(&cru->vpll_con[0], &vpll_config);
 713
 714         rk_clrsetreg(dclkreg_addr,
 715                      DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK |
 716                      DCLK_VOP_DIV_CON_MASK,
 717                      DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT |
 718                      DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT |
 719                      (1 - 1) << DCLK_VOP_DIV_CON_SHIFT);
 720
 721         return hz;
 722 }
 723
 724 static ulong rk3399_mmc_get_clk(struct rockchip_cru *cru, uint clk_id)
 725 {
 726         u32 div, con;
 727
 728         switch (clk_id) {
 729         case HCLK_SDMMC:
 730         case SCLK_SDMMC:
 731                 con = readl(&cru->clksel_con[16]);
 732                 /* dwmmc controller have internal div 2 */
 733                 div = 2;
 734                 break;
 735         case SCLK_EMMC:
 736                 con = readl(&cru->clksel_con[22]);
 737                 div = 1;
 738                 break;
 739         default:
 740                 return -EINVAL;
 741         }
 742
 743         div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
 744         if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
 745                         == CLK_EMMC_PLL_SEL_24M)
 746                 return DIV_TO_RATE(OSC_HZ, div);
 747         else
 748                 return DIV_TO_RATE(GPLL_HZ, div);
 749 }
 750
 751 static ulong rk3399_mmc_set_clk(struct rockchip_cru *cru,
 752                                 ulong clk_id, ulong set_rate)
 753 {
 754         int src_clk_div;
 755         int aclk_emmc = 198 * MHz;
 756
 757         switch (clk_id) {
 758         case HCLK_SDMMC:
 759         case SCLK_SDMMC:
 760                 /* Select clk_sdmmc source from GPLL by default */
 761                 /* mmc clock defaulg div 2 internal, provide double in cru */
 762                 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);
 763
 764                 if (src_clk_div > 128) {
 765                         /* use 24MHz source for 400KHz clock */
 766                         src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
 767                         assert(src_clk_div - 1 < 128);
 768                         rk_clrsetreg(&cru->clksel_con[16],
 769                                      CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
 770                                      CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
 771                                      (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
 772                 } else {
 773                         rk_clrsetreg(&cru->clksel_con[16],
 774                                      CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
 775                                      CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
 776                                      (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
 777                 }
 778                 break;
 779         case SCLK_EMMC:
 780                 /* Select aclk_emmc source from GPLL */
 781                 src_clk_div = DIV_ROUND_UP(GPLL_HZ, aclk_emmc);
 782                 assert(src_clk_div - 1 < 32);
 783
 784                 rk_clrsetreg(&cru->clksel_con[21],
 785                              ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK,
 786                              ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT |
 787                              (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT);
 788
 789                 /* Select clk_emmc source from GPLL too */
 790                 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate);
 791                 assert(src_clk_div - 1 < 128);
 792
 793                 rk_clrsetreg(&cru->clksel_con[22],
 794                              CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
 795                              CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
 796                              (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
 797                 break;
 798         default:
 799                 return -EINVAL;
 800         }
 801         return rk3399_mmc_get_clk(cru, clk_id);
 802 }
 803
 804 static ulong rk3399_gmac_set_clk(struct rockchip_cru *cru, ulong rate)
 805 {
 806         ulong ret;
 807
 808         /*
 809          * The RGMII CLK can be derived either from an external "clkin"
 810          * or can be generated from internally by a divider from SCLK_MAC.
 811          */
 812         if (readl(&cru->clksel_con[19]) & BIT(4)) {
 813                 /* An external clock will always generate the right rate... */
 814                 ret = rate;
 815         } else {
 816                 /*
 817                  * No platform uses an internal clock to date.
 818                  * Implement this once it becomes necessary and print an error
 819                  * if someone tries to use it (while it remains unimplemented).
 820                  */
 821                 pr_err("%s: internal clock is UNIMPLEMENTED\n", __func__);
 822                 ret = 0;
 823         }
 824
 825         return ret;
 826 }
 827
 828 #define PMUSGRF_DDR_RGN_CON16 0xff330040
 829 static ulong rk3399_ddr_set_clk(struct rockchip_cru *cru,
 830                                 ulong set_rate)
 831 {
 832         struct pll_div dpll_cfg;
 833
 834         /*  IC ECO bug, need to set this register */
 835         writel(0xc000c000, PMUSGRF_DDR_RGN_CON16);
 836
 837         /*  clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
 838         switch (set_rate) {
 839         case 50 * MHz:
 840                 dpll_cfg = (struct pll_div)
 841                 {.refdiv = 1, .fbdiv = 12, .postdiv1 = 3, .postdiv2 = 2};
 842                 break;
 843         case 200 * MHz:
 844                 dpll_cfg = (struct pll_div)
 845                 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1};
 846                 break;
 847         case 300 * MHz:
 848                 dpll_cfg = (struct pll_div)
 849                 {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1};
 850                 break;
 851         case 400 * MHz:
 852                 dpll_cfg = (struct pll_div)
 853                 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
 854                 break;
 855         case 666 * MHz:
 856                 dpll_cfg = (struct pll_div)
 857                 {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1};
 858                 break;
 859         case 800 * MHz:
 860                 dpll_cfg = (struct pll_div)
 861                 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
 862                 break;
 863         case 933 * MHz:
 864                 dpll_cfg = (struct pll_div)
 865                 {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1};
 866                 break;
 867         default:
 868                 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate);
 869         }
 870         rkclk_set_pll(&cru->dpll_con[0], &dpll_cfg);
 871
 872         return set_rate;
 873 }
 874
 875 static ulong rk3399_alive_get_clk(struct rockchip_cru *cru)
 876 {
 877         u32 div, val;
 878
 879         val = readl(&cru->clksel_con[57]);
 880         div = (val & PCLK_ALIVE_DIV_CON_MASK) >>
 881                PCLK_ALIVE_DIV_CON_SHIFT;
 882
 883         return DIV_TO_RATE(GPLL_HZ, div);
 884 }
 885
 886 static ulong rk3399_saradc_get_clk(struct rockchip_cru *cru)
 887 {
 888         u32 div, val;
 889
 890         val = readl(&cru->clksel_con[26]);
 891         div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
 892                                CLK_SARADC_DIV_CON_WIDTH);
 893
 894         return DIV_TO_RATE(OSC_HZ, div);
 895 }
 896
 897 static ulong rk3399_saradc_set_clk(struct rockchip_cru *cru, uint hz)
 898 {
 899         int src_clk_div;
 900
 901         src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
 902         assert(src_clk_div < 128);
 903
 904         rk_clrsetreg(&cru->clksel_con[26],
 905                      CLK_SARADC_DIV_CON_MASK,
 906                      src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
 907
 908         return rk3399_saradc_get_clk(cru);
 909 }
 910
 911 static ulong rk3399_clk_get_rate(struct clk *clk)
 912 {
 913         struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
 914         ulong rate = 0;
 915
 916         switch (clk->id) {
 917         case 0 ... 63:
 918                 return 0;
 919         case HCLK_SDMMC:
 920         case SCLK_SDMMC:
 921         case SCLK_EMMC:
 922                 rate = rk3399_mmc_get_clk(priv->cru, clk->id);
 923                 break;
 924         case SCLK_I2C1:
 925         case SCLK_I2C2:
 926         case SCLK_I2C3:
 927         case SCLK_I2C5:
 928         case SCLK_I2C6:
 929         case SCLK_I2C7:
 930                 rate = rk3399_i2c_get_clk(priv->cru, clk->id);
 931                 break;
 932         case SCLK_SPI0...SCLK_SPI5:
 933                 rate = rk3399_spi_get_clk(priv->cru, clk->id);
 934                 break;
 935         case SCLK_UART0:
 936         case SCLK_UART1:
 937         case SCLK_UART2:
 938         case SCLK_UART3:
 939                 return 24000000;
 940         case PCLK_HDMI_CTRL:
 941                 break;
 942         case DCLK_VOP0:
 943         case DCLK_VOP1:
 944                 break;
 945         case PCLK_EFUSE1024NS:
 946                 break;
 947         case SCLK_SARADC:
 948                 rate = rk3399_saradc_get_clk(priv->cru);
 949                 break;
 950         case ACLK_VIO:
 951         case ACLK_HDCP:
 952         case ACLK_GIC_PRE:
 953         case PCLK_DDR:
 954                 break;
 955         case PCLK_ALIVE:
 956         case PCLK_WDT:
 957                 rate = rk3399_alive_get_clk(priv->cru);
 958                 break;
 959         default:
 960                 log_debug("Unknown clock %lu\n", clk->id);
 961                 return -ENOENT;
 962         }
 963
 964         return rate;
 965 }
 966
 967 static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
 968 {
 969         struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
 970         ulong ret = 0;
 971
 972         switch (clk->id) {
 973         case 0 ... 63:
 974                 return 0;
 975
 976         case ACLK_PERIHP:
 977         case HCLK_PERIHP:
 978         case PCLK_PERIHP:
 979                 return 0;
 980
 981         case ACLK_PERILP0:
 982         case HCLK_PERILP0:
 983         case PCLK_PERILP0:
 984                 return 0;
 985
 986         case ACLK_CCI:
 987                 return 0;
 988
 989         case HCLK_PERILP1:
 990         case PCLK_PERILP1:
 991                 return 0;
 992
 993         case HCLK_SDMMC:
 994         case SCLK_SDMMC:
 995         case SCLK_EMMC:
 996                 ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate);
 997                 break;
 998         case SCLK_MAC:
 999                 ret = rk3399_gmac_set_clk(priv->cru, rate);
1000                 break;
1001         case SCLK_I2C1:
1002         case SCLK_I2C2:
1003         case SCLK_I2C3:
1004         case SCLK_I2C5:
1005         case SCLK_I2C6:
1006         case SCLK_I2C7:
1007                 ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate);
1008                 break;
1009         case SCLK_SPI0...SCLK_SPI5:
1010                 ret = rk3399_spi_set_clk(priv->cru, clk->id, rate);
1011                 break;
1012         case PCLK_HDMI_CTRL:
1013         case PCLK_VIO_GRF:
1014                 /* the PCLK gates for video are enabled by default */
1015                 break;
1016         case DCLK_VOP0:
1017         case DCLK_VOP1:
1018                 ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);
1019                 break;
1020         case ACLK_VOP1:
1021         case HCLK_VOP1:
1022         case HCLK_SD:
1023         case SCLK_UPHY0_TCPDCORE:
1024         case SCLK_UPHY1_TCPDCORE:
1025                 /**
1026                  * assigned-clocks handling won't require for vopl, so
1027                  * return 0 to satisfy clk_set_defaults during device probe.
1028                  */
1029                 return 0;
1030         case SCLK_DDRCLK:
1031                 ret = rk3399_ddr_set_clk(priv->cru, rate);
1032                 break;
1033         case PCLK_EFUSE1024NS:
1034                 break;
1035         case SCLK_SARADC:
1036                 ret = rk3399_saradc_set_clk(priv->cru, rate);
1037                 break;
1038         case ACLK_VIO:
1039         case ACLK_HDCP:
1040         case ACLK_GIC_PRE:
1041         case PCLK_DDR:
1042                 return 0;
1043         default:
1044                 log_debug("Unknown clock %lu\n", clk->id);
1045                 return -ENOENT;
1046         }
1047
1048         return ret;
1049 }
1050
1051 static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk,
1052                                                  struct clk *parent)
1053 {
1054         struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
1055         const char *clock_output_name;
1056         int ret;
1057
1058         /*
1059          * If the requested parent is in the same clock-controller and
1060          * the id is SCLK_MAC ("clk_gmac"), switch to the internal clock.
1061          */
1062         if (parent->dev == clk->dev && parent->id == SCLK_MAC) {
1063                 debug("%s: switching RGMII to SCLK_MAC\n", __func__);
1064                 rk_clrreg(&priv->cru->clksel_con[19], BIT(4));
1065                 return 0;
1066         }
1067
1068         /*
1069          * Otherwise, we need to check the clock-output-names of the
1070          * requested parent to see if the requested id is "clkin_gmac".
1071          */
1072         ret = dev_read_string_index(parent->dev, "clock-output-names",
1073                                     parent->id, &clock_output_name);
1074         if (ret < 0)
1075                 return -ENODATA;
1076
1077         /* If this is "clkin_gmac", switch to the external clock input */
1078         if (!strcmp(clock_output_name, "clkin_gmac")) {
1079                 debug("%s: switching RGMII to CLKIN\n", __func__);
1080                 rk_setreg(&priv->cru->clksel_con[19], BIT(4));
1081                 return 0;
1082         }
1083
1084         return -EINVAL;
1085 }
1086
1087 static int __maybe_unused rk3399_clk_set_parent(struct clk *clk,
1088                                                 struct clk *parent)
1089 {
1090         switch (clk->id) {
1091         case SCLK_RMII_SRC:
1092                 return rk3399_gmac_set_parent(clk, parent);
1093         }
1094
1095         debug("%s: unsupported clk %ld\n", __func__, clk->id);
1096         return -ENOENT;
1097 }
1098
1099 static int rk3399_clk_enable(struct clk *clk)
1100 {
1101         struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
1102
1103         switch (clk->id) {
1104         case SCLK_MAC:
1105                 rk_clrreg(&priv->cru->clkgate_con[5], BIT(5));
1106                 break;
1107         case SCLK_MAC_RX:
1108                 rk_clrreg(&priv->cru->clkgate_con[5], BIT(8));
1109                 break;
1110         case SCLK_MAC_TX:
1111                 rk_clrreg(&priv->cru->clkgate_con[5], BIT(9));
1112                 break;
1113         case SCLK_MACREF:
1114                 rk_clrreg(&priv->cru->clkgate_con[5], BIT(7));
1115                 break;
1116         case SCLK_MACREF_OUT:
1117                 rk_clrreg(&priv->cru->clkgate_con[5], BIT(6));
1118                 break;
1119         case SCLK_USB2PHY0_REF:
1120                 rk_clrreg(&priv->cru->clkgate_con[6], BIT(5));
1121                 break;
1122         case SCLK_USB2PHY1_REF:
1123                 rk_clrreg(&priv->cru->clkgate_con[6], BIT(6));
1124                 break;
1125         case ACLK_GMAC:
1126                 rk_clrreg(&priv->cru->clkgate_con[32], BIT(0));
1127                 break;
1128         case PCLK_GMAC:
1129                 rk_clrreg(&priv->cru->clkgate_con[32], BIT(2));
1130                 break;
1131         case SCLK_USB3OTG0_REF:
1132                 rk_clrreg(&priv->cru->clkgate_con[12], BIT(1));
1133                 break;
1134         case SCLK_USB3OTG1_REF:
1135                 rk_clrreg(&priv->cru->clkgate_con[12], BIT(2));
1136                 break;
1137         case SCLK_USB3OTG0_SUSPEND:
1138                 rk_clrreg(&priv->cru->clkgate_con[12], BIT(3));
1139                 break;
1140         case SCLK_USB3OTG1_SUSPEND:
1141                 rk_clrreg(&priv->cru->clkgate_con[12], BIT(4));
1142                 break;
1143         case ACLK_USB3OTG0:
1144                 rk_clrreg(&priv->cru->clkgate_con[30], BIT(1));
1145                 break;
1146         case ACLK_USB3OTG1:
1147                 rk_clrreg(&priv->cru->clkgate_con[30], BIT(2));
1148                 break;
1149         case ACLK_USB3_RKSOC_AXI_PERF:
1150                 rk_clrreg(&priv->cru->clkgate_con[30], BIT(3));
1151                 break;
1152         case ACLK_USB3:
1153                 rk_clrreg(&priv->cru->clkgate_con[12], BIT(0));
1154                 break;
1155         case ACLK_USB3_GRF:
1156                 rk_clrreg(&priv->cru->clkgate_con[30], BIT(4));
1157                 break;
1158         case HCLK_HOST0:
1159                 rk_clrreg(&priv->cru->clksel_con[20], BIT(5));
1160                 break;
1161         case HCLK_HOST0_ARB:
1162                 rk_clrreg(&priv->cru->clksel_con[20], BIT(6));
1163                 break;
1164         case HCLK_HOST1:
1165                 rk_clrreg(&priv->cru->clksel_con[20], BIT(7));
1166                 break;
1167         case HCLK_HOST1_ARB:
1168                 rk_clrreg(&priv->cru->clksel_con[20], BIT(8));
1169                 break;
1170         case SCLK_UPHY0_TCPDPHY_REF:
1171                 rk_clrreg(&priv->cru->clkgate_con[13], BIT(4));
1172                 break;
1173         case SCLK_UPHY0_TCPDCORE:
1174                 rk_clrreg(&priv->cru->clkgate_con[13], BIT(5));
1175                 break;
1176         case SCLK_UPHY1_TCPDPHY_REF:
1177                 rk_clrreg(&priv->cru->clkgate_con[13], BIT(6));
1178                 break;
1179         case SCLK_UPHY1_TCPDCORE:
1180                 rk_clrreg(&priv->cru->clkgate_con[13], BIT(7));
1181                 break;
1182         case SCLK_PCIEPHY_REF:
1183                 rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
1184                 break;
1185         default:
1186                 debug("%s: unsupported clk %ld\n", __func__, clk->id);
1187                 return -ENOENT;
1188         }
1189
1190         return 0;
1191 }
1192
1193 static int rk3399_clk_disable(struct clk *clk)
1194 {
1195         struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
1196
1197         switch (clk->id) {
1198         case SCLK_MAC:
1199                 rk_setreg(&priv->cru->clkgate_con[5], BIT(5));
1200                 break;
1201         case SCLK_MAC_RX:
1202                 rk_setreg(&priv->cru->clkgate_con[5], BIT(8));
1203                 break;
1204         case SCLK_MAC_TX:
1205                 rk_setreg(&priv->cru->clkgate_con[5], BIT(9));
1206                 break;
1207         case SCLK_MACREF:
1208                 rk_setreg(&priv->cru->clkgate_con[5], BIT(7));
1209                 break;
1210         case SCLK_MACREF_OUT:
1211                 rk_setreg(&priv->cru->clkgate_con[5], BIT(6));
1212                 break;
1213         case SCLK_USB2PHY0_REF:
1214                 rk_setreg(&priv->cru->clkgate_con[6], BIT(5));
1215                 break;
1216         case SCLK_USB2PHY1_REF:
1217                 rk_setreg(&priv->cru->clkgate_con[6], BIT(6));
1218                 break;
1219         case ACLK_GMAC:
1220                 rk_setreg(&priv->cru->clkgate_con[32], BIT(0));
1221                 break;
1222         case PCLK_GMAC:
1223                 rk_setreg(&priv->cru->clkgate_con[32], BIT(2));
1224                 break;
1225         case SCLK_USB3OTG0_REF:
1226                 rk_setreg(&priv->cru->clkgate_con[12], BIT(1));
1227                 break;
1228         case SCLK_USB3OTG1_REF:
1229                 rk_setreg(&priv->cru->clkgate_con[12], BIT(2));
1230                 break;
1231         case SCLK_USB3OTG0_SUSPEND:
1232                 rk_setreg(&priv->cru->clkgate_con[12], BIT(3));
1233                 break;
1234         case SCLK_USB3OTG1_SUSPEND:
1235                 rk_setreg(&priv->cru->clkgate_con[12], BIT(4));
1236                 break;
1237         case ACLK_USB3OTG0:
1238                 rk_setreg(&priv->cru->clkgate_con[30], BIT(1));
1239                 break;
1240         case ACLK_USB3OTG1:
1241                 rk_setreg(&priv->cru->clkgate_con[30], BIT(2));
1242                 break;
1243         case ACLK_USB3_RKSOC_AXI_PERF:
1244                 rk_setreg(&priv->cru->clkgate_con[30], BIT(3));
1245                 break;
1246         case ACLK_USB3:
1247                 rk_setreg(&priv->cru->clkgate_con[12], BIT(0));
1248                 break;
1249         case ACLK_USB3_GRF:
1250                 rk_setreg(&priv->cru->clkgate_con[30], BIT(4));
1251                 break;
1252         case HCLK_HOST0:
1253                 rk_setreg(&priv->cru->clksel_con[20], BIT(5));
1254                 break;
1255         case HCLK_HOST0_ARB:
1256                 rk_setreg(&priv->cru->clksel_con[20], BIT(6));
1257                 break;
1258         case HCLK_HOST1:
1259                 rk_setreg(&priv->cru->clksel_con[20], BIT(7));
1260                 break;
1261         case HCLK_HOST1_ARB:
1262                 rk_setreg(&priv->cru->clksel_con[20], BIT(8));
1263                 break;
1264         case SCLK_UPHY0_TCPDPHY_REF:
1265                 rk_setreg(&priv->cru->clkgate_con[13], BIT(4));
1266                 break;
1267         case SCLK_UPHY0_TCPDCORE:
1268                 rk_setreg(&priv->cru->clkgate_con[13], BIT(5));
1269                 break;
1270         case SCLK_UPHY1_TCPDPHY_REF:
1271                 rk_setreg(&priv->cru->clkgate_con[13], BIT(6));
1272                 break;
1273         case SCLK_UPHY1_TCPDCORE:
1274                 rk_setreg(&priv->cru->clkgate_con[13], BIT(7));
1275                 break;
1276         case SCLK_PCIEPHY_REF:
1277                 rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
1278                 break;
1279         default:
1280                 debug("%s: unsupported clk %ld\n", __func__, clk->id);
1281                 return -ENOENT;
1282         }
1283
1284         return 0;
1285 }
1286
1287 static struct clk_ops rk3399_clk_ops = {
1288         .get_rate = rk3399_clk_get_rate,
1289         .set_rate = rk3399_clk_set_rate,
1290 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1291         .set_parent = rk3399_clk_set_parent,
1292 #endif
1293         .enable = rk3399_clk_enable,
1294         .disable = rk3399_clk_disable,
1295 };
1296
1297 static void rkclk_init(struct rockchip_cru *cru)
1298 {
1299         u32 aclk_div;
1300         u32 hclk_div;
1301         u32 pclk_div;
1302
1303         rk3399_configure_cpu_l(cru, APLL_L_600_MHZ);
1304         rk3399_configure_cpu_b(cru, APLL_B_600_MHZ);
1305         /*
1306          * some cru registers changed by bootrom, we'd better reset them to
1307          * reset/default values described in TRM to avoid confusion in kernel.
1308          * Please consider these three lines as a fix of bootrom bug.
1309          */
1310         rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101);
1311         rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f);
1312         rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003);
1313
1314         /* configure gpll cpll */
1315         rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg);
1316         rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg);
1317
1318         /* configure perihp aclk, hclk, pclk */
1319         aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
1320         assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
1321
1322         hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
1323         assert((hclk_div + 1) * PERIHP_HCLK_HZ ==
1324                PERIHP_ACLK_HZ && (hclk_div < 0x4));
1325
1326         pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
1327         assert((pclk_div + 1) * PERIHP_PCLK_HZ ==
1328                PERIHP_ACLK_HZ && (pclk_div < 0x7));
1329
1330         rk_clrsetreg(&cru->clksel_con[14],
1331                      PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK |
1332                      ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK,
1333                      pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
1334                      hclk_div << HCLK_PERIHP_DIV_CON_SHIFT |
1335                      ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT |
1336                      aclk_div << ACLK_PERIHP_DIV_CON_SHIFT);
1337
1338         /* configure perilp0 aclk, hclk, pclk */
1339         aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1;
1340         assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
1341
1342         hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1;
1343         assert((hclk_div + 1) * PERILP0_HCLK_HZ ==
1344                PERILP0_ACLK_HZ && (hclk_div < 0x4));
1345
1346         pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1;
1347         assert((pclk_div + 1) * PERILP0_PCLK_HZ ==
1348                PERILP0_ACLK_HZ && (pclk_div < 0x7));
1349
1350         rk_clrsetreg(&cru->clksel_con[23],
1351                      PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK |
1352                      ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK,
1353                      pclk_div << PCLK_PERILP0_DIV_CON_SHIFT |
1354                      hclk_div << HCLK_PERILP0_DIV_CON_SHIFT |
1355                      ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT |
1356                      aclk_div << ACLK_PERILP0_DIV_CON_SHIFT);
1357
1358         /* perilp1 hclk select gpll as source */
1359         hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1;
1360         assert((hclk_div + 1) * PERILP1_HCLK_HZ ==
1361                GPLL_HZ && (hclk_div < 0x1f));
1362
1363         pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1;
1364         assert((pclk_div + 1) * PERILP1_HCLK_HZ ==
1365                PERILP1_HCLK_HZ && (hclk_div < 0x7));
1366
1367         rk_clrsetreg(&cru->clksel_con[25],
1368                      PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK |
1369                      HCLK_PERILP1_PLL_SEL_MASK,
1370                      pclk_div << PCLK_PERILP1_DIV_CON_SHIFT |
1371                      hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
1372                      HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
1373 }
1374
1375 static int rk3399_clk_probe(struct udevice *dev)
1376 {
1377         struct rk3399_clk_priv *priv = dev_get_priv(dev);
1378         bool init_clocks = false;
1379
1380 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1381         struct rk3399_clk_plat *plat = dev_get_platdata(dev);
1382
1383         priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
1384 #endif
1385
1386 #if defined(CONFIG_SPL_BUILD)
1387         init_clocks = true;
1388 #elif CONFIG_IS_ENABLED(HANDOFF)
1389         if (!(gd->flags & GD_FLG_RELOC)) {
1390                 if (!(gd->spl_handoff))
1391                         init_clocks = true;
1392         }
1393 #endif
1394
1395         if (init_clocks)
1396                 rkclk_init(priv->cru);
1397
1398         return 0;
1399 }
1400
1401 static int rk3399_clk_ofdata_to_platdata(struct udevice *dev)
1402 {
1403 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1404         struct rk3399_clk_priv *priv = dev_get_priv(dev);
1405
1406         priv->cru = dev_read_addr_ptr(dev);
1407 #endif
1408         return 0;
1409 }
1410
1411 static int rk3399_clk_bind(struct udevice *dev)
1412 {
1413         int ret;
1414         struct udevice *sys_child;
1415         struct sysreset_reg *priv;
1416
1417         /* The reset driver does not have a device node, so bind it here */
1418         ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
1419                                  &sys_child);
1420         if (ret) {
1421                 debug("Warning: No sysreset driver: ret=%d\n", ret);
1422         } else {
1423                 priv = malloc(sizeof(struct sysreset_reg));
1424                 priv->glb_srst_fst_value = offsetof(struct rockchip_cru,
1425                                                     glb_srst_fst_value);
1426                 priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
1427                                                     glb_srst_snd_value);
1428                 sys_child->priv = priv;
1429         }
1430
1431 #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
1432         ret = offsetof(struct rockchip_cru, softrst_con[0]);
1433         ret = rockchip_reset_bind(dev, ret, 21);
1434         if (ret)
1435                 debug("Warning: software reset driver bind faile\n");
1436 #endif
1437
1438         return 0;
1439 }
1440
1441 static const struct udevice_id rk3399_clk_ids[] = {
1442         { .compatible = "rockchip,rk3399-cru" },
1443         { }
1444 };
1445
1446 U_BOOT_DRIVER(clk_rk3399) = {
1447         .name           = "rockchip_rk3399_cru",
1448         .id             = UCLASS_CLK,
1449         .of_match       = rk3399_clk_ids,
1450         .priv_auto_alloc_size = sizeof(struct rk3399_clk_priv),
1451         .ofdata_to_platdata = rk3399_clk_ofdata_to_platdata,
1452         .ops            = &rk3399_clk_ops,
1453         .bind           = rk3399_clk_bind,
1454         .probe          = rk3399_clk_probe,
1455 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1456         .platdata_auto_alloc_size = sizeof(struct rk3399_clk_plat),
1457 #endif
1458 };
1459
1460 static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id)
1461 {
1462         u32 div, con;
1463
1464         switch (clk_id) {
1465         case SCLK_I2C0_PMU:
1466                 con = readl(&pmucru->pmucru_clksel[2]);
1467                 div = I2C_CLK_DIV_VALUE(con, 0);
1468                 break;
1469         case SCLK_I2C4_PMU:
1470                 con = readl(&pmucru->pmucru_clksel[3]);
1471                 div = I2C_CLK_DIV_VALUE(con, 4);
1472                 break;
1473         case SCLK_I2C8_PMU:
1474                 con = readl(&pmucru->pmucru_clksel[2]);
1475                 div = I2C_CLK_DIV_VALUE(con, 8);
1476                 break;
1477         default:
1478                 printf("do not support this i2c bus\n");
1479                 return -EINVAL;
1480         }
1481
1482         return DIV_TO_RATE(PPLL_HZ, div);
1483 }
1484
1485 static ulong rk3399_i2c_set_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id,
1486                                    uint hz)
1487 {
1488         int src_clk_div;
1489
1490         src_clk_div = PPLL_HZ / hz;
1491         assert(src_clk_div - 1 < 127);
1492
1493         switch (clk_id) {
1494         case SCLK_I2C0_PMU:
1495                 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(0),
1496                              I2C_PMUCLK_REG_VALUE(0, src_clk_div));
1497                 break;
1498         case SCLK_I2C4_PMU:
1499                 rk_clrsetreg(&pmucru->pmucru_clksel[3], I2C_PMUCLK_REG_MASK(4),
1500                              I2C_PMUCLK_REG_VALUE(4, src_clk_div));
1501                 break;
1502         case SCLK_I2C8_PMU:
1503                 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(8),
1504                              I2C_PMUCLK_REG_VALUE(8, src_clk_div));
1505                 break;
1506         default:
1507                 printf("do not support this i2c bus\n");
1508                 return -EINVAL;
1509         }
1510
1511         return DIV_TO_RATE(PPLL_HZ, src_clk_div);
1512 }
1513
1514 static ulong rk3399_pwm_get_clk(struct rk3399_pmucru *pmucru)
1515 {
1516         u32 div, con;
1517
1518         /* PWM closk rate is same as pclk_pmu */
1519         con = readl(&pmucru->pmucru_clksel[0]);
1520         div = con & PMU_PCLK_DIV_CON_MASK;
1521
1522         return DIV_TO_RATE(PPLL_HZ, div);
1523 }
1524
1525 static ulong rk3399_pmuclk_get_rate(struct clk *clk)
1526 {
1527         struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
1528         ulong rate = 0;
1529
1530         switch (clk->id) {
1531         case PLL_PPLL:
1532                 return PPLL_HZ;
1533         case PCLK_RKPWM_PMU:
1534         case PCLK_WDT_M0_PMU:
1535                 rate = rk3399_pwm_get_clk(priv->pmucru);
1536                 break;
1537         case SCLK_I2C0_PMU:
1538         case SCLK_I2C4_PMU:
1539         case SCLK_I2C8_PMU:
1540                 rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id);
1541                 break;
1542         default:
1543                 return -ENOENT;
1544         }
1545
1546         return rate;
1547 }
1548
1549 static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate)
1550 {
1551         struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
1552         ulong ret = 0;
1553
1554         switch (clk->id) {
1555         case PLL_PPLL:
1556                 /*
1557                  * This has already been set up and we don't want/need
1558                  * to change it here.  Accept the request though, as the
1559                  * device-tree has this in an 'assigned-clocks' list.
1560                  */
1561                 return PPLL_HZ;
1562         case SCLK_I2C0_PMU:
1563         case SCLK_I2C4_PMU:
1564         case SCLK_I2C8_PMU:
1565                 ret = rk3399_i2c_set_pmuclk(priv->pmucru, clk->id, rate);
1566                 break;
1567         default:
1568                 return -ENOENT;
1569         }
1570
1571         return ret;
1572 }
1573
1574 static struct clk_ops rk3399_pmuclk_ops = {
1575         .get_rate = rk3399_pmuclk_get_rate,
1576         .set_rate = rk3399_pmuclk_set_rate,
1577 };
1578
1579 #ifndef CONFIG_SPL_BUILD
1580 static void pmuclk_init(struct rk3399_pmucru *pmucru)
1581 {
1582         u32 pclk_div;
1583
1584         /*  configure pmu pll(ppll) */
1585         rkclk_set_pll(&pmucru->ppll_con[0], &ppll_init_cfg);
1586
1587         /*  configure pmu pclk */
1588         pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1;
1589         rk_clrsetreg(&pmucru->pmucru_clksel[0],
1590                      PMU_PCLK_DIV_CON_MASK,
1591                      pclk_div << PMU_PCLK_DIV_CON_SHIFT);
1592 }
1593 #endif
1594
1595 static int rk3399_pmuclk_probe(struct udevice *dev)
1596 {
1597 #if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD)
1598         struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
1599 #endif
1600
1601 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1602         struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev);
1603
1604         priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
1605 #endif
1606
1607 #ifndef CONFIG_SPL_BUILD
1608         pmuclk_init(priv->pmucru);
1609 #endif
1610         return 0;
1611 }
1612
1613 static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev)
1614 {
1615 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1616         struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
1617
1618         priv->pmucru = dev_read_addr_ptr(dev);
1619 #endif
1620         return 0;
1621 }
1622
1623 static int rk3399_pmuclk_bind(struct udevice *dev)
1624 {
1625 #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
1626         int ret;
1627
1628         ret = offsetof(struct rk3399_pmucru, pmucru_softrst_con[0]);
1629         ret = rockchip_reset_bind(dev, ret, 2);
1630         if (ret)
1631                 debug("Warning: software reset driver bind faile\n");
1632 #endif
1633         return 0;
1634 }
1635
1636 static const struct udevice_id rk3399_pmuclk_ids[] = {
1637         { .compatible = "rockchip,rk3399-pmucru" },
1638         { }
1639 };
1640
1641 U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = {
1642         .name           = "rockchip_rk3399_pmucru",
1643         .id             = UCLASS_CLK,
1644         .of_match       = rk3399_pmuclk_ids,
1645         .priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv),
1646         .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata,
1647         .ops            = &rk3399_pmuclk_ops,
1648         .probe          = rk3399_pmuclk_probe,
1649         .bind           = rk3399_pmuclk_bind,
1650 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1651         .platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat),
1652 #endif
1653 };