1 // SPDX-License-Identifier: GPL-2.0
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4 * Author: Andy Yan <andy.yan@rock-chips.com>
5 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
9 #include <clk-uclass.h>
11 #include <dt-structs.h>
18 #include <asm/arch-rockchip/clock.h>
19 #include <asm/arch-rockchip/cru_rk3368.h>
20 #include <asm/arch-rockchip/hardware.h>
23 #include <dt-bindings/clock/rk3368-cru.h>
24 #include <linux/delay.h>
25 #include <linux/stringify.h>
27 #if CONFIG_IS_ENABLED(OF_PLATDATA)
28 struct rk3368_clk_plat {
29 struct dtd_rockchip_rk3368_cru dtd;
39 #define OSC_HZ (24 * 1000 * 1000)
40 #define APLL_L_HZ (800 * 1000 * 1000)
41 #define APLL_B_HZ (816 * 1000 * 1000)
42 #define GPLL_HZ (576 * 1000 * 1000)
43 #define CPLL_HZ (400 * 1000 * 1000)
45 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
47 #define PLL_DIVISORS(hz, _nr, _no) { \
48 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no}; \
49 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
50 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \
51 "divisors on line " __stringify(__LINE__));
53 #if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
54 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2);
55 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2);
56 #if !defined(CONFIG_TPL_BUILD)
57 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2);
58 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);
62 static ulong rk3368_clk_get_rate(struct clk *clk);
64 /* Get pll rate by id */
65 static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru,
66 enum rk3368_pll_id pll_id)
70 struct rk3368_pll *pll = &cru->pll[pll_id];
72 con = readl(&pll->con3);
74 switch ((con & PLL_MODE_MASK) >> PLL_MODE_SHIFT) {
78 con = readl(&pll->con0);
79 no = ((con & PLL_OD_MASK) >> PLL_OD_SHIFT) + 1;
80 nr = ((con & PLL_NR_MASK) >> PLL_NR_SHIFT) + 1;
81 con = readl(&pll->con1);
82 nf = ((con & PLL_NF_MASK) >> PLL_NF_SHIFT) + 1;
84 return (24 * nf / (nr * no)) * 1000000;
85 case PLL_MODE_DEEP_SLOW:
91 #if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
92 static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,
93 const struct pll_div *div)
95 struct rk3368_pll *pll = &cru->pll[pll_id];
96 /* All PLLs have same VCO and output frequency range restrictions*/
97 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
98 uint output_hz = vco_hz / div->no;
100 debug("PLL at %p: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
101 pll, div->nf, div->nr, div->no, vco_hz, output_hz);
103 /* enter slow mode and reset pll */
104 rk_clrsetreg(&pll->con3, PLL_MODE_MASK | PLL_RESET_MASK,
105 PLL_RESET << PLL_RESET_SHIFT);
107 rk_clrsetreg(&pll->con0, PLL_NR_MASK | PLL_OD_MASK,
108 ((div->nr - 1) << PLL_NR_SHIFT) |
109 ((div->no - 1) << PLL_OD_SHIFT));
110 writel((div->nf - 1) << PLL_NF_SHIFT, &pll->con1);
112 * BWADJ should be set to NF / 2 to ensure the nominal bandwidth.
113 * Compare the RK3368 TRM, section "3.6.4 PLL Bandwidth Adjustment".
115 clrsetbits_le32(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
119 /* return from reset */
120 rk_clrreg(&pll->con3, PLL_RESET_MASK);
122 /* waiting for pll lock */
123 while (!(readl(&pll->con1) & PLL_LOCK_STA))
126 rk_clrsetreg(&pll->con3, PLL_MODE_MASK,
127 PLL_MODE_NORMAL << PLL_MODE_SHIFT);
133 #if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
134 static void rkclk_init(struct rk3368_cru *cru)
136 u32 apllb, aplll, dpll, cpll, gpll;
138 rkclk_set_pll(cru, APLLB, &apll_b_init_cfg);
139 rkclk_set_pll(cru, APLLL, &apll_l_init_cfg);
140 #if !defined(CONFIG_TPL_BUILD)
142 * If we plan to return to the boot ROM, we can't increase the
143 * GPLL rate from the SPL stage.
145 rkclk_set_pll(cru, GPLL, &gpll_init_cfg);
146 rkclk_set_pll(cru, CPLL, &cpll_init_cfg);
149 apllb = rkclk_pll_get_rate(cru, APLLB);
150 aplll = rkclk_pll_get_rate(cru, APLLL);
151 dpll = rkclk_pll_get_rate(cru, DPLL);
152 cpll = rkclk_pll_get_rate(cru, CPLL);
153 gpll = rkclk_pll_get_rate(cru, GPLL);
155 debug("%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\n",
156 __func__, apllb, aplll, dpll, cpll, gpll);
160 #if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
161 static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
163 u32 div, con, con_id, rate;
180 con = readl(&cru->clksel_con[con_id]);
181 switch (con & MMC_PLL_SEL_MASK) {
182 case MMC_PLL_SEL_GPLL:
183 pll_rate = rkclk_pll_get_rate(cru, GPLL);
185 case MMC_PLL_SEL_24M:
188 case MMC_PLL_SEL_CPLL:
189 pll_rate = rkclk_pll_get_rate(cru, CPLL);
191 case MMC_PLL_SEL_USBPHY_480M:
195 div = (con & MMC_CLK_DIV_MASK) >> MMC_CLK_DIV_SHIFT;
196 rate = DIV_TO_RATE(pll_rate, div);
198 debug("%s: raw rate %d (post-divide by 2)\n", __func__, rate);
202 static ulong rk3368_mmc_find_best_rate_and_parent(struct clk *clk,
209 const ulong MHz = 1000000;
214 { .mux = MMC_PLL_SEL_CPLL, .rate = CPLL_HZ },
215 { .mux = MMC_PLL_SEL_GPLL, .rate = GPLL_HZ },
216 { .mux = MMC_PLL_SEL_24M, .rate = 24 * MHz }
219 debug("%s: target rate %ld\n", __func__, rate);
220 for (i = 0; i < ARRAY_SIZE(parents); ++i) {
222 * Find the largest rate no larger than the target-rate for
223 * the current parent.
225 ulong parent_rate = parents[i].rate;
226 u32 div = DIV_ROUND_UP(parent_rate, rate);
228 ulong new_rate = parent_rate / adj_div;
230 debug("%s: rate %ld, parent-mux %d, parent-rate %ld, div %d\n",
231 __func__, rate, parents[i].mux, parents[i].rate, div);
233 /* Skip, if not representable */
234 if ((div - 1) > MMC_CLK_DIV_MASK)
237 /* Skip, if we already have a better (or equal) solution */
238 if (new_rate <= best_rate)
241 /* This is our new best rate. */
242 best_rate = new_rate;
243 *best_mux = parents[i].mux;
247 debug("%s: best_mux = %x, best_div = %d, best_rate = %ld\n",
248 __func__, *best_mux, *best_div, best_rate);
253 static ulong rk3368_mmc_set_clk(struct clk *clk, ulong rate)
255 struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
256 struct rk3368_cru *cru = priv->cru;
257 ulong clk_id = clk->id;
258 u32 con_id, mux = 0, div = 0;
260 /* Find the best parent and rate */
261 rk3368_mmc_find_best_rate_and_parent(clk, rate << 1, &mux, &div);
277 rk_clrsetreg(&cru->clksel_con[con_id],
278 MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK,
281 return rk3368_mmc_get_clk(cru, clk_id);
285 #if IS_ENABLED(CONFIG_TPL_BUILD)
286 static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru, ulong set_rate)
288 const struct pll_div *dpll_cfg = NULL;
289 const ulong MHz = 1000000;
291 /* Fout = ((Fin /NR) * NF )/ NO */
292 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1);
293 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1);
294 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2);
298 dpll_cfg = &dpll_1200;
301 dpll_cfg = &dpll_1332;
304 dpll_cfg = &dpll_1600;
307 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate);
309 rkclk_set_pll(cru, DPLL, dpll_cfg);
315 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
316 static ulong rk3368_gmac_set_clk(struct rk3368_cru *cru, ulong set_rate)
321 * The gmac clock can be derived either from an external clock
322 * or can be generated from internally by a divider from SCLK_MAC.
324 if (readl(&cru->clksel_con[43]) & GMAC_MUX_SEL_EXTCLK) {
325 /* An external clock will always generate the right rate... */
328 u32 con = readl(&cru->clksel_con[43]);
332 if (((con >> GMAC_PLL_SHIFT) & GMAC_PLL_MASK) ==
333 GMAC_PLL_SELECT_GENERAL)
335 else if (((con >> GMAC_PLL_SHIFT) & GMAC_PLL_MASK) ==
336 GMAC_PLL_SELECT_CODEC)
339 /* CPLL is not set */
342 div = DIV_ROUND_UP(pll_rate, set_rate) - 1;
344 rk_clrsetreg(&cru->clksel_con[43], GMAC_DIV_CON_MASK,
345 div << GMAC_DIV_CON_SHIFT);
347 debug("Unsupported div for gmac:%d\n", div);
349 return DIV_TO_RATE(pll_rate, div);
357 * RK3368 SPI clocks have a common divider-width (7 bits) and a single bit
358 * to select either CPLL or GPLL as the clock-parent. The location within
359 * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable.
363 uint8_t reg; /* CLKSEL_CON[reg] register in CRU */
369 * The entries are numbered relative to their offset from SCLK_SPI0.
371 static const struct spi_clkreg spi_clkregs[] = {
372 [0] = { .reg = 45, .div_shift = 0, .sel_shift = 7, },
373 [1] = { .reg = 45, .div_shift = 8, .sel_shift = 15, },
374 [2] = { .reg = 46, .div_shift = 8, .sel_shift = 15, },
377 static inline u32 extract_bits(u32 val, unsigned width, unsigned shift)
379 return (val >> shift) & ((1 << width) - 1);
382 static ulong rk3368_spi_get_clk(struct rk3368_cru *cru, ulong clk_id)
384 const struct spi_clkreg *spiclk = NULL;
388 case SCLK_SPI0 ... SCLK_SPI2:
389 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
393 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
397 val = readl(&cru->clksel_con[spiclk->reg]);
398 div = extract_bits(val, 7, spiclk->div_shift);
400 debug("%s: div 0x%x\n", __func__, div);
401 return DIV_TO_RATE(GPLL_HZ, div);
404 static ulong rk3368_spi_set_clk(struct rk3368_cru *cru, ulong clk_id, uint hz)
406 const struct spi_clkreg *spiclk = NULL;
409 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz);
410 assert(src_clk_div < 127);
413 case SCLK_SPI0 ... SCLK_SPI2:
414 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
418 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
422 rk_clrsetreg(&cru->clksel_con[spiclk->reg],
423 ((0x7f << spiclk->div_shift) |
424 (0x1 << spiclk->sel_shift)),
425 ((src_clk_div << spiclk->div_shift) |
426 (1 << spiclk->sel_shift)));
428 return rk3368_spi_get_clk(cru, clk_id);
431 static ulong rk3368_saradc_get_clk(struct rk3368_cru *cru)
435 val = readl(&cru->clksel_con[25]);
436 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
437 CLK_SARADC_DIV_CON_WIDTH);
439 return DIV_TO_RATE(OSC_HZ, div);
442 static ulong rk3368_saradc_set_clk(struct rk3368_cru *cru, uint hz)
446 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
447 assert(src_clk_div < 128);
449 rk_clrsetreg(&cru->clksel_con[25],
450 CLK_SARADC_DIV_CON_MASK,
451 src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
453 return rk3368_saradc_get_clk(cru);
456 static ulong rk3368_clk_get_rate(struct clk *clk)
458 struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
461 debug("%s: id %ld\n", __func__, clk->id);
464 rate = rkclk_pll_get_rate(priv->cru, CPLL);
467 rate = rkclk_pll_get_rate(priv->cru, GPLL);
469 case SCLK_SPI0 ... SCLK_SPI2:
470 rate = rk3368_spi_get_clk(priv->cru, clk->id);
472 #if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
475 rate = rk3368_mmc_get_clk(priv->cru, clk->id);
479 rate = rk3368_saradc_get_clk(priv->cru);
488 static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
490 __maybe_unused struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
493 debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate);
495 case SCLK_SPI0 ... SCLK_SPI2:
496 ret = rk3368_spi_set_clk(priv->cru, clk->id, rate);
498 #if IS_ENABLED(CONFIG_TPL_BUILD)
500 ret = rk3368_ddr_set_clk(priv->cru, rate);
503 #if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
506 ret = rk3368_mmc_set_clk(clk, rate);
509 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
511 /* select the external clock */
512 ret = rk3368_gmac_set_clk(priv->cru, rate);
516 ret = rk3368_saradc_set_clk(priv->cru, rate);
525 static int __maybe_unused rk3368_gmac_set_parent(struct clk *clk, struct clk *parent)
527 struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
528 struct rk3368_cru *cru = priv->cru;
529 const char *clock_output_name;
533 * If the requested parent is in the same clock-controller and
534 * the id is SCLK_MAC ("sclk_mac"), switch to the internal
537 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC)) {
538 debug("%s: switching GAMC to SCLK_MAC\n", __func__);
539 rk_clrreg(&cru->clksel_con[43], GMAC_MUX_SEL_EXTCLK);
544 * Otherwise, we need to check the clock-output-names of the
545 * requested parent to see if the requested id is "ext_gmac".
547 ret = dev_read_string_index(parent->dev, "clock-output-names",
548 parent->id, &clock_output_name);
552 /* If this is "ext_gmac", switch to the external clock input */
553 if (!strcmp(clock_output_name, "ext_gmac")) {
554 debug("%s: switching GMAC to external clock\n", __func__);
555 rk_setreg(&cru->clksel_con[43], GMAC_MUX_SEL_EXTCLK);
562 static int __maybe_unused rk3368_clk_set_parent(struct clk *clk, struct clk *parent)
566 return rk3368_gmac_set_parent(clk, parent);
569 debug("%s: unsupported clk %ld\n", __func__, clk->id);
573 static struct clk_ops rk3368_clk_ops = {
574 .get_rate = rk3368_clk_get_rate,
575 .set_rate = rk3368_clk_set_rate,
576 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
577 .set_parent = rk3368_clk_set_parent,
581 static int rk3368_clk_probe(struct udevice *dev)
583 struct rk3368_clk_priv __maybe_unused *priv = dev_get_priv(dev);
584 #if CONFIG_IS_ENABLED(OF_PLATDATA)
585 struct rk3368_clk_plat *plat = dev_get_plat(dev);
587 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
589 #if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
590 rkclk_init(priv->cru);
596 static int rk3368_clk_ofdata_to_platdata(struct udevice *dev)
598 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
599 struct rk3368_clk_priv *priv = dev_get_priv(dev);
601 priv->cru = dev_read_addr_ptr(dev);
607 static int rk3368_clk_bind(struct udevice *dev)
610 struct udevice *sys_child;
611 struct sysreset_reg *priv;
613 /* The reset driver does not have a device node, so bind it here */
614 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
617 debug("Warning: No sysreset driver: ret=%d\n", ret);
619 priv = malloc(sizeof(struct sysreset_reg));
620 priv->glb_srst_fst_value = offsetof(struct rk3368_cru,
622 priv->glb_srst_snd_value = offsetof(struct rk3368_cru,
624 sys_child->priv = priv;
627 #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
628 ret = offsetof(struct rk3368_cru, softrst_con[0]);
629 ret = rockchip_reset_bind(dev, ret, 15);
631 debug("Warning: software reset driver bind faile\n");
637 static const struct udevice_id rk3368_clk_ids[] = {
638 { .compatible = "rockchip,rk3368-cru" },
642 U_BOOT_DRIVER(rockchip_rk3368_cru) = {
643 .name = "rockchip_rk3368_cru",
645 .of_match = rk3368_clk_ids,
646 .priv_auto = sizeof(struct rk3368_clk_priv),
647 #if CONFIG_IS_ENABLED(OF_PLATDATA)
648 .plat_auto = sizeof(struct rk3368_clk_plat),
650 .ofdata_to_platdata = rk3368_clk_ofdata_to_platdata,
651 .ops = &rk3368_clk_ops,
652 .bind = rk3368_clk_bind,
653 .probe = rk3368_clk_probe,