1 // SPDX-License-Identifier: GPL-2.0
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
8 #include <clk-uclass.h>
12 #include <asm/arch-rockchip/clock.h>
13 #include <asm/arch-rockchip/cru_rk3328.h>
14 #include <asm/arch-rockchip/hardware.h>
15 #include <asm/arch-rockchip/grf_rk3328.h>
18 #include <dt-bindings/clock/rk3328-cru.h>
28 #define RATE_TO_DIV(input_rate, output_rate) \
29 ((input_rate) / (output_rate) - 1);
30 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
32 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
34 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
35 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
37 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 4, 1);
38 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 2, 1);
40 static const struct pll_div apll_816_cfg = PLL_DIVISORS(816 * MHz, 1, 2, 1);
41 static const struct pll_div apll_600_cfg = PLL_DIVISORS(600 * MHz, 1, 3, 1);
43 static const struct pll_div *apll_cfgs[] = {
44 [APLL_816_MHZ] = &apll_816_cfg,
45 [APLL_600_MHZ] = &apll_600_cfg,
50 PLL_POSTDIV1_SHIFT = 12,
51 PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT,
53 PLL_FBDIV_MASK = 0xfff,
57 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
59 PLL_LOCK_STATUS_SHIFT = 10,
60 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
61 PLL_POSTDIV2_SHIFT = 6,
62 PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT,
64 PLL_REFDIV_MASK = 0x3f,
67 PLL_FRACDIV_SHIFT = 0,
68 PLL_FRACDIV_MASK = 0xffffff,
80 CLK_CORE_PLL_SEL_APLL = 0,
81 CLK_CORE_PLL_SEL_GPLL,
82 CLK_CORE_PLL_SEL_DPLL,
83 CLK_CORE_PLL_SEL_NPLL,
84 CLK_CORE_PLL_SEL_SHIFT = 6,
85 CLK_CORE_PLL_SEL_MASK = 3 << CLK_CORE_PLL_SEL_SHIFT,
86 CLK_CORE_DIV_SHIFT = 0,
87 CLK_CORE_DIV_MASK = 0x1f,
90 ACLKM_CORE_DIV_SHIFT = 4,
91 ACLKM_CORE_DIV_MASK = 0x7 << ACLKM_CORE_DIV_SHIFT,
92 PCLK_DBG_DIV_SHIFT = 0,
93 PCLK_DBG_DIV_MASK = 0xF << PCLK_DBG_DIV_SHIFT,
96 GMAC2IO_PLL_SEL_SHIFT = 7,
97 GMAC2IO_PLL_SEL_MASK = 1 << GMAC2IO_PLL_SEL_SHIFT,
98 GMAC2IO_PLL_SEL_CPLL = 0,
99 GMAC2IO_PLL_SEL_GPLL = 1,
100 GMAC2IO_CLK_DIV_MASK = 0x1f,
101 GMAC2IO_CLK_DIV_SHIFT = 0,
104 ACLK_PERIHP_PLL_SEL_CPLL = 0,
105 ACLK_PERIHP_PLL_SEL_GPLL,
106 ACLK_PERIHP_PLL_SEL_HDMIPHY,
107 ACLK_PERIHP_PLL_SEL_SHIFT = 6,
108 ACLK_PERIHP_PLL_SEL_MASK = 3 << ACLK_PERIHP_PLL_SEL_SHIFT,
109 ACLK_PERIHP_DIV_CON_SHIFT = 0,
110 ACLK_PERIHP_DIV_CON_MASK = 0x1f,
113 PCLK_PERIHP_DIV_CON_SHIFT = 4,
114 PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT,
115 HCLK_PERIHP_DIV_CON_SHIFT = 0,
116 HCLK_PERIHP_DIV_CON_MASK = 3 << HCLK_PERIHP_DIV_CON_SHIFT,
119 CLK_TSADC_DIV_CON_SHIFT = 0,
120 CLK_TSADC_DIV_CON_MASK = 0x3ff,
123 CLK_SARADC_DIV_CON_SHIFT = 0,
124 CLK_SARADC_DIV_CON_MASK = GENMASK(9, 0),
125 CLK_SARADC_DIV_CON_WIDTH = 10,
128 CLK_PWM_PLL_SEL_CPLL = 0,
129 CLK_PWM_PLL_SEL_GPLL,
130 CLK_PWM_PLL_SEL_SHIFT = 15,
131 CLK_PWM_PLL_SEL_MASK = 1 << CLK_PWM_PLL_SEL_SHIFT,
132 CLK_PWM_DIV_CON_SHIFT = 8,
133 CLK_PWM_DIV_CON_MASK = 0x7f << CLK_PWM_DIV_CON_SHIFT,
135 CLK_SPI_PLL_SEL_CPLL = 0,
136 CLK_SPI_PLL_SEL_GPLL,
137 CLK_SPI_PLL_SEL_SHIFT = 7,
138 CLK_SPI_PLL_SEL_MASK = 1 << CLK_SPI_PLL_SEL_SHIFT,
139 CLK_SPI_DIV_CON_SHIFT = 0,
140 CLK_SPI_DIV_CON_MASK = 0x7f << CLK_SPI_DIV_CON_SHIFT,
143 CLK_SDMMC_PLL_SEL_CPLL = 0,
144 CLK_SDMMC_PLL_SEL_GPLL,
145 CLK_SDMMC_PLL_SEL_24M,
146 CLK_SDMMC_PLL_SEL_USBPHY,
147 CLK_SDMMC_PLL_SHIFT = 8,
148 CLK_SDMMC_PLL_MASK = 0x3 << CLK_SDMMC_PLL_SHIFT,
149 CLK_SDMMC_DIV_CON_SHIFT = 0,
150 CLK_SDMMC_DIV_CON_MASK = 0xff << CLK_SDMMC_DIV_CON_SHIFT,
153 CLK_EMMC_PLL_SEL_CPLL = 0,
154 CLK_EMMC_PLL_SEL_GPLL,
155 CLK_EMMC_PLL_SEL_24M,
156 CLK_EMMC_PLL_SEL_USBPHY,
157 CLK_EMMC_PLL_SHIFT = 8,
158 CLK_EMMC_PLL_MASK = 0x3 << CLK_EMMC_PLL_SHIFT,
159 CLK_EMMC_DIV_CON_SHIFT = 0,
160 CLK_EMMC_DIV_CON_MASK = 0xff << CLK_EMMC_DIV_CON_SHIFT,
163 CLK_I2C_PLL_SEL_CPLL = 0,
164 CLK_I2C_PLL_SEL_GPLL,
165 CLK_I2C_DIV_CON_MASK = 0x7f,
166 CLK_I2C_PLL_SEL_MASK = 1,
167 CLK_I2C1_PLL_SEL_SHIFT = 15,
168 CLK_I2C1_DIV_CON_SHIFT = 8,
169 CLK_I2C0_PLL_SEL_SHIFT = 7,
170 CLK_I2C0_DIV_CON_SHIFT = 0,
173 CLK_I2C3_PLL_SEL_SHIFT = 15,
174 CLK_I2C3_DIV_CON_SHIFT = 8,
175 CLK_I2C2_PLL_SEL_SHIFT = 7,
176 CLK_I2C2_DIV_CON_SHIFT = 0,
179 #define VCO_MAX_KHZ (3200 * (MHz / KHz))
180 #define VCO_MIN_KHZ (800 * (MHz / KHz))
181 #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz))
182 #define OUTPUT_MIN_KHZ (16 * (MHz / KHz))
185 * the div restructions of pll in integer mode, these are defined in
186 * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0
188 #define PLL_DIV_MIN 16
189 #define PLL_DIV_MAX 3200
192 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
193 * Formulas also embedded within the Fractional PLL Verilog model:
194 * If DSMPD = 1 (DSM is disabled, "integer mode")
195 * FOUTVCO = FREF / REFDIV * FBDIV
196 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
198 * FOUTVCO = Fractional PLL non-divided output frequency
199 * FOUTPOSTDIV = Fractional PLL divided output frequency
200 * (output of second post divider)
201 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
202 * REFDIV = Fractional PLL input reference clock divider
203 * FBDIV = Integer value programmed into feedback divide
206 static void rkclk_set_pll(struct rk3328_cru *cru, enum rk_clk_id clk_id,
207 const struct pll_div *div)
210 u32 mode_shift, mode_mask;
216 pll_con = cru->apll_con;
217 mode_shift = APLL_MODE_SHIFT;
220 pll_con = cru->dpll_con;
221 mode_shift = DPLL_MODE_SHIFT;
224 pll_con = cru->cpll_con;
225 mode_shift = CPLL_MODE_SHIFT;
228 pll_con = cru->gpll_con;
229 mode_shift = GPLL_MODE_SHIFT;
232 pll_con = cru->npll_con;
233 mode_shift = NPLL_MODE_SHIFT;
238 mode_mask = 1 << mode_shift;
240 /* All 8 PLLs have same VCO and output frequency range restrictions. */
241 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv;
242 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
244 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, \
245 postdiv2=%d, vco=%u khz, output=%u khz\n",
246 pll_con, div->fbdiv, div->refdiv, div->postdiv1,
247 div->postdiv2, vco_khz, output_khz);
248 assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
249 output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ &&
250 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX);
253 * When power on or changing PLL setting,
254 * we must force PLL into slow mode to ensure output stable clock.
256 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_SLOW << mode_shift);
258 /* use integer mode */
259 rk_clrsetreg(&pll_con[1], PLL_DSMPD_MASK,
260 PLL_INTEGER_MODE << PLL_DSMPD_SHIFT);
262 rk_clrsetreg(&pll_con[0],
263 PLL_FBDIV_MASK | PLL_POSTDIV1_MASK,
264 (div->fbdiv << PLL_FBDIV_SHIFT) |
265 (div->postdiv1 << PLL_POSTDIV1_SHIFT));
266 rk_clrsetreg(&pll_con[1],
267 PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
268 (div->postdiv2 << PLL_POSTDIV2_SHIFT) |
269 (div->refdiv << PLL_REFDIV_SHIFT));
271 /* waiting for pll lock */
272 while (!(readl(&pll_con[1]) & (1 << PLL_LOCK_STATUS_SHIFT)))
275 /* pll enter normal mode */
276 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift);
279 static void rkclk_init(struct rk3328_cru *cru)
285 rk3328_configure_cpu(cru, APLL_600_MHZ);
287 /* configure gpll cpll */
288 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
289 rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
291 /* configure perihp aclk, hclk, pclk */
292 aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
293 hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
294 pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
296 rk_clrsetreg(&cru->clksel_con[28],
297 ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK,
298 ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT |
299 aclk_div << ACLK_PERIHP_DIV_CON_SHIFT);
300 rk_clrsetreg(&cru->clksel_con[29],
301 PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK,
302 pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
303 hclk_div << HCLK_PERIHP_DIV_CON_SHIFT);
306 void rk3328_configure_cpu(struct rk3328_cru *cru,
307 enum apll_frequencies apll_freq)
313 rkclk_set_pll(cru, CLK_ARM, apll_cfgs[apll_freq]);
315 clk_core_div = APLL_HZ / CLK_CORE_HZ - 1;
316 aclkm_div = APLL_HZ / ACLKM_CORE_HZ / (clk_core_div + 1) - 1;
317 pclk_dbg_div = APLL_HZ / PCLK_DBG_HZ / (clk_core_div + 1) - 1;
319 rk_clrsetreg(&cru->clksel_con[0],
320 CLK_CORE_PLL_SEL_MASK | CLK_CORE_DIV_MASK,
321 CLK_CORE_PLL_SEL_APLL << CLK_CORE_PLL_SEL_SHIFT |
322 clk_core_div << CLK_CORE_DIV_SHIFT);
324 rk_clrsetreg(&cru->clksel_con[1],
325 PCLK_DBG_DIV_MASK | ACLKM_CORE_DIV_MASK,
326 pclk_dbg_div << PCLK_DBG_DIV_SHIFT |
327 aclkm_div << ACLKM_CORE_DIV_SHIFT);
331 static ulong rk3328_i2c_get_clk(struct rk3328_cru *cru, ulong clk_id)
337 con = readl(&cru->clksel_con[34]);
338 div = con >> CLK_I2C0_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
341 con = readl(&cru->clksel_con[34]);
342 div = con >> CLK_I2C1_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
345 con = readl(&cru->clksel_con[35]);
346 div = con >> CLK_I2C2_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
349 con = readl(&cru->clksel_con[35]);
350 div = con >> CLK_I2C3_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
353 printf("do not support this i2c bus\n");
357 return DIV_TO_RATE(GPLL_HZ, div);
360 static ulong rk3328_i2c_set_clk(struct rk3328_cru *cru, ulong clk_id, uint hz)
364 src_clk_div = GPLL_HZ / hz;
365 assert(src_clk_div - 1 < 127);
369 rk_clrsetreg(&cru->clksel_con[34],
370 CLK_I2C_DIV_CON_MASK << CLK_I2C0_DIV_CON_SHIFT |
371 CLK_I2C_PLL_SEL_MASK << CLK_I2C0_PLL_SEL_SHIFT,
372 (src_clk_div - 1) << CLK_I2C0_DIV_CON_SHIFT |
373 CLK_I2C_PLL_SEL_GPLL << CLK_I2C0_PLL_SEL_SHIFT);
376 rk_clrsetreg(&cru->clksel_con[34],
377 CLK_I2C_DIV_CON_MASK << CLK_I2C1_DIV_CON_SHIFT |
378 CLK_I2C_PLL_SEL_MASK << CLK_I2C1_PLL_SEL_SHIFT,
379 (src_clk_div - 1) << CLK_I2C1_DIV_CON_SHIFT |
380 CLK_I2C_PLL_SEL_GPLL << CLK_I2C1_PLL_SEL_SHIFT);
383 rk_clrsetreg(&cru->clksel_con[35],
384 CLK_I2C_DIV_CON_MASK << CLK_I2C2_DIV_CON_SHIFT |
385 CLK_I2C_PLL_SEL_MASK << CLK_I2C2_PLL_SEL_SHIFT,
386 (src_clk_div - 1) << CLK_I2C2_DIV_CON_SHIFT |
387 CLK_I2C_PLL_SEL_GPLL << CLK_I2C2_PLL_SEL_SHIFT);
390 rk_clrsetreg(&cru->clksel_con[35],
391 CLK_I2C_DIV_CON_MASK << CLK_I2C3_DIV_CON_SHIFT |
392 CLK_I2C_PLL_SEL_MASK << CLK_I2C3_PLL_SEL_SHIFT,
393 (src_clk_div - 1) << CLK_I2C3_DIV_CON_SHIFT |
394 CLK_I2C_PLL_SEL_GPLL << CLK_I2C3_PLL_SEL_SHIFT);
397 printf("do not support this i2c bus\n");
401 return DIV_TO_RATE(GPLL_HZ, src_clk_div);
404 static ulong rk3328_gmac2io_set_clk(struct rk3328_cru *cru, ulong rate)
406 struct rk3328_grf_regs *grf;
409 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
412 * The RGMII CLK can be derived either from an external "clkin"
413 * or can be generated from internally by a divider from SCLK_MAC.
415 if (readl(&grf->mac_con[1]) & BIT(10) &&
416 readl(&grf->soc_con[4]) & BIT(14)) {
417 /* An external clock will always generate the right rate... */
420 u32 con = readl(&cru->clksel_con[27]);
424 if ((con >> GMAC2IO_PLL_SEL_SHIFT) & GMAC2IO_PLL_SEL_GPLL)
429 div = DIV_ROUND_UP(pll_rate, rate) - 1;
431 rk_clrsetreg(&cru->clksel_con[27], GMAC2IO_CLK_DIV_MASK,
432 div << GMAC2IO_CLK_DIV_SHIFT);
434 debug("Unsupported div for gmac:%d\n", div);
436 return DIV_TO_RATE(pll_rate, div);
442 static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id)
444 u32 div, con, con_id;
458 con = readl(&cru->clksel_con[con_id]);
459 div = (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
461 if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
462 == CLK_EMMC_PLL_SEL_24M)
463 return DIV_TO_RATE(OSC_HZ, div) / 2;
465 return DIV_TO_RATE(GPLL_HZ, div) / 2;
468 static ulong rk3328_mmc_set_clk(struct rk3328_cru *cru,
469 ulong clk_id, ulong set_rate)
486 /* Select clk_sdmmc/emmc source from GPLL by default */
487 /* mmc clock defaulg div 2 internal, need provide double in cru */
488 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);
490 if (src_clk_div > 127) {
491 /* use 24MHz source for 400KHz clock */
492 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
493 rk_clrsetreg(&cru->clksel_con[con_id],
494 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
495 CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
496 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
498 rk_clrsetreg(&cru->clksel_con[con_id],
499 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
500 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
501 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
504 return rk3328_mmc_get_clk(cru, clk_id);
507 static ulong rk3328_pwm_get_clk(struct rk3328_cru *cru)
511 con = readl(&cru->clksel_con[24]);
512 div = (con & CLK_PWM_DIV_CON_MASK) >> CLK_PWM_DIV_CON_SHIFT;
514 return DIV_TO_RATE(GPLL_HZ, div);
517 static ulong rk3328_pwm_set_clk(struct rk3328_cru *cru, uint hz)
519 u32 div = GPLL_HZ / hz;
521 rk_clrsetreg(&cru->clksel_con[24],
522 CLK_PWM_PLL_SEL_MASK | CLK_PWM_DIV_CON_MASK,
523 CLK_PWM_PLL_SEL_GPLL << CLK_PWM_PLL_SEL_SHIFT |
524 (div - 1) << CLK_PWM_DIV_CON_SHIFT);
526 return DIV_TO_RATE(GPLL_HZ, div);
529 static ulong rk3328_saradc_get_clk(struct rk3328_cru *cru)
533 val = readl(&cru->clksel_con[23]);
534 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
535 CLK_SARADC_DIV_CON_WIDTH);
537 return DIV_TO_RATE(OSC_HZ, div);
540 static ulong rk3328_saradc_set_clk(struct rk3328_cru *cru, uint hz)
544 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
545 assert(src_clk_div < 128);
547 rk_clrsetreg(&cru->clksel_con[23],
548 CLK_SARADC_DIV_CON_MASK,
549 src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
551 return rk3328_saradc_get_clk(cru);
554 static ulong rk3328_clk_get_rate(struct clk *clk)
556 struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
566 rate = rk3328_mmc_get_clk(priv->cru, clk->id);
572 rate = rk3328_i2c_get_clk(priv->cru, clk->id);
575 rate = rk3328_pwm_get_clk(priv->cru);
578 rate = rk3328_saradc_get_clk(priv->cru);
587 static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
589 struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
599 ret = rk3328_mmc_set_clk(priv->cru, clk->id, rate);
605 ret = rk3328_i2c_set_clk(priv->cru, clk->id, rate);
608 ret = rk3328_gmac2io_set_clk(priv->cru, rate);
611 ret = rk3328_pwm_set_clk(priv->cru, rate);
614 ret = rk3328_saradc_set_clk(priv->cru, rate);
636 case ACLK_RKVDEC_PRE:
639 case SCLK_VDEC_CABAC:
647 case SCLK_USB3OTG_SUSPEND:
656 static int rk3328_gmac2io_set_parent(struct clk *clk, struct clk *parent)
658 struct rk3328_grf_regs *grf;
659 const char *clock_output_name;
662 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
665 * If the requested parent is in the same clock-controller and the id
666 * is SCLK_MAC2IO_SRC ("clk_mac2io_src"), switch to the internal clock.
668 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC2IO_SRC)) {
669 debug("%s: switching RGMII to SCLK_MAC2IO_SRC\n", __func__);
670 rk_clrreg(&grf->mac_con[1], BIT(10));
675 * Otherwise, we need to check the clock-output-names of the
676 * requested parent to see if the requested id is "gmac_clkin".
678 ret = dev_read_string_index(parent->dev, "clock-output-names",
679 parent->id, &clock_output_name);
683 /* If this is "gmac_clkin", switch to the external clock input */
684 if (!strcmp(clock_output_name, "gmac_clkin")) {
685 debug("%s: switching RGMII to CLKIN\n", __func__);
686 rk_setreg(&grf->mac_con[1], BIT(10));
693 static int rk3328_gmac2io_ext_set_parent(struct clk *clk, struct clk *parent)
695 struct rk3328_grf_regs *grf;
696 const char *clock_output_name;
699 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
702 * If the requested parent is in the same clock-controller and the id
703 * is SCLK_MAC2IO ("clk_mac2io"), switch to the internal clock.
705 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC2IO)) {
706 debug("%s: switching RGMII to SCLK_MAC2IO\n", __func__);
707 rk_clrreg(&grf->soc_con[4], BIT(14));
712 * Otherwise, we need to check the clock-output-names of the
713 * requested parent to see if the requested id is "gmac_clkin".
715 ret = dev_read_string_index(parent->dev, "clock-output-names",
716 parent->id, &clock_output_name);
720 /* If this is "gmac_clkin", switch to the external clock input */
721 if (!strcmp(clock_output_name, "gmac_clkin")) {
722 debug("%s: switching RGMII to CLKIN\n", __func__);
723 rk_setreg(&grf->soc_con[4], BIT(14));
730 static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent)
734 return rk3328_gmac2io_set_parent(clk, parent);
735 case SCLK_MAC2IO_EXT:
736 return rk3328_gmac2io_ext_set_parent(clk, parent);
746 debug("%s: unsupported clk %ld\n", __func__, clk->id);
750 static struct clk_ops rk3328_clk_ops = {
751 .get_rate = rk3328_clk_get_rate,
752 .set_rate = rk3328_clk_set_rate,
753 .set_parent = rk3328_clk_set_parent,
756 static int rk3328_clk_probe(struct udevice *dev)
758 struct rk3328_clk_priv *priv = dev_get_priv(dev);
760 rkclk_init(priv->cru);
765 static int rk3328_clk_ofdata_to_platdata(struct udevice *dev)
767 struct rk3328_clk_priv *priv = dev_get_priv(dev);
769 priv->cru = dev_read_addr_ptr(dev);
774 static int rk3328_clk_bind(struct udevice *dev)
777 struct udevice *sys_child;
778 struct sysreset_reg *priv;
780 /* The reset driver does not have a device node, so bind it here */
781 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
784 debug("Warning: No sysreset driver: ret=%d\n", ret);
786 priv = malloc(sizeof(struct sysreset_reg));
787 priv->glb_srst_fst_value = offsetof(struct rk3328_cru,
789 priv->glb_srst_snd_value = offsetof(struct rk3328_cru,
791 sys_child->priv = priv;
794 #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
795 ret = offsetof(struct rk3328_cru, softrst_con[0]);
796 ret = rockchip_reset_bind(dev, ret, 12);
798 debug("Warning: software reset driver bind faile\n");
804 static const struct udevice_id rk3328_clk_ids[] = {
805 { .compatible = "rockchip,rk3328-cru" },
809 U_BOOT_DRIVER(rockchip_rk3328_cru) = {
810 .name = "rockchip_rk3328_cru",
812 .of_match = rk3328_clk_ids,
813 .priv_auto_alloc_size = sizeof(struct rk3328_clk_priv),
814 .ofdata_to_platdata = rk3328_clk_ofdata_to_platdata,
815 .ops = &rk3328_clk_ops,
816 .bind = rk3328_clk_bind,
817 .probe = rk3328_clk_probe,