1 // SPDX-License-Identifier: GPL-2.0
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
8 #include <clk-uclass.h>
14 #include <asm/arch-rockchip/clock.h>
15 #include <asm/arch-rockchip/cru_rk3328.h>
16 #include <asm/arch-rockchip/hardware.h>
17 #include <asm/arch-rockchip/grf_rk3328.h>
20 #include <dt-bindings/clock/rk3328-cru.h>
21 #include <linux/bitops.h>
22 #include <linux/delay.h>
32 #define RATE_TO_DIV(input_rate, output_rate) \
33 ((input_rate) / (output_rate) - 1);
34 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
36 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
38 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
39 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
41 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 4, 1);
42 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 2, 1);
44 static const struct pll_div apll_816_cfg = PLL_DIVISORS(816 * MHz, 1, 2, 1);
45 static const struct pll_div apll_600_cfg = PLL_DIVISORS(600 * MHz, 1, 3, 1);
47 static const struct pll_div *apll_cfgs[] = {
48 [APLL_816_MHZ] = &apll_816_cfg,
49 [APLL_600_MHZ] = &apll_600_cfg,
54 PLL_POSTDIV1_SHIFT = 12,
55 PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT,
57 PLL_FBDIV_MASK = 0xfff,
61 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
63 PLL_LOCK_STATUS_SHIFT = 10,
64 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
65 PLL_POSTDIV2_SHIFT = 6,
66 PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT,
68 PLL_REFDIV_MASK = 0x3f,
71 PLL_FRACDIV_SHIFT = 0,
72 PLL_FRACDIV_MASK = 0xffffff,
84 CLK_CORE_PLL_SEL_APLL = 0,
85 CLK_CORE_PLL_SEL_GPLL,
86 CLK_CORE_PLL_SEL_DPLL,
87 CLK_CORE_PLL_SEL_NPLL,
88 CLK_CORE_PLL_SEL_SHIFT = 6,
89 CLK_CORE_PLL_SEL_MASK = 3 << CLK_CORE_PLL_SEL_SHIFT,
90 CLK_CORE_DIV_SHIFT = 0,
91 CLK_CORE_DIV_MASK = 0x1f,
94 ACLKM_CORE_DIV_SHIFT = 4,
95 ACLKM_CORE_DIV_MASK = 0x7 << ACLKM_CORE_DIV_SHIFT,
96 PCLK_DBG_DIV_SHIFT = 0,
97 PCLK_DBG_DIV_MASK = 0xF << PCLK_DBG_DIV_SHIFT,
100 GMAC2IO_PLL_SEL_SHIFT = 7,
101 GMAC2IO_PLL_SEL_MASK = 1 << GMAC2IO_PLL_SEL_SHIFT,
102 GMAC2IO_PLL_SEL_CPLL = 0,
103 GMAC2IO_PLL_SEL_GPLL = 1,
104 GMAC2IO_CLK_DIV_MASK = 0x1f,
105 GMAC2IO_CLK_DIV_SHIFT = 0,
108 ACLK_PERIHP_PLL_SEL_CPLL = 0,
109 ACLK_PERIHP_PLL_SEL_GPLL,
110 ACLK_PERIHP_PLL_SEL_HDMIPHY,
111 ACLK_PERIHP_PLL_SEL_SHIFT = 6,
112 ACLK_PERIHP_PLL_SEL_MASK = 3 << ACLK_PERIHP_PLL_SEL_SHIFT,
113 ACLK_PERIHP_DIV_CON_SHIFT = 0,
114 ACLK_PERIHP_DIV_CON_MASK = 0x1f,
117 PCLK_PERIHP_DIV_CON_SHIFT = 4,
118 PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT,
119 HCLK_PERIHP_DIV_CON_SHIFT = 0,
120 HCLK_PERIHP_DIV_CON_MASK = 3 << HCLK_PERIHP_DIV_CON_SHIFT,
123 CLK_TSADC_DIV_CON_SHIFT = 0,
124 CLK_TSADC_DIV_CON_MASK = 0x3ff,
127 CLK_SARADC_DIV_CON_SHIFT = 0,
128 CLK_SARADC_DIV_CON_MASK = GENMASK(9, 0),
129 CLK_SARADC_DIV_CON_WIDTH = 10,
132 CLK_PWM_PLL_SEL_CPLL = 0,
133 CLK_PWM_PLL_SEL_GPLL,
134 CLK_PWM_PLL_SEL_SHIFT = 15,
135 CLK_PWM_PLL_SEL_MASK = 1 << CLK_PWM_PLL_SEL_SHIFT,
136 CLK_PWM_DIV_CON_SHIFT = 8,
137 CLK_PWM_DIV_CON_MASK = 0x7f << CLK_PWM_DIV_CON_SHIFT,
139 CLK_SPI_PLL_SEL_CPLL = 0,
140 CLK_SPI_PLL_SEL_GPLL,
141 CLK_SPI_PLL_SEL_SHIFT = 7,
142 CLK_SPI_PLL_SEL_MASK = 1 << CLK_SPI_PLL_SEL_SHIFT,
143 CLK_SPI_DIV_CON_SHIFT = 0,
144 CLK_SPI_DIV_CON_MASK = 0x7f << CLK_SPI_DIV_CON_SHIFT,
147 CLK_SDMMC_PLL_SEL_CPLL = 0,
148 CLK_SDMMC_PLL_SEL_GPLL,
149 CLK_SDMMC_PLL_SEL_24M,
150 CLK_SDMMC_PLL_SEL_USBPHY,
151 CLK_SDMMC_PLL_SHIFT = 8,
152 CLK_SDMMC_PLL_MASK = 0x3 << CLK_SDMMC_PLL_SHIFT,
153 CLK_SDMMC_DIV_CON_SHIFT = 0,
154 CLK_SDMMC_DIV_CON_MASK = 0xff << CLK_SDMMC_DIV_CON_SHIFT,
157 CLK_EMMC_PLL_SEL_CPLL = 0,
158 CLK_EMMC_PLL_SEL_GPLL,
159 CLK_EMMC_PLL_SEL_24M,
160 CLK_EMMC_PLL_SEL_USBPHY,
161 CLK_EMMC_PLL_SHIFT = 8,
162 CLK_EMMC_PLL_MASK = 0x3 << CLK_EMMC_PLL_SHIFT,
163 CLK_EMMC_DIV_CON_SHIFT = 0,
164 CLK_EMMC_DIV_CON_MASK = 0xff << CLK_EMMC_DIV_CON_SHIFT,
167 CLK_I2C_PLL_SEL_CPLL = 0,
168 CLK_I2C_PLL_SEL_GPLL,
169 CLK_I2C_DIV_CON_MASK = 0x7f,
170 CLK_I2C_PLL_SEL_MASK = 1,
171 CLK_I2C1_PLL_SEL_SHIFT = 15,
172 CLK_I2C1_DIV_CON_SHIFT = 8,
173 CLK_I2C0_PLL_SEL_SHIFT = 7,
174 CLK_I2C0_DIV_CON_SHIFT = 0,
177 CLK_I2C3_PLL_SEL_SHIFT = 15,
178 CLK_I2C3_DIV_CON_SHIFT = 8,
179 CLK_I2C2_PLL_SEL_SHIFT = 7,
180 CLK_I2C2_DIV_CON_SHIFT = 0,
183 #define VCO_MAX_KHZ (3200 * (MHz / KHz))
184 #define VCO_MIN_KHZ (800 * (MHz / KHz))
185 #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz))
186 #define OUTPUT_MIN_KHZ (16 * (MHz / KHz))
189 * the div restructions of pll in integer mode, these are defined in
190 * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0
192 #define PLL_DIV_MIN 16
193 #define PLL_DIV_MAX 3200
196 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
197 * Formulas also embedded within the Fractional PLL Verilog model:
198 * If DSMPD = 1 (DSM is disabled, "integer mode")
199 * FOUTVCO = FREF / REFDIV * FBDIV
200 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
202 * FOUTVCO = Fractional PLL non-divided output frequency
203 * FOUTPOSTDIV = Fractional PLL divided output frequency
204 * (output of second post divider)
205 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
206 * REFDIV = Fractional PLL input reference clock divider
207 * FBDIV = Integer value programmed into feedback divide
210 static void rkclk_set_pll(struct rk3328_cru *cru, enum rk_clk_id clk_id,
211 const struct pll_div *div)
214 u32 mode_shift, mode_mask;
220 pll_con = cru->apll_con;
221 mode_shift = APLL_MODE_SHIFT;
224 pll_con = cru->dpll_con;
225 mode_shift = DPLL_MODE_SHIFT;
228 pll_con = cru->cpll_con;
229 mode_shift = CPLL_MODE_SHIFT;
232 pll_con = cru->gpll_con;
233 mode_shift = GPLL_MODE_SHIFT;
236 pll_con = cru->npll_con;
237 mode_shift = NPLL_MODE_SHIFT;
242 mode_mask = 1 << mode_shift;
244 /* All 8 PLLs have same VCO and output frequency range restrictions. */
245 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv;
246 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
248 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, \
249 postdiv2=%d, vco=%u khz, output=%u khz\n",
250 pll_con, div->fbdiv, div->refdiv, div->postdiv1,
251 div->postdiv2, vco_khz, output_khz);
252 assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
253 output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ &&
254 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX);
257 * When power on or changing PLL setting,
258 * we must force PLL into slow mode to ensure output stable clock.
260 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_SLOW << mode_shift);
262 /* use integer mode */
263 rk_clrsetreg(&pll_con[1], PLL_DSMPD_MASK,
264 PLL_INTEGER_MODE << PLL_DSMPD_SHIFT);
266 rk_clrsetreg(&pll_con[0],
267 PLL_FBDIV_MASK | PLL_POSTDIV1_MASK,
268 (div->fbdiv << PLL_FBDIV_SHIFT) |
269 (div->postdiv1 << PLL_POSTDIV1_SHIFT));
270 rk_clrsetreg(&pll_con[1],
271 PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
272 (div->postdiv2 << PLL_POSTDIV2_SHIFT) |
273 (div->refdiv << PLL_REFDIV_SHIFT));
275 /* waiting for pll lock */
276 while (!(readl(&pll_con[1]) & (1 << PLL_LOCK_STATUS_SHIFT)))
279 /* pll enter normal mode */
280 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift);
283 static void rkclk_init(struct rk3328_cru *cru)
289 rk3328_configure_cpu(cru, APLL_600_MHZ);
291 /* configure gpll cpll */
292 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
293 rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
295 /* configure perihp aclk, hclk, pclk */
296 aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
297 hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
298 pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
300 rk_clrsetreg(&cru->clksel_con[28],
301 ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK,
302 ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT |
303 aclk_div << ACLK_PERIHP_DIV_CON_SHIFT);
304 rk_clrsetreg(&cru->clksel_con[29],
305 PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK,
306 pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
307 hclk_div << HCLK_PERIHP_DIV_CON_SHIFT);
310 void rk3328_configure_cpu(struct rk3328_cru *cru,
311 enum apll_frequencies apll_freq)
317 rkclk_set_pll(cru, CLK_ARM, apll_cfgs[apll_freq]);
319 clk_core_div = APLL_HZ / CLK_CORE_HZ - 1;
320 aclkm_div = APLL_HZ / ACLKM_CORE_HZ / (clk_core_div + 1) - 1;
321 pclk_dbg_div = APLL_HZ / PCLK_DBG_HZ / (clk_core_div + 1) - 1;
323 rk_clrsetreg(&cru->clksel_con[0],
324 CLK_CORE_PLL_SEL_MASK | CLK_CORE_DIV_MASK,
325 CLK_CORE_PLL_SEL_APLL << CLK_CORE_PLL_SEL_SHIFT |
326 clk_core_div << CLK_CORE_DIV_SHIFT);
328 rk_clrsetreg(&cru->clksel_con[1],
329 PCLK_DBG_DIV_MASK | ACLKM_CORE_DIV_MASK,
330 pclk_dbg_div << PCLK_DBG_DIV_SHIFT |
331 aclkm_div << ACLKM_CORE_DIV_SHIFT);
335 static ulong rk3328_i2c_get_clk(struct rk3328_cru *cru, ulong clk_id)
341 con = readl(&cru->clksel_con[34]);
342 div = con >> CLK_I2C0_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
345 con = readl(&cru->clksel_con[34]);
346 div = con >> CLK_I2C1_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
349 con = readl(&cru->clksel_con[35]);
350 div = con >> CLK_I2C2_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
353 con = readl(&cru->clksel_con[35]);
354 div = con >> CLK_I2C3_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
357 printf("do not support this i2c bus\n");
361 return DIV_TO_RATE(GPLL_HZ, div);
364 static ulong rk3328_i2c_set_clk(struct rk3328_cru *cru, ulong clk_id, uint hz)
368 src_clk_div = GPLL_HZ / hz;
369 assert(src_clk_div - 1 < 127);
373 rk_clrsetreg(&cru->clksel_con[34],
374 CLK_I2C_DIV_CON_MASK << CLK_I2C0_DIV_CON_SHIFT |
375 CLK_I2C_PLL_SEL_MASK << CLK_I2C0_PLL_SEL_SHIFT,
376 (src_clk_div - 1) << CLK_I2C0_DIV_CON_SHIFT |
377 CLK_I2C_PLL_SEL_GPLL << CLK_I2C0_PLL_SEL_SHIFT);
380 rk_clrsetreg(&cru->clksel_con[34],
381 CLK_I2C_DIV_CON_MASK << CLK_I2C1_DIV_CON_SHIFT |
382 CLK_I2C_PLL_SEL_MASK << CLK_I2C1_PLL_SEL_SHIFT,
383 (src_clk_div - 1) << CLK_I2C1_DIV_CON_SHIFT |
384 CLK_I2C_PLL_SEL_GPLL << CLK_I2C1_PLL_SEL_SHIFT);
387 rk_clrsetreg(&cru->clksel_con[35],
388 CLK_I2C_DIV_CON_MASK << CLK_I2C2_DIV_CON_SHIFT |
389 CLK_I2C_PLL_SEL_MASK << CLK_I2C2_PLL_SEL_SHIFT,
390 (src_clk_div - 1) << CLK_I2C2_DIV_CON_SHIFT |
391 CLK_I2C_PLL_SEL_GPLL << CLK_I2C2_PLL_SEL_SHIFT);
394 rk_clrsetreg(&cru->clksel_con[35],
395 CLK_I2C_DIV_CON_MASK << CLK_I2C3_DIV_CON_SHIFT |
396 CLK_I2C_PLL_SEL_MASK << CLK_I2C3_PLL_SEL_SHIFT,
397 (src_clk_div - 1) << CLK_I2C3_DIV_CON_SHIFT |
398 CLK_I2C_PLL_SEL_GPLL << CLK_I2C3_PLL_SEL_SHIFT);
401 printf("do not support this i2c bus\n");
405 return DIV_TO_RATE(GPLL_HZ, src_clk_div);
408 static ulong rk3328_gmac2io_set_clk(struct rk3328_cru *cru, ulong rate)
410 struct rk3328_grf_regs *grf;
413 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
416 * The RGMII CLK can be derived either from an external "clkin"
417 * or can be generated from internally by a divider from SCLK_MAC.
419 if (readl(&grf->mac_con[1]) & BIT(10) &&
420 readl(&grf->soc_con[4]) & BIT(14)) {
421 /* An external clock will always generate the right rate... */
424 u32 con = readl(&cru->clksel_con[27]);
428 if ((con >> GMAC2IO_PLL_SEL_SHIFT) & GMAC2IO_PLL_SEL_GPLL)
433 div = DIV_ROUND_UP(pll_rate, rate) - 1;
435 rk_clrsetreg(&cru->clksel_con[27], GMAC2IO_CLK_DIV_MASK,
436 div << GMAC2IO_CLK_DIV_SHIFT);
438 debug("Unsupported div for gmac:%d\n", div);
440 return DIV_TO_RATE(pll_rate, div);
446 static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id)
448 u32 div, con, con_id;
462 con = readl(&cru->clksel_con[con_id]);
463 div = (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
465 if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
466 == CLK_EMMC_PLL_SEL_24M)
467 return DIV_TO_RATE(OSC_HZ, div) / 2;
469 return DIV_TO_RATE(GPLL_HZ, div) / 2;
472 static ulong rk3328_mmc_set_clk(struct rk3328_cru *cru,
473 ulong clk_id, ulong set_rate)
490 /* Select clk_sdmmc/emmc source from GPLL by default */
491 /* mmc clock defaulg div 2 internal, need provide double in cru */
492 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);
494 if (src_clk_div > 127) {
495 /* use 24MHz source for 400KHz clock */
496 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
497 rk_clrsetreg(&cru->clksel_con[con_id],
498 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
499 CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
500 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
502 rk_clrsetreg(&cru->clksel_con[con_id],
503 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
504 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
505 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
508 return rk3328_mmc_get_clk(cru, clk_id);
511 static ulong rk3328_pwm_get_clk(struct rk3328_cru *cru)
515 con = readl(&cru->clksel_con[24]);
516 div = (con & CLK_PWM_DIV_CON_MASK) >> CLK_PWM_DIV_CON_SHIFT;
518 return DIV_TO_RATE(GPLL_HZ, div);
521 static ulong rk3328_pwm_set_clk(struct rk3328_cru *cru, uint hz)
523 u32 div = GPLL_HZ / hz;
525 rk_clrsetreg(&cru->clksel_con[24],
526 CLK_PWM_PLL_SEL_MASK | CLK_PWM_DIV_CON_MASK,
527 CLK_PWM_PLL_SEL_GPLL << CLK_PWM_PLL_SEL_SHIFT |
528 (div - 1) << CLK_PWM_DIV_CON_SHIFT);
530 return DIV_TO_RATE(GPLL_HZ, div);
533 static ulong rk3328_saradc_get_clk(struct rk3328_cru *cru)
537 val = readl(&cru->clksel_con[23]);
538 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
539 CLK_SARADC_DIV_CON_WIDTH);
541 return DIV_TO_RATE(OSC_HZ, div);
544 static ulong rk3328_saradc_set_clk(struct rk3328_cru *cru, uint hz)
548 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
549 assert(src_clk_div < 128);
551 rk_clrsetreg(&cru->clksel_con[23],
552 CLK_SARADC_DIV_CON_MASK,
553 src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
555 return rk3328_saradc_get_clk(cru);
558 static ulong rk3328_spi_get_clk(struct rk3328_cru *cru)
562 val = readl(&cru->clksel_con[24]);
563 div = (val & CLK_SPI_DIV_CON_MASK) >> CLK_SPI_DIV_CON_SHIFT;
565 return DIV_TO_RATE(OSC_HZ, div);
568 static ulong rk3328_spi_set_clk(struct rk3328_cru *cru, uint hz)
572 src_clk_div = GPLL_HZ / hz;
573 assert(src_clk_div < 128);
575 rk_clrsetreg(&cru->clksel_con[24],
576 CLK_PWM_PLL_SEL_MASK | CLK_PWM_DIV_CON_MASK,
577 CLK_PWM_PLL_SEL_GPLL << CLK_PWM_PLL_SEL_SHIFT |
578 (src_clk_div - 1) << CLK_PWM_DIV_CON_SHIFT);
580 return rk3328_spi_get_clk(cru);
583 static ulong rk3328_clk_get_rate(struct clk *clk)
585 struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
595 rate = rk3328_mmc_get_clk(priv->cru, clk->id);
601 rate = rk3328_i2c_get_clk(priv->cru, clk->id);
604 rate = rk3328_pwm_get_clk(priv->cru);
607 rate = rk3328_saradc_get_clk(priv->cru);
610 rate = rk3328_spi_get_clk(priv->cru);
619 static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
621 struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
631 ret = rk3328_mmc_set_clk(priv->cru, clk->id, rate);
637 ret = rk3328_i2c_set_clk(priv->cru, clk->id, rate);
640 ret = rk3328_gmac2io_set_clk(priv->cru, rate);
643 ret = rk3328_pwm_set_clk(priv->cru, rate);
646 ret = rk3328_saradc_set_clk(priv->cru, rate);
649 ret = rk3328_spi_set_clk(priv->cru, rate);
671 case ACLK_RKVDEC_PRE:
674 case SCLK_VDEC_CABAC:
682 case SCLK_USB3OTG_SUSPEND:
691 static int rk3328_gmac2io_set_parent(struct clk *clk, struct clk *parent)
693 struct rk3328_grf_regs *grf;
694 const char *clock_output_name;
697 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
700 * If the requested parent is in the same clock-controller and the id
701 * is SCLK_MAC2IO_SRC ("clk_mac2io_src"), switch to the internal clock.
703 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC2IO_SRC)) {
704 debug("%s: switching RGMII to SCLK_MAC2IO_SRC\n", __func__);
705 rk_clrreg(&grf->mac_con[1], BIT(10));
710 * Otherwise, we need to check the clock-output-names of the
711 * requested parent to see if the requested id is "gmac_clkin".
713 ret = dev_read_string_index(parent->dev, "clock-output-names",
714 parent->id, &clock_output_name);
718 /* If this is "gmac_clkin", switch to the external clock input */
719 if (!strcmp(clock_output_name, "gmac_clkin")) {
720 debug("%s: switching RGMII to CLKIN\n", __func__);
721 rk_setreg(&grf->mac_con[1], BIT(10));
728 static int rk3328_gmac2io_ext_set_parent(struct clk *clk, struct clk *parent)
730 struct rk3328_grf_regs *grf;
731 const char *clock_output_name;
734 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
737 * If the requested parent is in the same clock-controller and the id
738 * is SCLK_MAC2IO ("clk_mac2io"), switch to the internal clock.
740 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC2IO)) {
741 debug("%s: switching RGMII to SCLK_MAC2IO\n", __func__);
742 rk_clrreg(&grf->soc_con[4], BIT(14));
747 * Otherwise, we need to check the clock-output-names of the
748 * requested parent to see if the requested id is "gmac_clkin".
750 ret = dev_read_string_index(parent->dev, "clock-output-names",
751 parent->id, &clock_output_name);
755 /* If this is "gmac_clkin", switch to the external clock input */
756 if (!strcmp(clock_output_name, "gmac_clkin")) {
757 debug("%s: switching RGMII to CLKIN\n", __func__);
758 rk_setreg(&grf->soc_con[4], BIT(14));
765 static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent)
769 return rk3328_gmac2io_set_parent(clk, parent);
770 case SCLK_MAC2IO_EXT:
771 return rk3328_gmac2io_ext_set_parent(clk, parent);
781 debug("%s: unsupported clk %ld\n", __func__, clk->id);
785 static struct clk_ops rk3328_clk_ops = {
786 .get_rate = rk3328_clk_get_rate,
787 .set_rate = rk3328_clk_set_rate,
788 .set_parent = rk3328_clk_set_parent,
791 static int rk3328_clk_probe(struct udevice *dev)
793 struct rk3328_clk_priv *priv = dev_get_priv(dev);
795 rkclk_init(priv->cru);
800 static int rk3328_clk_of_to_plat(struct udevice *dev)
802 struct rk3328_clk_priv *priv = dev_get_priv(dev);
804 priv->cru = dev_read_addr_ptr(dev);
809 static int rk3328_clk_bind(struct udevice *dev)
812 struct udevice *sys_child;
813 struct sysreset_reg *priv;
815 /* The reset driver does not have a device node, so bind it here */
816 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
819 debug("Warning: No sysreset driver: ret=%d\n", ret);
821 priv = malloc(sizeof(struct sysreset_reg));
822 priv->glb_srst_fst_value = offsetof(struct rk3328_cru,
824 priv->glb_srst_snd_value = offsetof(struct rk3328_cru,
826 sys_child->priv = priv;
829 #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
830 ret = offsetof(struct rk3328_cru, softrst_con[0]);
831 ret = rockchip_reset_bind(dev, ret, 12);
833 debug("Warning: software reset driver bind faile\n");
839 static const struct udevice_id rk3328_clk_ids[] = {
840 { .compatible = "rockchip,rk3328-cru" },
844 U_BOOT_DRIVER(rockchip_rk3328_cru) = {
845 .name = "rockchip_rk3328_cru",
847 .of_match = rk3328_clk_ids,
848 .priv_auto = sizeof(struct rk3328_clk_priv),
849 .of_to_plat = rk3328_clk_of_to_plat,
850 .ops = &rk3328_clk_ops,
851 .bind = rk3328_clk_bind,
852 .probe = rk3328_clk_probe,