drivers/clk/rockchip/clk_rk3308.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * (C) Copyright 2017-2019 Rockchip Electronics Co., Ltd
   4  */
   5 #include <common.h>
   6 #include <bitfield.h>
   7 #include <clk-uclass.h>
   8 #include <dm.h>
   9 #include <div64.h>
  10 #include <errno.h>
  11 #include <log.h>
  12 #include <malloc.h>
  13 #include <syscon.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/cru_rk3308.h>
  16 #include <asm/arch-rockchip/clock.h>
  17 #include <asm/arch-rockchip/hardware.h>
  18 #include <dm/lists.h>
  19 #include <dt-bindings/clock/rk3308-cru.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 enum {
  24         VCO_MAX_HZ      = 3200U * 1000000,
  25         VCO_MIN_HZ      = 800 * 1000000,
  26         OUTPUT_MAX_HZ   = 3200U * 1000000,
  27         OUTPUT_MIN_HZ   = 24 * 1000000,
  28 };
  29
  30 #define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))
  31
  32 #define RK3308_CPUCLK_RATE(_rate, _aclk_div, _pclk_div)         \
  33 {                                                               \
  34         .rate   = _rate##U,                                     \
  35         .aclk_div = _aclk_div,                                  \
  36         .pclk_div = _pclk_div,                                  \
  37 }
  38
  39 static struct rockchip_pll_rate_table rk3308_pll_rates[] = {
  40         /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
  41         RK3036_PLL_RATE(1300000000, 6, 325, 1, 1, 1, 0),
  42         RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
  43         RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
  44         RK3036_PLL_RATE(748000000, 2, 187, 3, 1, 1, 0),
  45 };
  46
  47 static struct rockchip_cpu_rate_table rk3308_cpu_rates[] = {
  48         RK3308_CPUCLK_RATE(1200000000, 1, 5),
  49         RK3308_CPUCLK_RATE(1008000000, 1, 5),
  50         RK3308_CPUCLK_RATE(816000000, 1, 3),
  51         RK3308_CPUCLK_RATE(600000000, 1, 3),
  52         RK3308_CPUCLK_RATE(408000000, 1, 1),
  53 };
  54
  55 static struct rockchip_pll_clock rk3308_pll_clks[] = {
  56         [APLL] = PLL(pll_rk3328, PLL_APLL, RK3308_PLL_CON(0),
  57                      RK3308_MODE_CON, 0, 10, 0, rk3308_pll_rates),
  58         [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3308_PLL_CON(8),
  59                      RK3308_MODE_CON, 2, 10, 0, NULL),
  60         [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
  61                       RK3308_MODE_CON, 4, 10, 0, NULL),
  62         [VPLL1] = PLL(pll_rk3328, PLL_VPLL1, RK3308_PLL_CON(24),
  63                       RK3308_MODE_CON, 6, 10, 0, NULL),
  64 };
  65
  66 static ulong rk3308_armclk_set_clk(struct rk3308_clk_priv *priv, ulong hz)
  67 {
  68         struct rk3308_cru *cru = priv->cru;
  69         const struct rockchip_cpu_rate_table *rate;
  70         ulong old_rate;
  71
  72         rate = rockchip_get_cpu_settings(rk3308_cpu_rates, hz);
  73         if (!rate) {
  74                 printf("%s unsupport rate\n", __func__);
  75                 return -EINVAL;
  76         }
  77
  78         /*
  79          * select apll as cpu/core clock pll source and
  80          * set up dependent divisors for PERI and ACLK clocks.
  81          * core hz : apll = 1:1
  82          */
  83         old_rate = rockchip_pll_get_rate(&rk3308_pll_clks[APLL],
  84                                          priv->cru, APLL);
  85         if (old_rate > hz) {
  86                 if (rockchip_pll_set_rate(&rk3308_pll_clks[APLL],
  87                                           priv->cru, APLL, hz))
  88                         return -EINVAL;
  89                 rk_clrsetreg(&cru->clksel_con[0],
  90                              CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK |
  91                              CORE_ACLK_DIV_MASK | CORE_DBG_DIV_MASK,
  92                              rate->aclk_div << CORE_ACLK_DIV_SHIFT |
  93                              rate->pclk_div << CORE_DBG_DIV_SHIFT |
  94                              CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
  95                              0 << CORE_DIV_CON_SHIFT);
  96         } else if (old_rate < hz) {
  97                 rk_clrsetreg(&cru->clksel_con[0],
  98                              CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK |
  99                              CORE_ACLK_DIV_MASK | CORE_DBG_DIV_MASK,
 100                              rate->aclk_div << CORE_ACLK_DIV_SHIFT |
 101                              rate->pclk_div << CORE_DBG_DIV_SHIFT |
 102                              CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
 103                              0 << CORE_DIV_CON_SHIFT);
 104                 if (rockchip_pll_set_rate(&rk3308_pll_clks[APLL],
 105                                           priv->cru, APLL, hz))
 106                         return -EINVAL;
 107         }
 108
 109         return rockchip_pll_get_rate(&rk3308_pll_clks[APLL], priv->cru, APLL);
 110 }
 111
 112 static void rk3308_clk_get_pll_rate(struct rk3308_clk_priv *priv)
 113 {
 114         if (!priv->dpll_hz)
 115                 priv->dpll_hz = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL],
 116                                                       priv->cru, DPLL);
 117         if (!priv->vpll0_hz)
 118                 priv->vpll0_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0],
 119                                                        priv->cru, VPLL0);
 120         if (!priv->vpll1_hz)
 121                 priv->vpll1_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL1],
 122                                                        priv->cru, VPLL1);
 123 }
 124
 125 static ulong rk3308_i2c_get_clk(struct clk *clk)
 126 {
 127         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 128         struct rk3308_cru *cru = priv->cru;
 129         u32 div, con, con_id;
 130
 131         switch (clk->id) {
 132         case SCLK_I2C0:
 133                 con_id = 25;
 134                 break;
 135         case SCLK_I2C1:
 136                 con_id = 26;
 137                 break;
 138         case SCLK_I2C2:
 139                 con_id = 27;
 140                 break;
 141         case SCLK_I2C3:
 142                 con_id = 28;
 143                 break;
 144         default:
 145                 printf("do not support this i2c bus\n");
 146                 return -EINVAL;
 147         }
 148
 149         con = readl(&cru->clksel_con[con_id]);
 150         div = con >> CLK_I2C_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
 151
 152         return DIV_TO_RATE(priv->dpll_hz, div);
 153 }
 154
 155 static ulong rk3308_i2c_set_clk(struct clk *clk, uint hz)
 156 {
 157         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 158         struct rk3308_cru *cru = priv->cru;
 159         u32 src_clk_div, con_id;
 160
 161         src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz);
 162         assert(src_clk_div - 1 <= 127);
 163
 164         switch (clk->id) {
 165         case SCLK_I2C0:
 166                 con_id = 25;
 167                 break;
 168         case SCLK_I2C1:
 169                 con_id = 26;
 170                 break;
 171         case SCLK_I2C2:
 172                 con_id = 27;
 173                 break;
 174         case SCLK_I2C3:
 175                 con_id = 28;
 176                 break;
 177         default:
 178                 printf("do not support this i2c bus\n");
 179                 return -EINVAL;
 180         }
 181         rk_clrsetreg(&cru->clksel_con[con_id],
 182                      CLK_I2C_PLL_SEL_MASK | CLK_I2C_DIV_CON_MASK,
 183                      CLK_I2C_PLL_SEL_DPLL << CLK_I2C_PLL_SEL_SHIFT |
 184                      (src_clk_div - 1) << CLK_I2C_DIV_CON_SHIFT);
 185
 186         return rk3308_i2c_get_clk(clk);
 187 }
 188
 189 static ulong rk3308_mac_set_clk(struct clk *clk, uint hz)
 190 {
 191         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 192         struct rk3308_cru *cru = priv->cru;
 193         u32 con = readl(&cru->clksel_con[43]);
 194         ulong pll_rate;
 195         u8 div;
 196
 197         if ((con >> MAC_PLL_SHIFT) & MAC_SEL_VPLL0)
 198                 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0],
 199                                                  priv->cru, VPLL0);
 200         else if ((con >> MAC_PLL_SHIFT) & MAC_SEL_VPLL1)
 201                 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL1],
 202                                                  priv->cru, VPLL1);
 203         else
 204                 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL],
 205                                                  priv->cru, DPLL);
 206
 207         /*default set 50MHZ for gmac*/
 208         if (!hz)
 209                 hz = 50000000;
 210
 211         div = DIV_ROUND_UP(pll_rate, hz) - 1;
 212         assert(div < 32);
 213         rk_clrsetreg(&cru->clksel_con[43], MAC_DIV_MASK,
 214                      div << MAC_DIV_SHIFT);
 215
 216         return DIV_TO_RATE(pll_rate, div);
 217 }
 218
 219 static int rk3308_mac_set_speed_clk(struct clk *clk, uint hz)
 220 {
 221         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 222         struct rk3308_cru *cru = priv->cru;
 223
 224         if (hz != 2500000 && hz != 25000000) {
 225                 debug("Unsupported mac speed:%d\n", hz);
 226                 return -EINVAL;
 227         }
 228
 229         rk_clrsetreg(&cru->clksel_con[43], MAC_CLK_SPEED_SEL_MASK,
 230                      ((hz == 2500000) ? 0 : 1) << MAC_CLK_SPEED_SEL_SHIFT);
 231
 232         return 0;
 233 }
 234
 235 static ulong rk3308_mmc_get_clk(struct clk *clk)
 236 {
 237         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 238         struct rk3308_cru *cru = priv->cru;
 239         u32 div, con, con_id;
 240
 241         switch (clk->id) {
 242         case HCLK_SDMMC:
 243         case SCLK_SDMMC:
 244                 con_id = 39;
 245                 break;
 246         case HCLK_EMMC:
 247         case SCLK_EMMC:
 248         case SCLK_EMMC_SAMPLE:
 249                 con_id = 41;
 250                 break;
 251         default:
 252                 return -EINVAL;
 253         }
 254
 255         con = readl(&cru->clksel_con[con_id]);
 256         div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
 257
 258         if ((con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT
 259             == EMMC_SEL_24M)
 260                 return DIV_TO_RATE(OSC_HZ, div) / 2;
 261         else
 262                 return DIV_TO_RATE(priv->vpll0_hz, div) / 2;
 263 }
 264
 265 static ulong rk3308_mmc_set_clk(struct clk *clk, ulong set_rate)
 266 {
 267         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 268         struct rk3308_cru *cru = priv->cru;
 269         int src_clk_div;
 270         u32 con_id;
 271
 272         switch (clk->id) {
 273         case HCLK_SDMMC:
 274         case SCLK_SDMMC:
 275                 con_id = 39;
 276                 break;
 277         case HCLK_EMMC:
 278         case SCLK_EMMC:
 279                 con_id = 41;
 280                 break;
 281         default:
 282                 return -EINVAL;
 283         }
 284         /* Select clk_sdmmc/emmc source from VPLL0 by default */
 285         /* mmc clock defaulg div 2 internal, need provide double in cru */
 286         src_clk_div = DIV_ROUND_UP(priv->vpll0_hz / 2, set_rate);
 287
 288         if (src_clk_div > 127) {
 289                 /* use 24MHz source for 400KHz clock */
 290                 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
 291                 rk_clrsetreg(&cru->clksel_con[con_id],
 292                              EMMC_PLL_MASK | EMMC_DIV_MASK | EMMC_CLK_SEL_MASK,
 293                              EMMC_CLK_SEL_EMMC << EMMC_CLK_SEL_SHIFT |
 294                              EMMC_SEL_24M << EMMC_PLL_SHIFT |
 295                              (src_clk_div - 1) << EMMC_DIV_SHIFT);
 296         } else {
 297                 rk_clrsetreg(&cru->clksel_con[con_id],
 298                              EMMC_PLL_MASK | EMMC_DIV_MASK | EMMC_CLK_SEL_MASK,
 299                              EMMC_CLK_SEL_EMMC << EMMC_CLK_SEL_SHIFT |
 300                              EMMC_SEL_VPLL0 << EMMC_PLL_SHIFT |
 301                              (src_clk_div - 1) << EMMC_DIV_SHIFT);
 302         }
 303
 304         return rk3308_mmc_get_clk(clk);
 305 }
 306
 307 static ulong rk3308_saradc_get_clk(struct clk *clk)
 308 {
 309         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 310         struct rk3308_cru *cru = priv->cru;
 311         u32 div, con;
 312
 313         con = readl(&cru->clksel_con[34]);
 314         div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK;
 315
 316         return DIV_TO_RATE(OSC_HZ, div);
 317 }
 318
 319 static ulong rk3308_saradc_set_clk(struct clk *clk, uint hz)
 320 {
 321         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 322         struct rk3308_cru *cru = priv->cru;
 323         int src_clk_div;
 324
 325         src_clk_div = DIV_ROUND_UP(OSC_HZ, hz);
 326         assert(src_clk_div - 1 <= 2047);
 327
 328         rk_clrsetreg(&cru->clksel_con[34],
 329                      CLK_SARADC_DIV_CON_MASK,
 330                      (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT);
 331
 332         return rk3308_saradc_get_clk(clk);
 333 }
 334
 335 static ulong rk3308_tsadc_get_clk(struct clk *clk)
 336 {
 337         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 338         struct rk3308_cru *cru = priv->cru;
 339         u32 div, con;
 340
 341         con = readl(&cru->clksel_con[33]);
 342         div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK;
 343
 344         return DIV_TO_RATE(OSC_HZ, div);
 345 }
 346
 347 static ulong rk3308_tsadc_set_clk(struct clk *clk, uint hz)
 348 {
 349         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 350         struct rk3308_cru *cru = priv->cru;
 351         int src_clk_div;
 352
 353         src_clk_div = DIV_ROUND_UP(OSC_HZ, hz);
 354         assert(src_clk_div - 1 <= 2047);
 355
 356         rk_clrsetreg(&cru->clksel_con[33],
 357                      CLK_SARADC_DIV_CON_MASK,
 358                      (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT);
 359
 360         return rk3308_tsadc_get_clk(clk);
 361 }
 362
 363 static ulong rk3308_spi_get_clk(struct clk *clk)
 364 {
 365         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 366         struct rk3308_cru *cru = priv->cru;
 367         u32 div, con, con_id;
 368
 369         switch (clk->id) {
 370         case SCLK_SPI0:
 371                 con_id = 30;
 372                 break;
 373         case SCLK_SPI1:
 374                 con_id = 31;
 375                 break;
 376         case SCLK_SPI2:
 377                 con_id = 32;
 378                 break;
 379         default:
 380                 printf("do not support this spi bus\n");
 381                 return -EINVAL;
 382         }
 383
 384         con = readl(&cru->clksel_con[con_id]);
 385         div = con >> CLK_SPI_DIV_CON_SHIFT & CLK_SPI_DIV_CON_MASK;
 386
 387         return DIV_TO_RATE(priv->dpll_hz, div);
 388 }
 389
 390 static ulong rk3308_spi_set_clk(struct clk *clk, uint hz)
 391 {
 392         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 393         struct rk3308_cru *cru = priv->cru;
 394         u32 src_clk_div, con_id;
 395
 396         src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz);
 397         assert(src_clk_div - 1 <= 127);
 398
 399         switch (clk->id) {
 400         case SCLK_SPI0:
 401                 con_id = 30;
 402                 break;
 403         case SCLK_SPI1:
 404                 con_id = 31;
 405                 break;
 406         case SCLK_SPI2:
 407                 con_id = 32;
 408                 break;
 409         default:
 410                 printf("do not support this spi bus\n");
 411                 return -EINVAL;
 412         }
 413
 414         rk_clrsetreg(&cru->clksel_con[con_id],
 415                      CLK_SPI_PLL_SEL_MASK | CLK_SPI_DIV_CON_MASK,
 416                      CLK_SPI_PLL_SEL_DPLL << CLK_SPI_PLL_SEL_SHIFT |
 417                      (src_clk_div - 1) << CLK_SPI_DIV_CON_SHIFT);
 418
 419         return rk3308_spi_get_clk(clk);
 420 }
 421
 422 static ulong rk3308_pwm_get_clk(struct clk *clk)
 423 {
 424         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 425         struct rk3308_cru *cru = priv->cru;
 426         u32 div, con;
 427
 428         con = readl(&cru->clksel_con[29]);
 429         div = con >> CLK_PWM_DIV_CON_SHIFT & CLK_PWM_DIV_CON_MASK;
 430
 431         return DIV_TO_RATE(priv->dpll_hz, div);
 432 }
 433
 434 static ulong rk3308_pwm_set_clk(struct clk *clk, uint hz)
 435 {
 436         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 437         struct rk3308_cru *cru = priv->cru;
 438         int src_clk_div;
 439
 440         src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz);
 441         assert(src_clk_div - 1 <= 127);
 442
 443         rk_clrsetreg(&cru->clksel_con[29],
 444                      CLK_PWM_PLL_SEL_MASK | CLK_PWM_DIV_CON_MASK,
 445                      CLK_PWM_PLL_SEL_DPLL << CLK_PWM_PLL_SEL_SHIFT |
 446                      (src_clk_div - 1) << CLK_PWM_DIV_CON_SHIFT);
 447
 448         return rk3308_pwm_get_clk(clk);
 449 }
 450
 451 static ulong rk3308_vop_get_clk(struct clk *clk)
 452 {
 453         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 454         struct rk3308_cru *cru = priv->cru;
 455         u32 div, pll_sel, vol_sel, con, parent;
 456
 457         con = readl(&cru->clksel_con[8]);
 458         vol_sel = (con & DCLK_VOP_SEL_MASK) >> DCLK_VOP_SEL_SHIFT;
 459         pll_sel = (con & DCLK_VOP_PLL_SEL_MASK) >> DCLK_VOP_PLL_SEL_SHIFT;
 460         div = con & DCLK_VOP_DIV_MASK;
 461
 462         if (vol_sel == DCLK_VOP_SEL_24M) {
 463                 parent = OSC_HZ;
 464         } else if (vol_sel == DCLK_VOP_SEL_DIVOUT) {
 465                 switch (pll_sel) {
 466                 case DCLK_VOP_PLL_SEL_DPLL:
 467                         parent = priv->dpll_hz;
 468                         break;
 469                 case DCLK_VOP_PLL_SEL_VPLL0:
 470                         parent = priv->vpll0_hz;
 471                         break;
 472                 case DCLK_VOP_PLL_SEL_VPLL1:
 473                         parent = priv->vpll0_hz;
 474                         break;
 475                 default:
 476                         printf("do not support this vop pll sel\n");
 477                         return -EINVAL;
 478                 }
 479         } else {
 480                 printf("do not support this vop sel\n");
 481                 return -EINVAL;
 482         }
 483
 484         return DIV_TO_RATE(parent, div);
 485 }
 486
 487 static ulong rk3308_vop_set_clk(struct clk *clk, ulong hz)
 488 {
 489         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 490         struct rk3308_cru *cru = priv->cru;
 491         ulong pll_rate, now, best_rate = 0;
 492         u32 i, div, best_div = 0, best_sel = 0;
 493
 494         for (i = 0; i <= DCLK_VOP_PLL_SEL_VPLL1; i++) {
 495                 switch (i) {
 496                 case DCLK_VOP_PLL_SEL_DPLL:
 497                         pll_rate = priv->dpll_hz;
 498                         break;
 499                 case DCLK_VOP_PLL_SEL_VPLL0:
 500                         pll_rate = priv->vpll0_hz;
 501                         break;
 502                 case DCLK_VOP_PLL_SEL_VPLL1:
 503                         pll_rate = priv->vpll1_hz;
 504                         break;
 505                 default:
 506                         printf("do not support this vop pll sel\n");
 507                         return -EINVAL;
 508                 }
 509
 510                 div = DIV_ROUND_UP(pll_rate, hz);
 511                 if (div > 255)
 512                         continue;
 513                 now = pll_rate / div;
 514                 if (abs(hz - now) < abs(hz - best_rate)) {
 515                         best_rate = now;
 516                         best_div = div;
 517                         best_sel = i;
 518                 }
 519                 debug("pll_rate=%lu, best_rate=%lu, best_div=%u, best_sel=%u\n",
 520                       pll_rate, best_rate, best_div, best_sel);
 521         }
 522
 523         if (best_rate != hz && hz == OSC_HZ) {
 524                 rk_clrsetreg(&cru->clksel_con[8],
 525                              DCLK_VOP_SEL_MASK,
 526                              DCLK_VOP_SEL_24M << DCLK_VOP_SEL_SHIFT);
 527         } else if (best_rate) {
 528                 rk_clrsetreg(&cru->clksel_con[8],
 529                              DCLK_VOP_SEL_MASK | DCLK_VOP_PLL_SEL_MASK |
 530                              DCLK_VOP_DIV_MASK,
 531                              DCLK_VOP_SEL_DIVOUT << DCLK_VOP_SEL_SHIFT |
 532                              best_sel << DCLK_VOP_PLL_SEL_SHIFT |
 533                              (best_div - 1) << DCLK_VOP_DIV_SHIFT);
 534         } else {
 535                 printf("do not support this vop freq\n");
 536                 return -EINVAL;
 537         }
 538
 539         return rk3308_vop_get_clk(clk);
 540 }
 541
 542 static ulong rk3308_bus_get_clk(struct rk3308_clk_priv *priv, ulong clk_id)
 543 {
 544         struct rk3308_cru *cru = priv->cru;
 545         u32 div, con, parent = priv->dpll_hz;
 546
 547         switch (clk_id) {
 548         case ACLK_BUS:
 549                 con = readl(&cru->clksel_con[5]);
 550                 div = (con & BUS_ACLK_DIV_MASK) >> BUS_ACLK_DIV_SHIFT;
 551                 break;
 552         case HCLK_BUS:
 553                 con = readl(&cru->clksel_con[6]);
 554                 div = (con & BUS_HCLK_DIV_MASK) >> BUS_HCLK_DIV_SHIFT;
 555                 break;
 556         case PCLK_BUS:
 557         case PCLK_WDT:
 558                 con = readl(&cru->clksel_con[6]);
 559                 div = (con & BUS_PCLK_DIV_MASK) >> BUS_PCLK_DIV_SHIFT;
 560                 break;
 561         default:
 562                 return -ENOENT;
 563         }
 564
 565         return DIV_TO_RATE(parent, div);
 566 }
 567
 568 static ulong rk3308_bus_set_clk(struct rk3308_clk_priv *priv, ulong clk_id,
 569                                 ulong hz)
 570 {
 571         struct rk3308_cru *cru = priv->cru;
 572         int src_clk_div;
 573
 574         src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz);
 575         assert(src_clk_div - 1 <= 31);
 576
 577         /*
 578          * select dpll as pd_bus bus clock source and
 579          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 580          */
 581         switch (clk_id) {
 582         case ACLK_BUS:
 583                 rk_clrsetreg(&cru->clksel_con[5],
 584                              BUS_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
 585                              BUS_PLL_SEL_DPLL << BUS_PLL_SEL_SHIFT |
 586                              (src_clk_div - 1) << BUS_ACLK_DIV_SHIFT);
 587                 break;
 588         case HCLK_BUS:
 589                 rk_clrsetreg(&cru->clksel_con[6],
 590                              BUS_HCLK_DIV_MASK,
 591                              (src_clk_div - 1) << BUS_HCLK_DIV_SHIFT);
 592                 break;
 593         case PCLK_BUS:
 594                 rk_clrsetreg(&cru->clksel_con[6],
 595                              BUS_PCLK_DIV_MASK,
 596                              (src_clk_div - 1) << BUS_PCLK_DIV_SHIFT);
 597                 break;
 598         default:
 599                 printf("do not support this bus freq\n");
 600                 return -EINVAL;
 601         }
 602
 603         return rk3308_bus_get_clk(priv, clk_id);
 604 }
 605
 606 static ulong rk3308_peri_get_clk(struct rk3308_clk_priv *priv, ulong clk_id)
 607 {
 608         struct rk3308_cru *cru = priv->cru;
 609         u32 div, con, parent = priv->dpll_hz;
 610
 611         switch (clk_id) {
 612         case ACLK_PERI:
 613                 con = readl(&cru->clksel_con[36]);
 614                 div = (con & PERI_ACLK_DIV_MASK) >> PERI_ACLK_DIV_SHIFT;
 615                 break;
 616         case HCLK_PERI:
 617                 con = readl(&cru->clksel_con[37]);
 618                 div = (con & PERI_HCLK_DIV_MASK) >> PERI_HCLK_DIV_SHIFT;
 619                 break;
 620         case PCLK_PERI:
 621                 con = readl(&cru->clksel_con[37]);
 622                 div = (con & PERI_PCLK_DIV_MASK) >> PERI_PCLK_DIV_SHIFT;
 623                 break;
 624         default:
 625                 return -ENOENT;
 626         }
 627
 628         return DIV_TO_RATE(parent, div);
 629 }
 630
 631 static ulong rk3308_peri_set_clk(struct rk3308_clk_priv *priv, ulong clk_id,
 632                                  ulong hz)
 633 {
 634         struct rk3308_cru *cru = priv->cru;
 635         int src_clk_div;
 636
 637         src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz);
 638         assert(src_clk_div - 1 <= 31);
 639
 640         /*
 641          * select dpll as pd_peri bus clock source and
 642          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 643          */
 644         switch (clk_id) {
 645         case ACLK_PERI:
 646                 rk_clrsetreg(&cru->clksel_con[36],
 647                              PERI_PLL_SEL_MASK | PERI_ACLK_DIV_MASK,
 648                              PERI_PLL_DPLL << PERI_PLL_SEL_SHIFT |
 649                              (src_clk_div - 1) << PERI_ACLK_DIV_SHIFT);
 650                 break;
 651         case HCLK_PERI:
 652                 rk_clrsetreg(&cru->clksel_con[37],
 653                              PERI_HCLK_DIV_MASK,
 654                              (src_clk_div - 1) << PERI_HCLK_DIV_SHIFT);
 655                 break;
 656         case PCLK_PERI:
 657                 rk_clrsetreg(&cru->clksel_con[37],
 658                              PERI_PCLK_DIV_MASK,
 659                              (src_clk_div - 1) << PERI_PCLK_DIV_SHIFT);
 660                 break;
 661         default:
 662                 printf("do not support this peri freq\n");
 663                 return -EINVAL;
 664         }
 665
 666         return rk3308_peri_get_clk(priv, clk_id);
 667 }
 668
 669 static ulong rk3308_audio_get_clk(struct rk3308_clk_priv *priv, ulong clk_id)
 670 {
 671         struct rk3308_cru *cru = priv->cru;
 672         u32 div, con, parent = priv->vpll0_hz;
 673
 674         switch (clk_id) {
 675         case HCLK_AUDIO:
 676                 con = readl(&cru->clksel_con[45]);
 677                 div = (con & AUDIO_HCLK_DIV_MASK) >> AUDIO_HCLK_DIV_SHIFT;
 678                 break;
 679         case PCLK_AUDIO:
 680                 con = readl(&cru->clksel_con[45]);
 681                 div = (con & AUDIO_PCLK_DIV_MASK) >> AUDIO_PCLK_DIV_SHIFT;
 682                 break;
 683         default:
 684                 return -ENOENT;
 685         }
 686
 687         return DIV_TO_RATE(parent, div);
 688 }
 689
 690 static ulong rk3308_audio_set_clk(struct rk3308_clk_priv *priv, ulong clk_id,
 691                                   ulong hz)
 692 {
 693         struct rk3308_cru *cru = priv->cru;
 694         int src_clk_div;
 695
 696         src_clk_div = DIV_ROUND_UP(priv->vpll0_hz, hz);
 697         assert(src_clk_div - 1 <= 31);
 698
 699         /*
 700          * select vpll0 as audio bus clock source and
 701          * set up dependent divisors for HCLK and PCLK clocks.
 702          */
 703         switch (clk_id) {
 704         case HCLK_AUDIO:
 705                 rk_clrsetreg(&cru->clksel_con[45],
 706                              AUDIO_PLL_SEL_MASK | AUDIO_HCLK_DIV_MASK,
 707                              AUDIO_PLL_VPLL0 << AUDIO_PLL_SEL_SHIFT |
 708                              (src_clk_div - 1) << AUDIO_HCLK_DIV_SHIFT);
 709                 break;
 710         case PCLK_AUDIO:
 711                 rk_clrsetreg(&cru->clksel_con[45],
 712                              AUDIO_PLL_SEL_MASK | AUDIO_PCLK_DIV_MASK,
 713                              AUDIO_PLL_VPLL0 << AUDIO_PLL_SEL_SHIFT |
 714                              (src_clk_div - 1) << AUDIO_PCLK_DIV_SHIFT);
 715                 break;
 716         default:
 717                 printf("do not support this audio freq\n");
 718                 return -EINVAL;
 719         }
 720
 721         return rk3308_peri_get_clk(priv, clk_id);
 722 }
 723
 724 static ulong rk3308_crypto_get_clk(struct rk3308_clk_priv *priv, ulong clk_id)
 725 {
 726         struct rk3308_cru *cru = priv->cru;
 727         u32 div, con, parent;
 728
 729         switch (clk_id) {
 730         case SCLK_CRYPTO:
 731                 con = readl(&cru->clksel_con[7]);
 732                 div = (con & CRYPTO_DIV_MASK) >> CRYPTO_DIV_SHIFT;
 733                 parent = priv->vpll0_hz;
 734                 break;
 735         case SCLK_CRYPTO_APK:
 736                 con = readl(&cru->clksel_con[7]);
 737                 div = (con & CRYPTO_APK_DIV_MASK) >> CRYPTO_APK_DIV_SHIFT;
 738                 parent = priv->vpll0_hz;
 739                 break;
 740         default:
 741                 return -ENOENT;
 742         }
 743
 744         return DIV_TO_RATE(parent, div);
 745 }
 746
 747 static ulong rk3308_crypto_set_clk(struct rk3308_clk_priv *priv, ulong clk_id,
 748                                    ulong hz)
 749 {
 750         struct rk3308_cru *cru = priv->cru;
 751         int src_clk_div;
 752
 753         src_clk_div = DIV_ROUND_UP(priv->vpll0_hz, hz);
 754         assert(src_clk_div - 1 <= 31);
 755
 756         /*
 757          * select gpll as crypto clock source and
 758          * set up dependent divisors for crypto clocks.
 759          */
 760         switch (clk_id) {
 761         case SCLK_CRYPTO:
 762                 rk_clrsetreg(&cru->clksel_con[7],
 763                              CRYPTO_PLL_SEL_MASK | CRYPTO_DIV_MASK,
 764                              CRYPTO_PLL_SEL_VPLL0 << CRYPTO_PLL_SEL_SHIFT |
 765                              (src_clk_div - 1) << CRYPTO_DIV_SHIFT);
 766                 break;
 767         case SCLK_CRYPTO_APK:
 768                 rk_clrsetreg(&cru->clksel_con[7],
 769                              CRYPTO_APK_PLL_SEL_MASK | CRYPTO_APK_DIV_MASK,
 770                              CRYPTO_PLL_SEL_VPLL0 << CRYPTO_APK_SEL_SHIFT |
 771                              (src_clk_div - 1) << CRYPTO_APK_DIV_SHIFT);
 772                 break;
 773         default:
 774                 printf("do not support this peri freq\n");
 775                 return -EINVAL;
 776         }
 777
 778         return rk3308_crypto_get_clk(priv, clk_id);
 779 }
 780
 781 static ulong rk3308_clk_get_rate(struct clk *clk)
 782 {
 783         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 784         ulong rate = 0;
 785
 786         debug("%s id:%ld\n", __func__, clk->id);
 787
 788         switch (clk->id) {
 789         case PLL_APLL:
 790         case ARMCLK:
 791                 rate = rockchip_pll_get_rate(&rk3308_pll_clks[APLL],
 792                                              priv->cru, APLL);
 793                 break;
 794         case PLL_DPLL:
 795                 rate = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL],
 796                                              priv->cru, DPLL);
 797                 break;
 798         case PLL_VPLL0:
 799                 rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0],
 800                                              priv->cru, VPLL0);
 801                 break;
 802         case PLL_VPLL1:
 803                 rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL1],
 804                                              priv->cru, VPLL1);
 805                 break;
 806         case HCLK_SDMMC:
 807         case HCLK_EMMC:
 808         case SCLK_SDMMC:
 809         case SCLK_EMMC:
 810         case SCLK_EMMC_SAMPLE:
 811                 rate = rk3308_mmc_get_clk(clk);
 812                 break;
 813         case SCLK_I2C0:
 814         case SCLK_I2C1:
 815         case SCLK_I2C2:
 816         case SCLK_I2C3:
 817                 rate = rk3308_i2c_get_clk(clk);
 818                 break;
 819         case SCLK_SARADC:
 820                 rate = rk3308_saradc_get_clk(clk);
 821                 break;
 822         case SCLK_TSADC:
 823                 rate = rk3308_tsadc_get_clk(clk);
 824                 break;
 825         case SCLK_SPI0:
 826         case SCLK_SPI1:
 827                 rate = rk3308_spi_get_clk(clk);
 828                 break;
 829         case SCLK_PWM0:
 830                 rate = rk3308_pwm_get_clk(clk);
 831                 break;
 832         case DCLK_VOP:
 833                 rate = rk3308_vop_get_clk(clk);
 834                 break;
 835         case ACLK_BUS:
 836         case HCLK_BUS:
 837         case PCLK_BUS:
 838         case PCLK_WDT:
 839                 rate = rk3308_bus_get_clk(priv, clk->id);
 840                 break;
 841         case ACLK_PERI:
 842         case HCLK_PERI:
 843         case PCLK_PERI:
 844                 rate = rk3308_peri_get_clk(priv, clk->id);
 845                 break;
 846         case HCLK_AUDIO:
 847         case PCLK_AUDIO:
 848                 rate = rk3308_audio_get_clk(priv, clk->id);
 849                 break;
 850         case SCLK_CRYPTO:
 851         case SCLK_CRYPTO_APK:
 852                 rate = rk3308_crypto_get_clk(priv, clk->id);
 853                 break;
 854         default:
 855                 return -ENOENT;
 856         }
 857
 858         return rate;
 859 }
 860
 861 static ulong rk3308_clk_set_rate(struct clk *clk, ulong rate)
 862 {
 863         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 864         ulong ret = 0;
 865
 866         debug("%s %ld %ld\n", __func__, clk->id, rate);
 867
 868         switch (clk->id) {
 869         case PLL_DPLL:
 870                 ret = rockchip_pll_set_rate(&rk3308_pll_clks[DPLL], priv->cru,
 871                                             DPLL, rate);
 872                 priv->dpll_hz = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL],
 873                                                       priv->cru, DPLL);
 874                 break;
 875         case ARMCLK:
 876                 if (priv->armclk_hz)
 877                         rk3308_armclk_set_clk(priv, rate);
 878                 priv->armclk_hz = rate;
 879                 break;
 880         case HCLK_SDMMC:
 881         case HCLK_EMMC:
 882         case SCLK_SDMMC:
 883         case SCLK_EMMC:
 884                 ret = rk3308_mmc_set_clk(clk, rate);
 885                 break;
 886         case SCLK_I2C0:
 887         case SCLK_I2C1:
 888         case SCLK_I2C2:
 889         case SCLK_I2C3:
 890                 ret = rk3308_i2c_set_clk(clk, rate);
 891                 break;
 892         case SCLK_MAC:
 893                 ret = rk3308_mac_set_clk(clk, rate);
 894                 break;
 895         case SCLK_MAC_RMII:
 896                 ret = rk3308_mac_set_speed_clk(clk, rate);
 897                 break;
 898         case SCLK_SARADC:
 899                 ret = rk3308_saradc_set_clk(clk, rate);
 900                 break;
 901         case SCLK_TSADC:
 902                 ret = rk3308_tsadc_set_clk(clk, rate);
 903                 break;
 904         case SCLK_SPI0:
 905         case SCLK_SPI1:
 906                 ret = rk3308_spi_set_clk(clk, rate);
 907                 break;
 908         case SCLK_PWM0:
 909                 ret = rk3308_pwm_set_clk(clk, rate);
 910                 break;
 911         case DCLK_VOP:
 912                 ret = rk3308_vop_set_clk(clk, rate);
 913                 break;
 914         case ACLK_BUS:
 915         case HCLK_BUS:
 916         case PCLK_BUS:
 917                 rate = rk3308_bus_set_clk(priv, clk->id, rate);
 918                 break;
 919         case ACLK_PERI:
 920         case HCLK_PERI:
 921         case PCLK_PERI:
 922                 rate = rk3308_peri_set_clk(priv, clk->id, rate);
 923                 break;
 924         case HCLK_AUDIO:
 925         case PCLK_AUDIO:
 926                 rate = rk3308_audio_set_clk(priv, clk->id, rate);
 927                 break;
 928         case SCLK_CRYPTO:
 929         case SCLK_CRYPTO_APK:
 930                 ret = rk3308_crypto_set_clk(priv, clk->id, rate);
 931                 break;
 932         default:
 933                 return -ENOENT;
 934         }
 935
 936         return ret;
 937 }
 938
 939 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
 940 static int __maybe_unused rk3308_mac_set_parent(struct clk *clk, struct clk *parent)
 941 {
 942         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 943
 944         /*
 945          * If the requested parent is in the same clock-controller and
 946          * the id is SCLK_MAC_SRC, switch to the internal clock.
 947          */
 948         if (parent->id == SCLK_MAC_SRC) {
 949                 debug("%s: switching RMII to SCLK_MAC\n", __func__);
 950                 rk_clrreg(&priv->cru->clksel_con[43], BIT(14));
 951         } else {
 952                 debug("%s: switching RMII to CLKIN\n", __func__);
 953                 rk_setreg(&priv->cru->clksel_con[43], BIT(14));
 954         }
 955
 956         return 0;
 957 }
 958
 959 static int __maybe_unused rk3308_clk_set_parent(struct clk *clk, struct clk *parent)
 960 {
 961         switch (clk->id) {
 962         case SCLK_MAC:
 963                 return rk3308_mac_set_parent(clk, parent);
 964         default:
 965                 break;
 966         }
 967
 968         debug("%s: unsupported clk %ld\n", __func__, clk->id);
 969         return -ENOENT;
 970 }
 971 #endif
 972
 973 static struct clk_ops rk3308_clk_ops = {
 974         .get_rate = rk3308_clk_get_rate,
 975         .set_rate = rk3308_clk_set_rate,
 976 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
 977         .set_parent = rk3308_clk_set_parent,
 978 #endif
 979 };
 980
 981 static void rk3308_clk_init(struct udevice *dev)
 982 {
 983         struct rk3308_clk_priv *priv = dev_get_priv(dev);
 984         int ret;
 985
 986         if (rockchip_pll_get_rate(&rk3308_pll_clks[APLL],
 987                                   priv->cru, APLL) != APLL_HZ) {
 988                 ret = rk3308_armclk_set_clk(priv, APLL_HZ);
 989                 if (ret < 0)
 990                         printf("%s failed to set armclk rate\n", __func__);
 991         }
 992
 993         rk3308_clk_get_pll_rate(priv);
 994
 995         rk3308_bus_set_clk(priv, ACLK_BUS, BUS_ACLK_HZ);
 996         rk3308_bus_set_clk(priv, HCLK_BUS, BUS_HCLK_HZ);
 997         rk3308_bus_set_clk(priv, PCLK_BUS, BUS_PCLK_HZ);
 998
 999         rk3308_peri_set_clk(priv, ACLK_PERI, PERI_ACLK_HZ);
1000         rk3308_peri_set_clk(priv, HCLK_PERI, PERI_HCLK_HZ);
1001         rk3308_peri_set_clk(priv, PCLK_PERI, PERI_PCLK_HZ);
1002
1003         rk3308_audio_set_clk(priv, HCLK_AUDIO, AUDIO_HCLK_HZ);
1004         rk3308_audio_set_clk(priv, PCLK_AUDIO, AUDIO_PCLK_HZ);
1005 }
1006
1007 static int rk3308_clk_probe(struct udevice *dev)
1008 {
1009         int ret;
1010
1011         rk3308_clk_init(dev);
1012
1013         /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
1014         ret = clk_set_defaults(dev, 1);
1015         if (ret)
1016                 debug("%s clk_set_defaults failed %d\n", __func__, ret);
1017
1018         return ret;
1019 }
1020
1021 static int rk3308_clk_ofdata_to_platdata(struct udevice *dev)
1022 {
1023         struct rk3308_clk_priv *priv = dev_get_priv(dev);
1024
1025         priv->cru = dev_read_addr_ptr(dev);
1026
1027         return 0;
1028 }
1029
1030 static int rk3308_clk_bind(struct udevice *dev)
1031 {
1032         int ret;
1033         struct udevice *sys_child;
1034         struct sysreset_reg *priv;
1035
1036         /* The reset driver does not have a device node, so bind it here */
1037         ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
1038                                  &sys_child);
1039         if (ret) {
1040                 debug("Warning: No sysreset driver: ret=%d\n", ret);
1041         } else {
1042                 priv = malloc(sizeof(struct sysreset_reg));
1043                 priv->glb_srst_fst_value = offsetof(struct rk3308_cru,
1044                                                     glb_srst_fst);
1045                 priv->glb_srst_snd_value = offsetof(struct rk3308_cru,
1046                                                     glb_srst_snd);
1047                 sys_child->priv = priv;
1048         }
1049
1050 #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
1051         ret = offsetof(struct rk3308_cru, softrst_con[0]);
1052         ret = rockchip_reset_bind(dev, ret, 12);
1053         if (ret)
1054                 debug("Warning: software reset driver bind faile\n");
1055 #endif
1056
1057         return 0;
1058 }
1059
1060 static const struct udevice_id rk3308_clk_ids[] = {
1061         { .compatible = "rockchip,rk3308-cru" },
1062         { }
1063 };
1064
1065 U_BOOT_DRIVER(rockchip_rk3308_cru) = {
1066         .name           = "rockchip_rk3308_cru",
1067         .id             = UCLASS_CLK,
1068         .of_match       = rk3308_clk_ids,
1069         .priv_auto_alloc_size = sizeof(struct rk3308_clk_priv),
1070         .ofdata_to_platdata = rk3308_clk_ofdata_to_platdata,
1071         .ops            = &rk3308_clk_ops,
1072         .bind           = rk3308_clk_bind,
1073         .probe          = rk3308_clk_probe,
1074 };