drivers/clk/rockchip/clk_rk3288.c

   1 /*
   2  * (C) Copyright 2015 Google, Inc
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0
   5  */
   6
   7 #include <common.h>
   8 #include <clk-uclass.h>
   9 #include <dm.h>
  10 #include <dt-structs.h>
  11 #include <errno.h>
  12 #include <mapmem.h>
  13 #include <syscon.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/cru_rk3288.h>
  17 #include <asm/arch/grf_rk3288.h>
  18 #include <asm/arch/hardware.h>
  19 #include <dt-bindings/clock/rk3288-cru.h>
  20 #include <dm/device-internal.h>
  21 #include <dm/lists.h>
  22 #include <dm/uclass-internal.h>
  23 #include <linux/log2.h>
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 struct rk3288_clk_plat {
  28 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  29         struct dtd_rockchip_rk3288_cru dtd;
  30 #endif
  31 };
  32
  33 struct rk3288_clk_priv {
  34         struct rk3288_grf *grf;
  35         struct rk3288_cru *cru;
  36         ulong rate;
  37 };
  38
  39 struct pll_div {
  40         u32 nr;
  41         u32 nf;
  42         u32 no;
  43 };
  44
  45 enum {
  46         VCO_MAX_HZ      = 2200U * 1000000,
  47         VCO_MIN_HZ      = 440 * 1000000,
  48         OUTPUT_MAX_HZ   = 2200U * 1000000,
  49         OUTPUT_MIN_HZ   = 27500000,
  50         FREF_MAX_HZ     = 2200U * 1000000,
  51         FREF_MIN_HZ     = 269 * 1000,
  52 };
  53
  54 enum {
  55         /* PLL CON0 */
  56         PLL_OD_MASK             = 0x0f,
  57
  58         /* PLL CON1 */
  59         PLL_NF_MASK             = 0x1fff,
  60
  61         /* PLL CON2 */
  62         PLL_BWADJ_MASK          = 0x0fff,
  63
  64         /* PLL CON3 */
  65         PLL_RESET_SHIFT         = 5,
  66
  67         /* CLKSEL0 */
  68         CORE_SEL_PLL_MASK       = 1,
  69         CORE_SEL_PLL_SHIFT      = 15,
  70         A17_DIV_MASK            = 0x1f,
  71         A17_DIV_SHIFT           = 8,
  72         MP_DIV_MASK             = 0xf,
  73         MP_DIV_SHIFT            = 4,
  74         M0_DIV_MASK             = 0xf,
  75         M0_DIV_SHIFT            = 0,
  76
  77         /* CLKSEL1: pd bus clk pll sel: codec or general */
  78         PD_BUS_SEL_PLL_MASK     = 15,
  79         PD_BUS_SEL_CPLL         = 0,
  80         PD_BUS_SEL_GPLL,
  81
  82         /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */
  83         PD_BUS_PCLK_DIV_SHIFT   = 12,
  84         PD_BUS_PCLK_DIV_MASK    = 7,
  85
  86         /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
  87         PD_BUS_HCLK_DIV_SHIFT   = 8,
  88         PD_BUS_HCLK_DIV_MASK    = 3,
  89
  90         /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */
  91         PD_BUS_ACLK_DIV0_SHIFT  = 3,
  92         PD_BUS_ACLK_DIV0_MASK   = 0x1f,
  93         PD_BUS_ACLK_DIV1_SHIFT  = 0,
  94         PD_BUS_ACLK_DIV1_MASK   = 0x7,
  95
  96         /*
  97          * CLKSEL10
  98          * peripheral bus pclk div:
  99          * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1
 100          */
 101         PERI_SEL_PLL_MASK        = 1,
 102         PERI_SEL_PLL_SHIFT       = 15,
 103         PERI_SEL_CPLL           = 0,
 104         PERI_SEL_GPLL,
 105
 106         PERI_PCLK_DIV_SHIFT     = 12,
 107         PERI_PCLK_DIV_MASK      = 3,
 108
 109         /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
 110         PERI_HCLK_DIV_SHIFT     = 8,
 111         PERI_HCLK_DIV_MASK      = 3,
 112
 113         /*
 114          * peripheral bus aclk div:
 115          *    aclk_periph = periph_clk_src / (peri_aclk_div_con + 1)
 116          */
 117         PERI_ACLK_DIV_SHIFT     = 0,
 118         PERI_ACLK_DIV_MASK      = 0x1f,
 119
 120         SOCSTS_DPLL_LOCK        = 1 << 5,
 121         SOCSTS_APLL_LOCK        = 1 << 6,
 122         SOCSTS_CPLL_LOCK        = 1 << 7,
 123         SOCSTS_GPLL_LOCK        = 1 << 8,
 124         SOCSTS_NPLL_LOCK        = 1 << 9,
 125 };
 126
 127 #define RATE_TO_DIV(input_rate, output_rate) \
 128         ((input_rate) / (output_rate) - 1);
 129
 130 #define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))
 131
 132 #define PLL_DIVISORS(hz, _nr, _no) {\
 133         .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
 134         _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
 135                        (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
 136                        "divisors on line " __stringify(__LINE__));
 137
 138 /* Keep divisors as low as possible to reduce jitter and power usage */
 139 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
 140 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
 141 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
 142
 143 void *rockchip_get_cru(void)
 144 {
 145         struct rk3288_clk_priv *priv;
 146         struct udevice *dev;
 147         int ret;
 148
 149         ret = rockchip_get_clk(&dev);
 150         if (ret)
 151                 return ERR_PTR(ret);
 152
 153         priv = dev_get_priv(dev);
 154
 155         return priv->cru;
 156 }
 157
 158 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
 159                          const struct pll_div *div)
 160 {
 161         int pll_id = rk_pll_id(clk_id);
 162         struct rk3288_pll *pll = &cru->pll[pll_id];
 163         /* All PLLs have same VCO and output frequency range restrictions. */
 164         uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
 165         uint output_hz = vco_hz / div->no;
 166
 167         debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
 168               (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
 169         assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
 170                output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
 171                (div->no == 1 || !(div->no % 2)));
 172
 173         /* enter reset */
 174         rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
 175
 176         rk_clrsetreg(&pll->con0,
 177                      CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK,
 178                      ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
 179         rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
 180         rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
 181
 182         udelay(10);
 183
 184         /* return from reset */
 185         rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
 186
 187         return 0;
 188 }
 189
 190 static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf,
 191                                unsigned int hz)
 192 {
 193         static const struct pll_div dpll_cfg[] = {
 194                 {.nf = 25, .nr = 2, .no = 1},
 195                 {.nf = 400, .nr = 9, .no = 2},
 196                 {.nf = 500, .nr = 9, .no = 2},
 197                 {.nf = 100, .nr = 3, .no = 1},
 198         };
 199         int cfg;
 200
 201         switch (hz) {
 202         case 300000000:
 203                 cfg = 0;
 204                 break;
 205         case 533000000: /* actually 533.3P MHz */
 206                 cfg = 1;
 207                 break;
 208         case 666000000: /* actually 666.6P MHz */
 209                 cfg = 2;
 210                 break;
 211         case 800000000:
 212                 cfg = 3;
 213                 break;
 214         default:
 215                 debug("Unsupported SDRAM frequency");
 216                 return -EINVAL;
 217         }
 218
 219         /* pll enter slow-mode */
 220         rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
 221                      DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
 222
 223         rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);
 224
 225         /* wait for pll lock */
 226         while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK))
 227                 udelay(1);
 228
 229         /* PLL enter normal-mode */
 230         rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
 231                      DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
 232
 233         return 0;
 234 }
 235
 236 #ifndef CONFIG_SPL_BUILD
 237 #define VCO_MAX_KHZ     2200000
 238 #define VCO_MIN_KHZ     440000
 239 #define FREF_MAX_KHZ    2200000
 240 #define FREF_MIN_KHZ    269
 241
 242 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
 243 {
 244         uint ref_khz = OSC_HZ / 1000, nr, nf = 0;
 245         uint fref_khz;
 246         uint diff_khz, best_diff_khz;
 247         const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4;
 248         uint vco_khz;
 249         uint no = 1;
 250         uint freq_khz = freq_hz / 1000;
 251
 252         if (!freq_hz) {
 253                 printf("%s: the frequency can not be 0 Hz\n", __func__);
 254                 return -EINVAL;
 255         }
 256
 257         no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
 258         if (ext_div) {
 259                 *ext_div = DIV_ROUND_UP(no, max_no);
 260                 no = DIV_ROUND_UP(no, *ext_div);
 261         }
 262
 263         /* only even divisors (and 1) are supported */
 264         if (no > 1)
 265                 no = DIV_ROUND_UP(no, 2) * 2;
 266
 267         vco_khz = freq_khz * no;
 268         if (ext_div)
 269                 vco_khz *= *ext_div;
 270
 271         if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) {
 272                 printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n",
 273                        __func__, freq_hz);
 274                 return -1;
 275         }
 276
 277         div->no = no;
 278
 279         best_diff_khz = vco_khz;
 280         for (nr = 1; nr < max_nr && best_diff_khz; nr++) {
 281                 fref_khz = ref_khz / nr;
 282                 if (fref_khz < FREF_MIN_KHZ)
 283                         break;
 284                 if (fref_khz > FREF_MAX_KHZ)
 285                         continue;
 286
 287                 nf = vco_khz / fref_khz;
 288                 if (nf >= max_nf)
 289                         continue;
 290                 diff_khz = vco_khz - nf * fref_khz;
 291                 if (nf + 1 < max_nf && diff_khz > fref_khz / 2) {
 292                         nf++;
 293                         diff_khz = fref_khz - diff_khz;
 294                 }
 295
 296                 if (diff_khz >= best_diff_khz)
 297                         continue;
 298
 299                 best_diff_khz = diff_khz;
 300                 div->nr = nr;
 301                 div->nf = nf;
 302         }
 303
 304         if (best_diff_khz > 4 * 1000) {
 305                 printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n",
 306                        __func__, freq_hz, best_diff_khz * 1000);
 307                 return -EINVAL;
 308         }
 309
 310         return 0;
 311 }
 312
 313 static int rockchip_mac_set_clk(struct rk3288_cru *cru,
 314                                   int periph, uint freq)
 315 {
 316         /* Assuming mac_clk is fed by an external clock */
 317         rk_clrsetreg(&cru->cru_clksel_con[21],
 318                      RMII_EXTCLK_MASK << RMII_EXTCLK_SHIFT,
 319                      RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT);
 320
 321          return 0;
 322 }
 323
 324 static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
 325                                 int periph, unsigned int rate_hz)
 326 {
 327         struct pll_div npll_config = {0};
 328         u32 lcdc_div;
 329         int ret;
 330
 331         ret = pll_para_config(rate_hz, &npll_config, &lcdc_div);
 332         if (ret)
 333                 return ret;
 334
 335         rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT,
 336                      NPLL_MODE_SLOW << NPLL_MODE_SHIFT);
 337         rkclk_set_pll(cru, CLK_NEW, &npll_config);
 338
 339         /* waiting for pll lock */
 340         while (1) {
 341                 if (readl(&grf->soc_status[1]) & SOCSTS_NPLL_LOCK)
 342                         break;
 343                 udelay(1);
 344         }
 345
 346         rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT,
 347                      NPLL_MODE_NORMAL << NPLL_MODE_SHIFT);
 348
 349         /* vop dclk source clk: npll,dclk_div: 1 */
 350         switch (periph) {
 351         case DCLK_VOP0:
 352                 rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0,
 353                              (lcdc_div - 1) << 8 | 2 << 0);
 354                 break;
 355         case DCLK_VOP1:
 356                 rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6,
 357                              (lcdc_div - 1) << 8 | 2 << 6);
 358                 break;
 359         }
 360
 361         return 0;
 362 }
 363 #endif
 364
 365 #ifdef CONFIG_SPL_BUILD
 366 static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
 367 {
 368         u32 aclk_div;
 369         u32 hclk_div;
 370         u32 pclk_div;
 371
 372         /* pll enter slow-mode */
 373         rk_clrsetreg(&cru->cru_mode_con,
 374                      GPLL_MODE_MASK << GPLL_MODE_SHIFT |
 375                      CPLL_MODE_MASK << CPLL_MODE_SHIFT,
 376                      GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
 377                      CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
 378
 379         /* init pll */
 380         rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
 381         rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
 382
 383         /* waiting for pll lock */
 384         while ((readl(&grf->soc_status[1]) &
 385                         (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
 386                         (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
 387                 udelay(1);
 388
 389         /*
 390          * pd_bus clock pll source selection and
 391          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 392          */
 393         aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1;
 394         assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
 395         hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1;
 396         assert((hclk_div + 1) * PD_BUS_HCLK_HZ ==
 397                 PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2));
 398
 399         pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1;
 400         assert((pclk_div + 1) * PD_BUS_PCLK_HZ ==
 401                 PD_BUS_ACLK_HZ && pclk_div < 0x7);
 402
 403         rk_clrsetreg(&cru->cru_clksel_con[1],
 404                      PD_BUS_PCLK_DIV_MASK << PD_BUS_PCLK_DIV_SHIFT |
 405                      PD_BUS_HCLK_DIV_MASK << PD_BUS_HCLK_DIV_SHIFT |
 406                      PD_BUS_ACLK_DIV0_MASK << PD_BUS_ACLK_DIV0_SHIFT |
 407                      PD_BUS_ACLK_DIV1_MASK << PD_BUS_ACLK_DIV1_SHIFT,
 408                      pclk_div << PD_BUS_PCLK_DIV_SHIFT |
 409                      hclk_div << PD_BUS_HCLK_DIV_SHIFT |
 410                      aclk_div << PD_BUS_ACLK_DIV0_SHIFT |
 411                      0 << 0);
 412
 413         /*
 414          * peri clock pll source selection and
 415          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 416          */
 417         aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
 418         assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
 419
 420         hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
 421         assert((1 << hclk_div) * PERI_HCLK_HZ ==
 422                 PERI_ACLK_HZ && (hclk_div < 0x4));
 423
 424         pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
 425         assert((1 << pclk_div) * PERI_PCLK_HZ ==
 426                 PERI_ACLK_HZ && (pclk_div < 0x4));
 427
 428         rk_clrsetreg(&cru->cru_clksel_con[10],
 429                      PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT |
 430                      PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT |
 431                      PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT,
 432                      PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
 433                      pclk_div << PERI_PCLK_DIV_SHIFT |
 434                      hclk_div << PERI_HCLK_DIV_SHIFT |
 435                      aclk_div << PERI_ACLK_DIV_SHIFT);
 436
 437         /* PLL enter normal-mode */
 438         rk_clrsetreg(&cru->cru_mode_con,
 439                      GPLL_MODE_MASK << GPLL_MODE_SHIFT |
 440                      CPLL_MODE_MASK << CPLL_MODE_SHIFT,
 441                      GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
 442                      CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
 443 }
 444 #endif
 445
 446 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
 447 {
 448         /* pll enter slow-mode */
 449         rk_clrsetreg(&cru->cru_mode_con,
 450                      APLL_MODE_MASK << APLL_MODE_SHIFT,
 451                      APLL_MODE_SLOW << APLL_MODE_SHIFT);
 452
 453         rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
 454
 455         /* waiting for pll lock */
 456         while (!(readl(&grf->soc_status[1]) & SOCSTS_APLL_LOCK))
 457                 udelay(1);
 458
 459         /*
 460          * core clock pll source selection and
 461          * set up dependent divisors for MPAXI/M0AXI and ARM clocks.
 462          * core clock select apll, apll clk = 1800MHz
 463          * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz
 464          */
 465         rk_clrsetreg(&cru->cru_clksel_con[0],
 466                      CORE_SEL_PLL_MASK << CORE_SEL_PLL_SHIFT |
 467                      A17_DIV_MASK << A17_DIV_SHIFT |
 468                      MP_DIV_MASK << MP_DIV_SHIFT |
 469                      M0_DIV_MASK << M0_DIV_SHIFT,
 470                      0 << A17_DIV_SHIFT |
 471                      3 << MP_DIV_SHIFT |
 472                      1 << M0_DIV_SHIFT);
 473
 474         /*
 475          * set up dependent divisors for L2RAM/ATCLK and PCLK clocks.
 476          * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz
 477          */
 478         rk_clrsetreg(&cru->cru_clksel_con[37],
 479                      CLK_L2RAM_DIV_MASK << CLK_L2RAM_DIV_SHIFT |
 480                      ATCLK_CORE_DIV_CON_MASK << ATCLK_CORE_DIV_CON_SHIFT |
 481                      PCLK_CORE_DBG_DIV_MASK >> PCLK_CORE_DBG_DIV_SHIFT,
 482                      1 << CLK_L2RAM_DIV_SHIFT |
 483                      3 << ATCLK_CORE_DIV_CON_SHIFT |
 484                      3 << PCLK_CORE_DBG_DIV_SHIFT);
 485
 486         /* PLL enter normal-mode */
 487         rk_clrsetreg(&cru->cru_mode_con,
 488                      APLL_MODE_MASK << APLL_MODE_SHIFT,
 489                      APLL_MODE_NORMAL << APLL_MODE_SHIFT);
 490 }
 491
 492 /* Get pll rate by id */
 493 static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
 494                                    enum rk_clk_id clk_id)
 495 {
 496         uint32_t nr, no, nf;
 497         uint32_t con;
 498         int pll_id = rk_pll_id(clk_id);
 499         struct rk3288_pll *pll = &cru->pll[pll_id];
 500         static u8 clk_shift[CLK_COUNT] = {
 501                 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
 502                 GPLL_MODE_SHIFT, NPLL_MODE_SHIFT
 503         };
 504         uint shift;
 505
 506         con = readl(&cru->cru_mode_con);
 507         shift = clk_shift[clk_id];
 508         switch ((con >> shift) & APLL_MODE_MASK) {
 509         case APLL_MODE_SLOW:
 510                 return OSC_HZ;
 511         case APLL_MODE_NORMAL:
 512                 /* normal mode */
 513                 con = readl(&pll->con0);
 514                 no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1;
 515                 nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1;
 516                 con = readl(&pll->con1);
 517                 nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1;
 518
 519                 return (24 * nf / (nr * no)) * 1000000;
 520         case APLL_MODE_DEEP:
 521         default:
 522                 return 32768;
 523         }
 524 }
 525
 526 static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
 527                                   int periph)
 528 {
 529         uint src_rate;
 530         uint div, mux;
 531         u32 con;
 532
 533         switch (periph) {
 534         case HCLK_EMMC:
 535                 con = readl(&cru->cru_clksel_con[12]);
 536                 mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK;
 537                 div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
 538                 break;
 539         case HCLK_SDMMC:
 540                 con = readl(&cru->cru_clksel_con[11]);
 541                 mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK;
 542                 div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
 543                 break;
 544         case HCLK_SDIO0:
 545                 con = readl(&cru->cru_clksel_con[12]);
 546                 mux = (con >> SDIO0_PLL_SHIFT) & SDIO0_PLL_MASK;
 547                 div = (con >> SDIO0_DIV_SHIFT) & SDIO0_DIV_MASK;
 548                 break;
 549         default:
 550                 return -EINVAL;
 551         }
 552
 553         src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate;
 554         return DIV_TO_RATE(src_rate, div);
 555 }
 556
 557 static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
 558                                   int  periph, uint freq)
 559 {
 560         int src_clk_div;
 561         int mux;
 562
 563         debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
 564         src_clk_div = RATE_TO_DIV(gclk_rate, freq);
 565
 566         if (src_clk_div > 0x3f) {
 567                 src_clk_div = RATE_TO_DIV(OSC_HZ, freq);
 568                 mux = EMMC_PLL_SELECT_24MHZ;
 569                 assert((int)EMMC_PLL_SELECT_24MHZ ==
 570                        (int)MMC0_PLL_SELECT_24MHZ);
 571         } else {
 572                 mux = EMMC_PLL_SELECT_GENERAL;
 573                 assert((int)EMMC_PLL_SELECT_GENERAL ==
 574                        (int)MMC0_PLL_SELECT_GENERAL);
 575         }
 576         switch (periph) {
 577         case HCLK_EMMC:
 578                 rk_clrsetreg(&cru->cru_clksel_con[12],
 579                              EMMC_PLL_MASK << EMMC_PLL_SHIFT |
 580                              EMMC_DIV_MASK << EMMC_DIV_SHIFT,
 581                              mux << EMMC_PLL_SHIFT |
 582                              (src_clk_div - 1) << EMMC_DIV_SHIFT);
 583                 break;
 584         case HCLK_SDMMC:
 585                 rk_clrsetreg(&cru->cru_clksel_con[11],
 586                              MMC0_PLL_MASK << MMC0_PLL_SHIFT |
 587                              MMC0_DIV_MASK << MMC0_DIV_SHIFT,
 588                              mux << MMC0_PLL_SHIFT |
 589                              (src_clk_div - 1) << MMC0_DIV_SHIFT);
 590                 break;
 591         case HCLK_SDIO0:
 592                 rk_clrsetreg(&cru->cru_clksel_con[12],
 593                              SDIO0_PLL_MASK << SDIO0_PLL_SHIFT |
 594                              SDIO0_DIV_MASK << SDIO0_DIV_SHIFT,
 595                              mux << SDIO0_PLL_SHIFT |
 596                              (src_clk_div - 1) << SDIO0_DIV_SHIFT);
 597                 break;
 598         default:
 599                 return -EINVAL;
 600         }
 601
 602         return rockchip_mmc_get_clk(cru, gclk_rate, periph);
 603 }
 604
 605 static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
 606                                   int periph)
 607 {
 608         uint div, mux;
 609         u32 con;
 610
 611         switch (periph) {
 612         case SCLK_SPI0:
 613                 con = readl(&cru->cru_clksel_con[25]);
 614                 mux = (con >> SPI0_PLL_SHIFT) & SPI0_PLL_MASK;
 615                 div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK;
 616                 break;
 617         case SCLK_SPI1:
 618                 con = readl(&cru->cru_clksel_con[25]);
 619                 mux = (con >> SPI1_PLL_SHIFT) & SPI1_PLL_MASK;
 620                 div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK;
 621                 break;
 622         case SCLK_SPI2:
 623                 con = readl(&cru->cru_clksel_con[39]);
 624                 mux = (con >> SPI2_PLL_SHIFT) & SPI2_PLL_MASK;
 625                 div = (con >> SPI2_DIV_SHIFT) & SPI2_DIV_MASK;
 626                 break;
 627         default:
 628                 return -EINVAL;
 629         }
 630         assert(mux == SPI0_PLL_SELECT_GENERAL);
 631
 632         return DIV_TO_RATE(gclk_rate, div);
 633 }
 634
 635 static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
 636                                   int periph, uint freq)
 637 {
 638         int src_clk_div;
 639
 640         debug("%s: clk_general_rate=%u\n", __func__, gclk_rate);
 641         src_clk_div = RATE_TO_DIV(gclk_rate, freq);
 642         switch (periph) {
 643         case SCLK_SPI0:
 644                 rk_clrsetreg(&cru->cru_clksel_con[25],
 645                              SPI0_PLL_MASK << SPI0_PLL_SHIFT |
 646                              SPI0_DIV_MASK << SPI0_DIV_SHIFT,
 647                              SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT |
 648                              src_clk_div << SPI0_DIV_SHIFT);
 649                 break;
 650         case SCLK_SPI1:
 651                 rk_clrsetreg(&cru->cru_clksel_con[25],
 652                              SPI1_PLL_MASK << SPI1_PLL_SHIFT |
 653                              SPI1_DIV_MASK << SPI1_DIV_SHIFT,
 654                              SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT |
 655                              src_clk_div << SPI1_DIV_SHIFT);
 656                 break;
 657         case SCLK_SPI2:
 658                 rk_clrsetreg(&cru->cru_clksel_con[39],
 659                              SPI2_PLL_MASK << SPI2_PLL_SHIFT |
 660                              SPI2_DIV_MASK << SPI2_DIV_SHIFT,
 661                              SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT |
 662                              src_clk_div << SPI2_DIV_SHIFT);
 663                 break;
 664         default:
 665                 return -EINVAL;
 666         }
 667
 668         return rockchip_spi_get_clk(cru, gclk_rate, periph);
 669 }
 670
 671 static ulong rk3288_clk_get_rate(struct clk *clk)
 672 {
 673         struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
 674         ulong new_rate, gclk_rate;
 675
 676         gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
 677         switch (clk->id) {
 678         case 0 ... 63:
 679                 new_rate = rkclk_pll_get_rate(priv->cru, clk->id);
 680                 break;
 681         case HCLK_EMMC:
 682         case HCLK_SDMMC:
 683         case HCLK_SDIO0:
 684                 new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
 685                 break;
 686         case SCLK_SPI0:
 687         case SCLK_SPI1:
 688         case SCLK_SPI2:
 689                 new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id);
 690                 break;
 691         case PCLK_I2C0:
 692         case PCLK_I2C1:
 693         case PCLK_I2C2:
 694         case PCLK_I2C3:
 695         case PCLK_I2C4:
 696         case PCLK_I2C5:
 697                 return gclk_rate;
 698         default:
 699                 return -ENOENT;
 700         }
 701
 702         return new_rate;
 703 }
 704
 705 static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
 706 {
 707         struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
 708         struct rk3288_cru *cru = priv->cru;
 709         ulong new_rate, gclk_rate;
 710
 711         gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
 712         switch (clk->id) {
 713         case CLK_DDR:
 714                 new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate);
 715                 break;
 716         case HCLK_EMMC:
 717         case HCLK_SDMMC:
 718         case HCLK_SDIO0:
 719                 new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate);
 720                 break;
 721         case SCLK_SPI0:
 722         case SCLK_SPI1:
 723         case SCLK_SPI2:
 724                 new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate);
 725                 break;
 726 #ifndef CONFIG_SPL_BUILD
 727         case SCLK_MAC:
 728                 new_rate = rockchip_mac_set_clk(priv->cru, clk->id, rate);
 729                 break;
 730         case DCLK_VOP0:
 731         case DCLK_VOP1:
 732                 new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate);
 733                 break;
 734         case SCLK_EDP_24M:
 735                 /* clk_edp_24M source: 24M */
 736                 rk_setreg(&cru->cru_clksel_con[28], 1 << 15);
 737
 738                 /* rst edp */
 739                 rk_setreg(&cru->cru_clksel_con[6], 1 << 15);
 740                 udelay(1);
 741                 rk_clrreg(&cru->cru_clksel_con[6], 1 << 15);
 742                 new_rate = rate;
 743                 break;
 744         case ACLK_VOP0:
 745         case ACLK_VOP1: {
 746                 u32 div;
 747
 748                 /* vop aclk source clk: cpll */
 749                 div = CPLL_HZ / rate;
 750                 assert((div - 1 < 64) && (div * rate == CPLL_HZ));
 751
 752                 switch (clk->id) {
 753                 case ACLK_VOP0:
 754                         rk_clrsetreg(&cru->cru_clksel_con[31],
 755                                      3 << 6 | 0x1f << 0,
 756                                      0 << 6 | (div - 1) << 0);
 757                         break;
 758                 case ACLK_VOP1:
 759                         rk_clrsetreg(&cru->cru_clksel_con[31],
 760                                      3 << 14 | 0x1f << 8,
 761                                      0 << 14 | (div - 1) << 8);
 762                         break;
 763                 }
 764                 new_rate = rate;
 765                 break;
 766         }
 767         case PCLK_HDMI_CTRL:
 768                 /* enable pclk hdmi ctrl */
 769                 rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9);
 770
 771                 /* software reset hdmi */
 772                 rk_setreg(&cru->cru_clkgate_con[7], 1 << 9);
 773                 udelay(1);
 774                 rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9);
 775                 new_rate = rate;
 776                 break;
 777 #endif
 778         default:
 779                 return -ENOENT;
 780         }
 781
 782         return new_rate;
 783 }
 784
 785 static struct clk_ops rk3288_clk_ops = {
 786         .get_rate       = rk3288_clk_get_rate,
 787         .set_rate       = rk3288_clk_set_rate,
 788 };
 789
 790 static int rk3288_clk_ofdata_to_platdata(struct udevice *dev)
 791 {
 792 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 793         struct rk3288_clk_priv *priv = dev_get_priv(dev);
 794
 795         priv->cru = (struct rk3288_cru *)dev_get_addr(dev);
 796 #endif
 797
 798         return 0;
 799 }
 800
 801 static int rk3288_clk_probe(struct udevice *dev)
 802 {
 803         struct rk3288_clk_priv *priv = dev_get_priv(dev);
 804
 805         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 806         if (IS_ERR(priv->grf))
 807                 return PTR_ERR(priv->grf);
 808 #ifdef CONFIG_SPL_BUILD
 809 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 810         struct rk3288_clk_plat *plat = dev_get_platdata(dev);
 811
 812         priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
 813 #endif
 814         rkclk_init(priv->cru, priv->grf);
 815 #endif
 816
 817         return 0;
 818 }
 819
 820 static int rk3288_clk_bind(struct udevice *dev)
 821 {
 822         int ret;
 823
 824         /* The reset driver does not have a device node, so bind it here */
 825         ret = device_bind_driver(gd->dm_root, "rk3288_sysreset", "reset", &dev);
 826         if (ret)
 827                 debug("Warning: No RK3288 reset driver: ret=%d\n", ret);
 828
 829         return 0;
 830 }
 831
 832 static const struct udevice_id rk3288_clk_ids[] = {
 833         { .compatible = "rockchip,rk3288-cru" },
 834         { }
 835 };
 836
 837 U_BOOT_DRIVER(rockchip_rk3288_cru) = {
 838         .name           = "rockchip_rk3288_cru",
 839         .id             = UCLASS_CLK,
 840         .of_match       = rk3288_clk_ids,
 841         .priv_auto_alloc_size = sizeof(struct rk3288_clk_priv),
 842         .platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat),
 843         .ops            = &rk3288_clk_ops,
 844         .bind           = rk3288_clk_bind,
 845         .ofdata_to_platdata     = rk3288_clk_ofdata_to_platdata,
 846         .probe          = rk3288_clk_probe,
 847 };