drivers/clk/rockchip/clk_rk3288.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * (C) Copyright 2015 Google, Inc
   4  */
   5
   6 #include <common.h>
   7 #include <bitfield.h>
   8 #include <clk-uclass.h>
   9 #include <div64.h>
  10 #include <dm.h>
  11 #include <dt-structs.h>
  12 #include <errno.h>
  13 #include <log.h>
  14 #include <malloc.h>
  15 #include <mapmem.h>
  16 #include <syscon.h>
  17 #include <asm/global_data.h>
  18 #include <asm/io.h>
  19 #include <asm/arch-rockchip/clock.h>
  20 #include <asm/arch-rockchip/cru.h>
  21 #include <asm/arch-rockchip/grf_rk3288.h>
  22 #include <asm/arch-rockchip/hardware.h>
  23 #include <dt-bindings/clock/rk3288-cru.h>
  24 #include <dm/device-internal.h>
  25 #include <dm/lists.h>
  26 #include <dm/uclass-internal.h>
  27 #include <linux/bitops.h>
  28 #include <linux/delay.h>
  29 #include <linux/err.h>
  30 #include <linux/log2.h>
  31 #include <linux/stringify.h>
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 struct rk3288_clk_plat {
  36 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  37         struct dtd_rockchip_rk3288_cru dtd;
  38 #endif
  39 };
  40
  41 struct pll_div {
  42         u32 nr;
  43         u32 nf;
  44         u32 no;
  45 };
  46
  47 enum {
  48         VCO_MAX_HZ      = 2200U * 1000000,
  49         VCO_MIN_HZ      = 440 * 1000000,
  50         OUTPUT_MAX_HZ   = 2200U * 1000000,
  51         OUTPUT_MIN_HZ   = 27500000,
  52         FREF_MAX_HZ     = 2200U * 1000000,
  53         FREF_MIN_HZ     = 269 * 1000,
  54 };
  55
  56 enum {
  57         /* PLL CON0 */
  58         PLL_OD_MASK             = 0x0f,
  59
  60         /* PLL CON1 */
  61         PLL_NF_MASK             = 0x1fff,
  62
  63         /* PLL CON2 */
  64         PLL_BWADJ_MASK          = 0x0fff,
  65
  66         /* PLL CON3 */
  67         PLL_RESET_SHIFT         = 5,
  68
  69         /* CLKSEL0 */
  70         CORE_SEL_PLL_SHIFT      = 15,
  71         CORE_SEL_PLL_MASK       = 1 << CORE_SEL_PLL_SHIFT,
  72         A17_DIV_SHIFT           = 8,
  73         A17_DIV_MASK            = 0x1f << A17_DIV_SHIFT,
  74         MP_DIV_SHIFT            = 4,
  75         MP_DIV_MASK             = 0xf << MP_DIV_SHIFT,
  76         M0_DIV_SHIFT            = 0,
  77         M0_DIV_MASK             = 0xf << M0_DIV_SHIFT,
  78
  79         /* CLKSEL1: pd bus clk pll sel: codec or general */
  80         PD_BUS_SEL_PLL_MASK     = 15,
  81         PD_BUS_SEL_CPLL         = 0,
  82         PD_BUS_SEL_GPLL,
  83
  84         /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */
  85         PD_BUS_PCLK_DIV_SHIFT   = 12,
  86         PD_BUS_PCLK_DIV_MASK    = 7 << PD_BUS_PCLK_DIV_SHIFT,
  87
  88         /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
  89         PD_BUS_HCLK_DIV_SHIFT   = 8,
  90         PD_BUS_HCLK_DIV_MASK    = 3 << PD_BUS_HCLK_DIV_SHIFT,
  91
  92         /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */
  93         PD_BUS_ACLK_DIV0_SHIFT  = 3,
  94         PD_BUS_ACLK_DIV0_MASK   = 0x1f << PD_BUS_ACLK_DIV0_SHIFT,
  95         PD_BUS_ACLK_DIV1_SHIFT  = 0,
  96         PD_BUS_ACLK_DIV1_MASK   = 0x7 << PD_BUS_ACLK_DIV1_SHIFT,
  97
  98         /*
  99          * CLKSEL10
 100          * peripheral bus pclk div:
 101          * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1
 102          */
 103         PERI_SEL_PLL_SHIFT       = 15,
 104         PERI_SEL_PLL_MASK        = 1 << PERI_SEL_PLL_SHIFT,
 105         PERI_SEL_CPLL           = 0,
 106         PERI_SEL_GPLL,
 107
 108         PERI_PCLK_DIV_SHIFT     = 12,
 109         PERI_PCLK_DIV_MASK      = 3 << PERI_PCLK_DIV_SHIFT,
 110
 111         /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
 112         PERI_HCLK_DIV_SHIFT     = 8,
 113         PERI_HCLK_DIV_MASK      = 3 << PERI_HCLK_DIV_SHIFT,
 114
 115         /*
 116          * peripheral bus aclk div:
 117          *    aclk_periph = periph_clk_src / (peri_aclk_div_con + 1)
 118          */
 119         PERI_ACLK_DIV_SHIFT     = 0,
 120         PERI_ACLK_DIV_MASK      = 0x1f << PERI_ACLK_DIV_SHIFT,
 121
 122         /*
 123          * CLKSEL24
 124          * saradc_div_con:
 125          * clk_saradc=24MHz/(saradc_div_con+1)
 126          */
 127         CLK_SARADC_DIV_CON_SHIFT        = 8,
 128         CLK_SARADC_DIV_CON_MASK         = GENMASK(15, 8),
 129         CLK_SARADC_DIV_CON_WIDTH        = 8,
 130
 131         SOCSTS_DPLL_LOCK        = 1 << 5,
 132         SOCSTS_APLL_LOCK        = 1 << 6,
 133         SOCSTS_CPLL_LOCK        = 1 << 7,
 134         SOCSTS_GPLL_LOCK        = 1 << 8,
 135         SOCSTS_NPLL_LOCK        = 1 << 9,
 136 };
 137
 138 #define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))
 139
 140 #define PLL_DIVISORS(hz, _nr, _no) {\
 141         .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
 142         _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
 143                        (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
 144                        "divisors on line " __stringify(__LINE__));
 145
 146 /* Keep divisors as low as possible to reduce jitter and power usage */
 147 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
 148 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
 149 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
 150
 151 static int rkclk_set_pll(struct rockchip_cru *cru, enum rk_clk_id clk_id,
 152                          const struct pll_div *div)
 153 {
 154         int pll_id = rk_pll_id(clk_id);
 155         struct rk3288_pll *pll = &cru->pll[pll_id];
 156         /* All PLLs have same VCO and output frequency range restrictions. */
 157         uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
 158         uint output_hz = vco_hz / div->no;
 159
 160         debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
 161               (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
 162         assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
 163                output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
 164                (div->no == 1 || !(div->no % 2)));
 165
 166         /* enter reset */
 167         rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
 168
 169         rk_clrsetreg(&pll->con0, CLKR_MASK | PLL_OD_MASK,
 170                      ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
 171         rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
 172         rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
 173
 174         udelay(10);
 175
 176         /* return from reset */
 177         rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
 178
 179         return 0;
 180 }
 181
 182 static int rkclk_configure_ddr(struct rockchip_cru *cru, struct rk3288_grf *grf,
 183                                unsigned int hz)
 184 {
 185         static const struct pll_div dpll_cfg[] = {
 186                 {.nf = 25, .nr = 2, .no = 1},
 187                 {.nf = 400, .nr = 9, .no = 2},
 188                 {.nf = 500, .nr = 9, .no = 2},
 189                 {.nf = 100, .nr = 3, .no = 1},
 190         };
 191         int cfg;
 192
 193         switch (hz) {
 194         case 300000000:
 195                 cfg = 0;
 196                 break;
 197         case 533000000: /* actually 533.3P MHz */
 198                 cfg = 1;
 199                 break;
 200         case 666000000: /* actually 666.6P MHz */
 201                 cfg = 2;
 202                 break;
 203         case 800000000:
 204                 cfg = 3;
 205                 break;
 206         default:
 207                 debug("Unsupported SDRAM frequency");
 208                 return -EINVAL;
 209         }
 210
 211         /* pll enter slow-mode */
 212         rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
 213                      DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
 214
 215         rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);
 216
 217         /* wait for pll lock */
 218         while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK))
 219                 udelay(1);
 220
 221         /* PLL enter normal-mode */
 222         rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
 223                      DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
 224
 225         return 0;
 226 }
 227
 228 #ifndef CONFIG_SPL_BUILD
 229 #define VCO_MAX_KHZ     2200000
 230 #define VCO_MIN_KHZ     440000
 231 #define FREF_MAX_KHZ    2200000
 232 #define FREF_MIN_KHZ    269
 233
 234 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
 235 {
 236         uint ref_khz = OSC_HZ / 1000, nr, nf = 0;
 237         uint fref_khz;
 238         uint diff_khz, best_diff_khz;
 239         const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4;
 240         uint vco_khz;
 241         uint no = 1;
 242         uint freq_khz = freq_hz / 1000;
 243
 244         if (!freq_hz) {
 245                 printf("%s: the frequency can not be 0 Hz\n", __func__);
 246                 return -EINVAL;
 247         }
 248
 249         no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
 250         if (ext_div) {
 251                 *ext_div = DIV_ROUND_UP(no, max_no);
 252                 no = DIV_ROUND_UP(no, *ext_div);
 253         }
 254
 255         /* only even divisors (and 1) are supported */
 256         if (no > 1)
 257                 no = DIV_ROUND_UP(no, 2) * 2;
 258
 259         vco_khz = freq_khz * no;
 260         if (ext_div)
 261                 vco_khz *= *ext_div;
 262
 263         if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) {
 264                 printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n",
 265                        __func__, freq_hz);
 266                 return -1;
 267         }
 268
 269         div->no = no;
 270
 271         best_diff_khz = vco_khz;
 272         for (nr = 1; nr < max_nr && best_diff_khz; nr++) {
 273                 fref_khz = ref_khz / nr;
 274                 if (fref_khz < FREF_MIN_KHZ)
 275                         break;
 276                 if (fref_khz > FREF_MAX_KHZ)
 277                         continue;
 278
 279                 nf = vco_khz / fref_khz;
 280                 if (nf >= max_nf)
 281                         continue;
 282                 diff_khz = vco_khz - nf * fref_khz;
 283                 if (nf + 1 < max_nf && diff_khz > fref_khz / 2) {
 284                         nf++;
 285                         diff_khz = fref_khz - diff_khz;
 286                 }
 287
 288                 if (diff_khz >= best_diff_khz)
 289                         continue;
 290
 291                 best_diff_khz = diff_khz;
 292                 div->nr = nr;
 293                 div->nf = nf;
 294         }
 295
 296         if (best_diff_khz > 4 * 1000) {
 297                 printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n",
 298                        __func__, freq_hz, best_diff_khz * 1000);
 299                 return -EINVAL;
 300         }
 301
 302         return 0;
 303 }
 304
 305 static int rockchip_mac_set_clk(struct rockchip_cru *cru, uint freq)
 306 {
 307         ulong ret;
 308
 309         /*
 310          * The gmac clock can be derived either from an external clock
 311          * or can be generated from internally by a divider from SCLK_MAC.
 312          */
 313         if (readl(&cru->cru_clksel_con[21]) & RMII_EXTCLK_MASK) {
 314                 /* An external clock will always generate the right rate... */
 315                 ret = freq;
 316         } else {
 317                 u32 con = readl(&cru->cru_clksel_con[21]);
 318                 ulong pll_rate;
 319                 u8 div;
 320
 321                 if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) ==
 322                     EMAC_PLL_SELECT_GENERAL)
 323                         pll_rate = GPLL_HZ;
 324                 else if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) ==
 325                          EMAC_PLL_SELECT_CODEC)
 326                         pll_rate = CPLL_HZ;
 327                 else
 328                         pll_rate = NPLL_HZ;
 329
 330                 div = DIV_ROUND_UP(pll_rate, freq) - 1;
 331                 if (div <= 0x1f)
 332                         rk_clrsetreg(&cru->cru_clksel_con[21], MAC_DIV_CON_MASK,
 333                                      div << MAC_DIV_CON_SHIFT);
 334                 else
 335                         debug("Unsupported div for gmac:%d\n", div);
 336
 337                 return DIV_TO_RATE(pll_rate, div);
 338         }
 339
 340         return ret;
 341 }
 342
 343 static int rockchip_vop_set_clk(struct rockchip_cru *cru, struct rk3288_grf *grf,
 344                                 int periph, unsigned int rate_hz)
 345 {
 346         struct pll_div npll_config = {0};
 347         u32 lcdc_div;
 348         int ret;
 349
 350         ret = pll_para_config(rate_hz, &npll_config, &lcdc_div);
 351         if (ret)
 352                 return ret;
 353
 354         rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK,
 355                      NPLL_MODE_SLOW << NPLL_MODE_SHIFT);
 356         rkclk_set_pll(cru, CLK_NEW, &npll_config);
 357
 358         /* waiting for pll lock */
 359         while (1) {
 360                 if (readl(&grf->soc_status[1]) & SOCSTS_NPLL_LOCK)
 361                         break;
 362                 udelay(1);
 363         }
 364
 365         rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK,
 366                      NPLL_MODE_NORMAL << NPLL_MODE_SHIFT);
 367
 368         /* vop dclk source clk: npll,dclk_div: 1 */
 369         switch (periph) {
 370         case DCLK_VOP0:
 371                 rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0,
 372                              (lcdc_div - 1) << 8 | 2 << 0);
 373                 break;
 374         case DCLK_VOP1:
 375                 rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6,
 376                              (lcdc_div - 1) << 8 | 2 << 6);
 377                 break;
 378         }
 379
 380         return 0;
 381 }
 382
 383 static u32 rockchip_clk_gcd(u32 a, u32 b)
 384 {
 385         while (b != 0) {
 386                 int r = b;
 387
 388                 b = a % b;
 389                 a = r;
 390         }
 391         return a;
 392 }
 393
 394 static ulong rockchip_i2s_get_clk(struct rockchip_cru *cru, uint gclk_rate)
 395 {
 396         unsigned long long rate;
 397         uint val;
 398         int n, d;
 399
 400         val = readl(&cru->cru_clksel_con[8]);
 401         n = (val & I2S0_FRAC_NUMER_MASK) >> I2S0_FRAC_NUMER_SHIFT;
 402         d = (val & I2S0_FRAC_DENOM_MASK) >> I2S0_FRAC_DENOM_SHIFT;
 403
 404         rate = (unsigned long long)gclk_rate * n;
 405         do_div(rate, d);
 406
 407         return (ulong)rate;
 408 }
 409
 410 static ulong rockchip_i2s_set_clk(struct rockchip_cru *cru, uint gclk_rate,
 411                                   uint freq)
 412 {
 413         int n, d;
 414         int v;
 415
 416         /* set frac divider */
 417         v = rockchip_clk_gcd(gclk_rate, freq);
 418         n = gclk_rate / v;
 419         d = freq / v;
 420         assert(freq == gclk_rate / n * d);
 421         writel(d << I2S0_FRAC_NUMER_SHIFT | n << I2S0_FRAC_DENOM_SHIFT,
 422                &cru->cru_clksel_con[8]);
 423
 424         return rockchip_i2s_get_clk(cru, gclk_rate);
 425 }
 426 #endif /* CONFIG_SPL_BUILD */
 427
 428 static void rkclk_init(struct rockchip_cru *cru, struct rk3288_grf *grf)
 429 {
 430         u32 aclk_div;
 431         u32 hclk_div;
 432         u32 pclk_div;
 433
 434         /* pll enter slow-mode */
 435         rk_clrsetreg(&cru->cru_mode_con,
 436                      GPLL_MODE_MASK | CPLL_MODE_MASK,
 437                      GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
 438                      CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
 439
 440         /* init pll */
 441         rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
 442         rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
 443
 444         /* waiting for pll lock */
 445         while ((readl(&grf->soc_status[1]) &
 446                         (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
 447                         (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
 448                 udelay(1);
 449
 450         /*
 451          * pd_bus clock pll source selection and
 452          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 453          */
 454         aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1;
 455         assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
 456         hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1;
 457         assert((hclk_div + 1) * PD_BUS_HCLK_HZ ==
 458                 PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2));
 459
 460         pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1;
 461         assert((pclk_div + 1) * PD_BUS_PCLK_HZ ==
 462                 PD_BUS_ACLK_HZ && pclk_div < 0x7);
 463
 464         rk_clrsetreg(&cru->cru_clksel_con[1],
 465                      PD_BUS_PCLK_DIV_MASK | PD_BUS_HCLK_DIV_MASK |
 466                      PD_BUS_ACLK_DIV0_MASK | PD_BUS_ACLK_DIV1_MASK,
 467                      pclk_div << PD_BUS_PCLK_DIV_SHIFT |
 468                      hclk_div << PD_BUS_HCLK_DIV_SHIFT |
 469                      aclk_div << PD_BUS_ACLK_DIV0_SHIFT |
 470                      0 << 0);
 471
 472         /*
 473          * peri clock pll source selection and
 474          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 475          */
 476         aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
 477         assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
 478
 479         hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
 480         assert((1 << hclk_div) * PERI_HCLK_HZ ==
 481                 PERI_ACLK_HZ && (hclk_div < 0x4));
 482
 483         pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
 484         assert((1 << pclk_div) * PERI_PCLK_HZ ==
 485                 PERI_ACLK_HZ && (pclk_div < 0x4));
 486
 487         rk_clrsetreg(&cru->cru_clksel_con[10],
 488                      PERI_PCLK_DIV_MASK | PERI_HCLK_DIV_MASK |
 489                      PERI_ACLK_DIV_MASK,
 490                      PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
 491                      pclk_div << PERI_PCLK_DIV_SHIFT |
 492                      hclk_div << PERI_HCLK_DIV_SHIFT |
 493                      aclk_div << PERI_ACLK_DIV_SHIFT);
 494
 495         /* PLL enter normal-mode */
 496         rk_clrsetreg(&cru->cru_mode_con,
 497                      GPLL_MODE_MASK | CPLL_MODE_MASK,
 498                      GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
 499                      CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
 500 }
 501
 502 void rk3288_clk_configure_cpu(struct rockchip_cru *cru, struct rk3288_grf *grf)
 503 {
 504         /* pll enter slow-mode */
 505         rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
 506                      APLL_MODE_SLOW << APLL_MODE_SHIFT);
 507
 508         rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
 509
 510         /* waiting for pll lock */
 511         while (!(readl(&grf->soc_status[1]) & SOCSTS_APLL_LOCK))
 512                 udelay(1);
 513
 514         /*
 515          * core clock pll source selection and
 516          * set up dependent divisors for MPAXI/M0AXI and ARM clocks.
 517          * core clock select apll, apll clk = 1800MHz
 518          * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz
 519          */
 520         rk_clrsetreg(&cru->cru_clksel_con[0],
 521                      CORE_SEL_PLL_MASK | A17_DIV_MASK | MP_DIV_MASK |
 522                      M0_DIV_MASK,
 523                      0 << A17_DIV_SHIFT |
 524                      3 << MP_DIV_SHIFT |
 525                      1 << M0_DIV_SHIFT);
 526
 527         /*
 528          * set up dependent divisors for L2RAM/ATCLK and PCLK clocks.
 529          * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz
 530          */
 531         rk_clrsetreg(&cru->cru_clksel_con[37],
 532                      CLK_L2RAM_DIV_MASK | ATCLK_CORE_DIV_CON_MASK |
 533                      PCLK_CORE_DBG_DIV_MASK,
 534                      1 << CLK_L2RAM_DIV_SHIFT |
 535                      3 << ATCLK_CORE_DIV_CON_SHIFT |
 536                      3 << PCLK_CORE_DBG_DIV_SHIFT);
 537
 538         /* PLL enter normal-mode */
 539         rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
 540                      APLL_MODE_NORMAL << APLL_MODE_SHIFT);
 541 }
 542
 543 /* Get pll rate by id */
 544 static uint32_t rkclk_pll_get_rate(struct rockchip_cru *cru,
 545                                    enum rk_clk_id clk_id)
 546 {
 547         uint32_t nr, no, nf;
 548         uint32_t con;
 549         int pll_id = rk_pll_id(clk_id);
 550         struct rk3288_pll *pll = &cru->pll[pll_id];
 551         static u8 clk_shift[CLK_COUNT] = {
 552                 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
 553                 GPLL_MODE_SHIFT, NPLL_MODE_SHIFT
 554         };
 555         uint shift;
 556
 557         con = readl(&cru->cru_mode_con);
 558         shift = clk_shift[clk_id];
 559         switch ((con >> shift) & CRU_MODE_MASK) {
 560         case APLL_MODE_SLOW:
 561                 return OSC_HZ;
 562         case APLL_MODE_NORMAL:
 563                 /* normal mode */
 564                 con = readl(&pll->con0);
 565                 no = ((con & CLKOD_MASK) >> CLKOD_SHIFT) + 1;
 566                 nr = ((con & CLKR_MASK) >> CLKR_SHIFT) + 1;
 567                 con = readl(&pll->con1);
 568                 nf = ((con & CLKF_MASK) >> CLKF_SHIFT) + 1;
 569
 570                 return (24 * nf / (nr * no)) * 1000000;
 571         case APLL_MODE_DEEP:
 572         default:
 573                 return 32768;
 574         }
 575 }
 576
 577 static ulong rockchip_mmc_get_clk(struct rockchip_cru *cru, uint gclk_rate,
 578                                   int periph)
 579 {
 580         uint src_rate;
 581         uint div, mux;
 582         u32 con;
 583
 584         switch (periph) {
 585         case HCLK_EMMC:
 586         case SCLK_EMMC:
 587                 con = readl(&cru->cru_clksel_con[12]);
 588                 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
 589                 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
 590                 break;
 591         case HCLK_SDMMC:
 592         case SCLK_SDMMC:
 593                 con = readl(&cru->cru_clksel_con[11]);
 594                 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
 595                 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
 596                 break;
 597         case HCLK_SDIO0:
 598         case SCLK_SDIO0:
 599                 con = readl(&cru->cru_clksel_con[12]);
 600                 mux = (con & SDIO0_PLL_MASK) >> SDIO0_PLL_SHIFT;
 601                 div = (con & SDIO0_DIV_MASK) >> SDIO0_DIV_SHIFT;
 602                 break;
 603         default:
 604                 return -EINVAL;
 605         }
 606
 607         src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate;
 608         return DIV_TO_RATE(src_rate, div);
 609 }
 610
 611 static ulong rockchip_mmc_set_clk(struct rockchip_cru *cru, uint gclk_rate,
 612                                   int  periph, uint freq)
 613 {
 614         int src_clk_div;
 615         int mux;
 616
 617         debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
 618         /* mmc clock default div 2 internal, need provide double in cru */
 619         src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq);
 620
 621         if (src_clk_div > 0x3f) {
 622                 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
 623                 assert(src_clk_div < 0x40);
 624                 mux = EMMC_PLL_SELECT_24MHZ;
 625                 assert((int)EMMC_PLL_SELECT_24MHZ ==
 626                        (int)MMC0_PLL_SELECT_24MHZ);
 627         } else {
 628                 mux = EMMC_PLL_SELECT_GENERAL;
 629                 assert((int)EMMC_PLL_SELECT_GENERAL ==
 630                        (int)MMC0_PLL_SELECT_GENERAL);
 631         }
 632         switch (periph) {
 633         case HCLK_EMMC:
 634         case SCLK_EMMC:
 635                 rk_clrsetreg(&cru->cru_clksel_con[12],
 636                              EMMC_PLL_MASK | EMMC_DIV_MASK,
 637                              mux << EMMC_PLL_SHIFT |
 638                              (src_clk_div - 1) << EMMC_DIV_SHIFT);
 639                 break;
 640         case HCLK_SDMMC:
 641         case SCLK_SDMMC:
 642                 rk_clrsetreg(&cru->cru_clksel_con[11],
 643                              MMC0_PLL_MASK | MMC0_DIV_MASK,
 644                              mux << MMC0_PLL_SHIFT |
 645                              (src_clk_div - 1) << MMC0_DIV_SHIFT);
 646                 break;
 647         case HCLK_SDIO0:
 648         case SCLK_SDIO0:
 649                 rk_clrsetreg(&cru->cru_clksel_con[12],
 650                              SDIO0_PLL_MASK | SDIO0_DIV_MASK,
 651                              mux << SDIO0_PLL_SHIFT |
 652                              (src_clk_div - 1) << SDIO0_DIV_SHIFT);
 653                 break;
 654         default:
 655                 return -EINVAL;
 656         }
 657
 658         return rockchip_mmc_get_clk(cru, gclk_rate, periph);
 659 }
 660
 661 static ulong rockchip_spi_get_clk(struct rockchip_cru *cru, uint gclk_rate,
 662                                   int periph)
 663 {
 664         uint div, mux;
 665         u32 con;
 666
 667         switch (periph) {
 668         case SCLK_SPI0:
 669                 con = readl(&cru->cru_clksel_con[25]);
 670                 mux = (con & SPI0_PLL_MASK) >> SPI0_PLL_SHIFT;
 671                 div = (con & SPI0_DIV_MASK) >> SPI0_DIV_SHIFT;
 672                 break;
 673         case SCLK_SPI1:
 674                 con = readl(&cru->cru_clksel_con[25]);
 675                 mux = (con & SPI1_PLL_MASK) >> SPI1_PLL_SHIFT;
 676                 div = (con & SPI1_DIV_MASK) >> SPI1_DIV_SHIFT;
 677                 break;
 678         case SCLK_SPI2:
 679                 con = readl(&cru->cru_clksel_con[39]);
 680                 mux = (con & SPI2_PLL_MASK) >> SPI2_PLL_SHIFT;
 681                 div = (con & SPI2_DIV_MASK) >> SPI2_DIV_SHIFT;
 682                 break;
 683         default:
 684                 return -EINVAL;
 685         }
 686         assert(mux == SPI0_PLL_SELECT_GENERAL);
 687
 688         return DIV_TO_RATE(gclk_rate, div);
 689 }
 690
 691 static ulong rockchip_spi_set_clk(struct rockchip_cru *cru, uint gclk_rate,
 692                                   int periph, uint freq)
 693 {
 694         int src_clk_div;
 695
 696         debug("%s: clk_general_rate=%u\n", __func__, gclk_rate);
 697         src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1;
 698         assert(src_clk_div < 128);
 699         switch (periph) {
 700         case SCLK_SPI0:
 701                 rk_clrsetreg(&cru->cru_clksel_con[25],
 702                              SPI0_PLL_MASK | SPI0_DIV_MASK,
 703                              SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT |
 704                              src_clk_div << SPI0_DIV_SHIFT);
 705                 break;
 706         case SCLK_SPI1:
 707                 rk_clrsetreg(&cru->cru_clksel_con[25],
 708                              SPI1_PLL_MASK | SPI1_DIV_MASK,
 709                              SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT |
 710                              src_clk_div << SPI1_DIV_SHIFT);
 711                 break;
 712         case SCLK_SPI2:
 713                 rk_clrsetreg(&cru->cru_clksel_con[39],
 714                              SPI2_PLL_MASK | SPI2_DIV_MASK,
 715                              SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT |
 716                              src_clk_div << SPI2_DIV_SHIFT);
 717                 break;
 718         default:
 719                 return -EINVAL;
 720         }
 721
 722         return rockchip_spi_get_clk(cru, gclk_rate, periph);
 723 }
 724
 725 static ulong rockchip_saradc_get_clk(struct rockchip_cru *cru)
 726 {
 727         u32 div, val;
 728
 729         val = readl(&cru->cru_clksel_con[24]);
 730         div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
 731                                CLK_SARADC_DIV_CON_WIDTH);
 732
 733         return DIV_TO_RATE(OSC_HZ, div);
 734 }
 735
 736 static ulong rockchip_saradc_set_clk(struct rockchip_cru *cru, uint hz)
 737 {
 738         int src_clk_div;
 739
 740         src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
 741         assert(src_clk_div < 128);
 742
 743         rk_clrsetreg(&cru->cru_clksel_con[24],
 744                      CLK_SARADC_DIV_CON_MASK,
 745                      src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
 746
 747         return rockchip_saradc_get_clk(cru);
 748 }
 749
 750 static ulong rk3288_clk_get_rate(struct clk *clk)
 751 {
 752         struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
 753         ulong new_rate, gclk_rate;
 754
 755         gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
 756         switch (clk->id) {
 757         case 0 ... 63:
 758                 new_rate = rkclk_pll_get_rate(priv->cru, clk->id);
 759                 break;
 760         case HCLK_EMMC:
 761         case HCLK_SDMMC:
 762         case HCLK_SDIO0:
 763         case SCLK_EMMC:
 764         case SCLK_SDMMC:
 765         case SCLK_SDIO0:
 766                 new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
 767                 break;
 768         case SCLK_SPI0:
 769         case SCLK_SPI1:
 770         case SCLK_SPI2:
 771                 new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id);
 772                 break;
 773         case PCLK_I2C0:
 774         case PCLK_I2C1:
 775         case PCLK_I2C2:
 776         case PCLK_I2C3:
 777         case PCLK_I2C4:
 778         case PCLK_I2C5:
 779                 return gclk_rate;
 780         case PCLK_PWM:
 781         case PCLK_RKPWM:
 782                 return PD_BUS_PCLK_HZ;
 783         case SCLK_SARADC:
 784                 new_rate = rockchip_saradc_get_clk(priv->cru);
 785                 break;
 786         default:
 787                 return -ENOENT;
 788         }
 789
 790         return new_rate;
 791 }
 792
 793 static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
 794 {
 795         struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
 796         struct rockchip_cru *cru = priv->cru;
 797         ulong new_rate, gclk_rate;
 798
 799         gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
 800         switch (clk->id) {
 801         case PLL_APLL:
 802                 /* We only support a fixed rate here */
 803                 if (rate != 1800000000)
 804                         return -EINVAL;
 805                 rk3288_clk_configure_cpu(priv->cru, priv->grf);
 806                 new_rate = rate;
 807                 break;
 808         case CLK_DDR:
 809                 new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate);
 810                 break;
 811         case HCLK_EMMC:
 812         case HCLK_SDMMC:
 813         case HCLK_SDIO0:
 814         case SCLK_EMMC:
 815         case SCLK_SDMMC:
 816         case SCLK_SDIO0:
 817                 new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate);
 818                 break;
 819         case SCLK_SPI0:
 820         case SCLK_SPI1:
 821         case SCLK_SPI2:
 822                 new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate);
 823                 break;
 824 #ifndef CONFIG_SPL_BUILD
 825         case SCLK_I2S0:
 826                 new_rate = rockchip_i2s_set_clk(cru, gclk_rate, rate);
 827                 break;
 828         case SCLK_MAC:
 829                 new_rate = rockchip_mac_set_clk(priv->cru, rate);
 830                 break;
 831         case DCLK_VOP0:
 832         case DCLK_VOP1:
 833                 new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate);
 834                 break;
 835         case SCLK_EDP_24M:
 836                 /* clk_edp_24M source: 24M */
 837                 rk_setreg(&cru->cru_clksel_con[28], 1 << 15);
 838
 839                 /* rst edp */
 840                 rk_setreg(&cru->cru_clksel_con[6], 1 << 15);
 841                 udelay(1);
 842                 rk_clrreg(&cru->cru_clksel_con[6], 1 << 15);
 843                 new_rate = rate;
 844                 break;
 845         case ACLK_VOP0:
 846         case ACLK_VOP1: {
 847                 u32 div;
 848
 849                 /* vop aclk source clk: cpll */
 850                 div = CPLL_HZ / rate;
 851                 assert((div - 1 < 64) && (div * rate == CPLL_HZ));
 852
 853                 switch (clk->id) {
 854                 case ACLK_VOP0:
 855                         rk_clrsetreg(&cru->cru_clksel_con[31],
 856                                      3 << 6 | 0x1f << 0,
 857                                      0 << 6 | (div - 1) << 0);
 858                         break;
 859                 case ACLK_VOP1:
 860                         rk_clrsetreg(&cru->cru_clksel_con[31],
 861                                      3 << 14 | 0x1f << 8,
 862                                      0 << 14 | (div - 1) << 8);
 863                         break;
 864                 }
 865                 new_rate = rate;
 866                 break;
 867         }
 868         case PCLK_HDMI_CTRL:
 869                 /* enable pclk hdmi ctrl */
 870                 rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9);
 871
 872                 /* software reset hdmi */
 873                 rk_setreg(&cru->cru_clkgate_con[7], 1 << 9);
 874                 udelay(1);
 875                 rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9);
 876                 new_rate = rate;
 877                 break;
 878 #endif
 879         case SCLK_SARADC:
 880                 new_rate = rockchip_saradc_set_clk(priv->cru, rate);
 881                 break;
 882         case PLL_GPLL:
 883         case PLL_CPLL:
 884         case PLL_NPLL:
 885         case ACLK_CPU:
 886         case HCLK_CPU:
 887         case PCLK_CPU:
 888         case ACLK_PERI:
 889         case HCLK_PERI:
 890         case PCLK_PERI:
 891         case SCLK_UART0:
 892                 return 0;
 893         default:
 894                 return -ENOENT;
 895         }
 896
 897         return new_rate;
 898 }
 899
 900 static int __maybe_unused rk3288_gmac_set_parent(struct clk *clk, struct clk *parent)
 901 {
 902         struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
 903         struct rockchip_cru *cru = priv->cru;
 904         const char *clock_output_name;
 905         int ret;
 906
 907         /*
 908          * If the requested parent is in the same clock-controller and
 909          * the id is SCLK_MAC_PLL ("mac_pll_src"), switch to the internal
 910          * clock.
 911          */
 912         if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_PLL)) {
 913                 debug("%s: switching GAMC to SCLK_MAC_PLL\n", __func__);
 914                 rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, 0);
 915                 return 0;
 916         }
 917
 918         /*
 919          * Otherwise, we need to check the clock-output-names of the
 920          * requested parent to see if the requested id is "ext_gmac".
 921          */
 922         ret = dev_read_string_index(parent->dev, "clock-output-names",
 923                                     parent->id, &clock_output_name);
 924         if (ret < 0)
 925                 return -ENODATA;
 926
 927         /* If this is "ext_gmac", switch to the external clock input */
 928         if (!strcmp(clock_output_name, "ext_gmac")) {
 929                 debug("%s: switching GMAC to external clock\n", __func__);
 930                 rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK,
 931                              RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT);
 932                 return 0;
 933         }
 934
 935         return -EINVAL;
 936 }
 937
 938 static int __maybe_unused rk3288_clk_set_parent(struct clk *clk, struct clk *parent)
 939 {
 940         switch (clk->id) {
 941         case SCLK_MAC:
 942                 return rk3288_gmac_set_parent(clk, parent);
 943         case SCLK_USBPHY480M_SRC:
 944                 return 0;
 945         }
 946
 947         debug("%s: unsupported clk %ld\n", __func__, clk->id);
 948         return -ENOENT;
 949 }
 950
 951 static struct clk_ops rk3288_clk_ops = {
 952         .get_rate       = rk3288_clk_get_rate,
 953         .set_rate       = rk3288_clk_set_rate,
 954 #if CONFIG_IS_ENABLED(OF_REAL)
 955         .set_parent     = rk3288_clk_set_parent,
 956 #endif
 957 };
 958
 959 static int rk3288_clk_of_to_plat(struct udevice *dev)
 960 {
 961         if (CONFIG_IS_ENABLED(OF_REAL)) {
 962                 struct rk3288_clk_priv *priv = dev_get_priv(dev);
 963
 964                 priv->cru = dev_read_addr_ptr(dev);
 965         }
 966
 967         return 0;
 968 }
 969
 970 static int rk3288_clk_probe(struct udevice *dev)
 971 {
 972         struct rk3288_clk_priv *priv = dev_get_priv(dev);
 973         bool init_clocks = false;
 974
 975         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 976         if (IS_ERR(priv->grf))
 977                 return PTR_ERR(priv->grf);
 978 #ifdef CONFIG_SPL_BUILD
 979 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 980         struct rk3288_clk_plat *plat = dev_get_plat(dev);
 981
 982         priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
 983 #endif
 984         init_clocks = true;
 985 #endif
 986         if (!(gd->flags & GD_FLG_RELOC)) {
 987                 u32 reg;
 988
 989                 /*
 990                  * Init clocks in U-Boot proper if the NPLL is runnning. This
 991                  * indicates that a previous boot loader set up the clocks, so
 992                  * we need to redo it. U-Boot's SPL does not set this clock.
 993                  */
 994                 reg = readl(&priv->cru->cru_mode_con);
 995                 if (((reg & NPLL_MODE_MASK) >> NPLL_MODE_SHIFT) ==
 996                                 NPLL_MODE_NORMAL)
 997                         init_clocks = true;
 998         }
 999
1000         if (init_clocks)
1001                 rkclk_init(priv->cru, priv->grf);
1002
1003         return 0;
1004 }
1005
1006 static int rk3288_clk_bind(struct udevice *dev)
1007 {
1008         int ret;
1009         struct udevice *sys_child;
1010         struct sysreset_reg *priv;
1011
1012         /* The reset driver does not have a device node, so bind it here */
1013         ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
1014                                  &sys_child);
1015         if (ret) {
1016                 debug("Warning: No sysreset driver: ret=%d\n", ret);
1017         } else {
1018                 priv = malloc(sizeof(struct sysreset_reg));
1019                 priv->glb_srst_fst_value = offsetof(struct rockchip_cru,
1020                                                     cru_glb_srst_fst_value);
1021                 priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
1022                                                     cru_glb_srst_snd_value);
1023                 dev_set_priv(sys_child, priv);
1024         }
1025
1026 #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
1027         ret = offsetof(struct rockchip_cru, cru_softrst_con[0]);
1028         ret = rockchip_reset_bind(dev, ret, 12);
1029         if (ret)
1030                 debug("Warning: software reset driver bind failed\n");
1031 #endif
1032
1033         return 0;
1034 }
1035
1036 static const struct udevice_id rk3288_clk_ids[] = {
1037         { .compatible = "rockchip,rk3288-cru" },
1038         { }
1039 };
1040
1041 U_BOOT_DRIVER(rockchip_rk3288_cru) = {
1042         .name           = "rockchip_rk3288_cru",
1043         .id             = UCLASS_CLK,
1044         .of_match       = rk3288_clk_ids,
1045         .priv_auto      = sizeof(struct rk3288_clk_priv),
1046         .plat_auto      = sizeof(struct rk3288_clk_plat),
1047         .ops            = &rk3288_clk_ops,
1048         .bind           = rk3288_clk_bind,
1049         .of_to_plat     = rk3288_clk_of_to_plat,
1050         .probe          = rk3288_clk_probe,
1051 };