drivers/clk/rockchip/clk_rk3288.c

   1 /*
   2  * (C) Copyright 2015 Google, Inc
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0
   5  */
   6
   7 #include <common.h>
   8 #include <clk-uclass.h>
   9 #include <dm.h>
  10 #include <dt-structs.h>
  11 #include <errno.h>
  12 #include <mapmem.h>
  13 #include <syscon.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/cru_rk3288.h>
  17 #include <asm/arch/grf_rk3288.h>
  18 #include <asm/arch/hardware.h>
  19 #include <dt-bindings/clock/rk3288-cru.h>
  20 #include <dm/device-internal.h>
  21 #include <dm/lists.h>
  22 #include <dm/uclass-internal.h>
  23 #include <linux/log2.h>
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 struct rk3288_clk_plat {
  28 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  29         struct dtd_rockchip_rk3288_cru dtd;
  30 #endif
  31 };
  32
  33 struct pll_div {
  34         u32 nr;
  35         u32 nf;
  36         u32 no;
  37 };
  38
  39 enum {
  40         VCO_MAX_HZ      = 2200U * 1000000,
  41         VCO_MIN_HZ      = 440 * 1000000,
  42         OUTPUT_MAX_HZ   = 2200U * 1000000,
  43         OUTPUT_MIN_HZ   = 27500000,
  44         FREF_MAX_HZ     = 2200U * 1000000,
  45         FREF_MIN_HZ     = 269 * 1000,
  46 };
  47
  48 enum {
  49         /* PLL CON0 */
  50         PLL_OD_MASK             = 0x0f,
  51
  52         /* PLL CON1 */
  53         PLL_NF_MASK             = 0x1fff,
  54
  55         /* PLL CON2 */
  56         PLL_BWADJ_MASK          = 0x0fff,
  57
  58         /* PLL CON3 */
  59         PLL_RESET_SHIFT         = 5,
  60
  61         /* CLKSEL0 */
  62         CORE_SEL_PLL_SHIFT      = 15,
  63         CORE_SEL_PLL_MASK       = 1 << CORE_SEL_PLL_SHIFT,
  64         A17_DIV_SHIFT           = 8,
  65         A17_DIV_MASK            = 0x1f << A17_DIV_SHIFT,
  66         MP_DIV_SHIFT            = 4,
  67         MP_DIV_MASK             = 0xf << MP_DIV_SHIFT,
  68         M0_DIV_SHIFT            = 0,
  69         M0_DIV_MASK             = 0xf << M0_DIV_SHIFT,
  70
  71         /* CLKSEL1: pd bus clk pll sel: codec or general */
  72         PD_BUS_SEL_PLL_MASK     = 15,
  73         PD_BUS_SEL_CPLL         = 0,
  74         PD_BUS_SEL_GPLL,
  75
  76         /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */
  77         PD_BUS_PCLK_DIV_SHIFT   = 12,
  78         PD_BUS_PCLK_DIV_MASK    = 7 << PD_BUS_PCLK_DIV_SHIFT,
  79
  80         /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
  81         PD_BUS_HCLK_DIV_SHIFT   = 8,
  82         PD_BUS_HCLK_DIV_MASK    = 3 << PD_BUS_HCLK_DIV_SHIFT,
  83
  84         /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */
  85         PD_BUS_ACLK_DIV0_SHIFT  = 3,
  86         PD_BUS_ACLK_DIV0_MASK   = 0x1f << PD_BUS_ACLK_DIV0_SHIFT,
  87         PD_BUS_ACLK_DIV1_SHIFT  = 0,
  88         PD_BUS_ACLK_DIV1_MASK   = 0x7 << PD_BUS_ACLK_DIV1_SHIFT,
  89
  90         /*
  91          * CLKSEL10
  92          * peripheral bus pclk div:
  93          * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1
  94          */
  95         PERI_SEL_PLL_SHIFT       = 15,
  96         PERI_SEL_PLL_MASK        = 1 << PERI_SEL_PLL_SHIFT,
  97         PERI_SEL_CPLL           = 0,
  98         PERI_SEL_GPLL,
  99
 100         PERI_PCLK_DIV_SHIFT     = 12,
 101         PERI_PCLK_DIV_MASK      = 3 << PERI_PCLK_DIV_SHIFT,
 102
 103         /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
 104         PERI_HCLK_DIV_SHIFT     = 8,
 105         PERI_HCLK_DIV_MASK      = 3 << PERI_HCLK_DIV_SHIFT,
 106
 107         /*
 108          * peripheral bus aclk div:
 109          *    aclk_periph = periph_clk_src / (peri_aclk_div_con + 1)
 110          */
 111         PERI_ACLK_DIV_SHIFT     = 0,
 112         PERI_ACLK_DIV_MASK      = 0x1f << PERI_ACLK_DIV_SHIFT,
 113
 114         SOCSTS_DPLL_LOCK        = 1 << 5,
 115         SOCSTS_APLL_LOCK        = 1 << 6,
 116         SOCSTS_CPLL_LOCK        = 1 << 7,
 117         SOCSTS_GPLL_LOCK        = 1 << 8,
 118         SOCSTS_NPLL_LOCK        = 1 << 9,
 119 };
 120
 121 #define RATE_TO_DIV(input_rate, output_rate) \
 122         ((input_rate) / (output_rate) - 1);
 123
 124 #define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))
 125
 126 #define PLL_DIVISORS(hz, _nr, _no) {\
 127         .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
 128         _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
 129                        (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
 130                        "divisors on line " __stringify(__LINE__));
 131
 132 /* Keep divisors as low as possible to reduce jitter and power usage */
 133 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
 134 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
 135 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
 136
 137 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
 138                          const struct pll_div *div)
 139 {
 140         int pll_id = rk_pll_id(clk_id);
 141         struct rk3288_pll *pll = &cru->pll[pll_id];
 142         /* All PLLs have same VCO and output frequency range restrictions. */
 143         uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
 144         uint output_hz = vco_hz / div->no;
 145
 146         debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
 147               (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
 148         assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
 149                output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
 150                (div->no == 1 || !(div->no % 2)));
 151
 152         /* enter reset */
 153         rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
 154
 155         rk_clrsetreg(&pll->con0, CLKR_MASK | PLL_OD_MASK,
 156                      ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
 157         rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
 158         rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
 159
 160         udelay(10);
 161
 162         /* return from reset */
 163         rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
 164
 165         return 0;
 166 }
 167
 168 static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf,
 169                                unsigned int hz)
 170 {
 171         static const struct pll_div dpll_cfg[] = {
 172                 {.nf = 25, .nr = 2, .no = 1},
 173                 {.nf = 400, .nr = 9, .no = 2},
 174                 {.nf = 500, .nr = 9, .no = 2},
 175                 {.nf = 100, .nr = 3, .no = 1},
 176         };
 177         int cfg;
 178
 179         switch (hz) {
 180         case 300000000:
 181                 cfg = 0;
 182                 break;
 183         case 533000000: /* actually 533.3P MHz */
 184                 cfg = 1;
 185                 break;
 186         case 666000000: /* actually 666.6P MHz */
 187                 cfg = 2;
 188                 break;
 189         case 800000000:
 190                 cfg = 3;
 191                 break;
 192         default:
 193                 debug("Unsupported SDRAM frequency");
 194                 return -EINVAL;
 195         }
 196
 197         /* pll enter slow-mode */
 198         rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
 199                      DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
 200
 201         rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);
 202
 203         /* wait for pll lock */
 204         while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK))
 205                 udelay(1);
 206
 207         /* PLL enter normal-mode */
 208         rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
 209                      DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
 210
 211         return 0;
 212 }
 213
 214 #ifndef CONFIG_SPL_BUILD
 215 #define VCO_MAX_KHZ     2200000
 216 #define VCO_MIN_KHZ     440000
 217 #define FREF_MAX_KHZ    2200000
 218 #define FREF_MIN_KHZ    269
 219
 220 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
 221 {
 222         uint ref_khz = OSC_HZ / 1000, nr, nf = 0;
 223         uint fref_khz;
 224         uint diff_khz, best_diff_khz;
 225         const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4;
 226         uint vco_khz;
 227         uint no = 1;
 228         uint freq_khz = freq_hz / 1000;
 229
 230         if (!freq_hz) {
 231                 printf("%s: the frequency can not be 0 Hz\n", __func__);
 232                 return -EINVAL;
 233         }
 234
 235         no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
 236         if (ext_div) {
 237                 *ext_div = DIV_ROUND_UP(no, max_no);
 238                 no = DIV_ROUND_UP(no, *ext_div);
 239         }
 240
 241         /* only even divisors (and 1) are supported */
 242         if (no > 1)
 243                 no = DIV_ROUND_UP(no, 2) * 2;
 244
 245         vco_khz = freq_khz * no;
 246         if (ext_div)
 247                 vco_khz *= *ext_div;
 248
 249         if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) {
 250                 printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n",
 251                        __func__, freq_hz);
 252                 return -1;
 253         }
 254
 255         div->no = no;
 256
 257         best_diff_khz = vco_khz;
 258         for (nr = 1; nr < max_nr && best_diff_khz; nr++) {
 259                 fref_khz = ref_khz / nr;
 260                 if (fref_khz < FREF_MIN_KHZ)
 261                         break;
 262                 if (fref_khz > FREF_MAX_KHZ)
 263                         continue;
 264
 265                 nf = vco_khz / fref_khz;
 266                 if (nf >= max_nf)
 267                         continue;
 268                 diff_khz = vco_khz - nf * fref_khz;
 269                 if (nf + 1 < max_nf && diff_khz > fref_khz / 2) {
 270                         nf++;
 271                         diff_khz = fref_khz - diff_khz;
 272                 }
 273
 274                 if (diff_khz >= best_diff_khz)
 275                         continue;
 276
 277                 best_diff_khz = diff_khz;
 278                 div->nr = nr;
 279                 div->nf = nf;
 280         }
 281
 282         if (best_diff_khz > 4 * 1000) {
 283                 printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n",
 284                        __func__, freq_hz, best_diff_khz * 1000);
 285                 return -EINVAL;
 286         }
 287
 288         return 0;
 289 }
 290
 291 static int rockchip_mac_set_clk(struct rk3288_cru *cru,
 292                                   int periph, uint freq)
 293 {
 294         /* Assuming mac_clk is fed by an external clock */
 295         rk_clrsetreg(&cru->cru_clksel_con[21],
 296                      RMII_EXTCLK_MASK,
 297                      RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT);
 298
 299          return 0;
 300 }
 301
 302 static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
 303                                 int periph, unsigned int rate_hz)
 304 {
 305         struct pll_div npll_config = {0};
 306         u32 lcdc_div;
 307         int ret;
 308
 309         ret = pll_para_config(rate_hz, &npll_config, &lcdc_div);
 310         if (ret)
 311                 return ret;
 312
 313         rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK,
 314                      NPLL_MODE_SLOW << NPLL_MODE_SHIFT);
 315         rkclk_set_pll(cru, CLK_NEW, &npll_config);
 316
 317         /* waiting for pll lock */
 318         while (1) {
 319                 if (readl(&grf->soc_status[1]) & SOCSTS_NPLL_LOCK)
 320                         break;
 321                 udelay(1);
 322         }
 323
 324         rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK,
 325                      NPLL_MODE_NORMAL << NPLL_MODE_SHIFT);
 326
 327         /* vop dclk source clk: npll,dclk_div: 1 */
 328         switch (periph) {
 329         case DCLK_VOP0:
 330                 rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0,
 331                              (lcdc_div - 1) << 8 | 2 << 0);
 332                 break;
 333         case DCLK_VOP1:
 334                 rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6,
 335                              (lcdc_div - 1) << 8 | 2 << 6);
 336                 break;
 337         }
 338
 339         return 0;
 340 }
 341 #endif /* CONFIG_SPL_BUILD */
 342
 343 static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
 344 {
 345         u32 aclk_div;
 346         u32 hclk_div;
 347         u32 pclk_div;
 348
 349         /* pll enter slow-mode */
 350         rk_clrsetreg(&cru->cru_mode_con,
 351                      GPLL_MODE_MASK | CPLL_MODE_MASK,
 352                      GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
 353                      CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
 354
 355         /* init pll */
 356         rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
 357         rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
 358
 359         /* waiting for pll lock */
 360         while ((readl(&grf->soc_status[1]) &
 361                         (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
 362                         (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
 363                 udelay(1);
 364
 365         /*
 366          * pd_bus clock pll source selection and
 367          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 368          */
 369         aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1;
 370         assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
 371         hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1;
 372         assert((hclk_div + 1) * PD_BUS_HCLK_HZ ==
 373                 PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2));
 374
 375         pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1;
 376         assert((pclk_div + 1) * PD_BUS_PCLK_HZ ==
 377                 PD_BUS_ACLK_HZ && pclk_div < 0x7);
 378
 379         rk_clrsetreg(&cru->cru_clksel_con[1],
 380                      PD_BUS_PCLK_DIV_MASK | PD_BUS_HCLK_DIV_MASK |
 381                      PD_BUS_ACLK_DIV0_MASK | PD_BUS_ACLK_DIV1_MASK,
 382                      pclk_div << PD_BUS_PCLK_DIV_SHIFT |
 383                      hclk_div << PD_BUS_HCLK_DIV_SHIFT |
 384                      aclk_div << PD_BUS_ACLK_DIV0_SHIFT |
 385                      0 << 0);
 386
 387         /*
 388          * peri clock pll source selection and
 389          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 390          */
 391         aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
 392         assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
 393
 394         hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
 395         assert((1 << hclk_div) * PERI_HCLK_HZ ==
 396                 PERI_ACLK_HZ && (hclk_div < 0x4));
 397
 398         pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
 399         assert((1 << pclk_div) * PERI_PCLK_HZ ==
 400                 PERI_ACLK_HZ && (pclk_div < 0x4));
 401
 402         rk_clrsetreg(&cru->cru_clksel_con[10],
 403                      PERI_PCLK_DIV_MASK | PERI_HCLK_DIV_MASK |
 404                      PERI_ACLK_DIV_MASK,
 405                      PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
 406                      pclk_div << PERI_PCLK_DIV_SHIFT |
 407                      hclk_div << PERI_HCLK_DIV_SHIFT |
 408                      aclk_div << PERI_ACLK_DIV_SHIFT);
 409
 410         /* PLL enter normal-mode */
 411         rk_clrsetreg(&cru->cru_mode_con,
 412                      GPLL_MODE_MASK | CPLL_MODE_MASK,
 413                      GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
 414                      CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
 415 }
 416
 417 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
 418 {
 419         /* pll enter slow-mode */
 420         rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
 421                      APLL_MODE_SLOW << APLL_MODE_SHIFT);
 422
 423         rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
 424
 425         /* waiting for pll lock */
 426         while (!(readl(&grf->soc_status[1]) & SOCSTS_APLL_LOCK))
 427                 udelay(1);
 428
 429         /*
 430          * core clock pll source selection and
 431          * set up dependent divisors for MPAXI/M0AXI and ARM clocks.
 432          * core clock select apll, apll clk = 1800MHz
 433          * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz
 434          */
 435         rk_clrsetreg(&cru->cru_clksel_con[0],
 436                      CORE_SEL_PLL_MASK | A17_DIV_MASK | MP_DIV_MASK |
 437                      M0_DIV_MASK,
 438                      0 << A17_DIV_SHIFT |
 439                      3 << MP_DIV_SHIFT |
 440                      1 << M0_DIV_SHIFT);
 441
 442         /*
 443          * set up dependent divisors for L2RAM/ATCLK and PCLK clocks.
 444          * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz
 445          */
 446         rk_clrsetreg(&cru->cru_clksel_con[37],
 447                      CLK_L2RAM_DIV_MASK | ATCLK_CORE_DIV_CON_MASK |
 448                      PCLK_CORE_DBG_DIV_MASK,
 449                      1 << CLK_L2RAM_DIV_SHIFT |
 450                      3 << ATCLK_CORE_DIV_CON_SHIFT |
 451                      3 << PCLK_CORE_DBG_DIV_SHIFT);
 452
 453         /* PLL enter normal-mode */
 454         rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
 455                      APLL_MODE_NORMAL << APLL_MODE_SHIFT);
 456 }
 457
 458 /* Get pll rate by id */
 459 static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
 460                                    enum rk_clk_id clk_id)
 461 {
 462         uint32_t nr, no, nf;
 463         uint32_t con;
 464         int pll_id = rk_pll_id(clk_id);
 465         struct rk3288_pll *pll = &cru->pll[pll_id];
 466         static u8 clk_shift[CLK_COUNT] = {
 467                 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
 468                 GPLL_MODE_SHIFT, NPLL_MODE_SHIFT
 469         };
 470         uint shift;
 471
 472         con = readl(&cru->cru_mode_con);
 473         shift = clk_shift[clk_id];
 474         switch ((con >> shift) & CRU_MODE_MASK) {
 475         case APLL_MODE_SLOW:
 476                 return OSC_HZ;
 477         case APLL_MODE_NORMAL:
 478                 /* normal mode */
 479                 con = readl(&pll->con0);
 480                 no = ((con & CLKOD_MASK) >> CLKOD_SHIFT) + 1;
 481                 nr = ((con & CLKR_MASK) >> CLKR_SHIFT) + 1;
 482                 con = readl(&pll->con1);
 483                 nf = ((con & CLKF_MASK) >> CLKF_SHIFT) + 1;
 484
 485                 return (24 * nf / (nr * no)) * 1000000;
 486         case APLL_MODE_DEEP:
 487         default:
 488                 return 32768;
 489         }
 490 }
 491
 492 static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
 493                                   int periph)
 494 {
 495         uint src_rate;
 496         uint div, mux;
 497         u32 con;
 498
 499         switch (periph) {
 500         case HCLK_EMMC:
 501         case SCLK_EMMC:
 502                 con = readl(&cru->cru_clksel_con[12]);
 503                 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
 504                 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
 505                 break;
 506         case HCLK_SDMMC:
 507         case SCLK_SDMMC:
 508                 con = readl(&cru->cru_clksel_con[11]);
 509                 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
 510                 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
 511                 break;
 512         case HCLK_SDIO0:
 513         case SCLK_SDIO0:
 514                 con = readl(&cru->cru_clksel_con[12]);
 515                 mux = (con & SDIO0_PLL_MASK) >> SDIO0_PLL_SHIFT;
 516                 div = (con & SDIO0_DIV_MASK) >> SDIO0_DIV_SHIFT;
 517                 break;
 518         default:
 519                 return -EINVAL;
 520         }
 521
 522         src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate;
 523         return DIV_TO_RATE(src_rate, div);
 524 }
 525
 526 static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
 527                                   int  periph, uint freq)
 528 {
 529         int src_clk_div;
 530         int mux;
 531
 532         debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
 533         src_clk_div = RATE_TO_DIV(gclk_rate, freq);
 534
 535         if (src_clk_div > 0x3f) {
 536                 src_clk_div = RATE_TO_DIV(OSC_HZ, freq);
 537                 mux = EMMC_PLL_SELECT_24MHZ;
 538                 assert((int)EMMC_PLL_SELECT_24MHZ ==
 539                        (int)MMC0_PLL_SELECT_24MHZ);
 540         } else {
 541                 mux = EMMC_PLL_SELECT_GENERAL;
 542                 assert((int)EMMC_PLL_SELECT_GENERAL ==
 543                        (int)MMC0_PLL_SELECT_GENERAL);
 544         }
 545         switch (periph) {
 546         case HCLK_EMMC:
 547         case SCLK_EMMC:
 548                 rk_clrsetreg(&cru->cru_clksel_con[12],
 549                              EMMC_PLL_MASK | EMMC_DIV_MASK,
 550                              mux << EMMC_PLL_SHIFT |
 551                              (src_clk_div - 1) << EMMC_DIV_SHIFT);
 552                 break;
 553         case HCLK_SDMMC:
 554         case SCLK_SDMMC:
 555                 rk_clrsetreg(&cru->cru_clksel_con[11],
 556                              MMC0_PLL_MASK | MMC0_DIV_MASK,
 557                              mux << MMC0_PLL_SHIFT |
 558                              (src_clk_div - 1) << MMC0_DIV_SHIFT);
 559                 break;
 560         case HCLK_SDIO0:
 561         case SCLK_SDIO0:
 562                 rk_clrsetreg(&cru->cru_clksel_con[12],
 563                              SDIO0_PLL_MASK | SDIO0_DIV_MASK,
 564                              mux << SDIO0_PLL_SHIFT |
 565                              (src_clk_div - 1) << SDIO0_DIV_SHIFT);
 566                 break;
 567         default:
 568                 return -EINVAL;
 569         }
 570
 571         return rockchip_mmc_get_clk(cru, gclk_rate, periph);
 572 }
 573
 574 static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
 575                                   int periph)
 576 {
 577         uint div, mux;
 578         u32 con;
 579
 580         switch (periph) {
 581         case SCLK_SPI0:
 582                 con = readl(&cru->cru_clksel_con[25]);
 583                 mux = (con & SPI0_PLL_MASK) >> SPI0_PLL_SHIFT;
 584                 div = (con & SPI0_DIV_MASK) >> SPI0_DIV_SHIFT;
 585                 break;
 586         case SCLK_SPI1:
 587                 con = readl(&cru->cru_clksel_con[25]);
 588                 mux = (con & SPI1_PLL_MASK) >> SPI1_PLL_SHIFT;
 589                 div = (con & SPI1_DIV_MASK) >> SPI1_DIV_SHIFT;
 590                 break;
 591         case SCLK_SPI2:
 592                 con = readl(&cru->cru_clksel_con[39]);
 593                 mux = (con & SPI2_PLL_MASK) >> SPI2_PLL_SHIFT;
 594                 div = (con & SPI2_DIV_MASK) >> SPI2_DIV_SHIFT;
 595                 break;
 596         default:
 597                 return -EINVAL;
 598         }
 599         assert(mux == SPI0_PLL_SELECT_GENERAL);
 600
 601         return DIV_TO_RATE(gclk_rate, div);
 602 }
 603
 604 static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
 605                                   int periph, uint freq)
 606 {
 607         int src_clk_div;
 608
 609         debug("%s: clk_general_rate=%u\n", __func__, gclk_rate);
 610         src_clk_div = RATE_TO_DIV(gclk_rate, freq);
 611         switch (periph) {
 612         case SCLK_SPI0:
 613                 rk_clrsetreg(&cru->cru_clksel_con[25],
 614                              SPI0_PLL_MASK | SPI0_DIV_MASK,
 615                              SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT |
 616                              src_clk_div << SPI0_DIV_SHIFT);
 617                 break;
 618         case SCLK_SPI1:
 619                 rk_clrsetreg(&cru->cru_clksel_con[25],
 620                              SPI1_PLL_MASK | SPI1_DIV_MASK,
 621                              SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT |
 622                              src_clk_div << SPI1_DIV_SHIFT);
 623                 break;
 624         case SCLK_SPI2:
 625                 rk_clrsetreg(&cru->cru_clksel_con[39],
 626                              SPI2_PLL_MASK | SPI2_DIV_MASK,
 627                              SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT |
 628                              src_clk_div << SPI2_DIV_SHIFT);
 629                 break;
 630         default:
 631                 return -EINVAL;
 632         }
 633
 634         return rockchip_spi_get_clk(cru, gclk_rate, periph);
 635 }
 636
 637 static ulong rk3288_clk_get_rate(struct clk *clk)
 638 {
 639         struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
 640         ulong new_rate, gclk_rate;
 641
 642         gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
 643         switch (clk->id) {
 644         case 0 ... 63:
 645                 new_rate = rkclk_pll_get_rate(priv->cru, clk->id);
 646                 break;
 647         case HCLK_EMMC:
 648         case HCLK_SDMMC:
 649         case HCLK_SDIO0:
 650         case SCLK_EMMC:
 651         case SCLK_SDMMC:
 652         case SCLK_SDIO0:
 653                 new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
 654                 break;
 655         case SCLK_SPI0:
 656         case SCLK_SPI1:
 657         case SCLK_SPI2:
 658                 new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id);
 659                 break;
 660         case PCLK_I2C0:
 661         case PCLK_I2C1:
 662         case PCLK_I2C2:
 663         case PCLK_I2C3:
 664         case PCLK_I2C4:
 665         case PCLK_I2C5:
 666                 return gclk_rate;
 667         case PCLK_PWM:
 668                 return PD_BUS_PCLK_HZ;
 669         default:
 670                 return -ENOENT;
 671         }
 672
 673         return new_rate;
 674 }
 675
 676 static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
 677 {
 678         struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
 679         struct rk3288_cru *cru = priv->cru;
 680         ulong new_rate, gclk_rate;
 681
 682         gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
 683         switch (clk->id) {
 684         case PLL_APLL:
 685                 /* We only support a fixed rate here */
 686                 if (rate != 1800000000)
 687                         return -EINVAL;
 688                 rk3288_clk_configure_cpu(priv->cru, priv->grf);
 689                 new_rate = rate;
 690                 break;
 691         case CLK_DDR:
 692                 new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate);
 693                 break;
 694         case HCLK_EMMC:
 695         case HCLK_SDMMC:
 696         case HCLK_SDIO0:
 697         case SCLK_EMMC:
 698         case SCLK_SDMMC:
 699         case SCLK_SDIO0:
 700                 new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate);
 701                 break;
 702         case SCLK_SPI0:
 703         case SCLK_SPI1:
 704         case SCLK_SPI2:
 705                 new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate);
 706                 break;
 707 #ifndef CONFIG_SPL_BUILD
 708         case SCLK_MAC:
 709                 new_rate = rockchip_mac_set_clk(priv->cru, clk->id, rate);
 710                 break;
 711         case DCLK_VOP0:
 712         case DCLK_VOP1:
 713                 new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate);
 714                 break;
 715         case SCLK_EDP_24M:
 716                 /* clk_edp_24M source: 24M */
 717                 rk_setreg(&cru->cru_clksel_con[28], 1 << 15);
 718
 719                 /* rst edp */
 720                 rk_setreg(&cru->cru_clksel_con[6], 1 << 15);
 721                 udelay(1);
 722                 rk_clrreg(&cru->cru_clksel_con[6], 1 << 15);
 723                 new_rate = rate;
 724                 break;
 725         case ACLK_VOP0:
 726         case ACLK_VOP1: {
 727                 u32 div;
 728
 729                 /* vop aclk source clk: cpll */
 730                 div = CPLL_HZ / rate;
 731                 assert((div - 1 < 64) && (div * rate == CPLL_HZ));
 732
 733                 switch (clk->id) {
 734                 case ACLK_VOP0:
 735                         rk_clrsetreg(&cru->cru_clksel_con[31],
 736                                      3 << 6 | 0x1f << 0,
 737                                      0 << 6 | (div - 1) << 0);
 738                         break;
 739                 case ACLK_VOP1:
 740                         rk_clrsetreg(&cru->cru_clksel_con[31],
 741                                      3 << 14 | 0x1f << 8,
 742                                      0 << 14 | (div - 1) << 8);
 743                         break;
 744                 }
 745                 new_rate = rate;
 746                 break;
 747         }
 748         case PCLK_HDMI_CTRL:
 749                 /* enable pclk hdmi ctrl */
 750                 rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9);
 751
 752                 /* software reset hdmi */
 753                 rk_setreg(&cru->cru_clkgate_con[7], 1 << 9);
 754                 udelay(1);
 755                 rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9);
 756                 new_rate = rate;
 757                 break;
 758 #endif
 759         default:
 760                 return -ENOENT;
 761         }
 762
 763         return new_rate;
 764 }
 765
 766 static struct clk_ops rk3288_clk_ops = {
 767         .get_rate       = rk3288_clk_get_rate,
 768         .set_rate       = rk3288_clk_set_rate,
 769 };
 770
 771 static int rk3288_clk_ofdata_to_platdata(struct udevice *dev)
 772 {
 773 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 774         struct rk3288_clk_priv *priv = dev_get_priv(dev);
 775
 776         priv->cru = (struct rk3288_cru *)devfdt_get_addr(dev);
 777 #endif
 778
 779         return 0;
 780 }
 781
 782 static int rk3288_clk_probe(struct udevice *dev)
 783 {
 784         struct rk3288_clk_priv *priv = dev_get_priv(dev);
 785         bool init_clocks = false;
 786
 787         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 788         if (IS_ERR(priv->grf))
 789                 return PTR_ERR(priv->grf);
 790 #ifdef CONFIG_SPL_BUILD
 791 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 792         struct rk3288_clk_plat *plat = dev_get_platdata(dev);
 793
 794         priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
 795 #endif
 796         init_clocks = true;
 797 #endif
 798         if (!(gd->flags & GD_FLG_RELOC)) {
 799                 u32 reg;
 800
 801                 /*
 802                  * Init clocks in U-Boot proper if the NPLL is runnning. This
 803                  * indicates that a previous boot loader set up the clocks, so
 804                  * we need to redo it. U-Boot's SPL does not set this clock.
 805                  */
 806                 reg = readl(&priv->cru->cru_mode_con);
 807                 if (((reg & NPLL_MODE_MASK) >> NPLL_MODE_SHIFT) ==
 808                                 NPLL_MODE_NORMAL)
 809                         init_clocks = true;
 810         }
 811
 812         if (init_clocks)
 813                 rkclk_init(priv->cru, priv->grf);
 814
 815         return 0;
 816 }
 817
 818 static int rk3288_clk_bind(struct udevice *dev)
 819 {
 820         int ret;
 821
 822         /* The reset driver does not have a device node, so bind it here */
 823         ret = device_bind_driver(gd->dm_root, "rk3288_sysreset", "reset", &dev);
 824         if (ret)
 825                 debug("Warning: No RK3288 reset driver: ret=%d\n", ret);
 826
 827         return 0;
 828 }
 829
 830 static const struct udevice_id rk3288_clk_ids[] = {
 831         { .compatible = "rockchip,rk3288-cru" },
 832         { }
 833 };
 834
 835 U_BOOT_DRIVER(rockchip_rk3288_cru) = {
 836         .name           = "rockchip_rk3288_cru",
 837         .id             = UCLASS_CLK,
 838         .of_match       = rk3288_clk_ids,
 839         .priv_auto_alloc_size = sizeof(struct rk3288_clk_priv),
 840         .platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat),
 841         .ops            = &rk3288_clk_ops,
 842         .bind           = rk3288_clk_bind,
 843         .ofdata_to_platdata     = rk3288_clk_ofdata_to_platdata,
 844         .probe          = rk3288_clk_probe,
 845 };