drivers/clk/rockchip/clk_rk3288.c

   1 /*
   2  * (C) Copyright 2015 Google, Inc
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0
   5  */
   6
   7 #include <common.h>
   8 #include <clk-uclass.h>
   9 #include <dm.h>
  10 #include <dt-structs.h>
  11 #include <errno.h>
  12 #include <mapmem.h>
  13 #include <syscon.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/cru_rk3288.h>
  17 #include <asm/arch/grf_rk3288.h>
  18 #include <asm/arch/hardware.h>
  19 #include <dt-bindings/clock/rk3288-cru.h>
  20 #include <dm/device-internal.h>
  21 #include <dm/lists.h>
  22 #include <dm/uclass-internal.h>
  23 #include <linux/log2.h>
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 struct rk3288_clk_plat {
  28 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  29         struct dtd_rockchip_rk3288_cru dtd;
  30 #endif
  31 };
  32
  33 struct pll_div {
  34         u32 nr;
  35         u32 nf;
  36         u32 no;
  37 };
  38
  39 enum {
  40         VCO_MAX_HZ      = 2200U * 1000000,
  41         VCO_MIN_HZ      = 440 * 1000000,
  42         OUTPUT_MAX_HZ   = 2200U * 1000000,
  43         OUTPUT_MIN_HZ   = 27500000,
  44         FREF_MAX_HZ     = 2200U * 1000000,
  45         FREF_MIN_HZ     = 269 * 1000,
  46 };
  47
  48 enum {
  49         /* PLL CON0 */
  50         PLL_OD_MASK             = 0x0f,
  51
  52         /* PLL CON1 */
  53         PLL_NF_MASK             = 0x1fff,
  54
  55         /* PLL CON2 */
  56         PLL_BWADJ_MASK          = 0x0fff,
  57
  58         /* PLL CON3 */
  59         PLL_RESET_SHIFT         = 5,
  60
  61         /* CLKSEL0 */
  62         CORE_SEL_PLL_MASK       = 1,
  63         CORE_SEL_PLL_SHIFT      = 15,
  64         A17_DIV_MASK            = 0x1f,
  65         A17_DIV_SHIFT           = 8,
  66         MP_DIV_MASK             = 0xf,
  67         MP_DIV_SHIFT            = 4,
  68         M0_DIV_MASK             = 0xf,
  69         M0_DIV_SHIFT            = 0,
  70
  71         /* CLKSEL1: pd bus clk pll sel: codec or general */
  72         PD_BUS_SEL_PLL_MASK     = 15,
  73         PD_BUS_SEL_CPLL         = 0,
  74         PD_BUS_SEL_GPLL,
  75
  76         /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */
  77         PD_BUS_PCLK_DIV_SHIFT   = 12,
  78         PD_BUS_PCLK_DIV_MASK    = 7,
  79
  80         /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
  81         PD_BUS_HCLK_DIV_SHIFT   = 8,
  82         PD_BUS_HCLK_DIV_MASK    = 3,
  83
  84         /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */
  85         PD_BUS_ACLK_DIV0_SHIFT  = 3,
  86         PD_BUS_ACLK_DIV0_MASK   = 0x1f,
  87         PD_BUS_ACLK_DIV1_SHIFT  = 0,
  88         PD_BUS_ACLK_DIV1_MASK   = 0x7,
  89
  90         /*
  91          * CLKSEL10
  92          * peripheral bus pclk div:
  93          * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1
  94          */
  95         PERI_SEL_PLL_MASK        = 1,
  96         PERI_SEL_PLL_SHIFT       = 15,
  97         PERI_SEL_CPLL           = 0,
  98         PERI_SEL_GPLL,
  99
 100         PERI_PCLK_DIV_SHIFT     = 12,
 101         PERI_PCLK_DIV_MASK      = 3,
 102
 103         /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
 104         PERI_HCLK_DIV_SHIFT     = 8,
 105         PERI_HCLK_DIV_MASK      = 3,
 106
 107         /*
 108          * peripheral bus aclk div:
 109          *    aclk_periph = periph_clk_src / (peri_aclk_div_con + 1)
 110          */
 111         PERI_ACLK_DIV_SHIFT     = 0,
 112         PERI_ACLK_DIV_MASK      = 0x1f,
 113
 114         SOCSTS_DPLL_LOCK        = 1 << 5,
 115         SOCSTS_APLL_LOCK        = 1 << 6,
 116         SOCSTS_CPLL_LOCK        = 1 << 7,
 117         SOCSTS_GPLL_LOCK        = 1 << 8,
 118         SOCSTS_NPLL_LOCK        = 1 << 9,
 119 };
 120
 121 #define RATE_TO_DIV(input_rate, output_rate) \
 122         ((input_rate) / (output_rate) - 1);
 123
 124 #define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))
 125
 126 #define PLL_DIVISORS(hz, _nr, _no) {\
 127         .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
 128         _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
 129                        (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
 130                        "divisors on line " __stringify(__LINE__));
 131
 132 /* Keep divisors as low as possible to reduce jitter and power usage */
 133 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
 134 #ifdef CONFIG_SPL_BUILD
 135 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
 136 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
 137 #endif
 138
 139 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
 140                          const struct pll_div *div)
 141 {
 142         int pll_id = rk_pll_id(clk_id);
 143         struct rk3288_pll *pll = &cru->pll[pll_id];
 144         /* All PLLs have same VCO and output frequency range restrictions. */
 145         uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
 146         uint output_hz = vco_hz / div->no;
 147
 148         debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
 149               (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
 150         assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
 151                output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
 152                (div->no == 1 || !(div->no % 2)));
 153
 154         /* enter reset */
 155         rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
 156
 157         rk_clrsetreg(&pll->con0,
 158                      CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK,
 159                      ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
 160         rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
 161         rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
 162
 163         udelay(10);
 164
 165         /* return from reset */
 166         rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
 167
 168         return 0;
 169 }
 170
 171 static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf,
 172                                unsigned int hz)
 173 {
 174         static const struct pll_div dpll_cfg[] = {
 175                 {.nf = 25, .nr = 2, .no = 1},
 176                 {.nf = 400, .nr = 9, .no = 2},
 177                 {.nf = 500, .nr = 9, .no = 2},
 178                 {.nf = 100, .nr = 3, .no = 1},
 179         };
 180         int cfg;
 181
 182         switch (hz) {
 183         case 300000000:
 184                 cfg = 0;
 185                 break;
 186         case 533000000: /* actually 533.3P MHz */
 187                 cfg = 1;
 188                 break;
 189         case 666000000: /* actually 666.6P MHz */
 190                 cfg = 2;
 191                 break;
 192         case 800000000:
 193                 cfg = 3;
 194                 break;
 195         default:
 196                 debug("Unsupported SDRAM frequency");
 197                 return -EINVAL;
 198         }
 199
 200         /* pll enter slow-mode */
 201         rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
 202                      DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
 203
 204         rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);
 205
 206         /* wait for pll lock */
 207         while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK))
 208                 udelay(1);
 209
 210         /* PLL enter normal-mode */
 211         rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
 212                      DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
 213
 214         return 0;
 215 }
 216
 217 #ifndef CONFIG_SPL_BUILD
 218 #define VCO_MAX_KHZ     2200000
 219 #define VCO_MIN_KHZ     440000
 220 #define FREF_MAX_KHZ    2200000
 221 #define FREF_MIN_KHZ    269
 222
 223 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
 224 {
 225         uint ref_khz = OSC_HZ / 1000, nr, nf = 0;
 226         uint fref_khz;
 227         uint diff_khz, best_diff_khz;
 228         const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4;
 229         uint vco_khz;
 230         uint no = 1;
 231         uint freq_khz = freq_hz / 1000;
 232
 233         if (!freq_hz) {
 234                 printf("%s: the frequency can not be 0 Hz\n", __func__);
 235                 return -EINVAL;
 236         }
 237
 238         no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
 239         if (ext_div) {
 240                 *ext_div = DIV_ROUND_UP(no, max_no);
 241                 no = DIV_ROUND_UP(no, *ext_div);
 242         }
 243
 244         /* only even divisors (and 1) are supported */
 245         if (no > 1)
 246                 no = DIV_ROUND_UP(no, 2) * 2;
 247
 248         vco_khz = freq_khz * no;
 249         if (ext_div)
 250                 vco_khz *= *ext_div;
 251
 252         if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) {
 253                 printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n",
 254                        __func__, freq_hz);
 255                 return -1;
 256         }
 257
 258         div->no = no;
 259
 260         best_diff_khz = vco_khz;
 261         for (nr = 1; nr < max_nr && best_diff_khz; nr++) {
 262                 fref_khz = ref_khz / nr;
 263                 if (fref_khz < FREF_MIN_KHZ)
 264                         break;
 265                 if (fref_khz > FREF_MAX_KHZ)
 266                         continue;
 267
 268                 nf = vco_khz / fref_khz;
 269                 if (nf >= max_nf)
 270                         continue;
 271                 diff_khz = vco_khz - nf * fref_khz;
 272                 if (nf + 1 < max_nf && diff_khz > fref_khz / 2) {
 273                         nf++;
 274                         diff_khz = fref_khz - diff_khz;
 275                 }
 276
 277                 if (diff_khz >= best_diff_khz)
 278                         continue;
 279
 280                 best_diff_khz = diff_khz;
 281                 div->nr = nr;
 282                 div->nf = nf;
 283         }
 284
 285         if (best_diff_khz > 4 * 1000) {
 286                 printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n",
 287                        __func__, freq_hz, best_diff_khz * 1000);
 288                 return -EINVAL;
 289         }
 290
 291         return 0;
 292 }
 293
 294 static int rockchip_mac_set_clk(struct rk3288_cru *cru,
 295                                   int periph, uint freq)
 296 {
 297         /* Assuming mac_clk is fed by an external clock */
 298         rk_clrsetreg(&cru->cru_clksel_con[21],
 299                      RMII_EXTCLK_MASK << RMII_EXTCLK_SHIFT,
 300                      RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT);
 301
 302          return 0;
 303 }
 304
 305 static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
 306                                 int periph, unsigned int rate_hz)
 307 {
 308         struct pll_div npll_config = {0};
 309         u32 lcdc_div;
 310         int ret;
 311
 312         ret = pll_para_config(rate_hz, &npll_config, &lcdc_div);
 313         if (ret)
 314                 return ret;
 315
 316         rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT,
 317                      NPLL_MODE_SLOW << NPLL_MODE_SHIFT);
 318         rkclk_set_pll(cru, CLK_NEW, &npll_config);
 319
 320         /* waiting for pll lock */
 321         while (1) {
 322                 if (readl(&grf->soc_status[1]) & SOCSTS_NPLL_LOCK)
 323                         break;
 324                 udelay(1);
 325         }
 326
 327         rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT,
 328                      NPLL_MODE_NORMAL << NPLL_MODE_SHIFT);
 329
 330         /* vop dclk source clk: npll,dclk_div: 1 */
 331         switch (periph) {
 332         case DCLK_VOP0:
 333                 rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0,
 334                              (lcdc_div - 1) << 8 | 2 << 0);
 335                 break;
 336         case DCLK_VOP1:
 337                 rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6,
 338                              (lcdc_div - 1) << 8 | 2 << 6);
 339                 break;
 340         }
 341
 342         return 0;
 343 }
 344 #endif
 345
 346 #ifdef CONFIG_SPL_BUILD
 347 static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
 348 {
 349         u32 aclk_div;
 350         u32 hclk_div;
 351         u32 pclk_div;
 352
 353         /* pll enter slow-mode */
 354         rk_clrsetreg(&cru->cru_mode_con,
 355                      GPLL_MODE_MASK << GPLL_MODE_SHIFT |
 356                      CPLL_MODE_MASK << CPLL_MODE_SHIFT,
 357                      GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
 358                      CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
 359
 360         /* init pll */
 361         rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
 362         rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
 363
 364         /* waiting for pll lock */
 365         while ((readl(&grf->soc_status[1]) &
 366                         (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
 367                         (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
 368                 udelay(1);
 369
 370         /*
 371          * pd_bus clock pll source selection and
 372          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 373          */
 374         aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1;
 375         assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
 376         hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1;
 377         assert((hclk_div + 1) * PD_BUS_HCLK_HZ ==
 378                 PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2));
 379
 380         pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1;
 381         assert((pclk_div + 1) * PD_BUS_PCLK_HZ ==
 382                 PD_BUS_ACLK_HZ && pclk_div < 0x7);
 383
 384         rk_clrsetreg(&cru->cru_clksel_con[1],
 385                      PD_BUS_PCLK_DIV_MASK << PD_BUS_PCLK_DIV_SHIFT |
 386                      PD_BUS_HCLK_DIV_MASK << PD_BUS_HCLK_DIV_SHIFT |
 387                      PD_BUS_ACLK_DIV0_MASK << PD_BUS_ACLK_DIV0_SHIFT |
 388                      PD_BUS_ACLK_DIV1_MASK << PD_BUS_ACLK_DIV1_SHIFT,
 389                      pclk_div << PD_BUS_PCLK_DIV_SHIFT |
 390                      hclk_div << PD_BUS_HCLK_DIV_SHIFT |
 391                      aclk_div << PD_BUS_ACLK_DIV0_SHIFT |
 392                      0 << 0);
 393
 394         /*
 395          * peri clock pll source selection and
 396          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 397          */
 398         aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
 399         assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
 400
 401         hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
 402         assert((1 << hclk_div) * PERI_HCLK_HZ ==
 403                 PERI_ACLK_HZ && (hclk_div < 0x4));
 404
 405         pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
 406         assert((1 << pclk_div) * PERI_PCLK_HZ ==
 407                 PERI_ACLK_HZ && (pclk_div < 0x4));
 408
 409         rk_clrsetreg(&cru->cru_clksel_con[10],
 410                      PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT |
 411                      PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT |
 412                      PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT,
 413                      PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
 414                      pclk_div << PERI_PCLK_DIV_SHIFT |
 415                      hclk_div << PERI_HCLK_DIV_SHIFT |
 416                      aclk_div << PERI_ACLK_DIV_SHIFT);
 417
 418         /* PLL enter normal-mode */
 419         rk_clrsetreg(&cru->cru_mode_con,
 420                      GPLL_MODE_MASK << GPLL_MODE_SHIFT |
 421                      CPLL_MODE_MASK << CPLL_MODE_SHIFT,
 422                      GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
 423                      CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
 424 }
 425 #endif
 426
 427 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
 428 {
 429         /* pll enter slow-mode */
 430         rk_clrsetreg(&cru->cru_mode_con,
 431                      APLL_MODE_MASK << APLL_MODE_SHIFT,
 432                      APLL_MODE_SLOW << APLL_MODE_SHIFT);
 433
 434         rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
 435
 436         /* waiting for pll lock */
 437         while (!(readl(&grf->soc_status[1]) & SOCSTS_APLL_LOCK))
 438                 udelay(1);
 439
 440         /*
 441          * core clock pll source selection and
 442          * set up dependent divisors for MPAXI/M0AXI and ARM clocks.
 443          * core clock select apll, apll clk = 1800MHz
 444          * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz
 445          */
 446         rk_clrsetreg(&cru->cru_clksel_con[0],
 447                      CORE_SEL_PLL_MASK << CORE_SEL_PLL_SHIFT |
 448                      A17_DIV_MASK << A17_DIV_SHIFT |
 449                      MP_DIV_MASK << MP_DIV_SHIFT |
 450                      M0_DIV_MASK << M0_DIV_SHIFT,
 451                      0 << A17_DIV_SHIFT |
 452                      3 << MP_DIV_SHIFT |
 453                      1 << M0_DIV_SHIFT);
 454
 455         /*
 456          * set up dependent divisors for L2RAM/ATCLK and PCLK clocks.
 457          * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz
 458          */
 459         rk_clrsetreg(&cru->cru_clksel_con[37],
 460                      CLK_L2RAM_DIV_MASK << CLK_L2RAM_DIV_SHIFT |
 461                      ATCLK_CORE_DIV_CON_MASK << ATCLK_CORE_DIV_CON_SHIFT |
 462                      PCLK_CORE_DBG_DIV_MASK >> PCLK_CORE_DBG_DIV_SHIFT,
 463                      1 << CLK_L2RAM_DIV_SHIFT |
 464                      3 << ATCLK_CORE_DIV_CON_SHIFT |
 465                      3 << PCLK_CORE_DBG_DIV_SHIFT);
 466
 467         /* PLL enter normal-mode */
 468         rk_clrsetreg(&cru->cru_mode_con,
 469                      APLL_MODE_MASK << APLL_MODE_SHIFT,
 470                      APLL_MODE_NORMAL << APLL_MODE_SHIFT);
 471 }
 472
 473 /* Get pll rate by id */
 474 static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
 475                                    enum rk_clk_id clk_id)
 476 {
 477         uint32_t nr, no, nf;
 478         uint32_t con;
 479         int pll_id = rk_pll_id(clk_id);
 480         struct rk3288_pll *pll = &cru->pll[pll_id];
 481         static u8 clk_shift[CLK_COUNT] = {
 482                 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
 483                 GPLL_MODE_SHIFT, NPLL_MODE_SHIFT
 484         };
 485         uint shift;
 486
 487         con = readl(&cru->cru_mode_con);
 488         shift = clk_shift[clk_id];
 489         switch ((con >> shift) & APLL_MODE_MASK) {
 490         case APLL_MODE_SLOW:
 491                 return OSC_HZ;
 492         case APLL_MODE_NORMAL:
 493                 /* normal mode */
 494                 con = readl(&pll->con0);
 495                 no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1;
 496                 nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1;
 497                 con = readl(&pll->con1);
 498                 nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1;
 499
 500                 return (24 * nf / (nr * no)) * 1000000;
 501         case APLL_MODE_DEEP:
 502         default:
 503                 return 32768;
 504         }
 505 }
 506
 507 static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
 508                                   int periph)
 509 {
 510         uint src_rate;
 511         uint div, mux;
 512         u32 con;
 513
 514         switch (periph) {
 515         case HCLK_EMMC:
 516                 con = readl(&cru->cru_clksel_con[12]);
 517                 mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK;
 518                 div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
 519                 break;
 520         case HCLK_SDMMC:
 521                 con = readl(&cru->cru_clksel_con[11]);
 522                 mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK;
 523                 div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
 524                 break;
 525         case HCLK_SDIO0:
 526                 con = readl(&cru->cru_clksel_con[12]);
 527                 mux = (con >> SDIO0_PLL_SHIFT) & SDIO0_PLL_MASK;
 528                 div = (con >> SDIO0_DIV_SHIFT) & SDIO0_DIV_MASK;
 529                 break;
 530         default:
 531                 return -EINVAL;
 532         }
 533
 534         src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate;
 535         return DIV_TO_RATE(src_rate, div);
 536 }
 537
 538 static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
 539                                   int  periph, uint freq)
 540 {
 541         int src_clk_div;
 542         int mux;
 543
 544         debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
 545         src_clk_div = RATE_TO_DIV(gclk_rate, freq);
 546
 547         if (src_clk_div > 0x3f) {
 548                 src_clk_div = RATE_TO_DIV(OSC_HZ, freq);
 549                 mux = EMMC_PLL_SELECT_24MHZ;
 550                 assert((int)EMMC_PLL_SELECT_24MHZ ==
 551                        (int)MMC0_PLL_SELECT_24MHZ);
 552         } else {
 553                 mux = EMMC_PLL_SELECT_GENERAL;
 554                 assert((int)EMMC_PLL_SELECT_GENERAL ==
 555                        (int)MMC0_PLL_SELECT_GENERAL);
 556         }
 557         switch (periph) {
 558         case HCLK_EMMC:
 559                 rk_clrsetreg(&cru->cru_clksel_con[12],
 560                              EMMC_PLL_MASK << EMMC_PLL_SHIFT |
 561                              EMMC_DIV_MASK << EMMC_DIV_SHIFT,
 562                              mux << EMMC_PLL_SHIFT |
 563                              (src_clk_div - 1) << EMMC_DIV_SHIFT);
 564                 break;
 565         case HCLK_SDMMC:
 566                 rk_clrsetreg(&cru->cru_clksel_con[11],
 567                              MMC0_PLL_MASK << MMC0_PLL_SHIFT |
 568                              MMC0_DIV_MASK << MMC0_DIV_SHIFT,
 569                              mux << MMC0_PLL_SHIFT |
 570                              (src_clk_div - 1) << MMC0_DIV_SHIFT);
 571                 break;
 572         case HCLK_SDIO0:
 573                 rk_clrsetreg(&cru->cru_clksel_con[12],
 574                              SDIO0_PLL_MASK << SDIO0_PLL_SHIFT |
 575                              SDIO0_DIV_MASK << SDIO0_DIV_SHIFT,
 576                              mux << SDIO0_PLL_SHIFT |
 577                              (src_clk_div - 1) << SDIO0_DIV_SHIFT);
 578                 break;
 579         default:
 580                 return -EINVAL;
 581         }
 582
 583         return rockchip_mmc_get_clk(cru, gclk_rate, periph);
 584 }
 585
 586 static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
 587                                   int periph)
 588 {
 589         uint div, mux;
 590         u32 con;
 591
 592         switch (periph) {
 593         case SCLK_SPI0:
 594                 con = readl(&cru->cru_clksel_con[25]);
 595                 mux = (con >> SPI0_PLL_SHIFT) & SPI0_PLL_MASK;
 596                 div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK;
 597                 break;
 598         case SCLK_SPI1:
 599                 con = readl(&cru->cru_clksel_con[25]);
 600                 mux = (con >> SPI1_PLL_SHIFT) & SPI1_PLL_MASK;
 601                 div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK;
 602                 break;
 603         case SCLK_SPI2:
 604                 con = readl(&cru->cru_clksel_con[39]);
 605                 mux = (con >> SPI2_PLL_SHIFT) & SPI2_PLL_MASK;
 606                 div = (con >> SPI2_DIV_SHIFT) & SPI2_DIV_MASK;
 607                 break;
 608         default:
 609                 return -EINVAL;
 610         }
 611         assert(mux == SPI0_PLL_SELECT_GENERAL);
 612
 613         return DIV_TO_RATE(gclk_rate, div);
 614 }
 615
 616 static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
 617                                   int periph, uint freq)
 618 {
 619         int src_clk_div;
 620
 621         debug("%s: clk_general_rate=%u\n", __func__, gclk_rate);
 622         src_clk_div = RATE_TO_DIV(gclk_rate, freq);
 623         switch (periph) {
 624         case SCLK_SPI0:
 625                 rk_clrsetreg(&cru->cru_clksel_con[25],
 626                              SPI0_PLL_MASK << SPI0_PLL_SHIFT |
 627                              SPI0_DIV_MASK << SPI0_DIV_SHIFT,
 628                              SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT |
 629                              src_clk_div << SPI0_DIV_SHIFT);
 630                 break;
 631         case SCLK_SPI1:
 632                 rk_clrsetreg(&cru->cru_clksel_con[25],
 633                              SPI1_PLL_MASK << SPI1_PLL_SHIFT |
 634                              SPI1_DIV_MASK << SPI1_DIV_SHIFT,
 635                              SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT |
 636                              src_clk_div << SPI1_DIV_SHIFT);
 637                 break;
 638         case SCLK_SPI2:
 639                 rk_clrsetreg(&cru->cru_clksel_con[39],
 640                              SPI2_PLL_MASK << SPI2_PLL_SHIFT |
 641                              SPI2_DIV_MASK << SPI2_DIV_SHIFT,
 642                              SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT |
 643                              src_clk_div << SPI2_DIV_SHIFT);
 644                 break;
 645         default:
 646                 return -EINVAL;
 647         }
 648
 649         return rockchip_spi_get_clk(cru, gclk_rate, periph);
 650 }
 651
 652 static ulong rk3288_clk_get_rate(struct clk *clk)
 653 {
 654         struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
 655         ulong new_rate, gclk_rate;
 656
 657         gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
 658         switch (clk->id) {
 659         case 0 ... 63:
 660                 new_rate = rkclk_pll_get_rate(priv->cru, clk->id);
 661                 break;
 662         case HCLK_EMMC:
 663         case HCLK_SDMMC:
 664         case HCLK_SDIO0:
 665                 new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
 666                 break;
 667         case SCLK_SPI0:
 668         case SCLK_SPI1:
 669         case SCLK_SPI2:
 670                 new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id);
 671                 break;
 672         case PCLK_I2C0:
 673         case PCLK_I2C1:
 674         case PCLK_I2C2:
 675         case PCLK_I2C3:
 676         case PCLK_I2C4:
 677         case PCLK_I2C5:
 678                 return gclk_rate;
 679         case PCLK_PWM:
 680                 return PD_BUS_PCLK_HZ;
 681         default:
 682                 return -ENOENT;
 683         }
 684
 685         return new_rate;
 686 }
 687
 688 static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
 689 {
 690         struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
 691         struct rk3288_cru *cru = priv->cru;
 692         ulong new_rate, gclk_rate;
 693
 694         gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
 695         switch (clk->id) {
 696         case PLL_APLL:
 697                 /* We only support a fixed rate here */
 698                 if (rate != 1800000000)
 699                         return -EINVAL;
 700                 rk3288_clk_configure_cpu(priv->cru, priv->grf);
 701                 new_rate = rate;
 702                 break;
 703         case CLK_DDR:
 704                 new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate);
 705                 break;
 706         case HCLK_EMMC:
 707         case HCLK_SDMMC:
 708         case HCLK_SDIO0:
 709                 new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate);
 710                 break;
 711         case SCLK_SPI0:
 712         case SCLK_SPI1:
 713         case SCLK_SPI2:
 714                 new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate);
 715                 break;
 716 #ifndef CONFIG_SPL_BUILD
 717         case SCLK_MAC:
 718                 new_rate = rockchip_mac_set_clk(priv->cru, clk->id, rate);
 719                 break;
 720         case DCLK_VOP0:
 721         case DCLK_VOP1:
 722                 new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate);
 723                 break;
 724         case SCLK_EDP_24M:
 725                 /* clk_edp_24M source: 24M */
 726                 rk_setreg(&cru->cru_clksel_con[28], 1 << 15);
 727
 728                 /* rst edp */
 729                 rk_setreg(&cru->cru_clksel_con[6], 1 << 15);
 730                 udelay(1);
 731                 rk_clrreg(&cru->cru_clksel_con[6], 1 << 15);
 732                 new_rate = rate;
 733                 break;
 734         case ACLK_VOP0:
 735         case ACLK_VOP1: {
 736                 u32 div;
 737
 738                 /* vop aclk source clk: cpll */
 739                 div = CPLL_HZ / rate;
 740                 assert((div - 1 < 64) && (div * rate == CPLL_HZ));
 741
 742                 switch (clk->id) {
 743                 case ACLK_VOP0:
 744                         rk_clrsetreg(&cru->cru_clksel_con[31],
 745                                      3 << 6 | 0x1f << 0,
 746                                      0 << 6 | (div - 1) << 0);
 747                         break;
 748                 case ACLK_VOP1:
 749                         rk_clrsetreg(&cru->cru_clksel_con[31],
 750                                      3 << 14 | 0x1f << 8,
 751                                      0 << 14 | (div - 1) << 8);
 752                         break;
 753                 }
 754                 new_rate = rate;
 755                 break;
 756         }
 757         case PCLK_HDMI_CTRL:
 758                 /* enable pclk hdmi ctrl */
 759                 rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9);
 760
 761                 /* software reset hdmi */
 762                 rk_setreg(&cru->cru_clkgate_con[7], 1 << 9);
 763                 udelay(1);
 764                 rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9);
 765                 new_rate = rate;
 766                 break;
 767 #endif
 768         default:
 769                 return -ENOENT;
 770         }
 771
 772         return new_rate;
 773 }
 774
 775 static struct clk_ops rk3288_clk_ops = {
 776         .get_rate       = rk3288_clk_get_rate,
 777         .set_rate       = rk3288_clk_set_rate,
 778 };
 779
 780 static int rk3288_clk_ofdata_to_platdata(struct udevice *dev)
 781 {
 782 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 783         struct rk3288_clk_priv *priv = dev_get_priv(dev);
 784
 785         priv->cru = (struct rk3288_cru *)dev_get_addr(dev);
 786 #endif
 787
 788         return 0;
 789 }
 790
 791 static int rk3288_clk_probe(struct udevice *dev)
 792 {
 793         struct rk3288_clk_priv *priv = dev_get_priv(dev);
 794
 795         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 796         if (IS_ERR(priv->grf))
 797                 return PTR_ERR(priv->grf);
 798 #ifdef CONFIG_SPL_BUILD
 799 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 800         struct rk3288_clk_plat *plat = dev_get_platdata(dev);
 801
 802         priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
 803 #endif
 804         rkclk_init(priv->cru, priv->grf);
 805 #endif
 806
 807         return 0;
 808 }
 809
 810 static int rk3288_clk_bind(struct udevice *dev)
 811 {
 812         int ret;
 813
 814         /* The reset driver does not have a device node, so bind it here */
 815         ret = device_bind_driver(gd->dm_root, "rk3288_sysreset", "reset", &dev);
 816         if (ret)
 817                 debug("Warning: No RK3288 reset driver: ret=%d\n", ret);
 818
 819         return 0;
 820 }
 821
 822 static const struct udevice_id rk3288_clk_ids[] = {
 823         { .compatible = "rockchip,rk3288-cru" },
 824         { }
 825 };
 826
 827 U_BOOT_DRIVER(rockchip_rk3288_cru) = {
 828         .name           = "rockchip_rk3288_cru",
 829         .id             = UCLASS_CLK,
 830         .of_match       = rk3288_clk_ids,
 831         .priv_auto_alloc_size = sizeof(struct rk3288_clk_priv),
 832         .platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat),
 833         .ops            = &rk3288_clk_ops,
 834         .bind           = rk3288_clk_bind,
 835         .ofdata_to_platdata     = rk3288_clk_ofdata_to_platdata,
 836         .probe          = rk3288_clk_probe,
 837 };