1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) 2014 MundoReader S.L.
4 * Author: Heiko Stuebner <heiko@sntech.de>
6 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
12 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
13 * Copyright (c) 2013 Linaro Ltd.
14 * Author: Thomas Abraham <thomas.ab@samsung.com>
17 #ifndef CLK_ROCKCHIP_CLK_H
18 #define CLK_ROCKCHIP_CLK_H
21 #include <linux/clk-provider.h>
25 #define HIWORD_UPDATE(val, mask, shift) \
26 ((val) << (shift) | (mask) << ((shift) + 16))
28 /* register positions shared by PX30, RV1108, RK2928, RK3036, RK3066, RK3188 and RK3228 */
29 #define BOOST_PLL_H_CON(x) ((x) * 0x4)
30 #define BOOST_CLK_CON 0x0008
31 #define BOOST_BOOST_CON 0x000c
32 #define BOOST_SWITCH_CNT 0x0010
33 #define BOOST_HIGH_PERF_CNT0 0x0014
34 #define BOOST_HIGH_PERF_CNT1 0x0018
35 #define BOOST_STATIS_THRESHOLD 0x001c
36 #define BOOST_SHORT_SWITCH_CNT 0x0020
37 #define BOOST_SWITCH_THRESHOLD 0x0024
38 #define BOOST_FSM_STATUS 0x0028
39 #define BOOST_PLL_L_CON(x) ((x) * 0x4 + 0x2c)
40 #define BOOST_RECOVERY_MASK 0x1
41 #define BOOST_RECOVERY_SHIFT 1
42 #define BOOST_SW_CTRL_MASK 0x1
43 #define BOOST_SW_CTRL_SHIFT 2
44 #define BOOST_LOW_FREQ_EN_MASK 0x1
45 #define BOOST_LOW_FREQ_EN_SHIFT 3
46 #define BOOST_BUSY_STATE BIT(8)
48 #define PX30_PLL_CON(x) ((x) * 0x4)
49 #define PX30_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
50 #define PX30_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
51 #define PX30_GLB_SRST_FST 0xb8
52 #define PX30_GLB_SRST_SND 0xbc
53 #define PX30_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
54 #define PX30_MODE_CON 0xa0
55 #define PX30_MISC_CON 0xa4
56 #define PX30_SDMMC_CON0 0x380
57 #define PX30_SDMMC_CON1 0x384
58 #define PX30_SDIO_CON0 0x388
59 #define PX30_SDIO_CON1 0x38c
60 #define PX30_EMMC_CON0 0x390
61 #define PX30_EMMC_CON1 0x394
63 #define PX30_PMU_PLL_CON(x) ((x) * 0x4)
64 #define PX30_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x40)
65 #define PX30_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x80)
66 #define PX30_PMU_MODE 0x0020
68 #define RV1108_PLL_CON(x) ((x) * 0x4)
69 #define RV1108_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
70 #define RV1108_CLKGATE_CON(x) ((x) * 0x4 + 0x120)
71 #define RV1108_SOFTRST_CON(x) ((x) * 0x4 + 0x180)
72 #define RV1108_GLB_SRST_FST 0x1c0
73 #define RV1108_GLB_SRST_SND 0x1c4
74 #define RV1108_MISC_CON 0x1cc
75 #define RV1108_SDMMC_CON0 0x1d8
76 #define RV1108_SDMMC_CON1 0x1dc
77 #define RV1108_SDIO_CON0 0x1e0
78 #define RV1108_SDIO_CON1 0x1e4
79 #define RV1108_EMMC_CON0 0x1e8
80 #define RV1108_EMMC_CON1 0x1ec
82 #define RV1126_PMU_MODE 0x0
83 #define RV1126_PMU_PLL_CON(x) ((x) * 0x4 + 0x10)
84 #define RV1126_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
85 #define RV1126_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180)
86 #define RV1126_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200)
87 #define RV1126_PLL_CON(x) ((x) * 0x4)
88 #define RV1126_MODE_CON 0x90
89 #define RV1126_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
90 #define RV1126_CLKGATE_CON(x) ((x) * 0x4 + 0x280)
91 #define RV1126_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
92 #define RV1126_GLB_SRST_FST 0x408
93 #define RV1126_GLB_SRST_SND 0x40c
94 #define RV1126_SDMMC_CON0 0x440
95 #define RV1126_SDMMC_CON1 0x444
96 #define RV1126_SDIO_CON0 0x448
97 #define RV1126_SDIO_CON1 0x44c
98 #define RV1126_EMMC_CON0 0x450
99 #define RV1126_EMMC_CON1 0x454
101 #define RK2928_PLL_CON(x) ((x) * 0x4)
102 #define RK2928_MODE_CON 0x40
103 #define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
104 #define RK2928_CLKGATE_CON(x) ((x) * 0x4 + 0xd0)
105 #define RK2928_GLB_SRST_FST 0x100
106 #define RK2928_GLB_SRST_SND 0x104
107 #define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
108 #define RK2928_MISC_CON 0x134
110 #define RK3036_SDMMC_CON0 0x144
111 #define RK3036_SDMMC_CON1 0x148
112 #define RK3036_SDIO_CON0 0x14c
113 #define RK3036_SDIO_CON1 0x150
114 #define RK3036_EMMC_CON0 0x154
115 #define RK3036_EMMC_CON1 0x158
117 #define RK3228_GLB_SRST_FST 0x1f0
118 #define RK3228_GLB_SRST_SND 0x1f4
119 #define RK3228_SDMMC_CON0 0x1c0
120 #define RK3228_SDMMC_CON1 0x1c4
121 #define RK3228_SDIO_CON0 0x1c8
122 #define RK3228_SDIO_CON1 0x1cc
123 #define RK3228_EMMC_CON0 0x1d8
124 #define RK3228_EMMC_CON1 0x1dc
126 #define RK3288_PLL_CON(x) RK2928_PLL_CON(x)
127 #define RK3288_MODE_CON 0x50
128 #define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
129 #define RK3288_CLKGATE_CON(x) ((x) * 0x4 + 0x160)
130 #define RK3288_GLB_SRST_FST 0x1b0
131 #define RK3288_GLB_SRST_SND 0x1b4
132 #define RK3288_SOFTRST_CON(x) ((x) * 0x4 + 0x1b8)
133 #define RK3288_MISC_CON 0x1e8
134 #define RK3288_SDMMC_CON0 0x200
135 #define RK3288_SDMMC_CON1 0x204
136 #define RK3288_SDIO0_CON0 0x208
137 #define RK3288_SDIO0_CON1 0x20c
138 #define RK3288_SDIO1_CON0 0x210
139 #define RK3288_SDIO1_CON1 0x214
140 #define RK3288_EMMC_CON0 0x218
141 #define RK3288_EMMC_CON1 0x21c
143 #define RK3308_PLL_CON(x) RK2928_PLL_CON(x)
144 #define RK3308_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
145 #define RK3308_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
146 #define RK3308_GLB_SRST_FST 0xb8
147 #define RK3308_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
148 #define RK3308_MODE_CON 0xa0
149 #define RK3308_SDMMC_CON0 0x480
150 #define RK3308_SDMMC_CON1 0x484
151 #define RK3308_SDIO_CON0 0x488
152 #define RK3308_SDIO_CON1 0x48c
153 #define RK3308_EMMC_CON0 0x490
154 #define RK3308_EMMC_CON1 0x494
156 #define RK3328_PLL_CON(x) RK2928_PLL_CON(x)
157 #define RK3328_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
158 #define RK3328_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
159 #define RK3328_GRFCLKSEL_CON(x) ((x) * 0x4 + 0x100)
160 #define RK3328_GLB_SRST_FST 0x9c
161 #define RK3328_GLB_SRST_SND 0x98
162 #define RK3328_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
163 #define RK3328_MODE_CON 0x80
164 #define RK3328_MISC_CON 0x84
165 #define RK3328_SDMMC_CON0 0x380
166 #define RK3328_SDMMC_CON1 0x384
167 #define RK3328_SDIO_CON0 0x388
168 #define RK3328_SDIO_CON1 0x38c
169 #define RK3328_EMMC_CON0 0x390
170 #define RK3328_EMMC_CON1 0x394
171 #define RK3328_SDMMC_EXT_CON0 0x398
172 #define RK3328_SDMMC_EXT_CON1 0x39C
174 #define RK3368_PLL_CON(x) RK2928_PLL_CON(x)
175 #define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
176 #define RK3368_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
177 #define RK3368_GLB_SRST_FST 0x280
178 #define RK3368_GLB_SRST_SND 0x284
179 #define RK3368_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
180 #define RK3368_MISC_CON 0x380
181 #define RK3368_SDMMC_CON0 0x400
182 #define RK3368_SDMMC_CON1 0x404
183 #define RK3368_SDIO0_CON0 0x408
184 #define RK3368_SDIO0_CON1 0x40c
185 #define RK3368_SDIO1_CON0 0x410
186 #define RK3368_SDIO1_CON1 0x414
187 #define RK3368_EMMC_CON0 0x418
188 #define RK3368_EMMC_CON1 0x41c
190 #define RK3399_PLL_CON(x) RK2928_PLL_CON(x)
191 #define RK3399_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
192 #define RK3399_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
193 #define RK3399_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
194 #define RK3399_GLB_SRST_FST 0x500
195 #define RK3399_GLB_SRST_SND 0x504
196 #define RK3399_GLB_CNT_TH 0x508
197 #define RK3399_MISC_CON 0x50c
198 #define RK3399_RST_CON 0x510
199 #define RK3399_RST_ST 0x514
200 #define RK3399_SDMMC_CON0 0x580
201 #define RK3399_SDMMC_CON1 0x584
202 #define RK3399_SDIO_CON0 0x588
203 #define RK3399_SDIO_CON1 0x58c
205 #define RK3399_PMU_PLL_CON(x) RK2928_PLL_CON(x)
206 #define RK3399_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x80)
207 #define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100)
208 #define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
210 #define RK3568_PLL_CON(x) RK2928_PLL_CON(x)
211 #define RK3568_MODE_CON0 0xc0
212 #define RK3568_MISC_CON0 0xc4
213 #define RK3568_MISC_CON1 0xc8
214 #define RK3568_MISC_CON2 0xcc
215 #define RK3568_GLB_CNT_TH 0xd0
216 #define RK3568_GLB_SRST_FST 0xd4
217 #define RK3568_GLB_SRST_SND 0xd8
218 #define RK3568_GLB_RST_CON 0xdc
219 #define RK3568_GLB_RST_ST 0xe0
220 #define RK3568_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
221 #define RK3568_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
222 #define RK3568_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
223 #define RK3568_SDMMC0_CON0 0x580
224 #define RK3568_SDMMC0_CON1 0x584
225 #define RK3568_SDMMC1_CON0 0x588
226 #define RK3568_SDMMC1_CON1 0x58c
227 #define RK3568_SDMMC2_CON0 0x590
228 #define RK3568_SDMMC2_CON1 0x594
229 #define RK3568_EMMC_CON0 0x598
230 #define RK3568_EMMC_CON1 0x59c
232 #define RK3568_PMU_PLL_CON(x) RK2928_PLL_CON(x)
233 #define RK3568_PMU_MODE_CON0 0x80
234 #define RK3568_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
235 #define RK3568_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180)
236 #define RK3568_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200)
238 enum rockchip_pll_type {
245 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
246 _postdiv2, _dsmpd, _frac) \
250 .postdiv1 = _postdiv1, \
252 .postdiv2 = _postdiv2, \
257 #define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \
263 .nb = ((_nf) < 2) ? 1 : (_nf) >> 1, \
266 #define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb) \
276 * struct rockchip_clk_provider - information about clock provider
277 * @reg_base: virtual address for the register base.
278 * @clk_data: holds clock related data like clk* and number of clocks.
279 * @cru_node: device-node of the clock-provider
280 * @grf: regmap of the general-register-files syscon
281 * @lock: maintains exclusion between callbacks for a given clock-provider.
283 struct rockchip_clk_provider {
284 void __iomem *reg_base;
285 struct clk_onecell_data clk_data;
286 struct device_node *cru_node;
291 struct rockchip_pll_rate_table {
302 /* for RK3036/RK3399 */
304 unsigned int postdiv1;
306 unsigned int postdiv2;
314 * struct rockchip_pll_clock - information about pll clock
315 * @id: platform specific id of the clock.
316 * @name: name of this pll clock.
317 * @parent_names: name of the parent clock.
318 * @num_parents: number of parents
319 * @flags: optional flags for basic clock.
320 * @con_offset: offset of the register for configuring the PLL.
321 * @mode_offset: offset of the register for configuring the PLL-mode.
322 * @mode_shift: offset inside the mode-register for the mode of this pll.
323 * @lock_shift: offset inside the lock register for the lock status.
324 * @type: Type of PLL to be registered.
325 * @pll_flags: hardware-specific flags
326 * @rate_table: Table of usable pll rates
329 * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
330 * rate_table parameters and ajust them if necessary.
332 struct rockchip_pll_clock {
335 const char *const *parent_names;
342 enum rockchip_pll_type type;
344 struct rockchip_pll_rate_table *rate_table;
347 #define ROCKCHIP_PLL_SYNC_RATE BIT(0)
349 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
350 _lshift, _pflags, _rtable) \
355 .parent_names = _pnames, \
356 .num_parents = ARRAY_SIZE(_pnames), \
357 .flags = CLK_GET_RATE_NOCACHE | _flags, \
358 .con_offset = _con, \
359 .mode_offset = _mode, \
360 .mode_shift = _mshift, \
361 .lock_shift = _lshift, \
362 .pll_flags = _pflags, \
363 .rate_table = _rtable, \
366 struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
367 enum rockchip_pll_type pll_type,
368 const char *name, const char *const *parent_names,
369 u8 num_parents, int con_offset, int grf_lock_offset,
370 int lock_shift, int mode_offset, int mode_shift,
371 struct rockchip_pll_rate_table *rate_table,
372 unsigned long flags, u8 clk_pll_flags);
374 struct rockchip_cpuclk_clksel {
379 #define ROCKCHIP_CPUCLK_NUM_DIVIDERS 5
380 #define ROCKCHIP_CPUCLK_MAX_CORES 4
381 struct rockchip_cpuclk_rate_table {
383 struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
387 * struct rockchip_cpuclk_reg_data - register offsets and masks of the cpuclock
388 * @core_reg[]: register offset of the cores setting register
389 * @div_core_shift[]: cores divider offset used to divide the pll value
390 * @div_core_mask[]: cores divider mask
391 * @num_cores: number of cpu cores
392 * @mux_core_main: mux value to select main parent of core
393 * @mux_core_shift: offset of the core multiplexer
394 * @mux_core_mask: core multiplexer mask
396 struct rockchip_cpuclk_reg_data {
397 int core_reg[ROCKCHIP_CPUCLK_MAX_CORES];
398 u8 div_core_shift[ROCKCHIP_CPUCLK_MAX_CORES];
399 u32 div_core_mask[ROCKCHIP_CPUCLK_MAX_CORES];
407 struct clk *rockchip_clk_register_cpuclk(const char *name,
408 const char *const *parent_names, u8 num_parents,
409 const struct rockchip_cpuclk_reg_data *reg_data,
410 const struct rockchip_cpuclk_rate_table *rates,
411 int nrates, void __iomem *reg_base, spinlock_t *lock);
413 struct clk *rockchip_clk_register_mmc(const char *name,
414 const char *const *parent_names, u8 num_parents,
415 void __iomem *reg, int shift);
418 * DDRCLK flags, including method of setting the rate
419 * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate.
421 #define ROCKCHIP_DDRCLK_SIP BIT(0)
423 struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
424 const char *const *parent_names,
425 u8 num_parents, int mux_offset,
426 int mux_shift, int mux_width,
427 int div_shift, int div_width,
428 int ddr_flags, void __iomem *reg_base,
431 #define ROCKCHIP_INVERTER_HIWORD_MASK BIT(0)
433 struct clk *rockchip_clk_register_inverter(const char *name,
434 const char *const *parent_names, u8 num_parents,
435 void __iomem *reg, int shift, int flags,
438 struct clk *rockchip_clk_register_muxgrf(const char *name,
439 const char *const *parent_names, u8 num_parents,
440 int flags, struct regmap *grf, int reg,
441 int shift, int width, int mux_flags);
443 #define PNAME(x) static const char *const x[] __initconst
445 enum rockchip_clk_branch_type {
450 branch_fraction_divider,
459 struct rockchip_clk_branch {
461 enum rockchip_clk_branch_type branch_type;
463 const char *const *parent_names;
475 struct clk_div_table *div_table;
479 struct rockchip_clk_branch *child;
482 #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
486 .branch_type = branch_composite, \
488 .parent_names = pnames, \
489 .num_parents = ARRAY_SIZE(pnames), \
491 .muxdiv_offset = mo, \
503 #define COMPOSITE_DIV_OFFSET(_id, cname, pnames, f, mo, ms, mw, \
504 mf, do, ds, dw, df, go, gs, gf) \
507 .branch_type = branch_composite, \
509 .parent_names = pnames, \
510 .num_parents = ARRAY_SIZE(pnames), \
512 .muxdiv_offset = mo, \
525 #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \
529 .branch_type = branch_composite, \
531 .parent_names = (const char *[]){ pname }, \
534 .muxdiv_offset = mo, \
543 #define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\
544 df, dt, go, gs, gf) \
547 .branch_type = branch_composite, \
549 .parent_names = (const char *[]){ pname }, \
552 .muxdiv_offset = mo, \
562 #define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf, \
566 .branch_type = branch_composite, \
568 .parent_names = pnames, \
569 .num_parents = ARRAY_SIZE(pnames), \
571 .muxdiv_offset = mo, \
580 #define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \
584 .branch_type = branch_composite, \
586 .parent_names = pnames, \
587 .num_parents = ARRAY_SIZE(pnames), \
589 .muxdiv_offset = mo, \
599 #define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms, \
600 mw, mf, ds, dw, df, dt) \
603 .branch_type = branch_composite, \
605 .parent_names = pnames, \
606 .num_parents = ARRAY_SIZE(pnames), \
608 .muxdiv_offset = mo, \
619 #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
622 .branch_type = branch_fraction_divider, \
624 .parent_names = (const char *[]){ pname }, \
627 .muxdiv_offset = mo, \
636 #define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \
639 .branch_type = branch_fraction_divider, \
641 .parent_names = (const char *[]){ pname }, \
644 .muxdiv_offset = mo, \
654 #define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch) \
657 .branch_type = branch_fraction_divider, \
659 .parent_names = (const char *[]){ pname }, \
662 .muxdiv_offset = mo, \
670 #define COMPOSITE_DDRCLK(_id, cname, pnames, f, mo, ms, mw, \
674 .branch_type = branch_ddrclk, \
676 .parent_names = pnames, \
677 .num_parents = ARRAY_SIZE(pnames), \
679 .muxdiv_offset = mo, \
688 #define MUX(_id, cname, pnames, f, o, s, w, mf) \
691 .branch_type = branch_mux, \
693 .parent_names = pnames, \
694 .num_parents = ARRAY_SIZE(pnames), \
696 .muxdiv_offset = o, \
703 #define MUXTBL(_id, cname, pnames, f, o, s, w, mf, mt) \
706 .branch_type = branch_mux, \
708 .parent_names = pnames, \
709 .num_parents = ARRAY_SIZE(pnames), \
711 .muxdiv_offset = o, \
719 #define MUXGRF(_id, cname, pnames, f, o, s, w, mf) \
722 .branch_type = branch_muxgrf, \
724 .parent_names = pnames, \
725 .num_parents = ARRAY_SIZE(pnames), \
727 .muxdiv_offset = o, \
734 #define DIV(_id, cname, pname, f, o, s, w, df) \
737 .branch_type = branch_divider, \
739 .parent_names = (const char *[]){ pname }, \
742 .muxdiv_offset = o, \
749 #define DIVTBL(_id, cname, pname, f, o, s, w, df, dt) \
752 .branch_type = branch_divider, \
754 .parent_names = (const char *[]){ pname }, \
757 .muxdiv_offset = o, \
764 #define GATE(_id, cname, pname, f, o, b, gf) \
767 .branch_type = branch_gate, \
769 .parent_names = (const char *[]){ pname }, \
777 #define MMC(_id, cname, pname, offset, shift) \
780 .branch_type = branch_mmc, \
782 .parent_names = (const char *[]){ pname }, \
784 .muxdiv_offset = offset, \
785 .div_shift = shift, \
788 #define INVERTER(_id, cname, pname, io, is, if) \
791 .branch_type = branch_inverter, \
793 .parent_names = (const char *[]){ pname }, \
795 .muxdiv_offset = io, \
800 #define FACTOR(_id, cname, pname, f, fm, fd) \
803 .branch_type = branch_factor, \
805 .parent_names = (const char *[]){ pname }, \
812 #define FACTOR_GATE(_id, cname, pname, f, fm, fd, go, gb, gf) \
815 .branch_type = branch_factor, \
817 .parent_names = (const char *[]){ pname }, \
827 #define COMPOSITE_HALFDIV(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
831 .branch_type = branch_half_divider, \
833 .parent_names = pnames, \
834 .num_parents = ARRAY_SIZE(pnames), \
836 .muxdiv_offset = mo, \
848 #define COMPOSITE_NOGATE_HALFDIV(_id, cname, pnames, f, mo, ms, mw, mf, \
852 .branch_type = branch_half_divider, \
854 .parent_names = pnames, \
855 .num_parents = ARRAY_SIZE(pnames), \
857 .muxdiv_offset = mo, \
867 #define COMPOSITE_NOMUX_HALFDIV(_id, cname, pname, f, mo, ds, dw, df, \
871 .branch_type = branch_half_divider, \
873 .parent_names = (const char *[]){ pname }, \
876 .muxdiv_offset = mo, \
885 #define DIV_HALF(_id, cname, pname, f, o, s, w, df) \
888 .branch_type = branch_half_divider, \
890 .parent_names = (const char *[]){ pname }, \
893 .muxdiv_offset = o, \
900 /* SGRF clocks are only accessible from secure mode, so not controllable */
901 #define SGRF_GATE(_id, cname, pname) \
902 FACTOR(_id, cname, pname, 0, 1, 1)
904 struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
905 void __iomem *base, unsigned long nr_clks);
906 void rockchip_clk_of_add_provider(struct device_node *np,
907 struct rockchip_clk_provider *ctx);
908 void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
909 struct clk *clk, unsigned int id);
910 void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
911 struct rockchip_clk_branch *list,
912 unsigned int nr_clk);
913 void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
914 struct rockchip_pll_clock *pll_list,
915 unsigned int nr_pll, int grf_lock_offset);
916 void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
917 unsigned int lookup_id, const char *name,
918 const char *const *parent_names, u8 num_parents,
919 const struct rockchip_cpuclk_reg_data *reg_data,
920 const struct rockchip_cpuclk_rate_table *rates,
922 void rockchip_clk_protect_critical(const char *const clocks[], int nclocks);
923 void rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
924 unsigned int reg, void (*cb)(void));
926 #define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0)
928 struct clk *rockchip_clk_register_halfdiv(const char *name,
929 const char *const *parent_names,
930 u8 num_parents, void __iomem *base,
931 int muxdiv_offset, u8 mux_shift,
932 u8 mux_width, u8 mux_flags,
933 u8 div_shift, u8 div_width,
934 u8 div_flags, int gate_offset,
935 u8 gate_shift, u8 gate_flags,
939 #ifdef CONFIG_RESET_CONTROLLER
940 void rockchip_register_softrst(struct device_node *np,
941 unsigned int num_regs,
942 void __iomem *base, u8 flags);
944 static inline void rockchip_register_softrst(struct device_node *np,
945 unsigned int num_regs,
946 void __iomem *base, u8 flags)