2 * R-Car Gen3 Clock Pulse Generator
4 * Copyright (C) 2015-2016 Glider bvba
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
11 #ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__
12 #define __CLK_RENESAS_RCAR_GEN3_CPG_H__
14 enum rcar_gen3_clk_types {
15 CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
23 CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */
26 CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
27 CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
32 /* SoC specific definitions start here */
33 CLK_TYPE_GEN3_SOC_BASE,
36 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \
37 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
39 #define DEF_GEN3_RPC(_name, _id, _parent, _offset) \
40 DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset)
42 #define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
43 DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
44 (_parent0) << 16 | (_parent1), \
45 .div = (_div0) << 16 | (_div1), .offset = _md)
47 #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
49 DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \
50 _parent_clean, _div_clean)
52 #define DEF_GEN3_OSC(_name, _id, _parent, _div) \
53 DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
55 #define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \
56 DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \
57 (_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1))
60 struct rcar_gen3_cpg_pll_config {
69 #define CPG_RPCCKCR 0x238
70 #define CPG_RCKCR 0x240
72 struct gen3_clk_priv {
74 struct cpg_mssr_info *info;
76 struct clk clk_extalr;
78 const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
81 int gen3_clk_probe(struct udevice *dev);
82 int gen3_clk_remove(struct udevice *dev);
84 extern const struct clk_ops gen3_clk_ops;