drivers/clk/renesas/r9a07g044-cpg.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * RZ/G2L CPG driver
   4  *
   5  * Copyright (C) 2021 Renesas Electronics Corp.
   6  */
   7
   8 #include <linux/clk-provider.h>
   9 #include <linux/device.h>
  10 #include <linux/init.h>
  11 #include <linux/kernel.h>
  12
  13 #include <dt-bindings/clock/r9a07g044-cpg.h>
  14 #include <dt-bindings/clock/r9a07g054-cpg.h>
  15
  16 #include "rzg2l-cpg.h"
  17
  18 enum clk_ids {
  19         /* Core Clock Outputs exported to DT */
  20         LAST_DT_CORE_CLK = R9A07G054_CLK_DRP_A,
  21
  22         /* External Input Clocks */
  23         CLK_EXTAL,
  24
  25         /* Internal Core Clocks */
  26         CLK_OSC_DIV1000,
  27         CLK_PLL1,
  28         CLK_PLL2,
  29         CLK_PLL2_DIV2,
  30         CLK_PLL2_DIV2_8,
  31         CLK_PLL2_DIV2_10,
  32         CLK_PLL3,
  33         CLK_PLL3_400,
  34         CLK_PLL3_533,
  35         CLK_PLL3_DIV2,
  36         CLK_PLL3_DIV2_2,
  37         CLK_PLL3_DIV2_4,
  38         CLK_PLL3_DIV2_4_2,
  39         CLK_SEL_PLL3_3,
  40         CLK_DIV_PLL3_C,
  41         CLK_PLL4,
  42         CLK_PLL5,
  43         CLK_PLL5_FOUT3,
  44         CLK_PLL5_250,
  45         CLK_PLL6,
  46         CLK_PLL6_250,
  47         CLK_P1_DIV2,
  48         CLK_PLL2_800,
  49         CLK_PLL2_SDHI_533,
  50         CLK_PLL2_SDHI_400,
  51         CLK_PLL2_SDHI_266,
  52         CLK_SD0_DIV4,
  53         CLK_SD1_DIV4,
  54         CLK_SEL_GPU2,
  55
  56         /* Module Clocks */
  57         MOD_CLK_BASE,
  58 };
  59
  60 /* Divider tables */
  61 static const struct clk_div_table dtable_1_8[] = {
  62         {0, 1},
  63         {1, 2},
  64         {2, 4},
  65         {3, 8},
  66         {0, 0},
  67 };
  68
  69 static const struct clk_div_table dtable_1_32[] = {
  70         {0, 1},
  71         {1, 2},
  72         {2, 4},
  73         {3, 8},
  74         {4, 32},
  75         {0, 0},
  76 };
  77
  78 /* Mux clock tables */
  79 static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
  80 static const char * const sel_pll6_2[]  = { ".pll6_250", ".pll5_250" };
  81 static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };
  82 static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" };
  83
  84 static const struct {
  85         struct cpg_core_clk common[44];
  86 #ifdef CONFIG_CLK_R9A07G054
  87         struct cpg_core_clk drp[0];
  88 #endif
  89 } core_clks __initconst = {
  90         .common = {
  91                 /* External Clock Inputs */
  92                 DEF_INPUT("extal", CLK_EXTAL),
  93
  94                 /* Internal Core Clocks */
  95                 DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1),
  96                 DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
  97                 DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
  98                 DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
  99                 DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
 100                 DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4),
 101                 DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3),
 102
 103                 DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),
 104                 DEF_FIXED(".pll5_fout3", CLK_PLL5_FOUT3, CLK_PLL5, 1, 6),
 105
 106                 DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),
 107
 108                 DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
 109                 DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2),
 110                 DEF_FIXED(".clk_533", CLK_PLL2_SDHI_533, CLK_PLL2, 1, 3),
 111                 DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2),
 112                 DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2),
 113
 114                 DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8),
 115                 DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10),
 116
 117                 DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
 118                 DEF_FIXED(".pll3_div2_2", CLK_PLL3_DIV2_2, CLK_PLL3_DIV2, 1, 2),
 119                 DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
 120                 DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
 121                 DEF_MUX(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3,
 122                         sel_pll3_3, ARRAY_SIZE(sel_pll3_3), 0, CLK_MUX_READ_ONLY),
 123                 DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3,
 124                         DIVPL3C, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
 125
 126                 DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2),
 127                 DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
 128                 DEF_MUX(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2,
 129                         sel_gpu2, ARRAY_SIZE(sel_gpu2), 0, CLK_MUX_READ_ONLY),
 130
 131                 /* Core output clk */
 132                 DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8,
 133                         CLK_DIVIDER_HIWORD_MASK),
 134                 DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A,
 135                         dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
 136                 DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2),
 137                 DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1),
 138                 DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4,
 139                         DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
 140                 DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2),
 141                 DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2,
 142                         DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
 143                 DEF_FIXED("M0", R9A07G044_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),
 144                 DEF_FIXED("ZT", R9A07G044_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),
 145                 DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2,
 146                         sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, CLK_MUX_HIWORD_MASK),
 147                 DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
 148                 DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
 149                 DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0,
 150                            sel_shdi, ARRAY_SIZE(sel_shdi)),
 151                 DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1,
 152                            sel_shdi, ARRAY_SIZE(sel_shdi)),
 153                 DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4),
 154                 DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4),
 155                 DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8,
 156                         CLK_DIVIDER_HIWORD_MASK),
 157         },
 158 #ifdef CONFIG_CLK_R9A07G054
 159         .drp = {
 160         },
 161 #endif
 162 };
 163
 164 static const struct {
 165         struct rzg2l_mod_clk common[62];
 166 #ifdef CONFIG_CLK_R9A07G054
 167         struct rzg2l_mod_clk drp[0];
 168 #endif
 169 } mod_clks = {
 170         .common = {
 171                 DEF_MOD("gic",          R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1,
 172                                         0x514, 0),
 173                 DEF_MOD("ia55_pclk",    R9A07G044_IA55_PCLK, R9A07G044_CLK_P2,
 174                                         0x518, 0),
 175                 DEF_MOD("ia55_clk",     R9A07G044_IA55_CLK, R9A07G044_CLK_P1,
 176                                         0x518, 1),
 177                 DEF_MOD("dmac_aclk",    R9A07G044_DMAC_ACLK, R9A07G044_CLK_P1,
 178                                         0x52c, 0),
 179                 DEF_MOD("dmac_pclk",    R9A07G044_DMAC_PCLK, CLK_P1_DIV2,
 180                                         0x52c, 1),
 181                 DEF_MOD("ostm0_pclk",   R9A07G044_OSTM0_PCLK, R9A07G044_CLK_P0,
 182                                         0x534, 0),
 183                 DEF_MOD("ostm1_clk",    R9A07G044_OSTM1_PCLK, R9A07G044_CLK_P0,
 184                                         0x534, 1),
 185                 DEF_MOD("ostm2_pclk",   R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0,
 186                                         0x534, 2),
 187                 DEF_MOD("wdt0_pclk",    R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0,
 188                                         0x548, 0),
 189                 DEF_MOD("wdt0_clk",     R9A07G044_WDT0_CLK, R9A07G044_OSCCLK,
 190                                         0x548, 1),
 191                 DEF_MOD("wdt1_pclk",    R9A07G044_WDT1_PCLK, R9A07G044_CLK_P0,
 192                                         0x548, 2),
 193                 DEF_MOD("wdt1_clk",     R9A07G044_WDT1_CLK, R9A07G044_OSCCLK,
 194                                         0x548, 3),
 195                 DEF_MOD("wdt2_pclk",    R9A07G044_WDT2_PCLK, R9A07G044_CLK_P0,
 196                                         0x548, 4),
 197                 DEF_MOD("wdt2_clk",     R9A07G044_WDT2_CLK, R9A07G044_OSCCLK,
 198                                         0x548, 5),
 199                 DEF_MOD("spi_clk2",     R9A07G044_SPI_CLK2, R9A07G044_CLK_SPI1,
 200                                         0x550, 0),
 201                 DEF_MOD("spi_clk",      R9A07G044_SPI_CLK, R9A07G044_CLK_SPI0,
 202                                         0x550, 1),
 203                 DEF_MOD("sdhi0_imclk",  R9A07G044_SDHI0_IMCLK, CLK_SD0_DIV4,
 204                                         0x554, 0),
 205                 DEF_MOD("sdhi0_imclk2", R9A07G044_SDHI0_IMCLK2, CLK_SD0_DIV4,
 206                                         0x554, 1),
 207                 DEF_MOD("sdhi0_clk_hs", R9A07G044_SDHI0_CLK_HS, R9A07G044_CLK_SD0,
 208                                         0x554, 2),
 209                 DEF_MOD("sdhi0_aclk",   R9A07G044_SDHI0_ACLK, R9A07G044_CLK_P1,
 210                                         0x554, 3),
 211                 DEF_MOD("sdhi1_imclk",  R9A07G044_SDHI1_IMCLK, CLK_SD1_DIV4,
 212                                         0x554, 4),
 213                 DEF_MOD("sdhi1_imclk2", R9A07G044_SDHI1_IMCLK2, CLK_SD1_DIV4,
 214                                         0x554, 5),
 215                 DEF_MOD("sdhi1_clk_hs", R9A07G044_SDHI1_CLK_HS, R9A07G044_CLK_SD1,
 216                                         0x554, 6),
 217                 DEF_MOD("sdhi1_aclk",   R9A07G044_SDHI1_ACLK, R9A07G044_CLK_P1,
 218                                         0x554, 7),
 219                 DEF_MOD("gpu_clk",      R9A07G044_GPU_CLK, R9A07G044_CLK_G,
 220                                         0x558, 0),
 221                 DEF_MOD("gpu_axi_clk",  R9A07G044_GPU_AXI_CLK, R9A07G044_CLK_P1,
 222                                         0x558, 1),
 223                 DEF_MOD("gpu_ace_clk",  R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1,
 224                                         0x558, 2),
 225                 DEF_MOD("ssi0_pclk",    R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0,
 226                                         0x570, 0),
 227                 DEF_MOD("ssi0_sfr",     R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0,
 228                                         0x570, 1),
 229                 DEF_MOD("ssi1_pclk",    R9A07G044_SSI1_PCLK2, R9A07G044_CLK_P0,
 230                                         0x570, 2),
 231                 DEF_MOD("ssi1_sfr",     R9A07G044_SSI1_PCLK_SFR, R9A07G044_CLK_P0,
 232                                         0x570, 3),
 233                 DEF_MOD("ssi2_pclk",    R9A07G044_SSI2_PCLK2, R9A07G044_CLK_P0,
 234                                         0x570, 4),
 235                 DEF_MOD("ssi2_sfr",     R9A07G044_SSI2_PCLK_SFR, R9A07G044_CLK_P0,
 236                                         0x570, 5),
 237                 DEF_MOD("ssi3_pclk",    R9A07G044_SSI3_PCLK2, R9A07G044_CLK_P0,
 238                                         0x570, 6),
 239                 DEF_MOD("ssi3_sfr",     R9A07G044_SSI3_PCLK_SFR, R9A07G044_CLK_P0,
 240                                         0x570, 7),
 241                 DEF_MOD("usb0_host",    R9A07G044_USB_U2H0_HCLK, R9A07G044_CLK_P1,
 242                                         0x578, 0),
 243                 DEF_MOD("usb1_host",    R9A07G044_USB_U2H1_HCLK, R9A07G044_CLK_P1,
 244                                         0x578, 1),
 245                 DEF_MOD("usb0_func",    R9A07G044_USB_U2P_EXR_CPUCLK, R9A07G044_CLK_P1,
 246                                         0x578, 2),
 247                 DEF_MOD("usb_pclk",     R9A07G044_USB_PCLK, R9A07G044_CLK_P1,
 248                                         0x578, 3),
 249                 DEF_COUPLED("eth0_axi", R9A07G044_ETH0_CLK_AXI, R9A07G044_CLK_M0,
 250                                         0x57c, 0),
 251                 DEF_COUPLED("eth0_chi", R9A07G044_ETH0_CLK_CHI, R9A07G044_CLK_ZT,
 252                                         0x57c, 0),
 253                 DEF_COUPLED("eth1_axi", R9A07G044_ETH1_CLK_AXI, R9A07G044_CLK_M0,
 254                                         0x57c, 1),
 255                 DEF_COUPLED("eth1_chi", R9A07G044_ETH1_CLK_CHI, R9A07G044_CLK_ZT,
 256                                         0x57c, 1),
 257                 DEF_MOD("i2c0",         R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0,
 258                                         0x580, 0),
 259                 DEF_MOD("i2c1",         R9A07G044_I2C1_PCLK, R9A07G044_CLK_P0,
 260                                         0x580, 1),
 261                 DEF_MOD("i2c2",         R9A07G044_I2C2_PCLK, R9A07G044_CLK_P0,
 262                                         0x580, 2),
 263                 DEF_MOD("i2c3",         R9A07G044_I2C3_PCLK, R9A07G044_CLK_P0,
 264                                         0x580, 3),
 265                 DEF_MOD("scif0",        R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0,
 266                                         0x584, 0),
 267                 DEF_MOD("scif1",        R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0,
 268                                         0x584, 1),
 269                 DEF_MOD("scif2",        R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0,
 270                                         0x584, 2),
 271                 DEF_MOD("scif3",        R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0,
 272                                         0x584, 3),
 273                 DEF_MOD("scif4",        R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0,
 274                                         0x584, 4),
 275                 DEF_MOD("sci0",         R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0,
 276                                         0x588, 0),
 277                 DEF_MOD("sci1",         R9A07G044_SCI1_CLKP, R9A07G044_CLK_P0,
 278                                         0x588, 1),
 279                 DEF_MOD("rspi0",        R9A07G044_RSPI0_CLKB, R9A07G044_CLK_P0,
 280                                         0x590, 0),
 281                 DEF_MOD("rspi1",        R9A07G044_RSPI1_CLKB, R9A07G044_CLK_P0,
 282                                         0x590, 1),
 283                 DEF_MOD("rspi2",        R9A07G044_RSPI2_CLKB, R9A07G044_CLK_P0,
 284                                         0x590, 2),
 285                 DEF_MOD("canfd",        R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0,
 286                                         0x594, 0),
 287                 DEF_MOD("gpio",         R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK,
 288                                         0x598, 0),
 289                 DEF_MOD("adc_adclk",    R9A07G044_ADC_ADCLK, R9A07G044_CLK_TSU,
 290                                         0x5a8, 0),
 291                 DEF_MOD("adc_pclk",     R9A07G044_ADC_PCLK, R9A07G044_CLK_P0,
 292                                         0x5a8, 1),
 293                 DEF_MOD("tsu_pclk",     R9A07G044_TSU_PCLK, R9A07G044_CLK_TSU,
 294                                         0x5ac, 0),
 295         },
 296 #ifdef CONFIG_CLK_R9A07G054
 297         .drp = {
 298         },
 299 #endif
 300 };
 301
 302 static struct rzg2l_reset r9a07g044_resets[] = {
 303         DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0),
 304         DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1),
 305         DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
 306         DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0),
 307         DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1),
 308         DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0),
 309         DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1),
 310         DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2),
 311         DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0),
 312         DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1),
 313         DEF_RST(R9A07G044_WDT2_PRESETN, 0x848, 2),
 314         DEF_RST(R9A07G044_SPI_RST, 0x850, 0),
 315         DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0),
 316         DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1),
 317         DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0),
 318         DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1),
 319         DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2),
 320         DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),
 321         DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),
 322         DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),
 323         DEF_RST(R9A07G044_SSI3_RST_M2_REG, 0x870, 3),
 324         DEF_RST(R9A07G044_USB_U2H0_HRESETN, 0x878, 0),
 325         DEF_RST(R9A07G044_USB_U2H1_HRESETN, 0x878, 1),
 326         DEF_RST(R9A07G044_USB_U2P_EXL_SYSRST, 0x878, 2),
 327         DEF_RST(R9A07G044_USB_PRESETN, 0x878, 3),
 328         DEF_RST(R9A07G044_ETH0_RST_HW_N, 0x87c, 0),
 329         DEF_RST(R9A07G044_ETH1_RST_HW_N, 0x87c, 1),
 330         DEF_RST(R9A07G044_I2C0_MRST, 0x880, 0),
 331         DEF_RST(R9A07G044_I2C1_MRST, 0x880, 1),
 332         DEF_RST(R9A07G044_I2C2_MRST, 0x880, 2),
 333         DEF_RST(R9A07G044_I2C3_MRST, 0x880, 3),
 334         DEF_RST(R9A07G044_SCIF0_RST_SYSTEM_N, 0x884, 0),
 335         DEF_RST(R9A07G044_SCIF1_RST_SYSTEM_N, 0x884, 1),
 336         DEF_RST(R9A07G044_SCIF2_RST_SYSTEM_N, 0x884, 2),
 337         DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3),
 338         DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4),
 339         DEF_RST(R9A07G044_SCI0_RST, 0x888, 0),
 340         DEF_RST(R9A07G044_SCI1_RST, 0x888, 1),
 341         DEF_RST(R9A07G044_RSPI0_RST, 0x890, 0),
 342         DEF_RST(R9A07G044_RSPI1_RST, 0x890, 1),
 343         DEF_RST(R9A07G044_RSPI2_RST, 0x890, 2),
 344         DEF_RST(R9A07G044_CANFD_RSTP_N, 0x894, 0),
 345         DEF_RST(R9A07G044_CANFD_RSTC_N, 0x894, 1),
 346         DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0),
 347         DEF_RST(R9A07G044_GPIO_PORT_RESETN, 0x898, 1),
 348         DEF_RST(R9A07G044_GPIO_SPARE_RESETN, 0x898, 2),
 349         DEF_RST(R9A07G044_ADC_PRESETN, 0x8a8, 0),
 350         DEF_RST(R9A07G044_ADC_ADRST_N, 0x8a8, 1),
 351         DEF_RST(R9A07G044_TSU_PRESETN, 0x8ac, 0),
 352 };
 353
 354 static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
 355         MOD_CLK_BASE + R9A07G044_GIC600_GICCLK,
 356         MOD_CLK_BASE + R9A07G044_IA55_CLK,
 357         MOD_CLK_BASE + R9A07G044_DMAC_ACLK,
 358 };
 359
 360 const struct rzg2l_cpg_info r9a07g044_cpg_info = {
 361         /* Core Clocks */
 362         .core_clks = core_clks.common,
 363         .num_core_clks = ARRAY_SIZE(core_clks.common),
 364         .last_dt_core_clk = LAST_DT_CORE_CLK,
 365         .num_total_core_clks = MOD_CLK_BASE,
 366
 367         /* Critical Module Clocks */
 368         .crit_mod_clks = r9a07g044_crit_mod_clks,
 369         .num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks),
 370
 371         /* Module Clocks */
 372         .mod_clks = mod_clks.common,
 373         .num_mod_clks = ARRAY_SIZE(mod_clks.common),
 374         .num_hw_mod_clks = R9A07G044_TSU_PCLK + 1,
 375
 376         /* Resets */
 377         .resets = r9a07g044_resets,
 378         .num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */
 379 };
 380
 381 #ifdef CONFIG_CLK_R9A07G054
 382 const struct rzg2l_cpg_info r9a07g054_cpg_info = {
 383         /* Core Clocks */
 384         .core_clks = core_clks.common,
 385         .num_core_clks = ARRAY_SIZE(core_clks.common) + ARRAY_SIZE(core_clks.drp),
 386         .last_dt_core_clk = LAST_DT_CORE_CLK,
 387         .num_total_core_clks = MOD_CLK_BASE,
 388
 389         /* Critical Module Clocks */
 390         .crit_mod_clks = r9a07g044_crit_mod_clks,
 391         .num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks),
 392
 393         /* Module Clocks */
 394         .mod_clks = mod_clks.common,
 395         .num_mod_clks = ARRAY_SIZE(mod_clks.common) + ARRAY_SIZE(mod_clks.drp),
 396         .num_hw_mod_clks = R9A07G054_STPAI_ACLK_DRP + 1,
 397
 398         /* Resets */
 399         .resets = r9a07g044_resets,
 400         .num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */
 401 };
 402 #endif