drivers/clk/renesas/r8a779g0-cpg-mssr.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * r8a779g0 Clock Pulse Generator / Module Standby and Software Reset
   4  *
   5  * Copyright (C) 2022 Renesas Electronics Corp.
   6  *
   7  * Based on r8a779f0-cpg-mssr.c
   8  */
   9
  10 #include <linux/bitfield.h>
  11 #include <linux/clk.h>
  12 #include <linux/clk-provider.h>
  13 #include <linux/device.h>
  14 #include <linux/err.h>
  15 #include <linux/kernel.h>
  16 #include <linux/soc/renesas/rcar-rst.h>
  17
  18 #include <dt-bindings/clock/r8a779g0-cpg-mssr.h>
  19
  20 #include "renesas-cpg-mssr.h"
  21 #include "rcar-gen4-cpg.h"
  22
  23 enum clk_ids {
  24         /* Core Clock Outputs exported to DT */
  25         LAST_DT_CORE_CLK = R8A779G0_CLK_R,
  26
  27         /* External Input Clocks */
  28         CLK_EXTAL,
  29         CLK_EXTALR,
  30
  31         /* Internal Core Clocks */
  32         CLK_MAIN,
  33         CLK_PLL1,
  34         CLK_PLL2,
  35         CLK_PLL3,
  36         CLK_PLL4,
  37         CLK_PLL5,
  38         CLK_PLL6,
  39         CLK_PLL1_DIV2,
  40         CLK_PLL2_DIV2,
  41         CLK_PLL3_DIV2,
  42         CLK_PLL4_DIV2,
  43         CLK_PLL5_DIV2,
  44         CLK_PLL5_DIV4,
  45         CLK_PLL6_DIV2,
  46         CLK_S0,
  47         CLK_S0_VIO,
  48         CLK_S0_VC,
  49         CLK_S0_HSC,
  50         CLK_SV_VIP,
  51         CLK_SV_IR,
  52         CLK_SDSRC,
  53         CLK_RPCSRC,
  54         CLK_VIO,
  55         CLK_VC,
  56         CLK_OCO,
  57
  58         /* Module Clocks */
  59         MOD_CLK_BASE
  60 };
  61
  62 static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
  63         /* External Clock Inputs */
  64         DEF_INPUT("extal",      CLK_EXTAL),
  65         DEF_INPUT("extalr",     CLK_EXTALR),
  66
  67         /* Internal Core Clocks */
  68         DEF_BASE(".main", CLK_MAIN,     CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
  69         DEF_BASE(".pll1", CLK_PLL1,     CLK_TYPE_GEN4_PLL1, CLK_MAIN),
  70         DEF_BASE(".pll2", CLK_PLL2,     CLK_TYPE_GEN4_PLL2, CLK_MAIN),
  71         DEF_BASE(".pll3", CLK_PLL3,     CLK_TYPE_GEN4_PLL3, CLK_MAIN),
  72         DEF_BASE(".pll4", CLK_PLL4,     CLK_TYPE_GEN4_PLL4, CLK_MAIN),
  73         DEF_BASE(".pll5", CLK_PLL5,     CLK_TYPE_GEN4_PLL5, CLK_MAIN),
  74         DEF_BASE(".pll6", CLK_PLL6,     CLK_TYPE_GEN4_PLL6, CLK_MAIN),
  75
  76         DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,  CLK_PLL1,       2, 1),
  77         DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2,  CLK_PLL2,       2, 1),
  78         DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2,  CLK_PLL3,       2, 1),
  79         DEF_FIXED(".pll4_div2", CLK_PLL4_DIV2,  CLK_PLL4,       2, 1),
  80         DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2,  CLK_PLL5,       2, 1),
  81         DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4,  CLK_PLL5_DIV2,  2, 1),
  82         DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2,  CLK_PLL6,       2, 1),
  83         DEF_FIXED(".s0",        CLK_S0,         CLK_PLL1_DIV2,  2, 1),
  84         DEF_FIXED(".s0_vio",    CLK_S0_VIO,     CLK_PLL1_DIV2,  2, 1),
  85         DEF_FIXED(".s0_vc",     CLK_S0_VC,      CLK_PLL1_DIV2,  2, 1),
  86         DEF_FIXED(".s0_hsc",    CLK_S0_HSC,     CLK_PLL1_DIV2,  2, 1),
  87         DEF_FIXED(".sv_vip",    CLK_SV_VIP,     CLK_PLL1,       5, 1),
  88         DEF_FIXED(".sv_ir",     CLK_SV_IR,      CLK_PLL1,       5, 1),
  89         DEF_BASE(".sdsrc",      CLK_SDSRC,      CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
  90         DEF_RATE(".oco",        CLK_OCO,        32768),
  91
  92         DEF_BASE(".rpcsrc",     CLK_RPCSRC,             CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
  93         DEF_FIXED(".vio",       CLK_VIO,        CLK_PLL5_DIV2,  3, 1),
  94         DEF_FIXED(".vc",        CLK_VC,         CLK_PLL5_DIV2,  3, 1),
  95
  96         /* Core Clock Outputs */
  97         DEF_FIXED("s0d2",       R8A779G0_CLK_S0D2,      CLK_S0,         2, 1),
  98         DEF_FIXED("s0d3",       R8A779G0_CLK_S0D3,      CLK_S0,         3, 1),
  99         DEF_FIXED("s0d4",       R8A779G0_CLK_S0D4,      CLK_S0,         4, 1),
 100         DEF_FIXED("cl16m",      R8A779G0_CLK_CL16M,     CLK_S0,         48, 1),
 101         DEF_FIXED("s0d1_vio",   R8A779G0_CLK_S0D1_VIO,  CLK_S0_VIO,     1, 1),
 102         DEF_FIXED("s0d2_vio",   R8A779G0_CLK_S0D2_VIO,  CLK_S0_VIO,     2, 1),
 103         DEF_FIXED("s0d4_vio",   R8A779G0_CLK_S0D4_VIO,  CLK_S0_VIO,     4, 1),
 104         DEF_FIXED("s0d8_vio",   R8A779G0_CLK_S0D8_VIO,  CLK_S0_VIO,     8, 1),
 105         DEF_FIXED("s0d1_vc",    R8A779G0_CLK_S0D1_VC,   CLK_S0_VC,      1, 1),
 106         DEF_FIXED("s0d2_vc",    R8A779G0_CLK_S0D2_VC,   CLK_S0_VC,      2, 1),
 107         DEF_FIXED("s0d4_vc",    R8A779G0_CLK_S0D4_VC,   CLK_S0_VC,      4, 1),
 108         DEF_FIXED("s0d2_mm",    R8A779G0_CLK_S0D2_MM,   CLK_S0,         2, 1),
 109         DEF_FIXED("s0d4_mm",    R8A779G0_CLK_S0D4_MM,   CLK_S0,         4, 1),
 110         DEF_FIXED("cl16m_mm",   R8A779G0_CLK_CL16M_MM,  CLK_S0,         48, 1),
 111         DEF_FIXED("s0d2_u3dg",  R8A779G0_CLK_S0D2_U3DG, CLK_S0,         2, 1),
 112         DEF_FIXED("s0d4_u3dg",  R8A779G0_CLK_S0D4_U3DG, CLK_S0,         4, 1),
 113         DEF_FIXED("s0d2_rt",    R8A779G0_CLK_S0D2_RT,   CLK_S0,         2, 1),
 114         DEF_FIXED("s0d3_rt",    R8A779G0_CLK_S0D3_RT,   CLK_S0,         3, 1),
 115         DEF_FIXED("s0d4_rt",    R8A779G0_CLK_S0D4_RT,   CLK_S0,         4, 1),
 116         DEF_FIXED("s0d6_rt",    R8A779G0_CLK_S0D6_RT,   CLK_S0,         6, 1),
 117         DEF_FIXED("s0d24_rt",   R8A779G0_CLK_S0D24_RT,  CLK_S0,         24, 1),
 118         DEF_FIXED("cl16m_rt",   R8A779G0_CLK_CL16M_RT,  CLK_S0,         48, 1),
 119         DEF_FIXED("s0d2_per",   R8A779G0_CLK_S0D2_PER,  CLK_S0,         2, 1),
 120         DEF_FIXED("s0d3_per",   R8A779G0_CLK_S0D3_PER,  CLK_S0,         3, 1),
 121         DEF_FIXED("s0d4_per",   R8A779G0_CLK_S0D4_PER,  CLK_S0,         4, 1),
 122         DEF_FIXED("s0d6_per",   R8A779G0_CLK_S0D6_PER,  CLK_S0,         6, 1),
 123         DEF_FIXED("s0d12_per",  R8A779G0_CLK_S0D12_PER, CLK_S0,         12, 1),
 124         DEF_FIXED("s0d24_per",  R8A779G0_CLK_S0D24_PER, CLK_S0,         24, 1),
 125         DEF_FIXED("cl16m_per",  R8A779G0_CLK_CL16M_PER, CLK_S0,         48, 1),
 126         DEF_FIXED("s0d1_hsc",   R8A779G0_CLK_S0D1_HSC,  CLK_S0_HSC,     1, 1),
 127         DEF_FIXED("s0d2_hsc",   R8A779G0_CLK_S0D2_HSC,  CLK_S0_HSC,     2, 1),
 128         DEF_FIXED("s0d4_hsc",   R8A779G0_CLK_S0D4_HSC,  CLK_S0_HSC,     4, 1),
 129         DEF_FIXED("cl16m_hsc",  R8A779G0_CLK_CL16M_HSC, CLK_S0_HSC,     48, 1),
 130         DEF_FIXED("s0d2_cc",    R8A779G0_CLK_S0D2_CC,   CLK_S0,         2, 1),
 131         DEF_FIXED("svd1_ir",    R8A779G0_CLK_SVD1_IR,   CLK_SV_IR,      1, 1),
 132         DEF_FIXED("svd2_ir",    R8A779G0_CLK_SVD2_IR,   CLK_SV_IR,      2, 1),
 133         DEF_FIXED("svd1_vip",   R8A779G0_CLK_SVD1_VIP,  CLK_SV_VIP,     1, 1),
 134         DEF_FIXED("svd2_vip",   R8A779G0_CLK_SVD2_VIP,  CLK_SV_VIP,     2, 1),
 135         DEF_FIXED("cbfusa",     R8A779G0_CLK_CBFUSA,    CLK_EXTAL,      2, 1),
 136         DEF_FIXED("cpex",       R8A779G0_CLK_CPEX,      CLK_EXTAL,      2, 1),
 137         DEF_FIXED("viobus",     R8A779G0_CLK_VIOBUS,    CLK_VIO,        1, 1),
 138         DEF_FIXED("viobusd2",   R8A779G0_CLK_VIOBUSD2,  CLK_VIO,        2, 1),
 139         DEF_FIXED("vcbus",      R8A779G0_CLK_VCBUS,     CLK_VC,         1, 1),
 140         DEF_FIXED("vcbusd2",    R8A779G0_CLK_VCBUSD2,   CLK_VC,         2, 1),
 141
 142         DEF_GEN4_SD("sd0",      R8A779G0_CLK_SD0,       CLK_SDSRC,      0x870),
 143         DEF_DIV6P1("mso",       R8A779G0_CLK_MSO,       CLK_PLL5_DIV4,  0x87c),
 144
 145         DEF_BASE("rpc",         R8A779G0_CLK_RPC,       CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
 146         DEF_BASE("rpcd2",       R8A779G0_CLK_RPCD2,     CLK_TYPE_GEN4_RPCD2, R8A779G0_CLK_RPC),
 147
 148         DEF_GEN4_OSC("osc",     R8A779G0_CLK_OSC,       CLK_EXTAL,      8),
 149         DEF_GEN4_MDSEL("r",     R8A779G0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
 150 };
 151
 152 static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
 153         DEF_MOD("hscif0",       514,    R8A779G0_CLK_S0D3_PER),
 154         DEF_MOD("hscif1",       515,    R8A779G0_CLK_S0D3_PER),
 155         DEF_MOD("hscif2",       516,    R8A779G0_CLK_S0D3_PER),
 156         DEF_MOD("hscif3",       517,    R8A779G0_CLK_S0D3_PER),
 157 };
 158
 159 /*
 160  * CPG Clock Data
 161  */
 162 /*
 163  *   MD  EXTAL          PLL1    PLL2    PLL3    PLL4    PLL5    PLL6    OSC
 164  * 14 13 (MHz)
 165  * ------------------------------------------------------------------------
 166  * 0  0  16.66 / 1      x192    x204    x192    x144    x192    x168    /15
 167  * 0  1  20    / 1      x160    x170    x160    x120    x160    x140    /19
 168  * 1  0  Prohibited setting
 169  * 1  1  33.33 / 2      x192    x204    x192    x144    x192    x168    /38
 170  */
 171 #define CPG_PLL_CONFIG_INDEX(md)        ((((md) & BIT(14)) >> 13) | \
 172                                          (((md) & BIT(13)) >> 13))
 173
 174 static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
 175         /* EXTAL div    PLL1 mult/div   PLL2 mult/div   PLL3 mult/div   PLL4 mult/div   PLL5 mult/div   PLL6 mult/div   OSC prediv */
 176         { 1,            192,    1,      204,    1,      192,    1,      144,    1,      192,    1,      168,    1,      15,     },
 177         { 1,            160,    1,      170,    1,      160,    1,      120,    1,      160,    1,      140,    1,      19,     },
 178         { 0,            0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      },
 179         { 2,            192,    1,      204,    1,      192,    1,      144,    1,      192,    1,      168,    1,      38,     },
 180 };
 181
 182 static int __init r8a779g0_cpg_mssr_init(struct device *dev)
 183 {
 184         const struct rcar_gen4_cpg_pll_config *cpg_pll_config;
 185         u32 cpg_mode;
 186         int error;
 187
 188         error = rcar_rst_read_mode_pins(&cpg_mode);
 189         if (error)
 190                 return error;
 191
 192         cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
 193         if (!cpg_pll_config->extal_div) {
 194                 dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
 195                 return -EINVAL;
 196         }
 197
 198         return rcar_gen4_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
 199 }
 200
 201 const struct cpg_mssr_info r8a779g0_cpg_mssr_info __initconst = {
 202         /* Core Clocks */
 203         .core_clks = r8a779g0_core_clks,
 204         .num_core_clks = ARRAY_SIZE(r8a779g0_core_clks),
 205         .last_dt_core_clk = LAST_DT_CORE_CLK,
 206         .num_total_core_clks = MOD_CLK_BASE,
 207
 208         /* Module Clocks */
 209         .mod_clks = r8a779g0_mod_clks,
 210         .num_mod_clks = ARRAY_SIZE(r8a779g0_mod_clks),
 211         .num_hw_mod_clks = 30 * 32,
 212
 213         /* Callbacks */
 214         .init = r8a779g0_cpg_mssr_init,
 215         .cpg_clk_register = rcar_gen4_cpg_clk_register,
 216
 217         .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
 218 };