drivers/clk/renesas/r8a779f0-cpg-mssr.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * r8a779f0 Clock Pulse Generator / Module Standby and Software Reset
   4  *
   5  * Copyright (C) 2021 Renesas Electronics Corp.
   6  *
   7  * Based on r8a779a0-cpg-mssr.c
   8  */
   9
  10 #include <linux/bitfield.h>
  11 #include <linux/clk.h>
  12 #include <linux/clk-provider.h>
  13 #include <linux/device.h>
  14 #include <linux/err.h>
  15 #include <linux/kernel.h>
  16 #include <linux/soc/renesas/rcar-rst.h>
  17
  18 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
  19
  20 #include "renesas-cpg-mssr.h"
  21 #include "rcar-gen4-cpg.h"
  22
  23 enum clk_ids {
  24         /* Core Clock Outputs exported to DT */
  25         LAST_DT_CORE_CLK = R8A779F0_CLK_R,
  26
  27         /* External Input Clocks */
  28         CLK_EXTAL,
  29         CLK_EXTALR,
  30
  31         /* Internal Core Clocks */
  32         CLK_MAIN,
  33         CLK_PLL1,
  34         CLK_PLL2,
  35         CLK_PLL3,
  36         CLK_PLL5,
  37         CLK_PLL6,
  38         CLK_PLL1_DIV2,
  39         CLK_PLL2_DIV2,
  40         CLK_PLL3_DIV2,
  41         CLK_PLL5_DIV2,
  42         CLK_PLL5_DIV4,
  43         CLK_PLL6_DIV2,
  44         CLK_S0,
  45         CLK_SDSRC,
  46         CLK_RPCSRC,
  47         CLK_OCO,
  48
  49         /* Module Clocks */
  50         MOD_CLK_BASE
  51 };
  52
  53 static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = {
  54         /* External Clock Inputs */
  55         DEF_INPUT("extal",      CLK_EXTAL),
  56         DEF_INPUT("extalr",     CLK_EXTALR),
  57
  58         /* Internal Core Clocks */
  59         DEF_BASE(".main", CLK_MAIN,     CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
  60         DEF_BASE(".pll1", CLK_PLL1,     CLK_TYPE_GEN4_PLL1, CLK_MAIN),
  61         DEF_BASE(".pll2", CLK_PLL2,     CLK_TYPE_GEN4_PLL2, CLK_MAIN),
  62         DEF_BASE(".pll3", CLK_PLL3,     CLK_TYPE_GEN4_PLL3, CLK_MAIN),
  63         DEF_BASE(".pll5", CLK_PLL5,     CLK_TYPE_GEN4_PLL5, CLK_MAIN),
  64         DEF_BASE(".pll6", CLK_PLL6,     CLK_TYPE_GEN4_PLL6, CLK_MAIN),
  65
  66         DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,  CLK_PLL1,       2, 1),
  67         DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2,  CLK_PLL2,       2, 1),
  68         DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2,  CLK_PLL3,       2, 1),
  69         DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2,  CLK_PLL5,       2, 1),
  70         DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4,  CLK_PLL5_DIV2,  2, 1),
  71         DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2,  CLK_PLL6,       2, 1),
  72         DEF_FIXED(".s0",        CLK_S0,         CLK_PLL1_DIV2,  2, 1),
  73         DEF_BASE(".sdsrc",      CLK_SDSRC,      CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
  74         DEF_RATE(".oco",        CLK_OCO,        32768),
  75
  76         DEF_BASE(".rpcsrc",     CLK_RPCSRC,             CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
  77         DEF_BASE(".rpc",        R8A779F0_CLK_RPC,       CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
  78         DEF_BASE("rpcd2",       R8A779F0_CLK_RPCD2,     CLK_TYPE_GEN4_RPCD2, R8A779F0_CLK_RPC),
  79
  80         /* Core Clock Outputs */
  81         DEF_FIXED("s0d2",       R8A779F0_CLK_S0D2,      CLK_S0,         2, 1),
  82         DEF_FIXED("s0d3",       R8A779F0_CLK_S0D3,      CLK_S0,         3, 1),
  83         DEF_FIXED("s0d4",       R8A779F0_CLK_S0D4,      CLK_S0,         4, 1),
  84         DEF_FIXED("cl16m",      R8A779F0_CLK_CL16M,     CLK_S0,         48, 1),
  85         DEF_FIXED("s0d2_mm",    R8A779F0_CLK_S0D2_MM,   CLK_S0,         2, 1),
  86         DEF_FIXED("s0d3_mm",    R8A779F0_CLK_S0D3_MM,   CLK_S0,         3, 1),
  87         DEF_FIXED("s0d4_mm",    R8A779F0_CLK_S0D4_MM,   CLK_S0,         4, 1),
  88         DEF_FIXED("cl16m_mm",   R8A779F0_CLK_CL16M_MM,  CLK_S0,         48, 1),
  89         DEF_FIXED("s0d2_rt",    R8A779F0_CLK_S0D2_RT,   CLK_S0,         2, 1),
  90         DEF_FIXED("s0d3_rt",    R8A779F0_CLK_S0D3_RT,   CLK_S0,         3, 1),
  91         DEF_FIXED("s0d4_rt",    R8A779F0_CLK_S0D4_RT,   CLK_S0,         4, 1),
  92         DEF_FIXED("s0d6_rt",    R8A779F0_CLK_S0D6_RT,   CLK_S0,         6, 1),
  93         DEF_FIXED("cl16m_rt",   R8A779F0_CLK_CL16M_RT,  CLK_S0,         48, 1),
  94         DEF_FIXED("s0d3_per",   R8A779F0_CLK_S0D3_PER,  CLK_S0,         3, 1),
  95         DEF_FIXED("s0d6_per",   R8A779F0_CLK_S0D6_PER,  CLK_S0,         6, 1),
  96         DEF_FIXED("s0d12_per",  R8A779F0_CLK_S0D12_PER, CLK_S0,         12, 1),
  97         DEF_FIXED("s0d24_per",  R8A779F0_CLK_S0D24_PER, CLK_S0,         24, 1),
  98         DEF_FIXED("cl16m_per",  R8A779F0_CLK_CL16M_PER, CLK_S0,         48, 1),
  99         DEF_FIXED("s0d2_hsc",   R8A779F0_CLK_S0D2_HSC,  CLK_S0,         2, 1),
 100         DEF_FIXED("s0d3_hsc",   R8A779F0_CLK_S0D3_HSC,  CLK_S0,         3, 1),
 101         DEF_FIXED("s0d4_hsc",   R8A779F0_CLK_S0D4_HSC,  CLK_S0,         4, 1),
 102         DEF_FIXED("s0d6_hsc",   R8A779F0_CLK_S0D6_HSC,  CLK_S0,         6, 1),
 103         DEF_FIXED("s0d12_hsc",  R8A779F0_CLK_S0D12_HSC, CLK_S0,         12, 1),
 104         DEF_FIXED("cl16m_hsc",  R8A779F0_CLK_CL16M_HSC, CLK_S0,         48, 1),
 105         DEF_FIXED("s0d2_cc",    R8A779F0_CLK_S0D2_CC,   CLK_S0,         2, 1),
 106         DEF_FIXED("rsw2",       R8A779F0_CLK_RSW2,      CLK_PLL5,       2, 1),
 107         DEF_FIXED("cbfusa",     R8A779F0_CLK_CBFUSA,    CLK_EXTAL,      2, 1),
 108         DEF_FIXED("cpex",       R8A779F0_CLK_CPEX,      CLK_EXTAL,      2, 1),
 109
 110         DEF_GEN4_SD("sd0",      R8A779F0_CLK_SD0,       CLK_SDSRC,      0x870),
 111         DEF_DIV6P1("mso",       R8A779F0_CLK_MSO,       CLK_PLL5_DIV4,  0x87c),
 112
 113         DEF_GEN4_OSC("osc",     R8A779F0_CLK_OSC,       CLK_EXTAL,      8),
 114         DEF_GEN4_MDSEL("r",     R8A779F0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
 115 };
 116
 117 static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {
 118         DEF_MOD("scif0",        702,    R8A779F0_CLK_S0D12_PER),
 119         DEF_MOD("scif1",        703,    R8A779F0_CLK_S0D12_PER),
 120         DEF_MOD("scif3",        704,    R8A779F0_CLK_S0D12_PER),
 121         DEF_MOD("scif4",        705,    R8A779F0_CLK_S0D12_PER),
 122 };
 123
 124 /*
 125  * CPG Clock Data
 126  */
 127 /*
 128  *   MD  EXTAL          PLL1    PLL2    PLL3    PLL5    PLL6    OSC
 129  * 14 13 (MHz)
 130  * ----------------------------------------------------------------
 131  * 0  0  16    / 1      x200    x150    x200    x200    x134    /15
 132  * 0  1  20    / 1      x160    x120    x160    x160    x106    /19
 133  * 1  0  Prohibited setting
 134  * 1  1  40    / 2      x160    x120    x160    x160    x106    /38
 135  */
 136 #define CPG_PLL_CONFIG_INDEX(md)        ((((md) & BIT(14)) >> 13) | \
 137                                          (((md) & BIT(13)) >> 13))
 138
 139 static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
 140         /* EXTAL div    PLL1 mult/div   PLL2 mult/div   PLL3 mult/div   PLL5 mult/div   PLL6 mult/div   OSC prediv */
 141         { 1,            200,    1,      150,    1,      200,    1,      200,    1,      134,    1,      15,     },
 142         { 1,            160,    1,      120,    1,      160,    1,      160,    1,      106,    1,      19,     },
 143         { 0,            0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      0,      },
 144         { 2,            160,    1,      120,    1,      160,    1,      160,    1,      106,    1,      38,     },
 145 };
 146
 147 static int __init r8a779f0_cpg_mssr_init(struct device *dev)
 148 {
 149         const struct rcar_gen4_cpg_pll_config *cpg_pll_config;
 150         u32 cpg_mode;
 151         int error;
 152
 153         error = rcar_rst_read_mode_pins(&cpg_mode);
 154         if (error)
 155                 return error;
 156
 157         cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
 158         if (!cpg_pll_config->extal_div) {
 159                 dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
 160                 return -EINVAL;
 161         }
 162
 163         return rcar_gen4_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
 164 }
 165
 166 const struct cpg_mssr_info r8a779f0_cpg_mssr_info __initconst = {
 167         /* Core Clocks */
 168         .core_clks = r8a779f0_core_clks,
 169         .num_core_clks = ARRAY_SIZE(r8a779f0_core_clks),
 170         .last_dt_core_clk = LAST_DT_CORE_CLK,
 171         .num_total_core_clks = MOD_CLK_BASE,
 172
 173         /* Module Clocks */
 174         .mod_clks = r8a779f0_mod_clks,
 175         .num_mod_clks = ARRAY_SIZE(r8a779f0_mod_clks),
 176         .num_hw_mod_clks = 28 * 32,
 177
 178         /* Callbacks */
 179         .init = r8a779f0_cpg_mssr_init,
 180         .cpg_clk_register = rcar_gen4_cpg_clk_register,
 181
 182         .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
 183 };