dm: treewide: Rename auto_alloc_size members to be shorter
[platform/kernel/u-boot.git] / drivers / clk / renesas / r8a7792-cpg-mssr.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * r8a7792 Clock Pulse Generator / Module Standby and Software Reset
4  *
5  * Copyright (C) 2017 Glider bvba
6  *
7  * Based on clk-rcar-gen2.c
8  *
9  * Copyright (C) 2013 Ideas On Board SPRL
10  */
11
12 #include <common.h>
13 #include <clk-uclass.h>
14 #include <dm.h>
15 #include <linux/bitops.h>
16
17 #include <dt-bindings/clock/r8a7792-cpg-mssr.h>
18
19 #include "renesas-cpg-mssr.h"
20 #include "rcar-gen2-cpg.h"
21
22 enum clk_ids {
23         /* Core Clock Outputs exported to DT */
24         LAST_DT_CORE_CLK = R8A7792_CLK_OSC,
25
26         /* External Input Clocks */
27         CLK_EXTAL,
28
29         /* Internal Core Clocks */
30         CLK_MAIN,
31         CLK_PLL0,
32         CLK_PLL1,
33         CLK_PLL3,
34         CLK_PLL1_DIV2,
35
36         /* Module Clocks */
37         MOD_CLK_BASE
38 };
39
40 static const struct cpg_core_clk r8a7792_core_clks[] = {
41         /* External Clock Inputs */
42         DEF_INPUT("extal",     CLK_EXTAL),
43
44         /* Internal Core Clocks */
45         DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
46         DEF_BASE(".pll0",       CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
47         DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
48         DEF_BASE(".pll3",       CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
49
50         DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
51
52         /* Core Clock Outputs */
53         DEF_BASE("qspi", R8A7792_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
54
55         DEF_FIXED("z",      R8A7792_CLK_Z,     CLK_PLL0,          1, 1),
56         DEF_FIXED("zg",     R8A7792_CLK_ZG,    CLK_PLL1,          5, 1),
57         DEF_FIXED("zx",     R8A7792_CLK_ZX,    CLK_PLL1,          3, 1),
58         DEF_FIXED("zs",     R8A7792_CLK_ZS,    CLK_PLL1,          6, 1),
59         DEF_FIXED("hp",     R8A7792_CLK_HP,    CLK_PLL1,         12, 1),
60         DEF_FIXED("i",      R8A7792_CLK_I,     CLK_PLL1,          3, 1),
61         DEF_FIXED("b",      R8A7792_CLK_B,     CLK_PLL1,         12, 1),
62         DEF_FIXED("lb",     R8A7792_CLK_LB,    CLK_PLL1,         24, 1),
63         DEF_FIXED("p",      R8A7792_CLK_P,     CLK_PLL1,         24, 1),
64         DEF_FIXED("cl",     R8A7792_CLK_CL,    CLK_PLL1,         48, 1),
65         DEF_FIXED("m2",     R8A7792_CLK_M2,    CLK_PLL1,          8, 1),
66         DEF_FIXED("imp",    R8A7792_CLK_IMP,   CLK_PLL1,          4, 1),
67         DEF_FIXED("zb3",    R8A7792_CLK_ZB3,   CLK_PLL3,          4, 1),
68         DEF_FIXED("zb3d2",  R8A7792_CLK_ZB3D2, CLK_PLL3,          8, 1),
69         DEF_FIXED("ddr",    R8A7792_CLK_DDR,   CLK_PLL3,          8, 1),
70         DEF_FIXED("sd",     R8A7792_CLK_SD,    CLK_PLL1_DIV2,     8, 1),
71         DEF_FIXED("mp",     R8A7792_CLK_MP,    CLK_PLL1_DIV2,    15, 1),
72         DEF_FIXED("cp",     R8A7792_CLK_CP,    CLK_PLL1,         48, 1),
73         DEF_FIXED("cpex",   R8A7792_CLK_CPEX,  CLK_EXTAL,         2, 1),
74         DEF_FIXED("rcan",   R8A7792_CLK_RCAN,  CLK_PLL1_DIV2,    49, 1),
75         DEF_FIXED("r",      R8A7792_CLK_R,     CLK_PLL1,      49152, 1),
76         DEF_FIXED("osc",    R8A7792_CLK_OSC,   CLK_PLL1,      12288, 1),
77 };
78
79 static const struct mssr_mod_clk r8a7792_mod_clks[] = {
80         DEF_MOD("msiof0",                  0,   R8A7792_CLK_MP),
81         DEF_MOD("jpu",                   106,   R8A7792_CLK_M2),
82         DEF_MOD("tmu1",                  111,   R8A7792_CLK_P),
83         DEF_MOD("3dg",                   112,   R8A7792_CLK_ZG),
84         DEF_MOD("2d-dmac",               115,   R8A7792_CLK_ZS),
85         DEF_MOD("tmu3",                  121,   R8A7792_CLK_P),
86         DEF_MOD("tmu2",                  122,   R8A7792_CLK_P),
87         DEF_MOD("cmt0",                  124,   R8A7792_CLK_R),
88         DEF_MOD("tmu0",                  125,   R8A7792_CLK_CP),
89         DEF_MOD("vsp1du1",               127,   R8A7792_CLK_ZS),
90         DEF_MOD("vsp1du0",               128,   R8A7792_CLK_ZS),
91         DEF_MOD("vsp1-sy",               131,   R8A7792_CLK_ZS),
92         DEF_MOD("msiof1",                208,   R8A7792_CLK_MP),
93         DEF_MOD("sys-dmac1",             218,   R8A7792_CLK_ZS),
94         DEF_MOD("sys-dmac0",             219,   R8A7792_CLK_ZS),
95         DEF_MOD("tpu0",                  304,   R8A7792_CLK_CP),
96         DEF_MOD("sdhi0",                 314,   R8A7792_CLK_SD),
97         DEF_MOD("cmt1",                  329,   R8A7792_CLK_R),
98         DEF_MOD("rwdt",                  402,   R8A7792_CLK_R),
99         DEF_MOD("irqc",                  407,   R8A7792_CLK_CP),
100         DEF_MOD("intc-sys",              408,   R8A7792_CLK_ZS),
101         DEF_MOD("audio-dmac0",           502,   R8A7792_CLK_HP),
102         DEF_MOD("thermal",               522,   CLK_EXTAL),
103         DEF_MOD("pwm",                   523,   R8A7792_CLK_P),
104         DEF_MOD("hscif1",                716,   R8A7792_CLK_ZS),
105         DEF_MOD("hscif0",                717,   R8A7792_CLK_ZS),
106         DEF_MOD("scif3",                 718,   R8A7792_CLK_P),
107         DEF_MOD("scif2",                 719,   R8A7792_CLK_P),
108         DEF_MOD("scif1",                 720,   R8A7792_CLK_P),
109         DEF_MOD("scif0",                 721,   R8A7792_CLK_P),
110         DEF_MOD("du1",                   723,   R8A7792_CLK_ZX),
111         DEF_MOD("du0",                   724,   R8A7792_CLK_ZX),
112         DEF_MOD("vin5",                  804,   R8A7792_CLK_ZG),
113         DEF_MOD("vin4",                  805,   R8A7792_CLK_ZG),
114         DEF_MOD("vin3",                  808,   R8A7792_CLK_ZG),
115         DEF_MOD("vin2",                  809,   R8A7792_CLK_ZG),
116         DEF_MOD("vin1",                  810,   R8A7792_CLK_ZG),
117         DEF_MOD("vin0",                  811,   R8A7792_CLK_ZG),
118         DEF_MOD("etheravb",              812,   R8A7792_CLK_HP),
119         DEF_MOD("imr-lx3",               821,   R8A7792_CLK_ZG),
120         DEF_MOD("imr-lsx3-1",            822,   R8A7792_CLK_ZG),
121         DEF_MOD("imr-lsx3-0",            823,   R8A7792_CLK_ZG),
122         DEF_MOD("imr-lsx3-5",            825,   R8A7792_CLK_ZG),
123         DEF_MOD("imr-lsx3-4",            826,   R8A7792_CLK_ZG),
124         DEF_MOD("imr-lsx3-3",            827,   R8A7792_CLK_ZG),
125         DEF_MOD("imr-lsx3-2",            828,   R8A7792_CLK_ZG),
126         DEF_MOD("gyro-adc",              901,   R8A7792_CLK_P),
127         DEF_MOD("gpio7",                 904,   R8A7792_CLK_CP),
128         DEF_MOD("gpio6",                 905,   R8A7792_CLK_CP),
129         DEF_MOD("gpio5",                 907,   R8A7792_CLK_CP),
130         DEF_MOD("gpio4",                 908,   R8A7792_CLK_CP),
131         DEF_MOD("gpio3",                 909,   R8A7792_CLK_CP),
132         DEF_MOD("gpio2",                 910,   R8A7792_CLK_CP),
133         DEF_MOD("gpio1",                 911,   R8A7792_CLK_CP),
134         DEF_MOD("gpio0",                 912,   R8A7792_CLK_CP),
135         DEF_MOD("gpio11",                913,   R8A7792_CLK_CP),
136         DEF_MOD("gpio10",                914,   R8A7792_CLK_CP),
137         DEF_MOD("can1",                  915,   R8A7792_CLK_P),
138         DEF_MOD("can0",                  916,   R8A7792_CLK_P),
139         DEF_MOD("qspi_mod",              917,   R8A7792_CLK_QSPI),
140         DEF_MOD("gpio9",                 919,   R8A7792_CLK_CP),
141         DEF_MOD("gpio8",                 921,   R8A7792_CLK_CP),
142         DEF_MOD("i2c5",                  925,   R8A7792_CLK_HP),
143         DEF_MOD("iicdvfs",               926,   R8A7792_CLK_CP),
144         DEF_MOD("i2c4",                  927,   R8A7792_CLK_HP),
145         DEF_MOD("i2c3",                  928,   R8A7792_CLK_HP),
146         DEF_MOD("i2c2",                  929,   R8A7792_CLK_HP),
147         DEF_MOD("i2c1",                  930,   R8A7792_CLK_HP),
148         DEF_MOD("i2c0",                  931,   R8A7792_CLK_HP),
149         DEF_MOD("ssi-all",              1005,   R8A7792_CLK_P),
150         DEF_MOD("ssi4",                 1011,   MOD_CLK_ID(1005)),
151         DEF_MOD("ssi3",                 1012,   MOD_CLK_ID(1005)),
152 };
153
154 /*
155  * CPG Clock Data
156  */
157
158 /*
159  *   MD         EXTAL           PLL0    PLL1    PLL3
160  * 14 13 19     (MHz)           *1      *2
161  *---------------------------------------------------
162  * 0  0  0      15              x200/3  x208/2  x106
163  * 0  0  1      15              x200/3  x208/2  x88
164  * 0  1  0      20              x150/3  x156/2  x80
165  * 0  1  1      20              x150/3  x156/2  x66
166  * 1  0  0      26 / 2          x230/3  x240/2  x122
167  * 1  0  1      26 / 2          x230/3  x240/2  x102
168  * 1  1  0      30 / 2          x200/3  x208/2  x106
169  * 1  1  1      30 / 2          x200/3  x208/2  x88
170  *
171  * *1 : Table 7.5b indicates VCO output (PLL0 = VCO/3)
172  * *2 : Table 7.5b indicates VCO output (PLL1 = VCO/2)
173  */
174 #define CPG_PLL_CONFIG_INDEX(md)        ((((md) & BIT(14)) >> 12) | \
175                                          (((md) & BIT(13)) >> 12) | \
176                                          (((md) & BIT(19)) >> 19))
177 static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = {
178         { 1, 208, 106, 200 },
179         { 1, 208,  88, 200 },
180         { 1, 156,  80, 150 },
181         { 1, 156,  66, 150 },
182         { 2, 240, 122, 230 },
183         { 2, 240, 102, 230 },
184         { 2, 208, 106, 200 },
185         { 2, 208,  88, 200 },
186 };
187
188 static const struct mstp_stop_table r8a7792_mstp_table[] = {
189         { 0x00400801, 0x400000, 0x00400801, 0x0 },
190         { 0x9B6F987F, 0x0, 0x9B6F987F, 0x0 },
191         { 0x108CE100, 0x0, 0x108CE100, 0x80000 },
192         { 0x20004010, 0x4000, 0x20004010, 0x0 },
193         { 0x80000184, 0x180, 0x80000184, 0x0 },
194         { 0x44C00004, 0x0, 0x44C00004, 0x0 },
195         { 0x0, 0x0, 0x0, 0x0 }, /* SMSTP6 is not present on Gen2 */
196         { 0x01BF0000, 0x200000, 0x01BF0000, 0x0 },
197         { 0x1FE01FB0, 0x0, 0x1FE01FB0, 0x0 },
198         { 0xFE2BFFB2, 0x20000, 0xFE2BFFB2, 0x0 },
199         { 0x00001820, 0x0, 0x00001820, 0x0 },
200         { 0x00000008, 0x0, 0x00000008, 0x0 },
201 };
202
203 static const void *r8a7792_get_pll_config(const u32 cpg_mode)
204 {
205         return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
206 }
207
208 static const struct cpg_mssr_info r8a7792_cpg_mssr_info = {
209         .core_clk               = r8a7792_core_clks,
210         .core_clk_size          = ARRAY_SIZE(r8a7792_core_clks),
211         .mod_clk                = r8a7792_mod_clks,
212         .mod_clk_size           = ARRAY_SIZE(r8a7792_mod_clks),
213         .mstp_table             = r8a7792_mstp_table,
214         .mstp_table_size        = ARRAY_SIZE(r8a7792_mstp_table),
215         .reset_node             = "renesas,r8a7792-rst",
216         .mod_clk_base           = MOD_CLK_BASE,
217         .clk_extal_id           = CLK_EXTAL,
218         .pll0_div               = 2,
219         .get_pll_config         = r8a7792_get_pll_config,
220 };
221
222 static const struct udevice_id r8a7792_clk_ids[] = {
223         {
224                 .compatible     = "renesas,r8a7792-cpg-mssr",
225                 .data           = (ulong)&r8a7792_cpg_mssr_info
226         },
227         {
228                 .compatible     = "renesas,r8a7793-cpg-mssr",
229                 .data           = (ulong)&r8a7792_cpg_mssr_info
230         },
231         { }
232 };
233
234 U_BOOT_DRIVER(clk_r8a7792) = {
235         .name           = "clk_r8a7792",
236         .id             = UCLASS_CLK,
237         .of_match       = r8a7792_clk_ids,
238         .priv_auto      = sizeof(struct gen2_clk_priv),
239         .ops            = &gen2_clk_ops,
240         .probe          = gen2_clk_probe,
241         .remove         = gen2_clk_remove,
242 };