drivers/clk/renesas/clk-rcar-gen3.c

   1 /*
   2  * Renesas RCar Gen3 R8A7795/R8A7796 CPG MSSR driver
   3  *
   4  * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
   5  *
   6  * Based on the following driver from Linux kernel:
   7  * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
   8  *
   9  * Copyright (C) 2016 Glider bvba
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 #include <common.h>
  15 #include <clk-uclass.h>
  16 #include <dm.h>
  17 #include <errno.h>
  18 #include <wait_bit.h>
  19 #include <asm/io.h>
  20
  21 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
  22 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
  23
  24 #define CPG_RST_MODEMR          0x0060
  25
  26 #define CPG_PLL0CR              0x00d8
  27 #define CPG_PLL2CR              0x002c
  28 #define CPG_PLL4CR              0x01f4
  29
  30 /*
  31  * Module Standby and Software Reset register offets.
  32  *
  33  * If the registers exist, these are valid for SH-Mobile, R-Mobile,
  34  * R-Car Gen2, R-Car Gen3, and RZ/G1.
  35  * These are NOT valid for R-Car Gen1 and RZ/A1!
  36  */
  37
  38 /*
  39  * Module Stop Status Register offsets
  40  */
  41
  42 static const u16 mstpsr[] = {
  43         0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
  44         0x9A0, 0x9A4, 0x9A8, 0x9AC,
  45 };
  46
  47 #define MSTPSR(i)       mstpsr[i]
  48
  49
  50 /*
  51  * System Module Stop Control Register offsets
  52  */
  53
  54 static const u16 smstpcr[] = {
  55         0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
  56         0x990, 0x994, 0x998, 0x99C,
  57 };
  58
  59 #define SMSTPCR(i)      smstpcr[i]
  60
  61
  62 /* Realtime Module Stop Control Register offsets */
  63 #define RMSTPCR(i)      (smstpcr[i] - 0x20)
  64
  65 /* Modem Module Stop Control Register offsets (r8a73a4) */
  66 #define MMSTPCR(i)      (smstpcr[i] + 0x20)
  67
  68 /* Software Reset Clearing Register offsets */
  69 #define SRSTCLR(i)      (0x940 + (i) * 4)
  70
  71 struct gen3_clk_priv {
  72         void __iomem    *base;
  73         struct clk      clk_extal;
  74         struct clk      clk_extalr;
  75         const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
  76         const struct mssr_mod_clk *mod_clk;
  77         u32             mod_clk_size;
  78 };
  79
  80 /*
  81  * Definitions of CPG Core Clocks
  82  *
  83  * These include:
  84  *   - Clock outputs exported to DT
  85  *   - External input clocks
  86  *   - Internal CPG clocks
  87  */
  88 struct cpg_core_clk {
  89         /* Common */
  90         const char *name;
  91         unsigned int id;
  92         unsigned int type;
  93         /* Depending on type */
  94         unsigned int parent;    /* Core Clocks only */
  95         unsigned int div;
  96         unsigned int mult;
  97         unsigned int offset;
  98 };
  99
 100 enum clk_types {
 101         /* Generic */
 102         CLK_TYPE_IN,            /* External Clock Input */
 103         CLK_TYPE_FF,            /* Fixed Factor Clock */
 104
 105         /* Custom definitions start here */
 106         CLK_TYPE_CUSTOM,
 107 };
 108
 109 #define DEF_TYPE(_name, _id, _type...)  \
 110         { .name = _name, .id = _id, .type = _type }
 111 #define DEF_BASE(_name, _id, _type, _parent...) \
 112         DEF_TYPE(_name, _id, _type, .parent = _parent)
 113
 114 #define DEF_INPUT(_name, _id) \
 115         DEF_TYPE(_name, _id, CLK_TYPE_IN)
 116 #define DEF_FIXED(_name, _id, _parent, _div, _mult)     \
 117         DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
 118 #define DEF_GEN3_SD(_name, _id, _parent, _offset)       \
 119         DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
 120
 121 /*
 122  * Definitions of Module Clocks
 123  */
 124 struct mssr_mod_clk {
 125         const char *name;
 126         unsigned int id;
 127         unsigned int parent;    /* Add MOD_CLK_BASE for Module Clocks */
 128 };
 129
 130 /* Convert from sparse base-100 to packed index space */
 131 #define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
 132
 133 #define MOD_CLK_ID(x)   (MOD_CLK_BASE + MOD_CLK_PACK(x))
 134
 135 #define DEF_MOD(_name, _mod, _parent...)        \
 136         { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
 137
 138 enum rcar_gen3_clk_types {
 139         CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
 140         CLK_TYPE_GEN3_PLL0,
 141         CLK_TYPE_GEN3_PLL1,
 142         CLK_TYPE_GEN3_PLL2,
 143         CLK_TYPE_GEN3_PLL3,
 144         CLK_TYPE_GEN3_PLL4,
 145         CLK_TYPE_GEN3_SD,
 146         CLK_TYPE_GEN3_R,
 147 };
 148
 149 struct rcar_gen3_cpg_pll_config {
 150         unsigned int extal_div;
 151         unsigned int pll1_mult;
 152         unsigned int pll3_mult;
 153 };
 154
 155 enum clk_ids {
 156         /* Core Clock Outputs exported to DT */
 157         LAST_DT_CORE_CLK = R8A7796_CLK_OSC,
 158
 159         /* External Input Clocks */
 160         CLK_EXTAL,
 161         CLK_EXTALR,
 162
 163         /* Internal Core Clocks */
 164         CLK_MAIN,
 165         CLK_PLL0,
 166         CLK_PLL1,
 167         CLK_PLL2,
 168         CLK_PLL3,
 169         CLK_PLL4,
 170         CLK_PLL1_DIV2,
 171         CLK_PLL1_DIV4,
 172         CLK_S0,
 173         CLK_S1,
 174         CLK_S2,
 175         CLK_S3,
 176         CLK_SDSRC,
 177         CLK_SSPSRC,
 178         CLK_RINT,
 179
 180         /* Module Clocks */
 181         MOD_CLK_BASE
 182 };
 183
 184 static const struct cpg_core_clk gen3_core_clks[] = {
 185         /* External Clock Inputs */
 186         DEF_INPUT("extal",      CLK_EXTAL),
 187         DEF_INPUT("extalr",     CLK_EXTALR),
 188
 189         /* Internal Core Clocks */
 190         DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
 191         DEF_BASE(".pll0",       CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
 192         DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
 193         DEF_BASE(".pll2",       CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
 194         DEF_BASE(".pll3",       CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
 195         DEF_BASE(".pll4",       CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
 196
 197         DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,     CLK_PLL1,       2, 1),
 198         DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4,     CLK_PLL1_DIV2,  2, 1),
 199         DEF_FIXED(".s0",        CLK_S0,            CLK_PLL1_DIV2,  2, 1),
 200         DEF_FIXED(".s1",        CLK_S1,            CLK_PLL1_DIV2,  3, 1),
 201         DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,  4, 1),
 202         DEF_FIXED(".s3",        CLK_S3,            CLK_PLL1_DIV2,  6, 1),
 203         DEF_FIXED(".sdsrc",     CLK_SDSRC,         CLK_PLL1_DIV2,  2, 1),
 204
 205         /* Core Clock Outputs */
 206         DEF_FIXED("ztr",        R8A7796_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
 207         DEF_FIXED("ztrd2",      R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
 208         DEF_FIXED("zt",         R8A7796_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
 209         DEF_FIXED("zx",         R8A7796_CLK_ZX,    CLK_PLL1_DIV2,  2, 1),
 210         DEF_FIXED("s0d1",       R8A7796_CLK_S0D1,  CLK_S0,         1, 1),
 211         DEF_FIXED("s0d2",       R8A7796_CLK_S0D2,  CLK_S0,         2, 1),
 212         DEF_FIXED("s0d3",       R8A7796_CLK_S0D3,  CLK_S0,         3, 1),
 213         DEF_FIXED("s0d4",       R8A7796_CLK_S0D4,  CLK_S0,         4, 1),
 214         DEF_FIXED("s0d6",       R8A7796_CLK_S0D6,  CLK_S0,         6, 1),
 215         DEF_FIXED("s0d8",       R8A7796_CLK_S0D8,  CLK_S0,         8, 1),
 216         DEF_FIXED("s0d12",      R8A7796_CLK_S0D12, CLK_S0,        12, 1),
 217         DEF_FIXED("s1d1",       R8A7796_CLK_S1D1,  CLK_S1,         1, 1),
 218         DEF_FIXED("s1d2",       R8A7796_CLK_S1D2,  CLK_S1,         2, 1),
 219         DEF_FIXED("s1d4",       R8A7796_CLK_S1D4,  CLK_S1,         4, 1),
 220         DEF_FIXED("s2d1",       R8A7796_CLK_S2D1,  CLK_S2,         1, 1),
 221         DEF_FIXED("s2d2",       R8A7796_CLK_S2D2,  CLK_S2,         2, 1),
 222         DEF_FIXED("s2d4",       R8A7796_CLK_S2D4,  CLK_S2,         4, 1),
 223         DEF_FIXED("s3d1",       R8A7796_CLK_S3D1,  CLK_S3,         1, 1),
 224         DEF_FIXED("s3d2",       R8A7796_CLK_S3D2,  CLK_S3,         2, 1),
 225         DEF_FIXED("s3d4",       R8A7796_CLK_S3D4,  CLK_S3,         4, 1),
 226
 227         DEF_GEN3_SD("sd0",      R8A7796_CLK_SD0,   CLK_SDSRC,     0x074),
 228         DEF_GEN3_SD("sd1",      R8A7796_CLK_SD1,   CLK_SDSRC,     0x078),
 229         DEF_GEN3_SD("sd2",      R8A7796_CLK_SD2,   CLK_SDSRC,     0x268),
 230         DEF_GEN3_SD("sd3",      R8A7796_CLK_SD3,   CLK_SDSRC,     0x26c),
 231
 232         DEF_FIXED("cl",         R8A7796_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
 233         DEF_FIXED("cp",         R8A7796_CLK_CP,    CLK_EXTAL,      2, 1),
 234
 235         /* NOTE: HDMI, CSI, CAN etc. clock are missing */
 236
 237         DEF_BASE("r",           R8A7796_CLK_R,     CLK_TYPE_GEN3_R, CLK_RINT),
 238 };
 239
 240 static const struct mssr_mod_clk r8a7795_mod_clks[] = {
 241         DEF_MOD("fdp1-2",                117,   R8A7795_CLK_S2D1), /* ES1.x */
 242         DEF_MOD("fdp1-1",                118,   R8A7795_CLK_S0D1),
 243         DEF_MOD("fdp1-0",                119,   R8A7795_CLK_S0D1),
 244         DEF_MOD("scif5",                 202,   R8A7795_CLK_S3D4),
 245         DEF_MOD("scif4",                 203,   R8A7795_CLK_S3D4),
 246         DEF_MOD("scif3",                 204,   R8A7795_CLK_S3D4),
 247         DEF_MOD("scif1",                 206,   R8A7795_CLK_S3D4),
 248         DEF_MOD("scif0",                 207,   R8A7795_CLK_S3D4),
 249         DEF_MOD("msiof3",                208,   R8A7795_CLK_MSO),
 250         DEF_MOD("msiof2",                209,   R8A7795_CLK_MSO),
 251         DEF_MOD("msiof1",                210,   R8A7795_CLK_MSO),
 252         DEF_MOD("msiof0",                211,   R8A7795_CLK_MSO),
 253         DEF_MOD("sys-dmac2",             217,   R8A7795_CLK_S0D3),
 254         DEF_MOD("sys-dmac1",             218,   R8A7795_CLK_S0D3),
 255         DEF_MOD("sys-dmac0",             219,   R8A7795_CLK_S0D3),
 256         DEF_MOD("cmt3",                  300,   R8A7795_CLK_R),
 257         DEF_MOD("cmt2",                  301,   R8A7795_CLK_R),
 258         DEF_MOD("cmt1",                  302,   R8A7795_CLK_R),
 259         DEF_MOD("cmt0",                  303,   R8A7795_CLK_R),
 260         DEF_MOD("scif2",                 310,   R8A7795_CLK_S3D4),
 261         DEF_MOD("sdif3",                 311,   R8A7795_CLK_SD3),
 262         DEF_MOD("sdif2",                 312,   R8A7795_CLK_SD2),
 263         DEF_MOD("sdif1",                 313,   R8A7795_CLK_SD1),
 264         DEF_MOD("sdif0",                 314,   R8A7795_CLK_SD0),
 265         DEF_MOD("pcie1",                 318,   R8A7795_CLK_S3D1),
 266         DEF_MOD("pcie0",                 319,   R8A7795_CLK_S3D1),
 267         DEF_MOD("usb-dmac30",            326,   R8A7795_CLK_S3D1),
 268         DEF_MOD("usb3-if1",              327,   R8A7795_CLK_S3D1), /* ES1.x */
 269         DEF_MOD("usb3-if0",              328,   R8A7795_CLK_S3D1),
 270         DEF_MOD("usb-dmac31",            329,   R8A7795_CLK_S3D1),
 271         DEF_MOD("usb-dmac0",             330,   R8A7795_CLK_S3D1),
 272         DEF_MOD("usb-dmac1",             331,   R8A7795_CLK_S3D1),
 273         DEF_MOD("rwdt",                  402,   R8A7795_CLK_R),
 274         DEF_MOD("intc-ex",               407,   R8A7795_CLK_CP),
 275         DEF_MOD("intc-ap",               408,   R8A7795_CLK_S3D1),
 276         DEF_MOD("audmac1",               501,   R8A7795_CLK_S0D3),
 277         DEF_MOD("audmac0",               502,   R8A7795_CLK_S0D3),
 278         DEF_MOD("drif7",                 508,   R8A7795_CLK_S3D2),
 279         DEF_MOD("drif6",                 509,   R8A7795_CLK_S3D2),
 280         DEF_MOD("drif5",                 510,   R8A7795_CLK_S3D2),
 281         DEF_MOD("drif4",                 511,   R8A7795_CLK_S3D2),
 282         DEF_MOD("drif3",                 512,   R8A7795_CLK_S3D2),
 283         DEF_MOD("drif2",                 513,   R8A7795_CLK_S3D2),
 284         DEF_MOD("drif1",                 514,   R8A7795_CLK_S3D2),
 285         DEF_MOD("drif0",                 515,   R8A7795_CLK_S3D2),
 286         DEF_MOD("hscif4",                516,   R8A7795_CLK_S3D1),
 287         DEF_MOD("hscif3",                517,   R8A7795_CLK_S3D1),
 288         DEF_MOD("hscif2",                518,   R8A7795_CLK_S3D1),
 289         DEF_MOD("hscif1",                519,   R8A7795_CLK_S3D1),
 290         DEF_MOD("hscif0",                520,   R8A7795_CLK_S3D1),
 291         DEF_MOD("thermal",               522,   R8A7795_CLK_CP),
 292         DEF_MOD("pwm",                   523,   R8A7795_CLK_S0D12),
 293         DEF_MOD("fcpvd3",                600,   R8A7795_CLK_S2D1), /* ES1.x */
 294         DEF_MOD("fcpvd2",                601,   R8A7795_CLK_S0D2),
 295         DEF_MOD("fcpvd1",                602,   R8A7795_CLK_S0D2),
 296         DEF_MOD("fcpvd0",                603,   R8A7795_CLK_S0D2),
 297         DEF_MOD("fcpvb1",                606,   R8A7795_CLK_S0D1),
 298         DEF_MOD("fcpvb0",                607,   R8A7795_CLK_S0D1),
 299         DEF_MOD("fcpvi2",                609,   R8A7795_CLK_S2D1), /* ES1.x */
 300         DEF_MOD("fcpvi1",                610,   R8A7795_CLK_S0D1),
 301         DEF_MOD("fcpvi0",                611,   R8A7795_CLK_S0D1),
 302         DEF_MOD("fcpf2",                 613,   R8A7795_CLK_S2D1), /* ES1.x */
 303         DEF_MOD("fcpf1",                 614,   R8A7795_CLK_S0D1),
 304         DEF_MOD("fcpf0",                 615,   R8A7795_CLK_S0D1),
 305         DEF_MOD("fcpci1",                616,   R8A7795_CLK_S2D1), /* ES1.x */
 306         DEF_MOD("fcpci0",                617,   R8A7795_CLK_S2D1), /* ES1.x */
 307         DEF_MOD("fcpcs",                 619,   R8A7795_CLK_S0D1),
 308         DEF_MOD("vspd3",                 620,   R8A7795_CLK_S2D1), /* ES1.x */
 309         DEF_MOD("vspd2",                 621,   R8A7795_CLK_S0D2),
 310         DEF_MOD("vspd1",                 622,   R8A7795_CLK_S0D2),
 311         DEF_MOD("vspd0",                 623,   R8A7795_CLK_S0D2),
 312         DEF_MOD("vspbc",                 624,   R8A7795_CLK_S0D1),
 313         DEF_MOD("vspbd",                 626,   R8A7795_CLK_S0D1),
 314         DEF_MOD("vspi2",                 629,   R8A7795_CLK_S2D1), /* ES1.x */
 315         DEF_MOD("vspi1",                 630,   R8A7795_CLK_S0D1),
 316         DEF_MOD("vspi0",                 631,   R8A7795_CLK_S0D1),
 317         DEF_MOD("ehci3",                 700,   R8A7795_CLK_S3D4),
 318         DEF_MOD("ehci2",                 701,   R8A7795_CLK_S3D4),
 319         DEF_MOD("ehci1",                 702,   R8A7795_CLK_S3D4),
 320         DEF_MOD("ehci0",                 703,   R8A7795_CLK_S3D4),
 321         DEF_MOD("hsusb",                 704,   R8A7795_CLK_S3D4),
 322         DEF_MOD("hsusb3",                705,   R8A7795_CLK_S3D4),
 323         DEF_MOD("csi21",                 713,   R8A7795_CLK_CSI0), /* ES1.x */
 324         DEF_MOD("csi20",                 714,   R8A7795_CLK_CSI0),
 325         DEF_MOD("csi41",                 715,   R8A7795_CLK_CSI0),
 326         DEF_MOD("csi40",                 716,   R8A7795_CLK_CSI0),
 327         DEF_MOD("du3",                   721,   R8A7795_CLK_S2D1),
 328         DEF_MOD("du2",                   722,   R8A7795_CLK_S2D1),
 329         DEF_MOD("du1",                   723,   R8A7795_CLK_S2D1),
 330         DEF_MOD("du0",                   724,   R8A7795_CLK_S2D1),
 331         DEF_MOD("lvds",                  727,   R8A7795_CLK_S0D4),
 332         DEF_MOD("hdmi1",                 728,   R8A7795_CLK_HDMI),
 333         DEF_MOD("hdmi0",                 729,   R8A7795_CLK_HDMI),
 334         DEF_MOD("vin7",                  804,   R8A7795_CLK_S0D2),
 335         DEF_MOD("vin6",                  805,   R8A7795_CLK_S0D2),
 336         DEF_MOD("vin5",                  806,   R8A7795_CLK_S0D2),
 337         DEF_MOD("vin4",                  807,   R8A7795_CLK_S0D2),
 338         DEF_MOD("vin3",                  808,   R8A7795_CLK_S0D2),
 339         DEF_MOD("vin2",                  809,   R8A7795_CLK_S0D2),
 340         DEF_MOD("vin1",                  810,   R8A7795_CLK_S0D2),
 341         DEF_MOD("vin0",                  811,   R8A7795_CLK_S0D2),
 342         DEF_MOD("etheravb",              812,   R8A7795_CLK_S0D6),
 343         DEF_MOD("sata0",                 815,   R8A7795_CLK_S3D2),
 344         DEF_MOD("imr3",                  820,   R8A7795_CLK_S0D2),
 345         DEF_MOD("imr2",                  821,   R8A7795_CLK_S0D2),
 346         DEF_MOD("imr1",                  822,   R8A7795_CLK_S0D2),
 347         DEF_MOD("imr0",                  823,   R8A7795_CLK_S0D2),
 348         DEF_MOD("gpio7",                 905,   R8A7795_CLK_S3D4),
 349         DEF_MOD("gpio6",                 906,   R8A7795_CLK_S3D4),
 350         DEF_MOD("gpio5",                 907,   R8A7795_CLK_S3D4),
 351         DEF_MOD("gpio4",                 908,   R8A7795_CLK_S3D4),
 352         DEF_MOD("gpio3",                 909,   R8A7795_CLK_S3D4),
 353         DEF_MOD("gpio2",                 910,   R8A7795_CLK_S3D4),
 354         DEF_MOD("gpio1",                 911,   R8A7795_CLK_S3D4),
 355         DEF_MOD("gpio0",                 912,   R8A7795_CLK_S3D4),
 356         DEF_MOD("can-fd",                914,   R8A7795_CLK_S3D2),
 357         DEF_MOD("can-if1",               915,   R8A7795_CLK_S3D4),
 358         DEF_MOD("can-if0",               916,   R8A7795_CLK_S3D4),
 359         DEF_MOD("i2c6",                  918,   R8A7795_CLK_S0D6),
 360         DEF_MOD("i2c5",                  919,   R8A7795_CLK_S0D6),
 361         DEF_MOD("i2c-dvfs",              926,   R8A7795_CLK_CP),
 362         DEF_MOD("i2c4",                  927,   R8A7795_CLK_S0D6),
 363         DEF_MOD("i2c3",                  928,   R8A7795_CLK_S0D6),
 364         DEF_MOD("i2c2",                  929,   R8A7795_CLK_S3D2),
 365         DEF_MOD("i2c1",                  930,   R8A7795_CLK_S3D2),
 366         DEF_MOD("i2c0",                  931,   R8A7795_CLK_S3D2),
 367         DEF_MOD("ssi-all",              1005,   R8A7795_CLK_S3D4),
 368         DEF_MOD("ssi9",                 1006,   MOD_CLK_ID(1005)),
 369         DEF_MOD("ssi8",                 1007,   MOD_CLK_ID(1005)),
 370         DEF_MOD("ssi7",                 1008,   MOD_CLK_ID(1005)),
 371         DEF_MOD("ssi6",                 1009,   MOD_CLK_ID(1005)),
 372         DEF_MOD("ssi5",                 1010,   MOD_CLK_ID(1005)),
 373         DEF_MOD("ssi4",                 1011,   MOD_CLK_ID(1005)),
 374         DEF_MOD("ssi3",                 1012,   MOD_CLK_ID(1005)),
 375         DEF_MOD("ssi2",                 1013,   MOD_CLK_ID(1005)),
 376         DEF_MOD("ssi1",                 1014,   MOD_CLK_ID(1005)),
 377         DEF_MOD("ssi0",                 1015,   MOD_CLK_ID(1005)),
 378         DEF_MOD("scu-all",              1017,   R8A7795_CLK_S3D4),
 379         DEF_MOD("scu-dvc1",             1018,   MOD_CLK_ID(1017)),
 380         DEF_MOD("scu-dvc0",             1019,   MOD_CLK_ID(1017)),
 381         DEF_MOD("scu-ctu1-mix1",        1020,   MOD_CLK_ID(1017)),
 382         DEF_MOD("scu-ctu0-mix0",        1021,   MOD_CLK_ID(1017)),
 383         DEF_MOD("scu-src9",             1022,   MOD_CLK_ID(1017)),
 384         DEF_MOD("scu-src8",             1023,   MOD_CLK_ID(1017)),
 385         DEF_MOD("scu-src7",             1024,   MOD_CLK_ID(1017)),
 386         DEF_MOD("scu-src6",             1025,   MOD_CLK_ID(1017)),
 387         DEF_MOD("scu-src5",             1026,   MOD_CLK_ID(1017)),
 388         DEF_MOD("scu-src4",             1027,   MOD_CLK_ID(1017)),
 389         DEF_MOD("scu-src3",             1028,   MOD_CLK_ID(1017)),
 390         DEF_MOD("scu-src2",             1029,   MOD_CLK_ID(1017)),
 391         DEF_MOD("scu-src1",             1030,   MOD_CLK_ID(1017)),
 392         DEF_MOD("scu-src0",             1031,   MOD_CLK_ID(1017)),
 393 };
 394
 395 static const struct mssr_mod_clk r8a7796_mod_clks[] = {
 396         DEF_MOD("scif5",                 202,   R8A7796_CLK_S3D4),
 397         DEF_MOD("scif4",                 203,   R8A7796_CLK_S3D4),
 398         DEF_MOD("scif3",                 204,   R8A7796_CLK_S3D4),
 399         DEF_MOD("scif1",                 206,   R8A7796_CLK_S3D4),
 400         DEF_MOD("scif0",                 207,   R8A7796_CLK_S3D4),
 401         DEF_MOD("msiof3",                208,   R8A7796_CLK_MSO),
 402         DEF_MOD("msiof2",                209,   R8A7796_CLK_MSO),
 403         DEF_MOD("msiof1",                210,   R8A7796_CLK_MSO),
 404         DEF_MOD("msiof0",                211,   R8A7796_CLK_MSO),
 405         DEF_MOD("sys-dmac2",             217,   R8A7796_CLK_S0D3),
 406         DEF_MOD("sys-dmac1",             218,   R8A7796_CLK_S0D3),
 407         DEF_MOD("sys-dmac0",             219,   R8A7796_CLK_S0D3),
 408         DEF_MOD("cmt3",                  300,   R8A7796_CLK_R),
 409         DEF_MOD("cmt2",                  301,   R8A7796_CLK_R),
 410         DEF_MOD("cmt1",                  302,   R8A7796_CLK_R),
 411         DEF_MOD("cmt0",                  303,   R8A7796_CLK_R),
 412         DEF_MOD("scif2",                 310,   R8A7796_CLK_S3D4),
 413         DEF_MOD("sdif3",                 311,   R8A7796_CLK_SD3),
 414         DEF_MOD("sdif2",                 312,   R8A7796_CLK_SD2),
 415         DEF_MOD("sdif1",                 313,   R8A7796_CLK_SD1),
 416         DEF_MOD("sdif0",                 314,   R8A7796_CLK_SD0),
 417         DEF_MOD("pcie1",                 318,   R8A7796_CLK_S3D1),
 418         DEF_MOD("pcie0",                 319,   R8A7796_CLK_S3D1),
 419         DEF_MOD("usb-dmac0",             330,   R8A7796_CLK_S3D1),
 420         DEF_MOD("usb-dmac1",             331,   R8A7796_CLK_S3D1),
 421         DEF_MOD("rwdt",                  402,   R8A7796_CLK_R),
 422         DEF_MOD("intc-ex",               407,   R8A7796_CLK_CP),
 423         DEF_MOD("intc-ap",               408,   R8A7796_CLK_S3D1),
 424         DEF_MOD("audmac1",               501,   R8A7796_CLK_S0D3),
 425         DEF_MOD("audmac0",               502,   R8A7796_CLK_S0D3),
 426         DEF_MOD("drif7",                 508,   R8A7796_CLK_S3D2),
 427         DEF_MOD("drif6",                 509,   R8A7796_CLK_S3D2),
 428         DEF_MOD("drif5",                 510,   R8A7796_CLK_S3D2),
 429         DEF_MOD("drif4",                 511,   R8A7796_CLK_S3D2),
 430         DEF_MOD("drif3",                 512,   R8A7796_CLK_S3D2),
 431         DEF_MOD("drif2",                 513,   R8A7796_CLK_S3D2),
 432         DEF_MOD("drif1",                 514,   R8A7796_CLK_S3D2),
 433         DEF_MOD("drif0",                 515,   R8A7796_CLK_S3D2),
 434         DEF_MOD("hscif4",                516,   R8A7796_CLK_S3D1),
 435         DEF_MOD("hscif3",                517,   R8A7796_CLK_S3D1),
 436         DEF_MOD("hscif2",                518,   R8A7796_CLK_S3D1),
 437         DEF_MOD("hscif1",                519,   R8A7796_CLK_S3D1),
 438         DEF_MOD("hscif0",                520,   R8A7796_CLK_S3D1),
 439         DEF_MOD("thermal",               522,   R8A7796_CLK_CP),
 440         DEF_MOD("pwm",                   523,   R8A7796_CLK_S0D12),
 441         DEF_MOD("fcpvd2",                601,   R8A7796_CLK_S0D2),
 442         DEF_MOD("fcpvd1",                602,   R8A7796_CLK_S0D2),
 443         DEF_MOD("fcpvd0",                603,   R8A7796_CLK_S0D2),
 444         DEF_MOD("fcpvb0",                607,   R8A7796_CLK_S0D1),
 445         DEF_MOD("fcpvi0",                611,   R8A7796_CLK_S0D1),
 446         DEF_MOD("fcpf0",                 615,   R8A7796_CLK_S0D1),
 447         DEF_MOD("fcpci0",                617,   R8A7796_CLK_S0D2),
 448         DEF_MOD("fcpcs",                 619,   R8A7796_CLK_S0D2),
 449         DEF_MOD("vspd2",                 621,   R8A7796_CLK_S0D2),
 450         DEF_MOD("vspd1",                 622,   R8A7796_CLK_S0D2),
 451         DEF_MOD("vspd0",                 623,   R8A7796_CLK_S0D2),
 452         DEF_MOD("vspb",                  626,   R8A7796_CLK_S0D1),
 453         DEF_MOD("vspi0",                 631,   R8A7796_CLK_S0D1),
 454         DEF_MOD("ehci1",                 702,   R8A7796_CLK_S3D4),
 455         DEF_MOD("ehci0",                 703,   R8A7796_CLK_S3D4),
 456         DEF_MOD("hsusb",                 704,   R8A7796_CLK_S3D4),
 457         DEF_MOD("csi20",                 714,   R8A7796_CLK_CSI0),
 458         DEF_MOD("csi40",                 716,   R8A7796_CLK_CSI0),
 459         DEF_MOD("du2",                   722,   R8A7796_CLK_S2D1),
 460         DEF_MOD("du1",                   723,   R8A7796_CLK_S2D1),
 461         DEF_MOD("du0",                   724,   R8A7796_CLK_S2D1),
 462         DEF_MOD("lvds",                  727,   R8A7796_CLK_S2D1),
 463         DEF_MOD("hdmi0",                 729,   R8A7796_CLK_HDMI),
 464         DEF_MOD("vin7",                  804,   R8A7796_CLK_S0D2),
 465         DEF_MOD("vin6",                  805,   R8A7796_CLK_S0D2),
 466         DEF_MOD("vin5",                  806,   R8A7796_CLK_S0D2),
 467         DEF_MOD("vin4",                  807,   R8A7796_CLK_S0D2),
 468         DEF_MOD("vin3",                  808,   R8A7796_CLK_S0D2),
 469         DEF_MOD("vin2",                  809,   R8A7796_CLK_S0D2),
 470         DEF_MOD("vin1",                  810,   R8A7796_CLK_S0D2),
 471         DEF_MOD("vin0",                  811,   R8A7796_CLK_S0D2),
 472         DEF_MOD("etheravb",              812,   R8A7796_CLK_S0D6),
 473         DEF_MOD("imr1",                  822,   R8A7796_CLK_S0D2),
 474         DEF_MOD("imr0",                  823,   R8A7796_CLK_S0D2),
 475         DEF_MOD("gpio7",                 905,   R8A7796_CLK_S3D4),
 476         DEF_MOD("gpio6",                 906,   R8A7796_CLK_S3D4),
 477         DEF_MOD("gpio5",                 907,   R8A7796_CLK_S3D4),
 478         DEF_MOD("gpio4",                 908,   R8A7796_CLK_S3D4),
 479         DEF_MOD("gpio3",                 909,   R8A7796_CLK_S3D4),
 480         DEF_MOD("gpio2",                 910,   R8A7796_CLK_S3D4),
 481         DEF_MOD("gpio1",                 911,   R8A7796_CLK_S3D4),
 482         DEF_MOD("gpio0",                 912,   R8A7796_CLK_S3D4),
 483         DEF_MOD("can-fd",                914,   R8A7796_CLK_S3D2),
 484         DEF_MOD("can-if1",               915,   R8A7796_CLK_S3D4),
 485         DEF_MOD("can-if0",               916,   R8A7796_CLK_S3D4),
 486         DEF_MOD("i2c6",                  918,   R8A7796_CLK_S0D6),
 487         DEF_MOD("i2c5",                  919,   R8A7796_CLK_S0D6),
 488         DEF_MOD("i2c-dvfs",              926,   R8A7796_CLK_CP),
 489         DEF_MOD("i2c4",                  927,   R8A7796_CLK_S0D6),
 490         DEF_MOD("i2c3",                  928,   R8A7796_CLK_S0D6),
 491         DEF_MOD("i2c2",                  929,   R8A7796_CLK_S3D2),
 492         DEF_MOD("i2c1",                  930,   R8A7796_CLK_S3D2),
 493         DEF_MOD("i2c0",                  931,   R8A7796_CLK_S3D2),
 494         DEF_MOD("ssi-all",              1005,   R8A7796_CLK_S3D4),
 495         DEF_MOD("ssi9",                 1006,   MOD_CLK_ID(1005)),
 496         DEF_MOD("ssi8",                 1007,   MOD_CLK_ID(1005)),
 497         DEF_MOD("ssi7",                 1008,   MOD_CLK_ID(1005)),
 498         DEF_MOD("ssi6",                 1009,   MOD_CLK_ID(1005)),
 499         DEF_MOD("ssi5",                 1010,   MOD_CLK_ID(1005)),
 500         DEF_MOD("ssi4",                 1011,   MOD_CLK_ID(1005)),
 501         DEF_MOD("ssi3",                 1012,   MOD_CLK_ID(1005)),
 502         DEF_MOD("ssi2",                 1013,   MOD_CLK_ID(1005)),
 503         DEF_MOD("ssi1",                 1014,   MOD_CLK_ID(1005)),
 504         DEF_MOD("ssi0",                 1015,   MOD_CLK_ID(1005)),
 505         DEF_MOD("scu-all",              1017,   R8A7796_CLK_S3D4),
 506         DEF_MOD("scu-dvc1",             1018,   MOD_CLK_ID(1017)),
 507         DEF_MOD("scu-dvc0",             1019,   MOD_CLK_ID(1017)),
 508         DEF_MOD("scu-ctu1-mix1",        1020,   MOD_CLK_ID(1017)),
 509         DEF_MOD("scu-ctu0-mix0",        1021,   MOD_CLK_ID(1017)),
 510         DEF_MOD("scu-src9",             1022,   MOD_CLK_ID(1017)),
 511         DEF_MOD("scu-src8",             1023,   MOD_CLK_ID(1017)),
 512         DEF_MOD("scu-src7",             1024,   MOD_CLK_ID(1017)),
 513         DEF_MOD("scu-src6",             1025,   MOD_CLK_ID(1017)),
 514         DEF_MOD("scu-src5",             1026,   MOD_CLK_ID(1017)),
 515         DEF_MOD("scu-src4",             1027,   MOD_CLK_ID(1017)),
 516         DEF_MOD("scu-src3",             1028,   MOD_CLK_ID(1017)),
 517         DEF_MOD("scu-src2",             1029,   MOD_CLK_ID(1017)),
 518         DEF_MOD("scu-src1",             1030,   MOD_CLK_ID(1017)),
 519         DEF_MOD("scu-src0",             1031,   MOD_CLK_ID(1017)),
 520 };
 521
 522 /*
 523  * CPG Clock Data
 524  */
 525
 526 /*
 527  *   MD         EXTAL           PLL0    PLL1    PLL2    PLL3    PLL4
 528  * 14 13 19 17  (MHz)
 529  *-------------------------------------------------------------------
 530  * 0  0  0  0   16.66 x 1       x180    x192    x144    x192    x144
 531  * 0  0  0  1   16.66 x 1       x180    x192    x144    x128    x144
 532  * 0  0  1  0   Prohibited setting
 533  * 0  0  1  1   16.66 x 1       x180    x192    x144    x192    x144
 534  * 0  1  0  0   20    x 1       x150    x160    x120    x160    x120
 535  * 0  1  0  1   20    x 1       x150    x160    x120    x106    x120
 536  * 0  1  1  0   Prohibited setting
 537  * 0  1  1  1   20    x 1       x150    x160    x120    x160    x120
 538  * 1  0  0  0   25    x 1       x120    x128    x96     x128    x96
 539  * 1  0  0  1   25    x 1       x120    x128    x96     x84     x96
 540  * 1  0  1  0   Prohibited setting
 541  * 1  0  1  1   25    x 1       x120    x128    x96     x128    x96
 542  * 1  1  0  0   33.33 / 2       x180    x192    x144    x192    x144
 543  * 1  1  0  1   33.33 / 2       x180    x192    x144    x128    x144
 544  * 1  1  1  0   Prohibited setting
 545  * 1  1  1  1   33.33 / 2       x180    x192    x144    x192    x144
 546  */
 547 #define CPG_PLL_CONFIG_INDEX(md)        ((((md) & BIT(14)) >> 11) | \
 548                                          (((md) & BIT(13)) >> 11) | \
 549                                          (((md) & BIT(19)) >> 18) | \
 550                                          (((md) & BIT(17)) >> 17))
 551
 552 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
 553         /* EXTAL div    PLL1 mult       PLL3 mult */
 554         { 1,            192,            192,    },
 555         { 1,            192,            128,    },
 556         { 0, /* Prohibited setting */           },
 557         { 1,            192,            192,    },
 558         { 1,            160,            160,    },
 559         { 1,            160,            106,    },
 560         { 0, /* Prohibited setting */           },
 561         { 1,            160,            160,    },
 562         { 1,            128,            128,    },
 563         { 1,            128,            84,     },
 564         { 0, /* Prohibited setting */           },
 565         { 1,            128,            128,    },
 566         { 2,            192,            192,    },
 567         { 2,            192,            128,    },
 568         { 0, /* Prohibited setting */           },
 569         { 2,            192,            192,    },
 570 };
 571
 572 /*
 573  * SDn Clock
 574  */
 575 #define CPG_SD_STP_HCK          BIT(9)
 576 #define CPG_SD_STP_CK           BIT(8)
 577
 578 #define CPG_SD_STP_MASK         (CPG_SD_STP_HCK | CPG_SD_STP_CK)
 579 #define CPG_SD_FC_MASK          (0x7 << 2 | 0x3 << 0)
 580
 581 #define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
 582 { \
 583         .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
 584                ((stp_ck) ? CPG_SD_STP_CK : 0) | \
 585                ((sd_srcfc) << 2) | \
 586                ((sd_fc) << 0), \
 587         .div = (sd_div), \
 588 }
 589
 590 struct sd_div_table {
 591         u32 val;
 592         unsigned int div;
 593 };
 594
 595 /* SDn divider
 596  *                     sd_srcfc   sd_fc   div
 597  * stp_hck   stp_ck    (div)      (div)     = sd_srcfc x sd_fc
 598  *-------------------------------------------------------------------
 599  *  0         0         0 (1)      1 (4)      4
 600  *  0         0         1 (2)      1 (4)      8
 601  *  1         0         2 (4)      1 (4)     16
 602  *  1         0         3 (8)      1 (4)     32
 603  *  1         0         4 (16)     1 (4)     64
 604  *  0         0         0 (1)      0 (2)      2
 605  *  0         0         1 (2)      0 (2)      4
 606  *  1         0         2 (4)      0 (2)      8
 607  *  1         0         3 (8)      0 (2)     16
 608  *  1         0         4 (16)     0 (2)     32
 609  */
 610 static const struct sd_div_table cpg_sd_div_table[] = {
 611 /*      CPG_SD_DIV_TABLE_DATA(stp_hck,  stp_ck,   sd_srcfc,   sd_fc,  sd_div) */
 612         CPG_SD_DIV_TABLE_DATA(0,        0,        0,          1,        4),
 613         CPG_SD_DIV_TABLE_DATA(0,        0,        1,          1,        8),
 614         CPG_SD_DIV_TABLE_DATA(1,        0,        2,          1,       16),
 615         CPG_SD_DIV_TABLE_DATA(1,        0,        3,          1,       32),
 616         CPG_SD_DIV_TABLE_DATA(1,        0,        4,          1,       64),
 617         CPG_SD_DIV_TABLE_DATA(0,        0,        0,          0,        2),
 618         CPG_SD_DIV_TABLE_DATA(0,        0,        1,          0,        4),
 619         CPG_SD_DIV_TABLE_DATA(1,        0,        2,          0,        8),
 620         CPG_SD_DIV_TABLE_DATA(1,        0,        3,          0,       16),
 621         CPG_SD_DIV_TABLE_DATA(1,        0,        4,          0,       32),
 622 };
 623
 624 static bool gen3_clk_is_mod(struct clk *clk)
 625 {
 626         return (clk->id >> 16) == CPG_MOD;
 627 }
 628
 629 static int gen3_clk_get_mod(struct clk *clk, const struct mssr_mod_clk **mssr)
 630 {
 631         struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
 632         const unsigned long clkid = clk->id & 0xffff;
 633         int i;
 634
 635         if (!gen3_clk_is_mod(clk))
 636                 return -EINVAL;
 637
 638         for (i = 0; i < priv->mod_clk_size; i++) {
 639                 if (priv->mod_clk[i].id != MOD_CLK_ID(clkid))
 640                         continue;
 641
 642                 *mssr = &priv->mod_clk[i];
 643                 return 0;
 644         }
 645
 646         return -ENODEV;
 647 }
 648
 649 static int gen3_clk_get_core(struct clk *clk, const struct cpg_core_clk **core)
 650 {
 651         const unsigned long clkid = clk->id & 0xffff;
 652         int i;
 653
 654         if (gen3_clk_is_mod(clk))
 655                 return -EINVAL;
 656
 657         for (i = 0; i < ARRAY_SIZE(gen3_core_clks); i++) {
 658                 if (gen3_core_clks[i].id != clkid)
 659                         continue;
 660
 661                 *core = &gen3_core_clks[i];
 662                 return 0;
 663         }
 664
 665         return -ENODEV;
 666 }
 667
 668 static int gen3_clk_get_parent(struct clk *clk, struct clk *parent)
 669 {
 670         const struct cpg_core_clk *core;
 671         const struct mssr_mod_clk *mssr;
 672         int ret;
 673
 674         if (gen3_clk_is_mod(clk)) {
 675                 ret = gen3_clk_get_mod(clk, &mssr);
 676                 if (ret)
 677                         return ret;
 678
 679                 parent->id = mssr->parent;
 680         } else {
 681                 ret = gen3_clk_get_core(clk, &core);
 682                 if (ret)
 683                         return ret;
 684
 685                 if (core->type == CLK_TYPE_IN)
 686                         parent->id = ~0;        /* Top-level clock */
 687                 else
 688                         parent->id = core->parent;
 689         }
 690
 691         parent->dev = clk->dev;
 692
 693         return 0;
 694 }
 695
 696 static int gen3_clk_endisable(struct clk *clk, bool enable)
 697 {
 698         struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
 699         const unsigned long clkid = clk->id & 0xffff;
 700         const unsigned int reg = clkid / 100;
 701         const unsigned int bit = clkid % 100;
 702         const u32 bitmask = BIT(bit);
 703
 704         if (!gen3_clk_is_mod(clk))
 705                 return -EINVAL;
 706
 707         debug("%s[%i] MSTP %lu=%02u/%02u %s\n", __func__, __LINE__,
 708               clkid, reg, bit, enable ? "ON" : "OFF");
 709
 710         if (enable) {
 711                 clrbits_le32(priv->base + SMSTPCR(reg), bitmask);
 712                 return wait_for_bit("MSTP", priv->base + MSTPSR(reg),
 713                                     bitmask, 0, 100, 0);
 714         } else {
 715                 setbits_le32(priv->base + SMSTPCR(reg), bitmask);
 716                 return 0;
 717         }
 718 }
 719
 720 static int gen3_clk_enable(struct clk *clk)
 721 {
 722         return gen3_clk_endisable(clk, true);
 723 }
 724
 725 static int gen3_clk_disable(struct clk *clk)
 726 {
 727         return gen3_clk_endisable(clk, false);
 728 }
 729
 730 static ulong gen3_clk_get_rate(struct clk *clk)
 731 {
 732         struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
 733         struct clk parent;
 734         const struct cpg_core_clk *core;
 735         const struct rcar_gen3_cpg_pll_config *pll_config =
 736                                         priv->cpg_pll_config;
 737         u32 value, mult, rate = 0;
 738         int i, ret;
 739
 740         debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
 741
 742         ret = gen3_clk_get_parent(clk, &parent);
 743         if (ret) {
 744                 printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
 745                 return ret;
 746         }
 747
 748         if (gen3_clk_is_mod(clk)) {
 749                 rate = gen3_clk_get_rate(&parent);
 750                 debug("%s[%i] MOD clk: parent=%lu => rate=%u\n",
 751                       __func__, __LINE__, parent.id, rate);
 752                 return rate;
 753         }
 754
 755         ret = gen3_clk_get_core(clk, &core);
 756         if (ret)
 757                 return ret;
 758
 759         switch (core->type) {
 760         case CLK_TYPE_IN:
 761                 if (core->id == CLK_EXTAL) {
 762                         rate = clk_get_rate(&priv->clk_extal);
 763                         debug("%s[%i] EXTAL clk: rate=%u\n",
 764                               __func__, __LINE__, rate);
 765                         return rate;
 766                 }
 767
 768                 if (core->id == CLK_EXTALR) {
 769                         rate = clk_get_rate(&priv->clk_extalr);
 770                         debug("%s[%i] EXTALR clk: rate=%u\n",
 771                               __func__, __LINE__, rate);
 772                         return rate;
 773                 }
 774
 775                 return -EINVAL;
 776
 777         case CLK_TYPE_GEN3_MAIN:
 778                 rate = gen3_clk_get_rate(&parent) / pll_config->extal_div;
 779                 debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%u\n",
 780                       __func__, __LINE__,
 781                       core->parent, pll_config->extal_div, rate);
 782                 return rate;
 783
 784         case CLK_TYPE_GEN3_PLL0:
 785                 value = readl(priv->base + CPG_PLL0CR);
 786                 mult = (((value >> 24) & 0x7f) + 1) * 2;
 787                 rate = gen3_clk_get_rate(&parent) * mult;
 788                 debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%u\n",
 789                       __func__, __LINE__, core->parent, mult, rate);
 790                 return rate;
 791
 792         case CLK_TYPE_GEN3_PLL1:
 793                 rate = gen3_clk_get_rate(&parent) * pll_config->pll1_mult;
 794                 debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%u\n",
 795                       __func__, __LINE__,
 796                       core->parent, pll_config->pll1_mult, rate);
 797                 return rate;
 798
 799         case CLK_TYPE_GEN3_PLL2:
 800                 value = readl(priv->base + CPG_PLL2CR);
 801                 mult = (((value >> 24) & 0x7f) + 1) * 2;
 802                 rate = gen3_clk_get_rate(&parent) * mult;
 803                 debug("%s[%i] PLL2 clk: parent=%i mult=%u => rate=%u\n",
 804                       __func__, __LINE__, core->parent, mult, rate);
 805                 return rate;
 806
 807         case CLK_TYPE_GEN3_PLL3:
 808                 rate = gen3_clk_get_rate(&parent) * pll_config->pll3_mult;
 809                 debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%u\n",
 810                       __func__, __LINE__,
 811                       core->parent, pll_config->pll3_mult, rate);
 812                 return rate;
 813
 814         case CLK_TYPE_GEN3_PLL4:
 815                 value = readl(priv->base + CPG_PLL4CR);
 816                 mult = (((value >> 24) & 0x7f) + 1) * 2;
 817                 rate = gen3_clk_get_rate(&parent) * mult;
 818                 debug("%s[%i] PLL4 clk: parent=%i mult=%u => rate=%u\n",
 819                       __func__, __LINE__, core->parent, mult, rate);
 820                 return rate;
 821
 822         case CLK_TYPE_FF:
 823                 rate = (gen3_clk_get_rate(&parent) * core->mult) / core->div;
 824                 debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n",
 825                       __func__, __LINE__,
 826                       core->parent, core->mult, core->div, rate);
 827                 return rate;
 828
 829         case CLK_TYPE_GEN3_SD:          /* FIXME */
 830                 value = readl(priv->base + core->offset);
 831                 value &= CPG_SD_STP_MASK | CPG_SD_FC_MASK;
 832
 833                 for (i = 0; i < ARRAY_SIZE(cpg_sd_div_table); i++) {
 834                         if (cpg_sd_div_table[i].val != value)
 835                                 continue;
 836
 837                         rate = gen3_clk_get_rate(&parent) /
 838                                cpg_sd_div_table[i].div;
 839                         debug("%s[%i] SD clk: parent=%i div=%i => rate=%u\n",
 840                               __func__, __LINE__,
 841                               core->parent, cpg_sd_div_table[i].div, rate);
 842
 843                         return rate;
 844                 }
 845
 846                 return -EINVAL;
 847         }
 848
 849         printf("%s[%i] unknown fail\n", __func__, __LINE__);
 850
 851         return -ENOENT;
 852 }
 853
 854 static ulong gen3_clk_set_rate(struct clk *clk, ulong rate)
 855 {
 856         return gen3_clk_get_rate(clk);
 857 }
 858
 859 static int gen3_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
 860 {
 861         if (args->args_count != 2) {
 862                 debug("Invaild args_count: %d\n", args->args_count);
 863                 return -EINVAL;
 864         }
 865
 866         clk->id = (args->args[0] << 16) | args->args[1];
 867
 868         return 0;
 869 }
 870
 871 static const struct clk_ops gen3_clk_ops = {
 872         .enable         = gen3_clk_enable,
 873         .disable        = gen3_clk_disable,
 874         .get_rate       = gen3_clk_get_rate,
 875         .set_rate       = gen3_clk_set_rate,
 876         .of_xlate       = gen3_clk_of_xlate,
 877 };
 878
 879 enum gen3_clk_model {
 880         CLK_R8A7795,
 881         CLK_R8A7796,
 882 };
 883
 884 static int gen3_clk_probe(struct udevice *dev)
 885 {
 886         struct gen3_clk_priv *priv = dev_get_priv(dev);
 887         enum gen3_clk_model model = dev_get_driver_data(dev);
 888         fdt_addr_t rst_base;
 889         u32 cpg_mode;
 890         int ret;
 891
 892         priv->base = (struct gen3_base *)devfdt_get_addr(dev);
 893         if (!priv->base)
 894                 return -EINVAL;
 895
 896         switch (model) {
 897         case CLK_R8A7795:
 898                 priv->mod_clk = r8a7795_mod_clks;
 899                 priv->mod_clk_size = ARRAY_SIZE(r8a7795_mod_clks);
 900                 ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
 901                                                     "renesas,r8a7795-rst");
 902                 if (ret < 0)
 903                         return ret;
 904                 break;
 905         case CLK_R8A7796:
 906                 priv->mod_clk = r8a7796_mod_clks;
 907                 priv->mod_clk_size = ARRAY_SIZE(r8a7796_mod_clks);
 908                 ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
 909                                                     "renesas,r8a7796-rst");
 910                 if (ret < 0)
 911                         return ret;
 912                 break;
 913         default:
 914                 return -EINVAL;
 915         }
 916
 917         rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg");
 918         if (rst_base == FDT_ADDR_T_NONE)
 919                 return -EINVAL;
 920
 921         cpg_mode = readl(rst_base + CPG_RST_MODEMR);
 922
 923         priv->cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
 924         if (!priv->cpg_pll_config->extal_div)
 925                 return -EINVAL;
 926
 927         ret = clk_get_by_name(dev, "extal", &priv->clk_extal);
 928         if (ret < 0)
 929                 return ret;
 930
 931         ret = clk_get_by_name(dev, "extalr", &priv->clk_extalr);
 932         if (ret < 0)
 933                 return ret;
 934
 935         return 0;
 936 }
 937
 938 static const struct udevice_id gen3_clk_ids[] = {
 939         { .compatible = "renesas,r8a7795-cpg-mssr", .data = CLK_R8A7795 },
 940         { .compatible = "renesas,r8a7796-cpg-mssr", .data = CLK_R8A7796 },
 941         { }
 942 };
 943
 944 U_BOOT_DRIVER(clk_gen3) = {
 945         .name           = "clk_gen3",
 946         .id             = UCLASS_CLK,
 947         .of_match       = gen3_clk_ids,
 948         .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
 949         .ops            = &gen3_clk_ops,
 950         .probe          = gen3_clk_probe,
 951 };