drivers/clk/renesas/clk-rcar-gen3.c

   1 /*
   2  * Renesas RCar Gen3 CPG MSSR driver
   3  *
   4  * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
   5  *
   6  * Based on the following driver from Linux kernel:
   7  * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
   8  *
   9  * Copyright (C) 2016 Glider bvba
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 #include <common.h>
  15 #include <clk-uclass.h>
  16 #include <dm.h>
  17 #include <errno.h>
  18 #include <wait_bit.h>
  19 #include <asm/io.h>
  20
  21 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
  22 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
  23 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
  24
  25 #define CPG_RST_MODEMR          0x0060
  26
  27 #define CPG_PLL0CR              0x00d8
  28 #define CPG_PLL2CR              0x002c
  29 #define CPG_PLL4CR              0x01f4
  30
  31 #define CPG_RPC_PREDIV_MASK     0x3
  32 #define CPG_RPC_PREDIV_OFFSET   3
  33 #define CPG_RPC_POSTDIV_MASK    0x7
  34 #define CPG_RPC_POSTDIV_OFFSET  0
  35
  36 /*
  37  * Module Standby and Software Reset register offets.
  38  *
  39  * If the registers exist, these are valid for SH-Mobile, R-Mobile,
  40  * R-Car Gen2, R-Car Gen3, and RZ/G1.
  41  * These are NOT valid for R-Car Gen1 and RZ/A1!
  42  */
  43
  44 /*
  45  * Module Stop Status Register offsets
  46  */
  47
  48 static const u16 mstpsr[] = {
  49         0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
  50         0x9A0, 0x9A4, 0x9A8, 0x9AC,
  51 };
  52
  53 #define MSTPSR(i)       mstpsr[i]
  54
  55
  56 /*
  57  * System Module Stop Control Register offsets
  58  */
  59
  60 static const u16 smstpcr[] = {
  61         0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
  62         0x990, 0x994, 0x998, 0x99C,
  63 };
  64
  65 #define SMSTPCR(i)      smstpcr[i]
  66
  67
  68 /* Realtime Module Stop Control Register offsets */
  69 #define RMSTPCR(i)      (smstpcr[i] - 0x20)
  70
  71 /* Modem Module Stop Control Register offsets (r8a73a4) */
  72 #define MMSTPCR(i)      (smstpcr[i] + 0x20)
  73
  74 /* Software Reset Clearing Register offsets */
  75 #define SRSTCLR(i)      (0x940 + (i) * 4)
  76
  77 struct gen3_clk_priv {
  78         void __iomem    *base;
  79         struct clk      clk_extal;
  80         struct clk      clk_extalr;
  81         const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
  82         const struct cpg_core_clk *core_clk;
  83         u32             core_clk_size;
  84         const struct mssr_mod_clk *mod_clk;
  85         u32             mod_clk_size;
  86 };
  87
  88 /*
  89  * Definitions of CPG Core Clocks
  90  *
  91  * These include:
  92  *   - Clock outputs exported to DT
  93  *   - External input clocks
  94  *   - Internal CPG clocks
  95  */
  96 struct cpg_core_clk {
  97         /* Common */
  98         const char *name;
  99         unsigned int id;
 100         unsigned int type;
 101         /* Depending on type */
 102         unsigned int parent;    /* Core Clocks only */
 103         unsigned int div;
 104         unsigned int mult;
 105         unsigned int offset;
 106 };
 107
 108 enum clk_types {
 109         /* Generic */
 110         CLK_TYPE_IN,            /* External Clock Input */
 111         CLK_TYPE_FF,            /* Fixed Factor Clock */
 112
 113         /* Custom definitions start here */
 114         CLK_TYPE_CUSTOM,
 115 };
 116
 117 #define DEF_TYPE(_name, _id, _type...)  \
 118         { .name = _name, .id = _id, .type = _type }
 119 #define DEF_BASE(_name, _id, _type, _parent...) \
 120         DEF_TYPE(_name, _id, _type, .parent = _parent)
 121
 122 #define DEF_INPUT(_name, _id) \
 123         DEF_TYPE(_name, _id, CLK_TYPE_IN)
 124 #define DEF_FIXED(_name, _id, _parent, _div, _mult)     \
 125         DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
 126 #define DEF_GEN3_SD(_name, _id, _parent, _offset)       \
 127         DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
 128 #define DEF_GEN3_RPC(_name, _id, _parent, _offset)      \
 129         DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset)
 130
 131 /*
 132  * Definitions of Module Clocks
 133  */
 134 struct mssr_mod_clk {
 135         const char *name;
 136         unsigned int id;
 137         unsigned int parent;    /* Add MOD_CLK_BASE for Module Clocks */
 138 };
 139
 140 /* Convert from sparse base-100 to packed index space */
 141 #define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
 142
 143 #define MOD_CLK_ID(x)   (MOD_CLK_BASE + MOD_CLK_PACK(x))
 144
 145 #define DEF_MOD(_name, _mod, _parent...)        \
 146         { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
 147
 148 enum rcar_gen3_clk_types {
 149         CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
 150         CLK_TYPE_GEN3_PLL0,
 151         CLK_TYPE_GEN3_PLL1,
 152         CLK_TYPE_GEN3_PLL2,
 153         CLK_TYPE_GEN3_PLL3,
 154         CLK_TYPE_GEN3_PLL4,
 155         CLK_TYPE_GEN3_SD,
 156         CLK_TYPE_GEN3_RPC,
 157         CLK_TYPE_GEN3_R,
 158         CLK_TYPE_GEN3_Z2,
 159 };
 160
 161 struct rcar_gen3_cpg_pll_config {
 162         unsigned int extal_div;
 163         unsigned int pll1_mult;
 164         unsigned int pll3_mult;
 165 };
 166
 167 enum clk_ids {
 168         /* Core Clock Outputs exported to DT */
 169         LAST_DT_CORE_CLK = R8A7796_CLK_OSC,
 170
 171         /* External Input Clocks */
 172         CLK_EXTAL,
 173         CLK_EXTALR,
 174
 175         /* Internal Core Clocks */
 176         CLK_MAIN,
 177         CLK_PLL0,
 178         CLK_PLL1,
 179         CLK_PLL2,
 180         CLK_PLL3,
 181         CLK_PLL4,
 182         CLK_PLL1_DIV2,
 183         CLK_PLL1_DIV4,
 184         CLK_S0,
 185         CLK_S1,
 186         CLK_S2,
 187         CLK_S3,
 188         CLK_SDSRC,
 189         CLK_RPCSRC,
 190         CLK_SSPSRC,
 191         CLK_RINT,
 192
 193         /* Module Clocks */
 194         MOD_CLK_BASE
 195 };
 196
 197 static const struct cpg_core_clk r8a7795_core_clks[] = {
 198         /* External Clock Inputs */
 199         DEF_INPUT("extal",      CLK_EXTAL),
 200         DEF_INPUT("extalr",     CLK_EXTALR),
 201
 202         /* Internal Core Clocks */
 203         DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
 204         DEF_BASE(".pll0",       CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
 205         DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
 206         DEF_BASE(".pll2",       CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
 207         DEF_BASE(".pll3",       CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
 208         DEF_BASE(".pll4",       CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
 209
 210         DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,     CLK_PLL1,       2, 1),
 211         DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4,     CLK_PLL1_DIV2,  2, 1),
 212         DEF_FIXED(".s0",        CLK_S0,            CLK_PLL1_DIV2,  2, 1),
 213         DEF_FIXED(".s1",        CLK_S1,            CLK_PLL1_DIV2,  3, 1),
 214         DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,  4, 1),
 215         DEF_FIXED(".s3",        CLK_S3,            CLK_PLL1_DIV2,  6, 1),
 216         DEF_FIXED(".sdsrc",     CLK_SDSRC,         CLK_PLL1_DIV2,  2, 1),
 217         DEF_FIXED(".rpcsrc",    CLK_RPCSRC,        CLK_PLL1,       2, 1),
 218
 219         /* Core Clock Outputs */
 220         DEF_FIXED("ztr",        R8A7795_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
 221         DEF_FIXED("ztrd2",      R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
 222         DEF_FIXED("zt",         R8A7795_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
 223         DEF_FIXED("zx",         R8A7795_CLK_ZX,    CLK_PLL1_DIV2,  2, 1),
 224         DEF_FIXED("s0d1",       R8A7795_CLK_S0D1,  CLK_S0,         1, 1),
 225         DEF_FIXED("s0d2",       R8A7795_CLK_S0D2,  CLK_S0,         2, 1),
 226         DEF_FIXED("s0d3",       R8A7795_CLK_S0D3,  CLK_S0,         3, 1),
 227         DEF_FIXED("s0d4",       R8A7795_CLK_S0D4,  CLK_S0,         4, 1),
 228         DEF_FIXED("s0d6",       R8A7795_CLK_S0D6,  CLK_S0,         6, 1),
 229         DEF_FIXED("s0d8",       R8A7795_CLK_S0D8,  CLK_S0,         8, 1),
 230         DEF_FIXED("s0d12",      R8A7795_CLK_S0D12, CLK_S0,        12, 1),
 231         DEF_FIXED("s1d1",       R8A7795_CLK_S1D1,  CLK_S1,         1, 1),
 232         DEF_FIXED("s1d2",       R8A7795_CLK_S1D2,  CLK_S1,         2, 1),
 233         DEF_FIXED("s1d4",       R8A7795_CLK_S1D4,  CLK_S1,         4, 1),
 234         DEF_FIXED("s2d1",       R8A7795_CLK_S2D1,  CLK_S2,         1, 1),
 235         DEF_FIXED("s2d2",       R8A7795_CLK_S2D2,  CLK_S2,         2, 1),
 236         DEF_FIXED("s2d4",       R8A7795_CLK_S2D4,  CLK_S2,         4, 1),
 237         DEF_FIXED("s3d1",       R8A7795_CLK_S3D1,  CLK_S3,         1, 1),
 238         DEF_FIXED("s3d2",       R8A7795_CLK_S3D2,  CLK_S3,         2, 1),
 239         DEF_FIXED("s3d4",       R8A7795_CLK_S3D4,  CLK_S3,         4, 1),
 240
 241         DEF_GEN3_SD("sd0",      R8A7795_CLK_SD0,   CLK_SDSRC,     0x074),
 242         DEF_GEN3_SD("sd1",      R8A7795_CLK_SD1,   CLK_SDSRC,     0x078),
 243         DEF_GEN3_SD("sd2",      R8A7795_CLK_SD2,   CLK_SDSRC,     0x268),
 244         DEF_GEN3_SD("sd3",      R8A7795_CLK_SD3,   CLK_SDSRC,     0x26c),
 245
 246         DEF_GEN3_RPC("rpc",     R8A7795_CLK_RPC,   CLK_RPCSRC,    0x238),
 247
 248         DEF_FIXED("cl",         R8A7795_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
 249         DEF_FIXED("cp",         R8A7795_CLK_CP,    CLK_EXTAL,      2, 1),
 250
 251         /* NOTE: HDMI, CSI, CAN etc. clock are missing */
 252
 253         DEF_BASE("r",           R8A7795_CLK_R,     CLK_TYPE_GEN3_R, CLK_RINT),
 254 };
 255
 256 static const struct mssr_mod_clk r8a7795_mod_clks[] = {
 257         DEF_MOD("fdp1-2",                117,   R8A7795_CLK_S2D1), /* ES1.x */
 258         DEF_MOD("fdp1-1",                118,   R8A7795_CLK_S0D1),
 259         DEF_MOD("fdp1-0",                119,   R8A7795_CLK_S0D1),
 260         DEF_MOD("scif5",                 202,   R8A7795_CLK_S3D4),
 261         DEF_MOD("scif4",                 203,   R8A7795_CLK_S3D4),
 262         DEF_MOD("scif3",                 204,   R8A7795_CLK_S3D4),
 263         DEF_MOD("scif1",                 206,   R8A7795_CLK_S3D4),
 264         DEF_MOD("scif0",                 207,   R8A7795_CLK_S3D4),
 265         DEF_MOD("msiof3",                208,   R8A7795_CLK_MSO),
 266         DEF_MOD("msiof2",                209,   R8A7795_CLK_MSO),
 267         DEF_MOD("msiof1",                210,   R8A7795_CLK_MSO),
 268         DEF_MOD("msiof0",                211,   R8A7795_CLK_MSO),
 269         DEF_MOD("sys-dmac2",             217,   R8A7795_CLK_S0D3),
 270         DEF_MOD("sys-dmac1",             218,   R8A7795_CLK_S0D3),
 271         DEF_MOD("sys-dmac0",             219,   R8A7795_CLK_S0D3),
 272         DEF_MOD("cmt3",                  300,   R8A7795_CLK_R),
 273         DEF_MOD("cmt2",                  301,   R8A7795_CLK_R),
 274         DEF_MOD("cmt1",                  302,   R8A7795_CLK_R),
 275         DEF_MOD("cmt0",                  303,   R8A7795_CLK_R),
 276         DEF_MOD("scif2",                 310,   R8A7795_CLK_S3D4),
 277         DEF_MOD("sdif3",                 311,   R8A7795_CLK_SD3),
 278         DEF_MOD("sdif2",                 312,   R8A7795_CLK_SD2),
 279         DEF_MOD("sdif1",                 313,   R8A7795_CLK_SD1),
 280         DEF_MOD("sdif0",                 314,   R8A7795_CLK_SD0),
 281         DEF_MOD("pcie1",                 318,   R8A7795_CLK_S3D1),
 282         DEF_MOD("pcie0",                 319,   R8A7795_CLK_S3D1),
 283         DEF_MOD("usb-dmac30",            326,   R8A7795_CLK_S3D1),
 284         DEF_MOD("usb3-if1",              327,   R8A7795_CLK_S3D1), /* ES1.x */
 285         DEF_MOD("usb3-if0",              328,   R8A7795_CLK_S3D1),
 286         DEF_MOD("usb-dmac31",            329,   R8A7795_CLK_S3D1),
 287         DEF_MOD("usb-dmac0",             330,   R8A7795_CLK_S3D1),
 288         DEF_MOD("usb-dmac1",             331,   R8A7795_CLK_S3D1),
 289         DEF_MOD("rwdt",                  402,   R8A7795_CLK_R),
 290         DEF_MOD("intc-ex",               407,   R8A7795_CLK_CP),
 291         DEF_MOD("intc-ap",               408,   R8A7795_CLK_S3D1),
 292         DEF_MOD("audmac1",               501,   R8A7795_CLK_S0D3),
 293         DEF_MOD("audmac0",               502,   R8A7795_CLK_S0D3),
 294         DEF_MOD("drif7",                 508,   R8A7795_CLK_S3D2),
 295         DEF_MOD("drif6",                 509,   R8A7795_CLK_S3D2),
 296         DEF_MOD("drif5",                 510,   R8A7795_CLK_S3D2),
 297         DEF_MOD("drif4",                 511,   R8A7795_CLK_S3D2),
 298         DEF_MOD("drif3",                 512,   R8A7795_CLK_S3D2),
 299         DEF_MOD("drif2",                 513,   R8A7795_CLK_S3D2),
 300         DEF_MOD("drif1",                 514,   R8A7795_CLK_S3D2),
 301         DEF_MOD("drif0",                 515,   R8A7795_CLK_S3D2),
 302         DEF_MOD("hscif4",                516,   R8A7795_CLK_S3D1),
 303         DEF_MOD("hscif3",                517,   R8A7795_CLK_S3D1),
 304         DEF_MOD("hscif2",                518,   R8A7795_CLK_S3D1),
 305         DEF_MOD("hscif1",                519,   R8A7795_CLK_S3D1),
 306         DEF_MOD("hscif0",                520,   R8A7795_CLK_S3D1),
 307         DEF_MOD("thermal",               522,   R8A7795_CLK_CP),
 308         DEF_MOD("pwm",                   523,   R8A7795_CLK_S0D12),
 309         DEF_MOD("fcpvd3",                600,   R8A7795_CLK_S2D1), /* ES1.x */
 310         DEF_MOD("fcpvd2",                601,   R8A7795_CLK_S0D2),
 311         DEF_MOD("fcpvd1",                602,   R8A7795_CLK_S0D2),
 312         DEF_MOD("fcpvd0",                603,   R8A7795_CLK_S0D2),
 313         DEF_MOD("fcpvb1",                606,   R8A7795_CLK_S0D1),
 314         DEF_MOD("fcpvb0",                607,   R8A7795_CLK_S0D1),
 315         DEF_MOD("fcpvi2",                609,   R8A7795_CLK_S2D1), /* ES1.x */
 316         DEF_MOD("fcpvi1",                610,   R8A7795_CLK_S0D1),
 317         DEF_MOD("fcpvi0",                611,   R8A7795_CLK_S0D1),
 318         DEF_MOD("fcpf2",                 613,   R8A7795_CLK_S2D1), /* ES1.x */
 319         DEF_MOD("fcpf1",                 614,   R8A7795_CLK_S0D1),
 320         DEF_MOD("fcpf0",                 615,   R8A7795_CLK_S0D1),
 321         DEF_MOD("fcpci1",                616,   R8A7795_CLK_S2D1), /* ES1.x */
 322         DEF_MOD("fcpci0",                617,   R8A7795_CLK_S2D1), /* ES1.x */
 323         DEF_MOD("fcpcs",                 619,   R8A7795_CLK_S0D1),
 324         DEF_MOD("vspd3",                 620,   R8A7795_CLK_S2D1), /* ES1.x */
 325         DEF_MOD("vspd2",                 621,   R8A7795_CLK_S0D2),
 326         DEF_MOD("vspd1",                 622,   R8A7795_CLK_S0D2),
 327         DEF_MOD("vspd0",                 623,   R8A7795_CLK_S0D2),
 328         DEF_MOD("vspbc",                 624,   R8A7795_CLK_S0D1),
 329         DEF_MOD("vspbd",                 626,   R8A7795_CLK_S0D1),
 330         DEF_MOD("vspi2",                 629,   R8A7795_CLK_S2D1), /* ES1.x */
 331         DEF_MOD("vspi1",                 630,   R8A7795_CLK_S0D1),
 332         DEF_MOD("vspi0",                 631,   R8A7795_CLK_S0D1),
 333         DEF_MOD("ehci3",                 700,   R8A7795_CLK_S3D4),
 334         DEF_MOD("ehci2",                 701,   R8A7795_CLK_S3D4),
 335         DEF_MOD("ehci1",                 702,   R8A7795_CLK_S3D4),
 336         DEF_MOD("ehci0",                 703,   R8A7795_CLK_S3D4),
 337         DEF_MOD("hsusb",                 704,   R8A7795_CLK_S3D4),
 338         DEF_MOD("hsusb3",                705,   R8A7795_CLK_S3D4),
 339         DEF_MOD("csi21",                 713,   R8A7795_CLK_CSI0), /* ES1.x */
 340         DEF_MOD("csi20",                 714,   R8A7795_CLK_CSI0),
 341         DEF_MOD("csi41",                 715,   R8A7795_CLK_CSI0),
 342         DEF_MOD("csi40",                 716,   R8A7795_CLK_CSI0),
 343         DEF_MOD("du3",                   721,   R8A7795_CLK_S2D1),
 344         DEF_MOD("du2",                   722,   R8A7795_CLK_S2D1),
 345         DEF_MOD("du1",                   723,   R8A7795_CLK_S2D1),
 346         DEF_MOD("du0",                   724,   R8A7795_CLK_S2D1),
 347         DEF_MOD("lvds",                  727,   R8A7795_CLK_S0D4),
 348         DEF_MOD("hdmi1",                 728,   R8A7795_CLK_HDMI),
 349         DEF_MOD("hdmi0",                 729,   R8A7795_CLK_HDMI),
 350         DEF_MOD("vin7",                  804,   R8A7795_CLK_S0D2),
 351         DEF_MOD("vin6",                  805,   R8A7795_CLK_S0D2),
 352         DEF_MOD("vin5",                  806,   R8A7795_CLK_S0D2),
 353         DEF_MOD("vin4",                  807,   R8A7795_CLK_S0D2),
 354         DEF_MOD("vin3",                  808,   R8A7795_CLK_S0D2),
 355         DEF_MOD("vin2",                  809,   R8A7795_CLK_S0D2),
 356         DEF_MOD("vin1",                  810,   R8A7795_CLK_S0D2),
 357         DEF_MOD("vin0",                  811,   R8A7795_CLK_S0D2),
 358         DEF_MOD("etheravb",              812,   R8A7795_CLK_S0D6),
 359         DEF_MOD("sata0",                 815,   R8A7795_CLK_S3D2),
 360         DEF_MOD("imr3",                  820,   R8A7795_CLK_S0D2),
 361         DEF_MOD("imr2",                  821,   R8A7795_CLK_S0D2),
 362         DEF_MOD("imr1",                  822,   R8A7795_CLK_S0D2),
 363         DEF_MOD("imr0",                  823,   R8A7795_CLK_S0D2),
 364         DEF_MOD("gpio7",                 905,   R8A7795_CLK_S3D4),
 365         DEF_MOD("gpio6",                 906,   R8A7795_CLK_S3D4),
 366         DEF_MOD("gpio5",                 907,   R8A7795_CLK_S3D4),
 367         DEF_MOD("gpio4",                 908,   R8A7795_CLK_S3D4),
 368         DEF_MOD("gpio3",                 909,   R8A7795_CLK_S3D4),
 369         DEF_MOD("gpio2",                 910,   R8A7795_CLK_S3D4),
 370         DEF_MOD("gpio1",                 911,   R8A7795_CLK_S3D4),
 371         DEF_MOD("gpio0",                 912,   R8A7795_CLK_S3D4),
 372         DEF_MOD("can-fd",                914,   R8A7795_CLK_S3D2),
 373         DEF_MOD("can-if1",               915,   R8A7795_CLK_S3D4),
 374         DEF_MOD("can-if0",               916,   R8A7795_CLK_S3D4),
 375         DEF_MOD("rpc",                   917,   R8A7795_CLK_RPC),
 376         DEF_MOD("i2c6",                  918,   R8A7795_CLK_S0D6),
 377         DEF_MOD("i2c5",                  919,   R8A7795_CLK_S0D6),
 378         DEF_MOD("i2c-dvfs",              926,   R8A7795_CLK_CP),
 379         DEF_MOD("i2c4",                  927,   R8A7795_CLK_S0D6),
 380         DEF_MOD("i2c3",                  928,   R8A7795_CLK_S0D6),
 381         DEF_MOD("i2c2",                  929,   R8A7795_CLK_S3D2),
 382         DEF_MOD("i2c1",                  930,   R8A7795_CLK_S3D2),
 383         DEF_MOD("i2c0",                  931,   R8A7795_CLK_S3D2),
 384         DEF_MOD("ssi-all",              1005,   R8A7795_CLK_S3D4),
 385         DEF_MOD("ssi9",                 1006,   MOD_CLK_ID(1005)),
 386         DEF_MOD("ssi8",                 1007,   MOD_CLK_ID(1005)),
 387         DEF_MOD("ssi7",                 1008,   MOD_CLK_ID(1005)),
 388         DEF_MOD("ssi6",                 1009,   MOD_CLK_ID(1005)),
 389         DEF_MOD("ssi5",                 1010,   MOD_CLK_ID(1005)),
 390         DEF_MOD("ssi4",                 1011,   MOD_CLK_ID(1005)),
 391         DEF_MOD("ssi3",                 1012,   MOD_CLK_ID(1005)),
 392         DEF_MOD("ssi2",                 1013,   MOD_CLK_ID(1005)),
 393         DEF_MOD("ssi1",                 1014,   MOD_CLK_ID(1005)),
 394         DEF_MOD("ssi0",                 1015,   MOD_CLK_ID(1005)),
 395         DEF_MOD("scu-all",              1017,   R8A7795_CLK_S3D4),
 396         DEF_MOD("scu-dvc1",             1018,   MOD_CLK_ID(1017)),
 397         DEF_MOD("scu-dvc0",             1019,   MOD_CLK_ID(1017)),
 398         DEF_MOD("scu-ctu1-mix1",        1020,   MOD_CLK_ID(1017)),
 399         DEF_MOD("scu-ctu0-mix0",        1021,   MOD_CLK_ID(1017)),
 400         DEF_MOD("scu-src9",             1022,   MOD_CLK_ID(1017)),
 401         DEF_MOD("scu-src8",             1023,   MOD_CLK_ID(1017)),
 402         DEF_MOD("scu-src7",             1024,   MOD_CLK_ID(1017)),
 403         DEF_MOD("scu-src6",             1025,   MOD_CLK_ID(1017)),
 404         DEF_MOD("scu-src5",             1026,   MOD_CLK_ID(1017)),
 405         DEF_MOD("scu-src4",             1027,   MOD_CLK_ID(1017)),
 406         DEF_MOD("scu-src3",             1028,   MOD_CLK_ID(1017)),
 407         DEF_MOD("scu-src2",             1029,   MOD_CLK_ID(1017)),
 408         DEF_MOD("scu-src1",             1030,   MOD_CLK_ID(1017)),
 409         DEF_MOD("scu-src0",             1031,   MOD_CLK_ID(1017)),
 410 };
 411
 412 static const struct cpg_core_clk r8a7796_core_clks[] = {
 413         /* External Clock Inputs */
 414         DEF_INPUT("extal",      CLK_EXTAL),
 415         DEF_INPUT("extalr",     CLK_EXTALR),
 416
 417         /* Internal Core Clocks */
 418         DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
 419         DEF_BASE(".pll0",       CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
 420         DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
 421         DEF_BASE(".pll2",       CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
 422         DEF_BASE(".pll3",       CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
 423         DEF_BASE(".pll4",       CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
 424
 425         DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,     CLK_PLL1,       2, 1),
 426         DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4,     CLK_PLL1_DIV2,  2, 1),
 427         DEF_FIXED(".s0",        CLK_S0,            CLK_PLL1_DIV2,  2, 1),
 428         DEF_FIXED(".s1",        CLK_S1,            CLK_PLL1_DIV2,  3, 1),
 429         DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,  4, 1),
 430         DEF_FIXED(".s3",        CLK_S3,            CLK_PLL1_DIV2,  6, 1),
 431         DEF_FIXED(".sdsrc",     CLK_SDSRC,         CLK_PLL1_DIV2,  2, 1),
 432         DEF_FIXED(".rpcsrc",    CLK_RPCSRC,        CLK_PLL1,       2, 1),
 433
 434         /* Core Clock Outputs */
 435         DEF_FIXED("ztr",        R8A7796_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
 436         DEF_FIXED("ztrd2",      R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
 437         DEF_FIXED("zt",         R8A7796_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
 438         DEF_FIXED("zx",         R8A7796_CLK_ZX,    CLK_PLL1_DIV2,  2, 1),
 439         DEF_FIXED("s0d1",       R8A7796_CLK_S0D1,  CLK_S0,         1, 1),
 440         DEF_FIXED("s0d2",       R8A7796_CLK_S0D2,  CLK_S0,         2, 1),
 441         DEF_FIXED("s0d3",       R8A7796_CLK_S0D3,  CLK_S0,         3, 1),
 442         DEF_FIXED("s0d4",       R8A7796_CLK_S0D4,  CLK_S0,         4, 1),
 443         DEF_FIXED("s0d6",       R8A7796_CLK_S0D6,  CLK_S0,         6, 1),
 444         DEF_FIXED("s0d8",       R8A7796_CLK_S0D8,  CLK_S0,         8, 1),
 445         DEF_FIXED("s0d12",      R8A7796_CLK_S0D12, CLK_S0,        12, 1),
 446         DEF_FIXED("s1d1",       R8A7796_CLK_S1D1,  CLK_S1,         1, 1),
 447         DEF_FIXED("s1d2",       R8A7796_CLK_S1D2,  CLK_S1,         2, 1),
 448         DEF_FIXED("s1d4",       R8A7796_CLK_S1D4,  CLK_S1,         4, 1),
 449         DEF_FIXED("s2d1",       R8A7796_CLK_S2D1,  CLK_S2,         1, 1),
 450         DEF_FIXED("s2d2",       R8A7796_CLK_S2D2,  CLK_S2,         2, 1),
 451         DEF_FIXED("s2d4",       R8A7796_CLK_S2D4,  CLK_S2,         4, 1),
 452         DEF_FIXED("s3d1",       R8A7796_CLK_S3D1,  CLK_S3,         1, 1),
 453         DEF_FIXED("s3d2",       R8A7796_CLK_S3D2,  CLK_S3,         2, 1),
 454         DEF_FIXED("s3d4",       R8A7796_CLK_S3D4,  CLK_S3,         4, 1),
 455
 456         DEF_GEN3_SD("sd0",      R8A7796_CLK_SD0,   CLK_SDSRC,     0x074),
 457         DEF_GEN3_SD("sd1",      R8A7796_CLK_SD1,   CLK_SDSRC,     0x078),
 458         DEF_GEN3_SD("sd2",      R8A7796_CLK_SD2,   CLK_SDSRC,     0x268),
 459         DEF_GEN3_SD("sd3",      R8A7796_CLK_SD3,   CLK_SDSRC,     0x26c),
 460
 461         DEF_GEN3_RPC("rpc",     R8A7796_CLK_RPC,   CLK_RPCSRC,    0x238),
 462
 463         DEF_FIXED("cl",         R8A7796_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
 464         DEF_FIXED("cp",         R8A7796_CLK_CP,    CLK_EXTAL,      2, 1),
 465
 466         /* NOTE: HDMI, CSI, CAN etc. clock are missing */
 467
 468         DEF_BASE("r",           R8A7796_CLK_R,     CLK_TYPE_GEN3_R, CLK_RINT),
 469 };
 470
 471 static const struct mssr_mod_clk r8a7796_mod_clks[] = {
 472         DEF_MOD("scif5",                 202,   R8A7796_CLK_S3D4),
 473         DEF_MOD("scif4",                 203,   R8A7796_CLK_S3D4),
 474         DEF_MOD("scif3",                 204,   R8A7796_CLK_S3D4),
 475         DEF_MOD("scif1",                 206,   R8A7796_CLK_S3D4),
 476         DEF_MOD("scif0",                 207,   R8A7796_CLK_S3D4),
 477         DEF_MOD("msiof3",                208,   R8A7796_CLK_MSO),
 478         DEF_MOD("msiof2",                209,   R8A7796_CLK_MSO),
 479         DEF_MOD("msiof1",                210,   R8A7796_CLK_MSO),
 480         DEF_MOD("msiof0",                211,   R8A7796_CLK_MSO),
 481         DEF_MOD("sys-dmac2",             217,   R8A7796_CLK_S0D3),
 482         DEF_MOD("sys-dmac1",             218,   R8A7796_CLK_S0D3),
 483         DEF_MOD("sys-dmac0",             219,   R8A7796_CLK_S0D3),
 484         DEF_MOD("cmt3",                  300,   R8A7796_CLK_R),
 485         DEF_MOD("cmt2",                  301,   R8A7796_CLK_R),
 486         DEF_MOD("cmt1",                  302,   R8A7796_CLK_R),
 487         DEF_MOD("cmt0",                  303,   R8A7796_CLK_R),
 488         DEF_MOD("scif2",                 310,   R8A7796_CLK_S3D4),
 489         DEF_MOD("sdif3",                 311,   R8A7796_CLK_SD3),
 490         DEF_MOD("sdif2",                 312,   R8A7796_CLK_SD2),
 491         DEF_MOD("sdif1",                 313,   R8A7796_CLK_SD1),
 492         DEF_MOD("sdif0",                 314,   R8A7796_CLK_SD0),
 493         DEF_MOD("pcie1",                 318,   R8A7796_CLK_S3D1),
 494         DEF_MOD("pcie0",                 319,   R8A7796_CLK_S3D1),
 495         DEF_MOD("usb3-if0",              328,   R8A7796_CLK_S3D1),
 496         DEF_MOD("usb-dmac0",             330,   R8A7796_CLK_S3D1),
 497         DEF_MOD("usb-dmac1",             331,   R8A7796_CLK_S3D1),
 498         DEF_MOD("rwdt",                  402,   R8A7796_CLK_R),
 499         DEF_MOD("intc-ex",               407,   R8A7796_CLK_CP),
 500         DEF_MOD("intc-ap",               408,   R8A7796_CLK_S3D1),
 501         DEF_MOD("audmac1",               501,   R8A7796_CLK_S0D3),
 502         DEF_MOD("audmac0",               502,   R8A7796_CLK_S0D3),
 503         DEF_MOD("drif7",                 508,   R8A7796_CLK_S3D2),
 504         DEF_MOD("drif6",                 509,   R8A7796_CLK_S3D2),
 505         DEF_MOD("drif5",                 510,   R8A7796_CLK_S3D2),
 506         DEF_MOD("drif4",                 511,   R8A7796_CLK_S3D2),
 507         DEF_MOD("drif3",                 512,   R8A7796_CLK_S3D2),
 508         DEF_MOD("drif2",                 513,   R8A7796_CLK_S3D2),
 509         DEF_MOD("drif1",                 514,   R8A7796_CLK_S3D2),
 510         DEF_MOD("drif0",                 515,   R8A7796_CLK_S3D2),
 511         DEF_MOD("hscif4",                516,   R8A7796_CLK_S3D1),
 512         DEF_MOD("hscif3",                517,   R8A7796_CLK_S3D1),
 513         DEF_MOD("hscif2",                518,   R8A7796_CLK_S3D1),
 514         DEF_MOD("hscif1",                519,   R8A7796_CLK_S3D1),
 515         DEF_MOD("hscif0",                520,   R8A7796_CLK_S3D1),
 516         DEF_MOD("thermal",               522,   R8A7796_CLK_CP),
 517         DEF_MOD("pwm",                   523,   R8A7796_CLK_S0D12),
 518         DEF_MOD("fcpvd2",                601,   R8A7796_CLK_S0D2),
 519         DEF_MOD("fcpvd1",                602,   R8A7796_CLK_S0D2),
 520         DEF_MOD("fcpvd0",                603,   R8A7796_CLK_S0D2),
 521         DEF_MOD("fcpvb0",                607,   R8A7796_CLK_S0D1),
 522         DEF_MOD("fcpvi0",                611,   R8A7796_CLK_S0D1),
 523         DEF_MOD("fcpf0",                 615,   R8A7796_CLK_S0D1),
 524         DEF_MOD("fcpci0",                617,   R8A7796_CLK_S0D2),
 525         DEF_MOD("fcpcs",                 619,   R8A7796_CLK_S0D2),
 526         DEF_MOD("vspd2",                 621,   R8A7796_CLK_S0D2),
 527         DEF_MOD("vspd1",                 622,   R8A7796_CLK_S0D2),
 528         DEF_MOD("vspd0",                 623,   R8A7796_CLK_S0D2),
 529         DEF_MOD("vspb",                  626,   R8A7796_CLK_S0D1),
 530         DEF_MOD("vspi0",                 631,   R8A7796_CLK_S0D1),
 531         DEF_MOD("ehci1",                 702,   R8A7796_CLK_S3D4),
 532         DEF_MOD("ehci0",                 703,   R8A7796_CLK_S3D4),
 533         DEF_MOD("hsusb",                 704,   R8A7796_CLK_S3D4),
 534         DEF_MOD("csi20",                 714,   R8A7796_CLK_CSI0),
 535         DEF_MOD("csi40",                 716,   R8A7796_CLK_CSI0),
 536         DEF_MOD("du2",                   722,   R8A7796_CLK_S2D1),
 537         DEF_MOD("du1",                   723,   R8A7796_CLK_S2D1),
 538         DEF_MOD("du0",                   724,   R8A7796_CLK_S2D1),
 539         DEF_MOD("lvds",                  727,   R8A7796_CLK_S2D1),
 540         DEF_MOD("hdmi0",                 729,   R8A7796_CLK_HDMI),
 541         DEF_MOD("vin7",                  804,   R8A7796_CLK_S0D2),
 542         DEF_MOD("vin6",                  805,   R8A7796_CLK_S0D2),
 543         DEF_MOD("vin5",                  806,   R8A7796_CLK_S0D2),
 544         DEF_MOD("vin4",                  807,   R8A7796_CLK_S0D2),
 545         DEF_MOD("vin3",                  808,   R8A7796_CLK_S0D2),
 546         DEF_MOD("vin2",                  809,   R8A7796_CLK_S0D2),
 547         DEF_MOD("vin1",                  810,   R8A7796_CLK_S0D2),
 548         DEF_MOD("vin0",                  811,   R8A7796_CLK_S0D2),
 549         DEF_MOD("etheravb",              812,   R8A7796_CLK_S0D6),
 550         DEF_MOD("imr1",                  822,   R8A7796_CLK_S0D2),
 551         DEF_MOD("imr0",                  823,   R8A7796_CLK_S0D2),
 552         DEF_MOD("gpio7",                 905,   R8A7796_CLK_S3D4),
 553         DEF_MOD("gpio6",                 906,   R8A7796_CLK_S3D4),
 554         DEF_MOD("gpio5",                 907,   R8A7796_CLK_S3D4),
 555         DEF_MOD("gpio4",                 908,   R8A7796_CLK_S3D4),
 556         DEF_MOD("gpio3",                 909,   R8A7796_CLK_S3D4),
 557         DEF_MOD("gpio2",                 910,   R8A7796_CLK_S3D4),
 558         DEF_MOD("gpio1",                 911,   R8A7796_CLK_S3D4),
 559         DEF_MOD("gpio0",                 912,   R8A7796_CLK_S3D4),
 560         DEF_MOD("can-fd",                914,   R8A7796_CLK_S3D2),
 561         DEF_MOD("can-if1",               915,   R8A7796_CLK_S3D4),
 562         DEF_MOD("can-if0",               916,   R8A7796_CLK_S3D4),
 563         DEF_MOD("rpc",                   917,   R8A7796_CLK_RPC),
 564         DEF_MOD("i2c6",                  918,   R8A7796_CLK_S0D6),
 565         DEF_MOD("i2c5",                  919,   R8A7796_CLK_S0D6),
 566         DEF_MOD("i2c-dvfs",              926,   R8A7796_CLK_CP),
 567         DEF_MOD("i2c4",                  927,   R8A7796_CLK_S0D6),
 568         DEF_MOD("i2c3",                  928,   R8A7796_CLK_S0D6),
 569         DEF_MOD("i2c2",                  929,   R8A7796_CLK_S3D2),
 570         DEF_MOD("i2c1",                  930,   R8A7796_CLK_S3D2),
 571         DEF_MOD("i2c0",                  931,   R8A7796_CLK_S3D2),
 572         DEF_MOD("ssi-all",              1005,   R8A7796_CLK_S3D4),
 573         DEF_MOD("ssi9",                 1006,   MOD_CLK_ID(1005)),
 574         DEF_MOD("ssi8",                 1007,   MOD_CLK_ID(1005)),
 575         DEF_MOD("ssi7",                 1008,   MOD_CLK_ID(1005)),
 576         DEF_MOD("ssi6",                 1009,   MOD_CLK_ID(1005)),
 577         DEF_MOD("ssi5",                 1010,   MOD_CLK_ID(1005)),
 578         DEF_MOD("ssi4",                 1011,   MOD_CLK_ID(1005)),
 579         DEF_MOD("ssi3",                 1012,   MOD_CLK_ID(1005)),
 580         DEF_MOD("ssi2",                 1013,   MOD_CLK_ID(1005)),
 581         DEF_MOD("ssi1",                 1014,   MOD_CLK_ID(1005)),
 582         DEF_MOD("ssi0",                 1015,   MOD_CLK_ID(1005)),
 583         DEF_MOD("scu-all",              1017,   R8A7796_CLK_S3D4),
 584         DEF_MOD("scu-dvc1",             1018,   MOD_CLK_ID(1017)),
 585         DEF_MOD("scu-dvc0",             1019,   MOD_CLK_ID(1017)),
 586         DEF_MOD("scu-ctu1-mix1",        1020,   MOD_CLK_ID(1017)),
 587         DEF_MOD("scu-ctu0-mix0",        1021,   MOD_CLK_ID(1017)),
 588         DEF_MOD("scu-src9",             1022,   MOD_CLK_ID(1017)),
 589         DEF_MOD("scu-src8",             1023,   MOD_CLK_ID(1017)),
 590         DEF_MOD("scu-src7",             1024,   MOD_CLK_ID(1017)),
 591         DEF_MOD("scu-src6",             1025,   MOD_CLK_ID(1017)),
 592         DEF_MOD("scu-src5",             1026,   MOD_CLK_ID(1017)),
 593         DEF_MOD("scu-src4",             1027,   MOD_CLK_ID(1017)),
 594         DEF_MOD("scu-src3",             1028,   MOD_CLK_ID(1017)),
 595         DEF_MOD("scu-src2",             1029,   MOD_CLK_ID(1017)),
 596         DEF_MOD("scu-src1",             1030,   MOD_CLK_ID(1017)),
 597         DEF_MOD("scu-src0",             1031,   MOD_CLK_ID(1017)),
 598 };
 599
 600 static const struct cpg_core_clk r8a77970_core_clks[] = {
 601         /* External Clock Inputs */
 602         DEF_INPUT("extal",  CLK_EXTAL),
 603         DEF_INPUT("extalr", CLK_EXTALR),
 604
 605         /* Internal Core Clocks */
 606         DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
 607         DEF_BASE(".pll0",       CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
 608         DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
 609         DEF_BASE(".pll3",       CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
 610
 611         DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,     CLK_PLL1,       2, 1),
 612         DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4,     CLK_PLL1_DIV2,  2, 1),
 613         DEF_FIXED(".s1",        CLK_S1,            CLK_PLL1_DIV2,  4, 1),
 614         DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,  6, 1),
 615         DEF_FIXED(".rpcsrc",    CLK_RPCSRC,        CLK_PLL1,       2, 1),
 616
 617         /* Core Clock Outputs */
 618         DEF_BASE("z2",          R8A77970_CLK_Z2,    CLK_TYPE_GEN3_Z2, CLK_PLL1_DIV4),
 619         DEF_FIXED("ztr",        R8A77970_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
 620         DEF_FIXED("ztrd2",      R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
 621         DEF_FIXED("zt",         R8A77970_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
 622         DEF_FIXED("zx",         R8A77970_CLK_ZX,    CLK_PLL1_DIV2,  3, 1),
 623         DEF_FIXED("s1d1",       R8A77970_CLK_S1D1,  CLK_S1,         1, 1),
 624         DEF_FIXED("s1d2",       R8A77970_CLK_S1D2,  CLK_S1,         2, 1),
 625         DEF_FIXED("s1d4",       R8A77970_CLK_S1D4,  CLK_S1,         4, 1),
 626         DEF_FIXED("s2d1",       R8A77970_CLK_S2D1,  CLK_S2,         1, 1),
 627         DEF_FIXED("s2d2",       R8A77970_CLK_S2D2,  CLK_S2,         2, 1),
 628         DEF_FIXED("s2d4",       R8A77970_CLK_S2D4,  CLK_S2,         4, 1),
 629
 630         DEF_GEN3_SD("sd0",      R8A77970_CLK_SD0,   CLK_PLL1_DIV4, 0x0074),
 631
 632         DEF_GEN3_RPC("rpc",     R8A77970_CLK_RPC,   CLK_RPCSRC,    0x238),
 633
 634         DEF_FIXED("cl",         R8A77970_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
 635         DEF_FIXED("cp",         R8A77970_CLK_CP,    CLK_EXTAL,      2, 1),
 636
 637         /* NOTE: HDMI, CSI, CAN etc. clock are missing */
 638
 639         DEF_BASE("r",           R8A77970_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
 640 };
 641
 642 static const struct mssr_mod_clk r8a77970_mod_clks[] = {
 643         DEF_MOD("ivcp1e",                127,   R8A77970_CLK_S2D1),
 644         DEF_MOD("scif4",                 203,   R8A77970_CLK_S2D4),     /* @@ H3=S3D4 */
 645         DEF_MOD("scif3",                 204,   R8A77970_CLK_S2D4),     /* @@ H3=S3D4 */
 646         DEF_MOD("scif1",                 206,   R8A77970_CLK_S2D4),     /* @@ H3=S3D4 */
 647         DEF_MOD("scif0",                 207,   R8A77970_CLK_S2D4),     /* @@ H3=S3D4 */
 648         DEF_MOD("msiof3",                208,   R8A77970_CLK_MSO),
 649         DEF_MOD("msiof2",                209,   R8A77970_CLK_MSO),
 650         DEF_MOD("msiof1",                210,   R8A77970_CLK_MSO),
 651         DEF_MOD("msiof0",                211,   R8A77970_CLK_MSO),
 652         DEF_MOD("mfis",                  213,   R8A77970_CLK_S2D2),     /* @@ H3=S3D2 */
 653         DEF_MOD("sys-dmac2",     217,   R8A77970_CLK_S2D1),     /* @@ H3=S3D1 */
 654         DEF_MOD("sys-dmac1",     218,   R8A77970_CLK_S2D1),     /* @@ H3=S3D1 */
 655         DEF_MOD("sdif",                  314,   R8A77970_CLK_SD0),
 656         DEF_MOD("rwdt0",                 402,   R8A77970_CLK_R),
 657         DEF_MOD("intc-ex",               407,   R8A77970_CLK_CP),
 658         DEF_MOD("intc-ap",               408,   R8A77970_CLK_S2D1),     /* @@ H3=S3D1 */
 659         DEF_MOD("hscif3",                517,   R8A77970_CLK_S2D1),     /* @@ H3=S3D1 */
 660         DEF_MOD("hscif2",                518,   R8A77970_CLK_S2D1),     /* @@ H3=S3D1 */
 661         DEF_MOD("hscif1",                519,   R8A77970_CLK_S2D1),     /* @@ H3=S3D1 */
 662         DEF_MOD("hscif0",                520,   R8A77970_CLK_S2D1),     /* @@ H3=S3D1 */
 663         DEF_MOD("thermal",               522,   R8A77970_CLK_CP),
 664         DEF_MOD("pwm",                   523,   R8A77970_CLK_S2D4),
 665         DEF_MOD("fcpvd0",                603,   R8A77970_CLK_S2D1),
 666         DEF_MOD("vspd0",                 623,   R8A77970_CLK_S2D1),
 667         DEF_MOD("csi40",                 716,   R8A77970_CLK_CSI0),
 668         DEF_MOD("du0",                   724,   R8A77970_CLK_S2D1),
 669         DEF_MOD("lvds",                  727,   R8A77970_CLK_S2D1),
 670         DEF_MOD("vin3",                  808,   R8A77970_CLK_S2D1),
 671         DEF_MOD("vin2",                  809,   R8A77970_CLK_S2D1),
 672         DEF_MOD("vin1",                  810,   R8A77970_CLK_S2D1),
 673         DEF_MOD("vin0",                  811,   R8A77970_CLK_S2D1),
 674         DEF_MOD("etheravb",              812,   R8A77970_CLK_S2D2),
 675         DEF_MOD("isp",                   817,   R8A77970_CLK_S2D1),
 676         DEF_MOD("gpio5",                 907,   R8A77970_CLK_CP),
 677         DEF_MOD("gpio4",                 908,   R8A77970_CLK_CP),
 678         DEF_MOD("gpio3",                 909,   R8A77970_CLK_CP),
 679         DEF_MOD("gpio2",                 910,   R8A77970_CLK_CP),
 680         DEF_MOD("gpio1",                 911,   R8A77970_CLK_CP),
 681         DEF_MOD("gpio0",                 912,   R8A77970_CLK_CP),
 682         DEF_MOD("can-fd",                914,   R8A77970_CLK_S2D2),
 683         DEF_MOD("rpc",                   917,   R8A77970_CLK_RPC),
 684         DEF_MOD("i2c4",                  927,   R8A77970_CLK_S2D2),
 685         DEF_MOD("i2c3",                  928,   R8A77970_CLK_S2D2),
 686         DEF_MOD("i2c2",                  929,   R8A77970_CLK_S2D2),
 687         DEF_MOD("i2c1",                  930,   R8A77970_CLK_S2D2),
 688         DEF_MOD("i2c0",                  931,   R8A77970_CLK_S2D2),
 689 };
 690
 691 /*
 692  * CPG Clock Data
 693  */
 694
 695 /*
 696  *   MD         EXTAL           PLL0    PLL1    PLL2    PLL3    PLL4
 697  * 14 13 19 17  (MHz)
 698  *-------------------------------------------------------------------
 699  * 0  0  0  0   16.66 x 1       x180    x192    x144    x192    x144
 700  * 0  0  0  1   16.66 x 1       x180    x192    x144    x128    x144
 701  * 0  0  1  0   Prohibited setting
 702  * 0  0  1  1   16.66 x 1       x180    x192    x144    x192    x144
 703  * 0  1  0  0   20    x 1       x150    x160    x120    x160    x120
 704  * 0  1  0  1   20    x 1       x150    x160    x120    x106    x120
 705  * 0  1  1  0   Prohibited setting
 706  * 0  1  1  1   20    x 1       x150    x160    x120    x160    x120
 707  * 1  0  0  0   25    x 1       x120    x128    x96     x128    x96
 708  * 1  0  0  1   25    x 1       x120    x128    x96     x84     x96
 709  * 1  0  1  0   Prohibited setting
 710  * 1  0  1  1   25    x 1       x120    x128    x96     x128    x96
 711  * 1  1  0  0   33.33 / 2       x180    x192    x144    x192    x144
 712  * 1  1  0  1   33.33 / 2       x180    x192    x144    x128    x144
 713  * 1  1  1  0   Prohibited setting
 714  * 1  1  1  1   33.33 / 2       x180    x192    x144    x192    x144
 715  */
 716 #define CPG_PLL_CONFIG_INDEX(md)        ((((md) & BIT(14)) >> 11) | \
 717                                          (((md) & BIT(13)) >> 11) | \
 718                                          (((md) & BIT(19)) >> 18) | \
 719                                          (((md) & BIT(17)) >> 17))
 720
 721 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
 722         /* EXTAL div    PLL1 mult       PLL3 mult */
 723         { 1,            192,            192,    },
 724         { 1,            192,            128,    },
 725         { 0, /* Prohibited setting */           },
 726         { 1,            192,            192,    },
 727         { 1,            160,            160,    },
 728         { 1,            160,            106,    },
 729         { 0, /* Prohibited setting */           },
 730         { 1,            160,            160,    },
 731         { 1,            128,            128,    },
 732         { 1,            128,            84,     },
 733         { 0, /* Prohibited setting */           },
 734         { 1,            128,            128,    },
 735         { 2,            192,            192,    },
 736         { 2,            192,            128,    },
 737         { 0, /* Prohibited setting */           },
 738         { 2,            192,            192,    },
 739 };
 740
 741 /*
 742  * SDn Clock
 743  */
 744 #define CPG_SD_STP_HCK          BIT(9)
 745 #define CPG_SD_STP_CK           BIT(8)
 746
 747 #define CPG_SD_STP_MASK         (CPG_SD_STP_HCK | CPG_SD_STP_CK)
 748 #define CPG_SD_FC_MASK          (0x7 << 2 | 0x3 << 0)
 749
 750 #define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
 751 { \
 752         .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
 753                ((stp_ck) ? CPG_SD_STP_CK : 0) | \
 754                ((sd_srcfc) << 2) | \
 755                ((sd_fc) << 0), \
 756         .div = (sd_div), \
 757 }
 758
 759 struct sd_div_table {
 760         u32 val;
 761         unsigned int div;
 762 };
 763
 764 /* SDn divider
 765  *                     sd_srcfc   sd_fc   div
 766  * stp_hck   stp_ck    (div)      (div)     = sd_srcfc x sd_fc
 767  *-------------------------------------------------------------------
 768  *  0         0         0 (1)      1 (4)      4
 769  *  0         0         1 (2)      1 (4)      8
 770  *  1         0         2 (4)      1 (4)     16
 771  *  1         0         3 (8)      1 (4)     32
 772  *  1         0         4 (16)     1 (4)     64
 773  *  0         0         0 (1)      0 (2)      2
 774  *  0         0         1 (2)      0 (2)      4
 775  *  1         0         2 (4)      0 (2)      8
 776  *  1         0         3 (8)      0 (2)     16
 777  *  1         0         4 (16)     0 (2)     32
 778  */
 779 static const struct sd_div_table cpg_sd_div_table[] = {
 780 /*      CPG_SD_DIV_TABLE_DATA(stp_hck,  stp_ck,   sd_srcfc,   sd_fc,  sd_div) */
 781         CPG_SD_DIV_TABLE_DATA(0,        0,        0,          1,        4),
 782         CPG_SD_DIV_TABLE_DATA(0,        0,        1,          1,        8),
 783         CPG_SD_DIV_TABLE_DATA(1,        0,        2,          1,       16),
 784         CPG_SD_DIV_TABLE_DATA(1,        0,        3,          1,       32),
 785         CPG_SD_DIV_TABLE_DATA(1,        0,        4,          1,       64),
 786         CPG_SD_DIV_TABLE_DATA(0,        0,        0,          0,        2),
 787         CPG_SD_DIV_TABLE_DATA(0,        0,        1,          0,        4),
 788         CPG_SD_DIV_TABLE_DATA(1,        0,        2,          0,        8),
 789         CPG_SD_DIV_TABLE_DATA(1,        0,        3,          0,       16),
 790         CPG_SD_DIV_TABLE_DATA(1,        0,        4,          0,       32),
 791 };
 792
 793 static bool gen3_clk_is_mod(struct clk *clk)
 794 {
 795         return (clk->id >> 16) == CPG_MOD;
 796 }
 797
 798 static int gen3_clk_get_mod(struct clk *clk, const struct mssr_mod_clk **mssr)
 799 {
 800         struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
 801         const unsigned long clkid = clk->id & 0xffff;
 802         int i;
 803
 804         if (!gen3_clk_is_mod(clk))
 805                 return -EINVAL;
 806
 807         for (i = 0; i < priv->mod_clk_size; i++) {
 808                 if (priv->mod_clk[i].id != MOD_CLK_ID(clkid))
 809                         continue;
 810
 811                 *mssr = &priv->mod_clk[i];
 812                 return 0;
 813         }
 814
 815         return -ENODEV;
 816 }
 817
 818 static int gen3_clk_get_core(struct clk *clk, const struct cpg_core_clk **core)
 819 {
 820         struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
 821         const unsigned long clkid = clk->id & 0xffff;
 822         int i;
 823
 824         if (gen3_clk_is_mod(clk))
 825                 return -EINVAL;
 826
 827         for (i = 0; i < priv->core_clk_size; i++) {
 828                 if (priv->core_clk[i].id != clkid)
 829                         continue;
 830
 831                 *core = &priv->core_clk[i];
 832                 return 0;
 833         }
 834
 835         return -ENODEV;
 836 }
 837
 838 static int gen3_clk_get_parent(struct clk *clk, struct clk *parent)
 839 {
 840         const struct cpg_core_clk *core;
 841         const struct mssr_mod_clk *mssr;
 842         int ret;
 843
 844         if (gen3_clk_is_mod(clk)) {
 845                 ret = gen3_clk_get_mod(clk, &mssr);
 846                 if (ret)
 847                         return ret;
 848
 849                 parent->id = mssr->parent;
 850         } else {
 851                 ret = gen3_clk_get_core(clk, &core);
 852                 if (ret)
 853                         return ret;
 854
 855                 if (core->type == CLK_TYPE_IN)
 856                         parent->id = ~0;        /* Top-level clock */
 857                 else
 858                         parent->id = core->parent;
 859         }
 860
 861         parent->dev = clk->dev;
 862
 863         return 0;
 864 }
 865
 866 static int gen3_clk_setup_sdif_div(struct clk *clk)
 867 {
 868         struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
 869         const struct cpg_core_clk *core;
 870         struct clk parent;
 871         int ret;
 872
 873         ret = gen3_clk_get_parent(clk, &parent);
 874         if (ret) {
 875                 printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
 876                 return ret;
 877         }
 878
 879         if (gen3_clk_is_mod(&parent))
 880                 return 0;
 881
 882         ret = gen3_clk_get_core(&parent, &core);
 883         if (ret)
 884                 return ret;
 885
 886         if (core->type != CLK_TYPE_GEN3_SD)
 887                 return 0;
 888
 889         debug("%s[%i] SDIF offset=%x\n", __func__, __LINE__, core->offset);
 890
 891         writel(1, priv->base + core->offset);
 892
 893         return 0;
 894 }
 895
 896 static int gen3_clk_endisable(struct clk *clk, bool enable)
 897 {
 898         struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
 899         const unsigned long clkid = clk->id & 0xffff;
 900         const unsigned int reg = clkid / 100;
 901         const unsigned int bit = clkid % 100;
 902         const u32 bitmask = BIT(bit);
 903         int ret;
 904
 905         if (!gen3_clk_is_mod(clk))
 906                 return -EINVAL;
 907
 908         debug("%s[%i] MSTP %lu=%02u/%02u %s\n", __func__, __LINE__,
 909               clkid, reg, bit, enable ? "ON" : "OFF");
 910
 911         if (enable) {
 912                 ret = gen3_clk_setup_sdif_div(clk);
 913                 if (ret)
 914                         return ret;
 915                 clrbits_le32(priv->base + SMSTPCR(reg), bitmask);
 916                 return wait_for_bit("MSTP", priv->base + MSTPSR(reg),
 917                                     bitmask, 0, 100, 0);
 918         } else {
 919                 setbits_le32(priv->base + SMSTPCR(reg), bitmask);
 920                 return 0;
 921         }
 922 }
 923
 924 static int gen3_clk_enable(struct clk *clk)
 925 {
 926         return gen3_clk_endisable(clk, true);
 927 }
 928
 929 static int gen3_clk_disable(struct clk *clk)
 930 {
 931         return gen3_clk_endisable(clk, false);
 932 }
 933
 934 static ulong gen3_clk_get_rate(struct clk *clk)
 935 {
 936         struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
 937         struct clk parent;
 938         const struct cpg_core_clk *core;
 939         const struct rcar_gen3_cpg_pll_config *pll_config =
 940                                         priv->cpg_pll_config;
 941         u32 value, mult, prediv, postdiv, rate = 0;
 942         int i, ret;
 943
 944         debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
 945
 946         ret = gen3_clk_get_parent(clk, &parent);
 947         if (ret) {
 948                 printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
 949                 return ret;
 950         }
 951
 952         if (gen3_clk_is_mod(clk)) {
 953                 rate = gen3_clk_get_rate(&parent);
 954                 debug("%s[%i] MOD clk: parent=%lu => rate=%u\n",
 955                       __func__, __LINE__, parent.id, rate);
 956                 return rate;
 957         }
 958
 959         ret = gen3_clk_get_core(clk, &core);
 960         if (ret)
 961                 return ret;
 962
 963         switch (core->type) {
 964         case CLK_TYPE_IN:
 965                 if (core->id == CLK_EXTAL) {
 966                         rate = clk_get_rate(&priv->clk_extal);
 967                         debug("%s[%i] EXTAL clk: rate=%u\n",
 968                               __func__, __LINE__, rate);
 969                         return rate;
 970                 }
 971
 972                 if (core->id == CLK_EXTALR) {
 973                         rate = clk_get_rate(&priv->clk_extalr);
 974                         debug("%s[%i] EXTALR clk: rate=%u\n",
 975                               __func__, __LINE__, rate);
 976                         return rate;
 977                 }
 978
 979                 return -EINVAL;
 980
 981         case CLK_TYPE_GEN3_MAIN:
 982                 rate = gen3_clk_get_rate(&parent) / pll_config->extal_div;
 983                 debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%u\n",
 984                       __func__, __LINE__,
 985                       core->parent, pll_config->extal_div, rate);
 986                 return rate;
 987
 988         case CLK_TYPE_GEN3_PLL0:
 989                 value = readl(priv->base + CPG_PLL0CR);
 990                 mult = (((value >> 24) & 0x7f) + 1) * 2;
 991                 rate = gen3_clk_get_rate(&parent) * mult;
 992                 debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%u\n",
 993                       __func__, __LINE__, core->parent, mult, rate);
 994                 return rate;
 995
 996         case CLK_TYPE_GEN3_PLL1:
 997                 rate = gen3_clk_get_rate(&parent) * pll_config->pll1_mult;
 998                 debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%u\n",
 999                       __func__, __LINE__,
1000                       core->parent, pll_config->pll1_mult, rate);
1001                 return rate;
1002
1003         case CLK_TYPE_GEN3_PLL2:
1004                 value = readl(priv->base + CPG_PLL2CR);
1005                 mult = (((value >> 24) & 0x7f) + 1) * 2;
1006                 rate = gen3_clk_get_rate(&parent) * mult;
1007                 debug("%s[%i] PLL2 clk: parent=%i mult=%u => rate=%u\n",
1008                       __func__, __LINE__, core->parent, mult, rate);
1009                 return rate;
1010
1011         case CLK_TYPE_GEN3_PLL3:
1012                 rate = gen3_clk_get_rate(&parent) * pll_config->pll3_mult;
1013                 debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%u\n",
1014                       __func__, __LINE__,
1015                       core->parent, pll_config->pll3_mult, rate);
1016                 return rate;
1017
1018         case CLK_TYPE_GEN3_PLL4:
1019                 value = readl(priv->base + CPG_PLL4CR);
1020                 mult = (((value >> 24) & 0x7f) + 1) * 2;
1021                 rate = gen3_clk_get_rate(&parent) * mult;
1022                 debug("%s[%i] PLL4 clk: parent=%i mult=%u => rate=%u\n",
1023                       __func__, __LINE__, core->parent, mult, rate);
1024                 return rate;
1025
1026         case CLK_TYPE_FF:
1027                 rate = (gen3_clk_get_rate(&parent) * core->mult) / core->div;
1028                 debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n",
1029                       __func__, __LINE__,
1030                       core->parent, core->mult, core->div, rate);
1031                 return rate;
1032
1033         case CLK_TYPE_GEN3_SD:          /* FIXME */
1034                 value = readl(priv->base + core->offset);
1035                 value &= CPG_SD_STP_MASK | CPG_SD_FC_MASK;
1036
1037                 for (i = 0; i < ARRAY_SIZE(cpg_sd_div_table); i++) {
1038                         if (cpg_sd_div_table[i].val != value)
1039                                 continue;
1040
1041                         rate = gen3_clk_get_rate(&parent) /
1042                                cpg_sd_div_table[i].div;
1043                         debug("%s[%i] SD clk: parent=%i div=%i => rate=%u\n",
1044                               __func__, __LINE__,
1045                               core->parent, cpg_sd_div_table[i].div, rate);
1046
1047                         return rate;
1048                 }
1049
1050                 return -EINVAL;
1051
1052         case CLK_TYPE_GEN3_RPC:
1053                 rate = gen3_clk_get_rate(&parent);
1054
1055                 value = readl(priv->base + core->offset);
1056
1057                 prediv = (value >> CPG_RPC_PREDIV_OFFSET) &
1058                          CPG_RPC_PREDIV_MASK;
1059                 if (prediv == 2)
1060                         rate /= 5;
1061                 else if (prediv == 3)
1062                         rate /= 6;
1063                 else
1064                         return -EINVAL;
1065
1066                 postdiv = (value >> CPG_RPC_POSTDIV_OFFSET) &
1067                           CPG_RPC_POSTDIV_MASK;
1068                 rate /= postdiv + 1;
1069
1070                 debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%u\n",
1071                       __func__, __LINE__,
1072                       core->parent, prediv, postdiv, rate);
1073
1074                 return -EINVAL;
1075
1076         }
1077
1078         printf("%s[%i] unknown fail\n", __func__, __LINE__);
1079
1080         return -ENOENT;
1081 }
1082
1083 static ulong gen3_clk_set_rate(struct clk *clk, ulong rate)
1084 {
1085         return gen3_clk_get_rate(clk);
1086 }
1087
1088 static int gen3_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
1089 {
1090         if (args->args_count != 2) {
1091                 debug("Invaild args_count: %d\n", args->args_count);
1092                 return -EINVAL;
1093         }
1094
1095         clk->id = (args->args[0] << 16) | args->args[1];
1096
1097         return 0;
1098 }
1099
1100 static const struct clk_ops gen3_clk_ops = {
1101         .enable         = gen3_clk_enable,
1102         .disable        = gen3_clk_disable,
1103         .get_rate       = gen3_clk_get_rate,
1104         .set_rate       = gen3_clk_set_rate,
1105         .of_xlate       = gen3_clk_of_xlate,
1106 };
1107
1108 enum gen3_clk_model {
1109         CLK_R8A7795,
1110         CLK_R8A7796,
1111         CLK_R8A77970,
1112 };
1113
1114 static int gen3_clk_probe(struct udevice *dev)
1115 {
1116         struct gen3_clk_priv *priv = dev_get_priv(dev);
1117         enum gen3_clk_model model = dev_get_driver_data(dev);
1118         fdt_addr_t rst_base;
1119         u32 cpg_mode;
1120         int ret;
1121
1122         priv->base = (struct gen3_base *)devfdt_get_addr(dev);
1123         if (!priv->base)
1124                 return -EINVAL;
1125
1126         switch (model) {
1127         case CLK_R8A7795:
1128                 priv->core_clk = r8a7795_core_clks;
1129                 priv->core_clk_size = ARRAY_SIZE(r8a7795_core_clks);
1130                 priv->mod_clk = r8a7795_mod_clks;
1131                 priv->mod_clk_size = ARRAY_SIZE(r8a7795_mod_clks);
1132                 ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
1133                                                     "renesas,r8a7795-rst");
1134                 if (ret < 0)
1135                         return ret;
1136                 break;
1137         case CLK_R8A7796:
1138                 priv->core_clk = r8a7796_core_clks;
1139                 priv->core_clk_size = ARRAY_SIZE(r8a7796_core_clks);
1140                 priv->mod_clk = r8a7796_mod_clks;
1141                 priv->mod_clk_size = ARRAY_SIZE(r8a7796_mod_clks);
1142                 ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
1143                                                     "renesas,r8a7796-rst");
1144                 if (ret < 0)
1145                         return ret;
1146                 break;
1147         case CLK_R8A77970:
1148                 priv->core_clk = r8a77970_core_clks;
1149                 priv->core_clk_size = ARRAY_SIZE(r8a77970_core_clks);
1150                 priv->mod_clk = r8a77970_mod_clks;
1151                 priv->mod_clk_size = ARRAY_SIZE(r8a77970_mod_clks);
1152                 ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
1153                                                     "renesas,r8a77970-rst");
1154                 if (ret < 0)
1155                         return ret;
1156                 break;
1157         default:
1158                 return -EINVAL;
1159         }
1160
1161         rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg");
1162         if (rst_base == FDT_ADDR_T_NONE)
1163                 return -EINVAL;
1164
1165         cpg_mode = readl(rst_base + CPG_RST_MODEMR);
1166
1167         priv->cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
1168         if (!priv->cpg_pll_config->extal_div)
1169                 return -EINVAL;
1170
1171         ret = clk_get_by_name(dev, "extal", &priv->clk_extal);
1172         if (ret < 0)
1173                 return ret;
1174
1175         ret = clk_get_by_name(dev, "extalr", &priv->clk_extalr);
1176         if (ret < 0)
1177                 return ret;
1178
1179         return 0;
1180 }
1181
1182 struct mstp_stop_table {
1183         u32     dis;
1184         u32     en;
1185 };
1186
1187 static struct mstp_stop_table r8a7795_mstp_table[] = {
1188         { 0x00640800, 0x0 },    { 0xF3EE9390, 0x0 },
1189         { 0x340FAFDC, 0x2040 }, { 0xD80C7CDF, 0x400 },
1190         { 0x80000184, 0x180 },  { 0x40BFFF46, 0x0 },
1191         { 0xE5FBEECF, 0x0 },    { 0x39FFFF0E, 0x0 },
1192         { 0x01F19FF4, 0x0 },    { 0xFFDFFFFF, 0x0 },
1193         { 0xFFFEFFE0, 0x0 },    { 0x00000000, 0x0 },
1194 };
1195
1196 static struct mstp_stop_table r8a7796_mstp_table[] = {
1197         { 0x00200000, 0x0 },    { 0xFFFFFFFF, 0x0 },
1198         { 0x340E2FDC, 0x2040 }, { 0xFFFFFFDF, 0x400 },
1199         { 0x80000184, 0x180 },  { 0xC3FFFFFF, 0x0 },
1200         { 0xFFFFFFFF, 0x0 },    { 0xFFFFFFFF, 0x0 },
1201         { 0x01F1FFF7, 0x0 },    { 0xFFFFFFFE, 0x0 },
1202         { 0xFFFEFFE0, 0x0 },    { 0x000000B7, 0x0 },
1203 };
1204
1205 static struct mstp_stop_table r8a77970_mstp_table[] = {
1206         { 0x00230000, 0x0 },    { 0xFFFFFFFF, 0x0 },
1207         { 0x14062FD8, 0x2040 }, { 0xFFFFFFDF, 0x400 },
1208         { 0x80000184, 0x180 },  { 0x83FFFFFF, 0x0 },
1209         { 0xFFFFFFFF, 0x0 },    { 0xFFFFFFFF, 0x0 },
1210         { 0x7FF3FFF4, 0x0 },    { 0xFBF7FF97, 0x0 },
1211         { 0xFFFEFFE0, 0x0 },    { 0x000000B7, 0x0 },
1212 };
1213
1214 #define TSTR0           0x04
1215 #define TSTR0_STR0      BIT(0)
1216
1217 static int gen3_clk_remove(struct udevice *dev)
1218 {
1219         struct gen3_clk_priv *priv = dev_get_priv(dev);
1220         enum gen3_clk_model model = dev_get_driver_data(dev);
1221         struct mstp_stop_table *tbl;
1222         unsigned int i, tbl_size;
1223
1224         switch (model) {
1225         case CLK_R8A7795:
1226                 tbl = r8a7795_mstp_table;
1227                 tbl_size = ARRAY_SIZE(r8a7795_mstp_table);
1228                 break;
1229         case CLK_R8A7796:
1230                 tbl = r8a7796_mstp_table;
1231                 tbl_size = ARRAY_SIZE(r8a7796_mstp_table);
1232                 break;
1233         case CLK_R8A77970:
1234                 tbl = r8a77970_mstp_table;
1235                 tbl_size = ARRAY_SIZE(r8a77970_mstp_table);
1236                 break;
1237         default:
1238                 return -EINVAL;
1239         }
1240
1241         /* Stop TMU0 */
1242         clrbits_le32(TMU_BASE + TSTR0, TSTR0_STR0);
1243
1244         /* Stop module clock */
1245         for (i = 0; i < tbl_size; i++) {
1246                 clrsetbits_le32(priv->base + SMSTPCR(i), tbl[i].dis, tbl[i].en);
1247                 clrsetbits_le32(priv->base + RMSTPCR(i), tbl[i].dis, 0x0);
1248         }
1249
1250         return 0;
1251 }
1252
1253 static const struct udevice_id gen3_clk_ids[] = {
1254         { .compatible = "renesas,r8a7795-cpg-mssr", .data = CLK_R8A7795 },
1255         { .compatible = "renesas,r8a7796-cpg-mssr", .data = CLK_R8A7796 },
1256         { .compatible = "renesas,r8a77970-cpg-mssr", .data = CLK_R8A77970 },
1257         { }
1258 };
1259
1260 U_BOOT_DRIVER(clk_gen3) = {
1261         .name           = "clk_gen3",
1262         .id             = UCLASS_CLK,
1263         .of_match       = gen3_clk_ids,
1264         .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
1265         .ops            = &gen3_clk_ops,
1266         .probe          = gen3_clk_probe,
1267         .remove         = gen3_clk_remove,
1268 };