1 // SPDX-License-Identifier: GPL-2.0+
3 * Renesas RCar Gen3 CPG MSSR driver
5 * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
7 * Based on the following driver from Linux kernel:
8 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
10 * Copyright (C) 2016 Glider bvba
14 #include <clk-uclass.h>
19 #include <asm/global_data.h>
21 #include <linux/bitops.h>
23 #include <dt-bindings/clock/renesas-cpg-mssr.h>
25 #include "renesas-cpg-mssr.h"
26 #include "rcar-gen3-cpg.h"
28 #define CPG_RST_MODEMR 0x0060
30 #define CPG_PLL0CR 0x00d8
31 #define CPG_PLL2CR 0x002c
32 #define CPG_PLL4CR 0x01f4
34 #define CPG_RPC_PREDIV_MASK 0x3
35 #define CPG_RPC_PREDIV_OFFSET 3
36 #define CPG_RPC_POSTDIV_MASK 0x7
37 #define CPG_RPC_POSTDIV_OFFSET 0
42 #define CPG_SD_STP_HCK BIT(9)
43 #define CPG_SD_STP_CK BIT(8)
45 #define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK)
46 #define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0)
48 #define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
50 .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
51 ((stp_ck) ? CPG_SD_STP_CK : 0) | \
64 * stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc
65 *-------------------------------------------------------------------
77 static const struct sd_div_table cpg_sd_div_table[] = {
78 /* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */
79 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4),
80 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8),
81 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16),
82 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32),
83 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64),
84 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2),
85 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4),
86 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8),
87 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16),
88 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
91 static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk,
92 struct cpg_mssr_info *info, struct clk *parent)
94 const struct cpg_core_clk *core;
97 if (!renesas_clk_is_mod(clk)) {
98 ret = renesas_clk_get_core(clk, info, &core);
102 if (core->type == CLK_TYPE_GEN3_MDSEL) {
103 parent->dev = clk->dev;
104 parent->id = core->parent >> (priv->sscg ? 16 : 0);
105 parent->id &= 0xffff;
110 return renesas_clk_get_parent(clk, info, parent);
113 static int gen3_clk_setup_sdif_div(struct clk *clk, ulong rate)
115 struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
116 struct cpg_mssr_info *info = priv->info;
117 const struct cpg_core_clk *core;
121 ret = gen3_clk_get_parent(priv, clk, info, &parent);
123 printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
127 if (renesas_clk_is_mod(&parent))
130 ret = renesas_clk_get_core(&parent, info, &core);
134 if (core->type != CLK_TYPE_GEN3_SD)
137 debug("%s[%i] SDIF offset=%x\n", __func__, __LINE__, core->offset);
139 writel((rate == 400000000) ? 0x4 : 0x1, priv->base + core->offset);
144 static int gen3_clk_enable(struct clk *clk)
146 struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
148 return renesas_clk_endisable(clk, priv->base, true);
151 static int gen3_clk_disable(struct clk *clk)
153 struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
155 return renesas_clk_endisable(clk, priv->base, false);
158 static u64 gen3_clk_get_rate64(struct clk *clk)
160 struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
161 struct cpg_mssr_info *info = priv->info;
163 const struct cpg_core_clk *core;
164 const struct rcar_gen3_cpg_pll_config *pll_config =
165 priv->cpg_pll_config;
166 u32 value, mult, div, prediv, postdiv;
170 debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
172 ret = gen3_clk_get_parent(priv, clk, info, &parent);
174 printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
178 if (renesas_clk_is_mod(clk)) {
179 rate = gen3_clk_get_rate64(&parent);
180 debug("%s[%i] MOD clk: parent=%lu => rate=%llu\n",
181 __func__, __LINE__, parent.id, rate);
185 ret = renesas_clk_get_core(clk, info, &core);
189 switch (core->type) {
191 if (core->id == info->clk_extal_id) {
192 rate = clk_get_rate(&priv->clk_extal);
193 debug("%s[%i] EXTAL clk: rate=%llu\n",
194 __func__, __LINE__, rate);
198 if (core->id == info->clk_extalr_id) {
199 rate = clk_get_rate(&priv->clk_extalr);
200 debug("%s[%i] EXTALR clk: rate=%llu\n",
201 __func__, __LINE__, rate);
207 case CLK_TYPE_GEN3_MAIN:
208 rate = gen3_clk_get_rate64(&parent) / pll_config->extal_div;
209 debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%llu\n",
211 core->parent, pll_config->extal_div, rate);
214 case CLK_TYPE_GEN3_PLL0:
215 value = readl(priv->base + CPG_PLL0CR);
216 mult = (((value >> 24) & 0x7f) + 1) * 2;
217 rate = gen3_clk_get_rate64(&parent) * mult;
218 debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%llu\n",
219 __func__, __LINE__, core->parent, mult, rate);
222 case CLK_TYPE_GEN3_PLL1:
223 rate = gen3_clk_get_rate64(&parent) * pll_config->pll1_mult;
224 rate /= pll_config->pll1_div;
225 debug("%s[%i] PLL1 clk: parent=%i mul=%i div=%i => rate=%llu\n",
227 core->parent, pll_config->pll1_mult,
228 pll_config->pll1_div, rate);
231 case CLK_TYPE_GEN3_PLL2:
232 value = readl(priv->base + CPG_PLL2CR);
233 mult = (((value >> 24) & 0x7f) + 1) * 2;
234 rate = gen3_clk_get_rate64(&parent) * mult;
235 debug("%s[%i] PLL2 clk: parent=%i mult=%u => rate=%llu\n",
236 __func__, __LINE__, core->parent, mult, rate);
239 case CLK_TYPE_GEN3_PLL3:
240 rate = gen3_clk_get_rate64(&parent) * pll_config->pll3_mult;
241 rate /= pll_config->pll3_div;
242 debug("%s[%i] PLL3 clk: parent=%i mul=%i div=%i => rate=%llu\n",
244 core->parent, pll_config->pll3_mult,
245 pll_config->pll3_div, rate);
248 case CLK_TYPE_GEN3_PLL4:
249 value = readl(priv->base + CPG_PLL4CR);
250 mult = (((value >> 24) & 0x7f) + 1) * 2;
251 rate = gen3_clk_get_rate64(&parent) * mult;
252 debug("%s[%i] PLL4 clk: parent=%i mult=%u => rate=%llu\n",
253 __func__, __LINE__, core->parent, mult, rate);
257 rate = (gen3_clk_get_rate64(&parent) * core->mult) / core->div;
258 debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i => rate=%llu\n",
260 core->parent, core->mult, core->div, rate);
263 case CLK_TYPE_GEN3_MDSEL:
264 div = (core->div >> (priv->sscg ? 16 : 0)) & 0xffff;
265 rate = gen3_clk_get_rate64(&parent) / div;
266 debug("%s[%i] PE clk: parent=%i div=%u => rate=%llu\n",
268 (core->parent >> (priv->sscg ? 16 : 0)) & 0xffff,
272 case CLK_TYPE_GEN3_SD: /* FIXME */
273 value = readl(priv->base + core->offset);
274 value &= CPG_SD_STP_MASK | CPG_SD_FC_MASK;
276 for (i = 0; i < ARRAY_SIZE(cpg_sd_div_table); i++) {
277 if (cpg_sd_div_table[i].val != value)
280 rate = gen3_clk_get_rate64(&parent) /
281 cpg_sd_div_table[i].div;
282 debug("%s[%i] SD clk: parent=%i div=%i => rate=%llu\n",
284 core->parent, cpg_sd_div_table[i].div, rate);
291 case CLK_TYPE_GEN3_RPC:
292 case CLK_TYPE_GEN3_RPCD2:
293 rate = gen3_clk_get_rate64(&parent);
295 value = readl(priv->base + core->offset);
297 prediv = (value >> CPG_RPC_PREDIV_OFFSET) &
301 else if (prediv == 3)
306 postdiv = (value >> CPG_RPC_POSTDIV_OFFSET) &
307 CPG_RPC_POSTDIV_MASK;
309 if (postdiv % 2 != 0) {
312 if (core->type == CLK_TYPE_GEN3_RPCD2)
315 debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%llu\n",
317 core->parent, prediv, postdiv, rate);
326 printf("%s[%i] unknown fail\n", __func__, __LINE__);
331 static ulong gen3_clk_get_rate(struct clk *clk)
333 return gen3_clk_get_rate64(clk);
336 static ulong gen3_clk_set_rate(struct clk *clk, ulong rate)
338 /* Force correct SD-IF divider configuration if applicable */
339 gen3_clk_setup_sdif_div(clk, rate);
340 return gen3_clk_get_rate64(clk);
343 static int gen3_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
345 if (args->args_count != 2) {
346 debug("Invaild args_count: %d\n", args->args_count);
350 clk->id = (args->args[0] << 16) | args->args[1];
355 const struct clk_ops gen3_clk_ops = {
356 .enable = gen3_clk_enable,
357 .disable = gen3_clk_disable,
358 .get_rate = gen3_clk_get_rate,
359 .set_rate = gen3_clk_set_rate,
360 .of_xlate = gen3_clk_of_xlate,
363 int gen3_clk_probe(struct udevice *dev)
365 struct gen3_clk_priv *priv = dev_get_priv(dev);
366 struct cpg_mssr_info *info =
367 (struct cpg_mssr_info *)dev_get_driver_data(dev);
372 priv->base = dev_read_addr_ptr(dev);
377 ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, info->reset_node);
381 rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg");
382 if (rst_base == FDT_ADDR_T_NONE)
385 cpg_mode = readl(rst_base + CPG_RST_MODEMR);
387 priv->cpg_pll_config =
388 (struct rcar_gen3_cpg_pll_config *)info->get_pll_config(cpg_mode);
389 if (!priv->cpg_pll_config->extal_div)
392 priv->sscg = !(cpg_mode & BIT(12));
394 ret = clk_get_by_name(dev, "extal", &priv->clk_extal);
398 if (info->extalr_node) {
399 ret = clk_get_by_name(dev, info->extalr_node, &priv->clk_extalr);
407 int gen3_clk_remove(struct udevice *dev)
409 struct gen3_clk_priv *priv = dev_get_priv(dev);
411 return renesas_clk_remove(priv->base, priv->info);