drivers/clk/renesas/clk-rcar-gen3.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Renesas RCar Gen3 CPG MSSR driver
   4  *
   5  * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
   6  *
   7  * Based on the following driver from Linux kernel:
   8  * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
   9  *
  10  * Copyright (C) 2016 Glider bvba
  11  */
  12
  13 #include <common.h>
  14 #include <clk-uclass.h>
  15 #include <dm.h>
  16 #include <errno.h>
  17 #include <log.h>
  18 #include <wait_bit.h>
  19 #include <asm/io.h>
  20 #include <linux/bitops.h>
  21
  22 #include <dt-bindings/clock/renesas-cpg-mssr.h>
  23
  24 #include "renesas-cpg-mssr.h"
  25 #include "rcar-gen3-cpg.h"
  26
  27 #define CPG_RST_MODEMR          0x0060
  28
  29 #define CPG_PLL0CR              0x00d8
  30 #define CPG_PLL2CR              0x002c
  31 #define CPG_PLL4CR              0x01f4
  32
  33 #define CPG_RPC_PREDIV_MASK     0x3
  34 #define CPG_RPC_PREDIV_OFFSET   3
  35 #define CPG_RPC_POSTDIV_MASK    0x7
  36 #define CPG_RPC_POSTDIV_OFFSET  0
  37
  38 /*
  39  * SDn Clock
  40  */
  41 #define CPG_SD_STP_HCK          BIT(9)
  42 #define CPG_SD_STP_CK           BIT(8)
  43
  44 #define CPG_SD_STP_MASK         (CPG_SD_STP_HCK | CPG_SD_STP_CK)
  45 #define CPG_SD_FC_MASK          (0x7 << 2 | 0x3 << 0)
  46
  47 #define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
  48 { \
  49         .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
  50                ((stp_ck) ? CPG_SD_STP_CK : 0) | \
  51                ((sd_srcfc) << 2) | \
  52                ((sd_fc) << 0), \
  53         .div = (sd_div), \
  54 }
  55
  56 struct sd_div_table {
  57         u32 val;
  58         unsigned int div;
  59 };
  60
  61 /* SDn divider
  62  *                     sd_srcfc   sd_fc   div
  63  * stp_hck   stp_ck    (div)      (div)     = sd_srcfc x sd_fc
  64  *-------------------------------------------------------------------
  65  *  0         0         0 (1)      1 (4)      4
  66  *  0         0         1 (2)      1 (4)      8
  67  *  1         0         2 (4)      1 (4)     16
  68  *  1         0         3 (8)      1 (4)     32
  69  *  1         0         4 (16)     1 (4)     64
  70  *  0         0         0 (1)      0 (2)      2
  71  *  0         0         1 (2)      0 (2)      4
  72  *  1         0         2 (4)      0 (2)      8
  73  *  1         0         3 (8)      0 (2)     16
  74  *  1         0         4 (16)     0 (2)     32
  75  */
  76 static const struct sd_div_table cpg_sd_div_table[] = {
  77 /*      CPG_SD_DIV_TABLE_DATA(stp_hck,  stp_ck,   sd_srcfc,   sd_fc,  sd_div) */
  78         CPG_SD_DIV_TABLE_DATA(0,        0,        0,          1,        4),
  79         CPG_SD_DIV_TABLE_DATA(0,        0,        1,          1,        8),
  80         CPG_SD_DIV_TABLE_DATA(1,        0,        2,          1,       16),
  81         CPG_SD_DIV_TABLE_DATA(1,        0,        3,          1,       32),
  82         CPG_SD_DIV_TABLE_DATA(1,        0,        4,          1,       64),
  83         CPG_SD_DIV_TABLE_DATA(0,        0,        0,          0,        2),
  84         CPG_SD_DIV_TABLE_DATA(0,        0,        1,          0,        4),
  85         CPG_SD_DIV_TABLE_DATA(1,        0,        2,          0,        8),
  86         CPG_SD_DIV_TABLE_DATA(1,        0,        3,          0,       16),
  87         CPG_SD_DIV_TABLE_DATA(1,        0,        4,          0,       32),
  88 };
  89
  90 static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk,
  91                                struct cpg_mssr_info *info, struct clk *parent)
  92 {
  93         const struct cpg_core_clk *core;
  94         int ret;
  95
  96         if (!renesas_clk_is_mod(clk)) {
  97                 ret = renesas_clk_get_core(clk, info, &core);
  98                 if (ret)
  99                         return ret;
 100
 101                 if (core->type == CLK_TYPE_GEN3_MDSEL) {
 102                         parent->dev = clk->dev;
 103                         parent->id = core->parent >> (priv->sscg ? 16 : 0);
 104                         parent->id &= 0xffff;
 105                         return 0;
 106                 }
 107         }
 108
 109         return renesas_clk_get_parent(clk, info, parent);
 110 }
 111
 112 static int gen3_clk_setup_sdif_div(struct clk *clk, ulong rate)
 113 {
 114         struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
 115         struct cpg_mssr_info *info = priv->info;
 116         const struct cpg_core_clk *core;
 117         struct clk parent;
 118         int ret;
 119
 120         ret = gen3_clk_get_parent(priv, clk, info, &parent);
 121         if (ret) {
 122                 printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
 123                 return ret;
 124         }
 125
 126         if (renesas_clk_is_mod(&parent))
 127                 return 0;
 128
 129         ret = renesas_clk_get_core(&parent, info, &core);
 130         if (ret)
 131                 return ret;
 132
 133         if (core->type != CLK_TYPE_GEN3_SD)
 134                 return 0;
 135
 136         debug("%s[%i] SDIF offset=%x\n", __func__, __LINE__, core->offset);
 137
 138         writel((rate == 400000000) ? 0x4 : 0x1, priv->base + core->offset);
 139
 140         return 0;
 141 }
 142
 143 static int gen3_clk_enable(struct clk *clk)
 144 {
 145         struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
 146
 147         return renesas_clk_endisable(clk, priv->base, true);
 148 }
 149
 150 static int gen3_clk_disable(struct clk *clk)
 151 {
 152         struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
 153
 154         return renesas_clk_endisable(clk, priv->base, false);
 155 }
 156
 157 static u64 gen3_clk_get_rate64(struct clk *clk)
 158 {
 159         struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
 160         struct cpg_mssr_info *info = priv->info;
 161         struct clk parent;
 162         const struct cpg_core_clk *core;
 163         const struct rcar_gen3_cpg_pll_config *pll_config =
 164                                         priv->cpg_pll_config;
 165         u32 value, mult, div, prediv, postdiv;
 166         u64 rate = 0;
 167         int i, ret;
 168
 169         debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
 170
 171         ret = gen3_clk_get_parent(priv, clk, info, &parent);
 172         if (ret) {
 173                 printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
 174                 return ret;
 175         }
 176
 177         if (renesas_clk_is_mod(clk)) {
 178                 rate = gen3_clk_get_rate64(&parent);
 179                 debug("%s[%i] MOD clk: parent=%lu => rate=%llu\n",
 180                       __func__, __LINE__, parent.id, rate);
 181                 return rate;
 182         }
 183
 184         ret = renesas_clk_get_core(clk, info, &core);
 185         if (ret)
 186                 return ret;
 187
 188         switch (core->type) {
 189         case CLK_TYPE_IN:
 190                 if (core->id == info->clk_extal_id) {
 191                         rate = clk_get_rate(&priv->clk_extal);
 192                         debug("%s[%i] EXTAL clk: rate=%llu\n",
 193                               __func__, __LINE__, rate);
 194                         return rate;
 195                 }
 196
 197                 if (core->id == info->clk_extalr_id) {
 198                         rate = clk_get_rate(&priv->clk_extalr);
 199                         debug("%s[%i] EXTALR clk: rate=%llu\n",
 200                               __func__, __LINE__, rate);
 201                         return rate;
 202                 }
 203
 204                 return -EINVAL;
 205
 206         case CLK_TYPE_GEN3_MAIN:
 207                 rate = gen3_clk_get_rate64(&parent) / pll_config->extal_div;
 208                 debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%llu\n",
 209                       __func__, __LINE__,
 210                       core->parent, pll_config->extal_div, rate);
 211                 return rate;
 212
 213         case CLK_TYPE_GEN3_PLL0:
 214                 value = readl(priv->base + CPG_PLL0CR);
 215                 mult = (((value >> 24) & 0x7f) + 1) * 2;
 216                 rate = gen3_clk_get_rate64(&parent) * mult;
 217                 debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%llu\n",
 218                       __func__, __LINE__, core->parent, mult, rate);
 219                 return rate;
 220
 221         case CLK_TYPE_GEN3_PLL1:
 222                 rate = gen3_clk_get_rate64(&parent) * pll_config->pll1_mult;
 223                 rate /= pll_config->pll1_div;
 224                 debug("%s[%i] PLL1 clk: parent=%i mul=%i div=%i => rate=%llu\n",
 225                       __func__, __LINE__,
 226                       core->parent, pll_config->pll1_mult,
 227                       pll_config->pll1_div, rate);
 228                 return rate;
 229
 230         case CLK_TYPE_GEN3_PLL2:
 231                 value = readl(priv->base + CPG_PLL2CR);
 232                 mult = (((value >> 24) & 0x7f) + 1) * 2;
 233                 rate = gen3_clk_get_rate64(&parent) * mult;
 234                 debug("%s[%i] PLL2 clk: parent=%i mult=%u => rate=%llu\n",
 235                       __func__, __LINE__, core->parent, mult, rate);
 236                 return rate;
 237
 238         case CLK_TYPE_GEN3_PLL3:
 239                 rate = gen3_clk_get_rate64(&parent) * pll_config->pll3_mult;
 240                 rate /= pll_config->pll3_div;
 241                 debug("%s[%i] PLL3 clk: parent=%i mul=%i div=%i => rate=%llu\n",
 242                       __func__, __LINE__,
 243                       core->parent, pll_config->pll3_mult,
 244                       pll_config->pll3_div, rate);
 245                 return rate;
 246
 247         case CLK_TYPE_GEN3_PLL4:
 248                 value = readl(priv->base + CPG_PLL4CR);
 249                 mult = (((value >> 24) & 0x7f) + 1) * 2;
 250                 rate = gen3_clk_get_rate64(&parent) * mult;
 251                 debug("%s[%i] PLL4 clk: parent=%i mult=%u => rate=%llu\n",
 252                       __func__, __LINE__, core->parent, mult, rate);
 253                 return rate;
 254
 255         case CLK_TYPE_FF:
 256                 rate = (gen3_clk_get_rate64(&parent) * core->mult) / core->div;
 257                 debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i => rate=%llu\n",
 258                       __func__, __LINE__,
 259                       core->parent, core->mult, core->div, rate);
 260                 return rate;
 261
 262         case CLK_TYPE_GEN3_MDSEL:
 263                 div = (core->div >> (priv->sscg ? 16 : 0)) & 0xffff;
 264                 rate = gen3_clk_get_rate64(&parent) / div;
 265                 debug("%s[%i] PE clk: parent=%i div=%u => rate=%llu\n",
 266                       __func__, __LINE__,
 267                       (core->parent >> (priv->sscg ? 16 : 0)) & 0xffff,
 268                       div, rate);
 269                 return rate;
 270
 271         case CLK_TYPE_GEN3_SD:          /* FIXME */
 272                 value = readl(priv->base + core->offset);
 273                 value &= CPG_SD_STP_MASK | CPG_SD_FC_MASK;
 274
 275                 for (i = 0; i < ARRAY_SIZE(cpg_sd_div_table); i++) {
 276                         if (cpg_sd_div_table[i].val != value)
 277                                 continue;
 278
 279                         rate = gen3_clk_get_rate64(&parent) /
 280                                cpg_sd_div_table[i].div;
 281                         debug("%s[%i] SD clk: parent=%i div=%i => rate=%llu\n",
 282                               __func__, __LINE__,
 283                               core->parent, cpg_sd_div_table[i].div, rate);
 284
 285                         return rate;
 286                 }
 287
 288                 return -EINVAL;
 289
 290         case CLK_TYPE_GEN3_RPC:
 291                 rate = gen3_clk_get_rate64(&parent);
 292
 293                 value = readl(priv->base + core->offset);
 294
 295                 prediv = (value >> CPG_RPC_PREDIV_OFFSET) &
 296                          CPG_RPC_PREDIV_MASK;
 297                 if (prediv == 2)
 298                         rate /= 5;
 299                 else if (prediv == 3)
 300                         rate /= 6;
 301                 else
 302                         return -EINVAL;
 303
 304                 postdiv = (value >> CPG_RPC_POSTDIV_OFFSET) &
 305                           CPG_RPC_POSTDIV_MASK;
 306                 rate /= postdiv + 1;
 307
 308                 debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%llu\n",
 309                       __func__, __LINE__,
 310                       core->parent, prediv, postdiv, rate);
 311
 312                 return -EINVAL;
 313
 314         }
 315
 316         printf("%s[%i] unknown fail\n", __func__, __LINE__);
 317
 318         return -ENOENT;
 319 }
 320
 321 static ulong gen3_clk_get_rate(struct clk *clk)
 322 {
 323         return gen3_clk_get_rate64(clk);
 324 }
 325
 326 static ulong gen3_clk_set_rate(struct clk *clk, ulong rate)
 327 {
 328         /* Force correct SD-IF divider configuration if applicable */
 329         gen3_clk_setup_sdif_div(clk, rate);
 330         return gen3_clk_get_rate64(clk);
 331 }
 332
 333 static int gen3_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
 334 {
 335         if (args->args_count != 2) {
 336                 debug("Invaild args_count: %d\n", args->args_count);
 337                 return -EINVAL;
 338         }
 339
 340         clk->id = (args->args[0] << 16) | args->args[1];
 341
 342         return 0;
 343 }
 344
 345 const struct clk_ops gen3_clk_ops = {
 346         .enable         = gen3_clk_enable,
 347         .disable        = gen3_clk_disable,
 348         .get_rate       = gen3_clk_get_rate,
 349         .set_rate       = gen3_clk_set_rate,
 350         .of_xlate       = gen3_clk_of_xlate,
 351 };
 352
 353 int gen3_clk_probe(struct udevice *dev)
 354 {
 355         struct gen3_clk_priv *priv = dev_get_priv(dev);
 356         struct cpg_mssr_info *info =
 357                 (struct cpg_mssr_info *)dev_get_driver_data(dev);
 358         fdt_addr_t rst_base;
 359         u32 cpg_mode;
 360         int ret;
 361
 362         priv->base = dev_read_addr_ptr(dev);
 363         if (!priv->base)
 364                 return -EINVAL;
 365
 366         priv->info = info;
 367         ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, info->reset_node);
 368         if (ret < 0)
 369                 return ret;
 370
 371         rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg");
 372         if (rst_base == FDT_ADDR_T_NONE)
 373                 return -EINVAL;
 374
 375         cpg_mode = readl(rst_base + CPG_RST_MODEMR);
 376
 377         priv->cpg_pll_config =
 378                 (struct rcar_gen3_cpg_pll_config *)info->get_pll_config(cpg_mode);
 379         if (!priv->cpg_pll_config->extal_div)
 380                 return -EINVAL;
 381
 382         priv->sscg = !(cpg_mode & BIT(12));
 383
 384         ret = clk_get_by_name(dev, "extal", &priv->clk_extal);
 385         if (ret < 0)
 386                 return ret;
 387
 388         if (info->extalr_node) {
 389                 ret = clk_get_by_name(dev, info->extalr_node, &priv->clk_extalr);
 390                 if (ret < 0)
 391                         return ret;
 392         }
 393
 394         return 0;
 395 }
 396
 397 int gen3_clk_remove(struct udevice *dev)
 398 {
 399         struct gen3_clk_priv *priv = dev_get_priv(dev);
 400
 401         return renesas_clk_remove(priv->base, priv->info);
 402 }