drivers/clk/qcom/mmcc-msm8960.c

   1 /*
   2  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/bitops.h>
  16 #include <linux/err.h>
  17 #include <linux/delay.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/of_device.h>
  22 #include <linux/clk-provider.h>
  23 #include <linux/regmap.h>
  24 #include <linux/reset-controller.h>
  25
  26 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
  27 #include <dt-bindings/reset/qcom,mmcc-msm8960.h>
  28
  29 #include "clk-regmap.h"
  30 #include "clk-pll.h"
  31 #include "clk-rcg.h"
  32 #include "clk-branch.h"
  33 #include "reset.h"
  34
  35 #define P_PXO   0
  36 #define P_PLL8  1
  37 #define P_PLL2  2
  38 #define P_PLL3  3
  39
  40 #define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n }
  41
  42 static u8 mmcc_pxo_pll8_pll2_map[] = {
  43         [P_PXO]         = 0,
  44         [P_PLL8]        = 2,
  45         [P_PLL2]        = 1,
  46 };
  47
  48 static const char *mmcc_pxo_pll8_pll2[] = {
  49         "pxo",
  50         "pll8_vote",
  51         "pll2",
  52 };
  53
  54 static u8 mmcc_pxo_pll8_pll2_pll3_map[] = {
  55         [P_PXO]         = 0,
  56         [P_PLL8]        = 2,
  57         [P_PLL2]        = 1,
  58         [P_PLL3]        = 3,
  59 };
  60
  61 static const char *mmcc_pxo_pll8_pll2_pll3[] = {
  62         "pxo",
  63         "pll8_vote",
  64         "pll2",
  65         "pll3",
  66 };
  67
  68 static struct clk_pll pll2 = {
  69         .l_reg = 0x320,
  70         .m_reg = 0x324,
  71         .n_reg = 0x328,
  72         .config_reg = 0x32c,
  73         .mode_reg = 0x31c,
  74         .status_reg = 0x334,
  75         .status_bit = 16,
  76         .clkr.hw.init = &(struct clk_init_data){
  77                 .name = "pll2",
  78                 .parent_names = (const char *[]){ "pxo" },
  79                 .num_parents = 1,
  80                 .ops = &clk_pll_ops,
  81         },
  82 };
  83
  84 static struct freq_tbl clk_tbl_cam[] = {
  85         {   6000000, P_PLL8, 4, 1, 16 },
  86         {   8000000, P_PLL8, 4, 1, 12 },
  87         {  12000000, P_PLL8, 4, 1,  8 },
  88         {  16000000, P_PLL8, 4, 1,  6 },
  89         {  19200000, P_PLL8, 4, 1,  5 },
  90         {  24000000, P_PLL8, 4, 1,  4 },
  91         {  32000000, P_PLL8, 4, 1,  3 },
  92         {  48000000, P_PLL8, 4, 1,  2 },
  93         {  64000000, P_PLL8, 3, 1,  2 },
  94         {  96000000, P_PLL8, 4, 0,  0 },
  95         { 128000000, P_PLL8, 3, 0,  0 },
  96         { }
  97 };
  98
  99 static struct clk_rcg camclk0_src = {
 100         .ns_reg = 0x0148,
 101         .md_reg = 0x0144,
 102         .mn = {
 103                 .mnctr_en_bit = 5,
 104                 .mnctr_reset_bit = 8,
 105                 .reset_in_cc = true,
 106                 .mnctr_mode_shift = 6,
 107                 .n_val_shift = 24,
 108                 .m_val_shift = 8,
 109                 .width = 8,
 110         },
 111         .p = {
 112                 .pre_div_shift = 14,
 113                 .pre_div_width = 2,
 114         },
 115         .s = {
 116                 .src_sel_shift = 0,
 117                 .parent_map = mmcc_pxo_pll8_pll2_map,
 118         },
 119         .freq_tbl = clk_tbl_cam,
 120         .clkr = {
 121                 .enable_reg = 0x0140,
 122                 .enable_mask = BIT(2),
 123                 .hw.init = &(struct clk_init_data){
 124                         .name = "camclk0_src",
 125                         .parent_names = mmcc_pxo_pll8_pll2,
 126                         .num_parents = 3,
 127                         .ops = &clk_rcg_ops,
 128                 },
 129         },
 130 };
 131
 132 static struct clk_branch camclk0_clk = {
 133         .halt_reg = 0x01e8,
 134         .halt_bit = 15,
 135         .clkr = {
 136                 .enable_reg = 0x0140,
 137                 .enable_mask = BIT(0),
 138                 .hw.init = &(struct clk_init_data){
 139                         .name = "camclk0_clk",
 140                         .parent_names = (const char *[]){ "camclk0_src" },
 141                         .num_parents = 1,
 142                         .ops = &clk_branch_ops,
 143                 },
 144         },
 145
 146 };
 147
 148 static struct clk_rcg camclk1_src = {
 149         .ns_reg = 0x015c,
 150         .md_reg = 0x0158,
 151         .mn = {
 152                 .mnctr_en_bit = 5,
 153                 .mnctr_reset_bit = 8,
 154                 .reset_in_cc = true,
 155                 .mnctr_mode_shift = 6,
 156                 .n_val_shift = 24,
 157                 .m_val_shift = 8,
 158                 .width = 8,
 159         },
 160         .p = {
 161                 .pre_div_shift = 14,
 162                 .pre_div_width = 2,
 163         },
 164         .s = {
 165                 .src_sel_shift = 0,
 166                 .parent_map = mmcc_pxo_pll8_pll2_map,
 167         },
 168         .freq_tbl = clk_tbl_cam,
 169         .clkr = {
 170                 .enable_reg = 0x0154,
 171                 .enable_mask = BIT(2),
 172                 .hw.init = &(struct clk_init_data){
 173                         .name = "camclk1_src",
 174                         .parent_names = mmcc_pxo_pll8_pll2,
 175                         .num_parents = 3,
 176                         .ops = &clk_rcg_ops,
 177                 },
 178         },
 179 };
 180
 181 static struct clk_branch camclk1_clk = {
 182         .halt_reg = 0x01e8,
 183         .halt_bit = 16,
 184         .clkr = {
 185                 .enable_reg = 0x0154,
 186                 .enable_mask = BIT(0),
 187                 .hw.init = &(struct clk_init_data){
 188                         .name = "camclk1_clk",
 189                         .parent_names = (const char *[]){ "camclk1_src" },
 190                         .num_parents = 1,
 191                         .ops = &clk_branch_ops,
 192                 },
 193         },
 194
 195 };
 196
 197 static struct clk_rcg camclk2_src = {
 198         .ns_reg = 0x0228,
 199         .md_reg = 0x0224,
 200         .mn = {
 201                 .mnctr_en_bit = 5,
 202                 .mnctr_reset_bit = 8,
 203                 .reset_in_cc = true,
 204                 .mnctr_mode_shift = 6,
 205                 .n_val_shift = 24,
 206                 .m_val_shift = 8,
 207                 .width = 8,
 208         },
 209         .p = {
 210                 .pre_div_shift = 14,
 211                 .pre_div_width = 2,
 212         },
 213         .s = {
 214                 .src_sel_shift = 0,
 215                 .parent_map = mmcc_pxo_pll8_pll2_map,
 216         },
 217         .freq_tbl = clk_tbl_cam,
 218         .clkr = {
 219                 .enable_reg = 0x0220,
 220                 .enable_mask = BIT(2),
 221                 .hw.init = &(struct clk_init_data){
 222                         .name = "camclk2_src",
 223                         .parent_names = mmcc_pxo_pll8_pll2,
 224                         .num_parents = 3,
 225                         .ops = &clk_rcg_ops,
 226                 },
 227         },
 228 };
 229
 230 static struct clk_branch camclk2_clk = {
 231         .halt_reg = 0x01e8,
 232         .halt_bit = 16,
 233         .clkr = {
 234                 .enable_reg = 0x0220,
 235                 .enable_mask = BIT(0),
 236                 .hw.init = &(struct clk_init_data){
 237                         .name = "camclk2_clk",
 238                         .parent_names = (const char *[]){ "camclk2_src" },
 239                         .num_parents = 1,
 240                         .ops = &clk_branch_ops,
 241                 },
 242         },
 243
 244 };
 245
 246 static struct freq_tbl clk_tbl_csi[] = {
 247         {  27000000, P_PXO,  1, 0, 0 },
 248         {  85330000, P_PLL8, 1, 2, 9 },
 249         { 177780000, P_PLL2, 1, 2, 9 },
 250         { }
 251 };
 252
 253 static struct clk_rcg csi0_src = {
 254         .ns_reg = 0x0048,
 255         .md_reg = 0x0044,
 256         .mn = {
 257                 .mnctr_en_bit = 5,
 258                 .mnctr_reset_bit = 7,
 259                 .mnctr_mode_shift = 6,
 260                 .n_val_shift = 24,
 261                 .m_val_shift = 8,
 262                 .width = 8,
 263         },
 264         .p = {
 265                 .pre_div_shift = 14,
 266                 .pre_div_width = 2,
 267         },
 268         .s = {
 269                 .src_sel_shift = 0,
 270                 .parent_map = mmcc_pxo_pll8_pll2_map,
 271         },
 272         .freq_tbl = clk_tbl_csi,
 273         .clkr = {
 274                 .enable_reg = 0x0040,
 275                 .enable_mask = BIT(2),
 276                 .hw.init = &(struct clk_init_data){
 277                         .name = "csi0_src",
 278                         .parent_names = mmcc_pxo_pll8_pll2,
 279                         .num_parents = 3,
 280                         .ops = &clk_rcg_ops,
 281                 },
 282         },
 283 };
 284
 285 static struct clk_branch csi0_clk = {
 286         .halt_reg = 0x01cc,
 287         .halt_bit = 13,
 288         .clkr = {
 289                 .enable_reg = 0x0040,
 290                 .enable_mask = BIT(0),
 291                 .hw.init = &(struct clk_init_data){
 292                         .parent_names = (const char *[]){ "csi0_src" },
 293                         .num_parents = 1,
 294                         .name = "csi0_clk",
 295                         .ops = &clk_branch_ops,
 296                         .flags = CLK_SET_RATE_PARENT,
 297                 },
 298         },
 299 };
 300
 301 static struct clk_branch csi0_phy_clk = {
 302         .halt_reg = 0x01e8,
 303         .halt_bit = 9,
 304         .clkr = {
 305                 .enable_reg = 0x0040,
 306                 .enable_mask = BIT(8),
 307                 .hw.init = &(struct clk_init_data){
 308                         .parent_names = (const char *[]){ "csi0_src" },
 309                         .num_parents = 1,
 310                         .name = "csi0_phy_clk",
 311                         .ops = &clk_branch_ops,
 312                         .flags = CLK_SET_RATE_PARENT,
 313                 },
 314         },
 315 };
 316
 317 static struct clk_rcg csi1_src = {
 318         .ns_reg = 0x0010,
 319         .md_reg = 0x0028,
 320         .mn = {
 321                 .mnctr_en_bit = 5,
 322                 .mnctr_reset_bit = 7,
 323                 .mnctr_mode_shift = 6,
 324                 .n_val_shift = 24,
 325                 .m_val_shift = 8,
 326                 .width = 8,
 327         },
 328         .p = {
 329                 .pre_div_shift = 14,
 330                 .pre_div_width = 2,
 331         },
 332         .s = {
 333                 .src_sel_shift = 0,
 334                 .parent_map = mmcc_pxo_pll8_pll2_map,
 335         },
 336         .freq_tbl = clk_tbl_csi,
 337         .clkr = {
 338                 .enable_reg = 0x0024,
 339                 .enable_mask = BIT(2),
 340                 .hw.init = &(struct clk_init_data){
 341                         .name = "csi1_src",
 342                         .parent_names = mmcc_pxo_pll8_pll2,
 343                         .num_parents = 3,
 344                         .ops = &clk_rcg_ops,
 345                 },
 346         },
 347 };
 348
 349 static struct clk_branch csi1_clk = {
 350         .halt_reg = 0x01cc,
 351         .halt_bit = 14,
 352         .clkr = {
 353                 .enable_reg = 0x0024,
 354                 .enable_mask = BIT(0),
 355                 .hw.init = &(struct clk_init_data){
 356                         .parent_names = (const char *[]){ "csi1_src" },
 357                         .num_parents = 1,
 358                         .name = "csi1_clk",
 359                         .ops = &clk_branch_ops,
 360                         .flags = CLK_SET_RATE_PARENT,
 361                 },
 362         },
 363 };
 364
 365 static struct clk_branch csi1_phy_clk = {
 366         .halt_reg = 0x01e8,
 367         .halt_bit = 10,
 368         .clkr = {
 369                 .enable_reg = 0x0024,
 370                 .enable_mask = BIT(8),
 371                 .hw.init = &(struct clk_init_data){
 372                         .parent_names = (const char *[]){ "csi1_src" },
 373                         .num_parents = 1,
 374                         .name = "csi1_phy_clk",
 375                         .ops = &clk_branch_ops,
 376                         .flags = CLK_SET_RATE_PARENT,
 377                 },
 378         },
 379 };
 380
 381 static struct clk_rcg csi2_src = {
 382         .ns_reg = 0x0234,
 383         .md_reg = 0x022c,
 384         .mn = {
 385                 .mnctr_en_bit = 5,
 386                 .mnctr_reset_bit = 7,
 387                 .mnctr_mode_shift = 6,
 388                 .n_val_shift = 24,
 389                 .m_val_shift = 8,
 390                 .width = 8,
 391         },
 392         .p = {
 393                 .pre_div_shift = 14,
 394                 .pre_div_width = 2,
 395         },
 396         .s = {
 397                 .src_sel_shift = 0,
 398                 .parent_map = mmcc_pxo_pll8_pll2_map,
 399         },
 400         .freq_tbl = clk_tbl_csi,
 401         .clkr = {
 402                 .enable_reg = 0x022c,
 403                 .enable_mask = BIT(2),
 404                 .hw.init = &(struct clk_init_data){
 405                         .name = "csi2_src",
 406                         .parent_names = mmcc_pxo_pll8_pll2,
 407                         .num_parents = 3,
 408                         .ops = &clk_rcg_ops,
 409                 },
 410         },
 411 };
 412
 413 static struct clk_branch csi2_clk = {
 414         .halt_reg = 0x01cc,
 415         .halt_bit = 29,
 416         .clkr = {
 417                 .enable_reg = 0x022c,
 418                 .enable_mask = BIT(0),
 419                 .hw.init = &(struct clk_init_data){
 420                         .parent_names = (const char *[]){ "csi2_src" },
 421                         .num_parents = 1,
 422                         .name = "csi2_clk",
 423                         .ops = &clk_branch_ops,
 424                         .flags = CLK_SET_RATE_PARENT,
 425                 },
 426         },
 427 };
 428
 429 static struct clk_branch csi2_phy_clk = {
 430         .halt_reg = 0x01e8,
 431         .halt_bit = 29,
 432         .clkr = {
 433                 .enable_reg = 0x022c,
 434                 .enable_mask = BIT(8),
 435                 .hw.init = &(struct clk_init_data){
 436                         .parent_names = (const char *[]){ "csi2_src" },
 437                         .num_parents = 1,
 438                         .name = "csi2_phy_clk",
 439                         .ops = &clk_branch_ops,
 440                         .flags = CLK_SET_RATE_PARENT,
 441                 },
 442         },
 443 };
 444
 445 struct clk_pix_rdi {
 446         u32 s_reg;
 447         u32 s_mask;
 448         u32 s2_reg;
 449         u32 s2_mask;
 450         struct clk_regmap clkr;
 451 };
 452
 453 #define to_clk_pix_rdi(_hw) \
 454         container_of(to_clk_regmap(_hw), struct clk_pix_rdi, clkr)
 455
 456 static int pix_rdi_set_parent(struct clk_hw *hw, u8 index)
 457 {
 458         int i;
 459         int ret = 0;
 460         u32 val;
 461         struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
 462         struct clk *clk = hw->clk;
 463         int num_parents = __clk_get_num_parents(hw->clk);
 464
 465         /*
 466          * These clocks select three inputs via two muxes. One mux selects
 467          * between csi0 and csi1 and the second mux selects between that mux's
 468          * output and csi2. The source and destination selections for each
 469          * mux must be clocking for the switch to succeed so just turn on
 470          * all three sources because it's easier than figuring out what source
 471          * needs to be on at what time.
 472          */
 473         for (i = 0; i < num_parents; i++) {
 474                 ret = clk_prepare_enable(clk_get_parent_by_index(clk, i));
 475                 if (ret)
 476                         goto err;
 477         }
 478
 479         if (index == 2)
 480                 val = rdi->s2_mask;
 481         else
 482                 val = 0;
 483         regmap_update_bits(rdi->clkr.regmap, rdi->s2_reg, rdi->s2_mask, val);
 484         /*
 485          * Wait at least 6 cycles of slowest clock
 486          * for the glitch-free MUX to fully switch sources.
 487          */
 488         udelay(1);
 489
 490         if (index == 1)
 491                 val = rdi->s_mask;
 492         else
 493                 val = 0;
 494         regmap_update_bits(rdi->clkr.regmap, rdi->s_reg, rdi->s_mask, val);
 495         /*
 496          * Wait at least 6 cycles of slowest clock
 497          * for the glitch-free MUX to fully switch sources.
 498          */
 499         udelay(1);
 500
 501 err:
 502         for (i--; i >= 0; i--)
 503                 clk_disable_unprepare(clk_get_parent_by_index(clk, i));
 504
 505         return ret;
 506 }
 507
 508 static u8 pix_rdi_get_parent(struct clk_hw *hw)
 509 {
 510         u32 val;
 511         struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
 512
 513
 514         regmap_read(rdi->clkr.regmap, rdi->s2_reg, &val);
 515         if (val & rdi->s2_mask)
 516                 return 2;
 517
 518         regmap_read(rdi->clkr.regmap, rdi->s_reg, &val);
 519         if (val & rdi->s_mask)
 520                 return 1;
 521
 522         return 0;
 523 }
 524
 525 static const struct clk_ops clk_ops_pix_rdi = {
 526         .enable = clk_enable_regmap,
 527         .disable = clk_disable_regmap,
 528         .set_parent = pix_rdi_set_parent,
 529         .get_parent = pix_rdi_get_parent,
 530         .determine_rate = __clk_mux_determine_rate,
 531 };
 532
 533 static const char *pix_rdi_parents[] = {
 534         "csi0_clk",
 535         "csi1_clk",
 536         "csi2_clk",
 537 };
 538
 539 static struct clk_pix_rdi csi_pix_clk = {
 540         .s_reg = 0x0058,
 541         .s_mask = BIT(25),
 542         .s2_reg = 0x0238,
 543         .s2_mask = BIT(13),
 544         .clkr = {
 545                 .enable_reg = 0x0058,
 546                 .enable_mask = BIT(26),
 547                 .hw.init = &(struct clk_init_data){
 548                         .name = "csi_pix_clk",
 549                         .parent_names = pix_rdi_parents,
 550                         .num_parents = 3,
 551                         .ops = &clk_ops_pix_rdi,
 552                 },
 553         },
 554 };
 555
 556 static struct clk_pix_rdi csi_pix1_clk = {
 557         .s_reg = 0x0238,
 558         .s_mask = BIT(8),
 559         .s2_reg = 0x0238,
 560         .s2_mask = BIT(9),
 561         .clkr = {
 562                 .enable_reg = 0x0238,
 563                 .enable_mask = BIT(10),
 564                 .hw.init = &(struct clk_init_data){
 565                         .name = "csi_pix1_clk",
 566                         .parent_names = pix_rdi_parents,
 567                         .num_parents = 3,
 568                         .ops = &clk_ops_pix_rdi,
 569                 },
 570         },
 571 };
 572
 573 static struct clk_pix_rdi csi_rdi_clk = {
 574         .s_reg = 0x0058,
 575         .s_mask = BIT(12),
 576         .s2_reg = 0x0238,
 577         .s2_mask = BIT(12),
 578         .clkr = {
 579                 .enable_reg = 0x0058,
 580                 .enable_mask = BIT(13),
 581                 .hw.init = &(struct clk_init_data){
 582                         .name = "csi_rdi_clk",
 583                         .parent_names = pix_rdi_parents,
 584                         .num_parents = 3,
 585                         .ops = &clk_ops_pix_rdi,
 586                 },
 587         },
 588 };
 589
 590 static struct clk_pix_rdi csi_rdi1_clk = {
 591         .s_reg = 0x0238,
 592         .s_mask = BIT(0),
 593         .s2_reg = 0x0238,
 594         .s2_mask = BIT(1),
 595         .clkr = {
 596                 .enable_reg = 0x0238,
 597                 .enable_mask = BIT(2),
 598                 .hw.init = &(struct clk_init_data){
 599                         .name = "csi_rdi1_clk",
 600                         .parent_names = pix_rdi_parents,
 601                         .num_parents = 3,
 602                         .ops = &clk_ops_pix_rdi,
 603                 },
 604         },
 605 };
 606
 607 static struct clk_pix_rdi csi_rdi2_clk = {
 608         .s_reg = 0x0238,
 609         .s_mask = BIT(4),
 610         .s2_reg = 0x0238,
 611         .s2_mask = BIT(5),
 612         .clkr = {
 613                 .enable_reg = 0x0238,
 614                 .enable_mask = BIT(6),
 615                 .hw.init = &(struct clk_init_data){
 616                         .name = "csi_rdi2_clk",
 617                         .parent_names = pix_rdi_parents,
 618                         .num_parents = 3,
 619                         .ops = &clk_ops_pix_rdi,
 620                 },
 621         },
 622 };
 623
 624 static struct freq_tbl clk_tbl_csiphytimer[] = {
 625         {  85330000, P_PLL8, 1, 2, 9 },
 626         { 177780000, P_PLL2, 1, 2, 9 },
 627         { }
 628 };
 629
 630 static struct clk_rcg csiphytimer_src = {
 631         .ns_reg = 0x0168,
 632         .md_reg = 0x0164,
 633         .mn = {
 634                 .mnctr_en_bit = 5,
 635                 .mnctr_reset_bit = 8,
 636                 .reset_in_cc = true,
 637                 .mnctr_mode_shift = 6,
 638                 .n_val_shift = 24,
 639                 .m_val_shift = 8,
 640                 .width = 8,
 641         },
 642         .p = {
 643                 .pre_div_shift = 14,
 644                 .pre_div_width = 2,
 645         },
 646         .s = {
 647                 .src_sel_shift = 0,
 648                 .parent_map = mmcc_pxo_pll8_pll2_map,
 649         },
 650         .freq_tbl = clk_tbl_csiphytimer,
 651         .clkr = {
 652                 .enable_reg = 0x0160,
 653                 .enable_mask = BIT(2),
 654                 .hw.init = &(struct clk_init_data){
 655                         .name = "csiphytimer_src",
 656                         .parent_names = mmcc_pxo_pll8_pll2,
 657                         .num_parents = 3,
 658                         .ops = &clk_rcg_ops,
 659                 },
 660         },
 661 };
 662
 663 static const char *csixphy_timer_src[] = { "csiphytimer_src" };
 664
 665 static struct clk_branch csiphy0_timer_clk = {
 666         .halt_reg = 0x01e8,
 667         .halt_bit = 17,
 668         .clkr = {
 669                 .enable_reg = 0x0160,
 670                 .enable_mask = BIT(0),
 671                 .hw.init = &(struct clk_init_data){
 672                         .parent_names = csixphy_timer_src,
 673                         .num_parents = 1,
 674                         .name = "csiphy0_timer_clk",
 675                         .ops = &clk_branch_ops,
 676                         .flags = CLK_SET_RATE_PARENT,
 677                 },
 678         },
 679 };
 680
 681 static struct clk_branch csiphy1_timer_clk = {
 682         .halt_reg = 0x01e8,
 683         .halt_bit = 18,
 684         .clkr = {
 685                 .enable_reg = 0x0160,
 686                 .enable_mask = BIT(9),
 687                 .hw.init = &(struct clk_init_data){
 688                         .parent_names = csixphy_timer_src,
 689                         .num_parents = 1,
 690                         .name = "csiphy1_timer_clk",
 691                         .ops = &clk_branch_ops,
 692                         .flags = CLK_SET_RATE_PARENT,
 693                 },
 694         },
 695 };
 696
 697 static struct clk_branch csiphy2_timer_clk = {
 698         .halt_reg = 0x01e8,
 699         .halt_bit = 30,
 700         .clkr = {
 701                 .enable_reg = 0x0160,
 702                 .enable_mask = BIT(11),
 703                 .hw.init = &(struct clk_init_data){
 704                         .parent_names = csixphy_timer_src,
 705                         .num_parents = 1,
 706                         .name = "csiphy2_timer_clk",
 707                         .ops = &clk_branch_ops,
 708                         .flags = CLK_SET_RATE_PARENT,
 709                 },
 710         },
 711 };
 712
 713 static struct freq_tbl clk_tbl_gfx2d[] = {
 714         F_MN( 27000000, P_PXO,  1,  0),
 715         F_MN( 48000000, P_PLL8, 1,  8),
 716         F_MN( 54857000, P_PLL8, 1,  7),
 717         F_MN( 64000000, P_PLL8, 1,  6),
 718         F_MN( 76800000, P_PLL8, 1,  5),
 719         F_MN( 96000000, P_PLL8, 1,  4),
 720         F_MN(128000000, P_PLL8, 1,  3),
 721         F_MN(145455000, P_PLL2, 2, 11),
 722         F_MN(160000000, P_PLL2, 1,  5),
 723         F_MN(177778000, P_PLL2, 2,  9),
 724         F_MN(200000000, P_PLL2, 1,  4),
 725         F_MN(228571000, P_PLL2, 2,  7),
 726         { }
 727 };
 728
 729 static struct clk_dyn_rcg gfx2d0_src = {
 730         .ns_reg = 0x0070,
 731         .md_reg[0] = 0x0064,
 732         .md_reg[1] = 0x0068,
 733         .mn[0] = {
 734                 .mnctr_en_bit = 8,
 735                 .mnctr_reset_bit = 25,
 736                 .mnctr_mode_shift = 9,
 737                 .n_val_shift = 20,
 738                 .m_val_shift = 4,
 739                 .width = 4,
 740         },
 741         .mn[1] = {
 742                 .mnctr_en_bit = 5,
 743                 .mnctr_reset_bit = 24,
 744                 .mnctr_mode_shift = 6,
 745                 .n_val_shift = 16,
 746                 .m_val_shift = 4,
 747                 .width = 4,
 748         },
 749         .s[0] = {
 750                 .src_sel_shift = 3,
 751                 .parent_map = mmcc_pxo_pll8_pll2_map,
 752         },
 753         .s[1] = {
 754                 .src_sel_shift = 0,
 755                 .parent_map = mmcc_pxo_pll8_pll2_map,
 756         },
 757         .mux_sel_bit = 11,
 758         .freq_tbl = clk_tbl_gfx2d,
 759         .clkr = {
 760                 .enable_reg = 0x0060,
 761                 .enable_mask = BIT(2),
 762                 .hw.init = &(struct clk_init_data){
 763                         .name = "gfx2d0_src",
 764                         .parent_names = mmcc_pxo_pll8_pll2,
 765                         .num_parents = 3,
 766                         .ops = &clk_dyn_rcg_ops,
 767                 },
 768         },
 769 };
 770
 771 static struct clk_branch gfx2d0_clk = {
 772         .halt_reg = 0x01c8,
 773         .halt_bit = 9,
 774         .clkr = {
 775                 .enable_reg = 0x0060,
 776                 .enable_mask = BIT(0),
 777                 .hw.init = &(struct clk_init_data){
 778                         .name = "gfx2d0_clk",
 779                         .parent_names = (const char *[]){ "gfx2d0_src" },
 780                         .num_parents = 1,
 781                         .ops = &clk_branch_ops,
 782                         .flags = CLK_SET_RATE_PARENT,
 783                 },
 784         },
 785 };
 786
 787 static struct clk_dyn_rcg gfx2d1_src = {
 788         .ns_reg = 0x007c,
 789         .md_reg[0] = 0x0078,
 790         .md_reg[1] = 0x006c,
 791         .mn[0] = {
 792                 .mnctr_en_bit = 8,
 793                 .mnctr_reset_bit = 25,
 794                 .mnctr_mode_shift = 9,
 795                 .n_val_shift = 20,
 796                 .m_val_shift = 4,
 797                 .width = 4,
 798         },
 799         .mn[1] = {
 800                 .mnctr_en_bit = 5,
 801                 .mnctr_reset_bit = 24,
 802                 .mnctr_mode_shift = 6,
 803                 .n_val_shift = 16,
 804                 .m_val_shift = 4,
 805                 .width = 4,
 806         },
 807         .s[0] = {
 808                 .src_sel_shift = 3,
 809                 .parent_map = mmcc_pxo_pll8_pll2_map,
 810         },
 811         .s[1] = {
 812                 .src_sel_shift = 0,
 813                 .parent_map = mmcc_pxo_pll8_pll2_map,
 814         },
 815         .mux_sel_bit = 11,
 816         .freq_tbl = clk_tbl_gfx2d,
 817         .clkr = {
 818                 .enable_reg = 0x0074,
 819                 .enable_mask = BIT(2),
 820                 .hw.init = &(struct clk_init_data){
 821                         .name = "gfx2d1_src",
 822                         .parent_names = mmcc_pxo_pll8_pll2,
 823                         .num_parents = 3,
 824                         .ops = &clk_dyn_rcg_ops,
 825                 },
 826         },
 827 };
 828
 829 static struct clk_branch gfx2d1_clk = {
 830         .halt_reg = 0x01c8,
 831         .halt_bit = 14,
 832         .clkr = {
 833                 .enable_reg = 0x0074,
 834                 .enable_mask = BIT(0),
 835                 .hw.init = &(struct clk_init_data){
 836                         .name = "gfx2d1_clk",
 837                         .parent_names = (const char *[]){ "gfx2d1_src" },
 838                         .num_parents = 1,
 839                         .ops = &clk_branch_ops,
 840                         .flags = CLK_SET_RATE_PARENT,
 841                 },
 842         },
 843 };
 844
 845 static struct freq_tbl clk_tbl_gfx3d[] = {
 846         F_MN( 27000000, P_PXO,  1,  0),
 847         F_MN( 48000000, P_PLL8, 1,  8),
 848         F_MN( 54857000, P_PLL8, 1,  7),
 849         F_MN( 64000000, P_PLL8, 1,  6),
 850         F_MN( 76800000, P_PLL8, 1,  5),
 851         F_MN( 96000000, P_PLL8, 1,  4),
 852         F_MN(128000000, P_PLL8, 1,  3),
 853         F_MN(145455000, P_PLL2, 2, 11),
 854         F_MN(160000000, P_PLL2, 1,  5),
 855         F_MN(177778000, P_PLL2, 2,  9),
 856         F_MN(200000000, P_PLL2, 1,  4),
 857         F_MN(228571000, P_PLL2, 2,  7),
 858         F_MN(266667000, P_PLL2, 1,  3),
 859         F_MN(300000000, P_PLL3, 1,  4),
 860         F_MN(320000000, P_PLL2, 2,  5),
 861         F_MN(400000000, P_PLL2, 1,  2),
 862         { }
 863 };
 864
 865 static struct clk_dyn_rcg gfx3d_src = {
 866         .ns_reg = 0x008c,
 867         .md_reg[0] = 0x0084,
 868         .md_reg[1] = 0x0088,
 869         .mn[0] = {
 870                 .mnctr_en_bit = 8,
 871                 .mnctr_reset_bit = 25,
 872                 .mnctr_mode_shift = 9,
 873                 .n_val_shift = 18,
 874                 .m_val_shift = 4,
 875                 .width = 4,
 876         },
 877         .mn[1] = {
 878                 .mnctr_en_bit = 5,
 879                 .mnctr_reset_bit = 24,
 880                 .mnctr_mode_shift = 6,
 881                 .n_val_shift = 14,
 882                 .m_val_shift = 4,
 883                 .width = 4,
 884         },
 885         .s[0] = {
 886                 .src_sel_shift = 3,
 887                 .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
 888         },
 889         .s[1] = {
 890                 .src_sel_shift = 0,
 891                 .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
 892         },
 893         .mux_sel_bit = 11,
 894         .freq_tbl = clk_tbl_gfx3d,
 895         .clkr = {
 896                 .enable_reg = 0x0080,
 897                 .enable_mask = BIT(2),
 898                 .hw.init = &(struct clk_init_data){
 899                         .name = "gfx3d_src",
 900                         .parent_names = mmcc_pxo_pll8_pll2_pll3,
 901                         .num_parents = 4,
 902                         .ops = &clk_dyn_rcg_ops,
 903                 },
 904         },
 905 };
 906
 907 static struct clk_branch gfx3d_clk = {
 908         .halt_reg = 0x01c8,
 909         .halt_bit = 4,
 910         .clkr = {
 911                 .enable_reg = 0x0080,
 912                 .enable_mask = BIT(0),
 913                 .hw.init = &(struct clk_init_data){
 914                         .name = "gfx3d_clk",
 915                         .parent_names = (const char *[]){ "gfx3d_src" },
 916                         .num_parents = 1,
 917                         .ops = &clk_branch_ops,
 918                         .flags = CLK_SET_RATE_PARENT,
 919                 },
 920         },
 921 };
 922
 923 static struct freq_tbl clk_tbl_ijpeg[] = {
 924         {  27000000, P_PXO,  1, 0,  0 },
 925         {  36570000, P_PLL8, 1, 2, 21 },
 926         {  54860000, P_PLL8, 7, 0,  0 },
 927         {  96000000, P_PLL8, 4, 0,  0 },
 928         { 109710000, P_PLL8, 1, 2,  7 },
 929         { 128000000, P_PLL8, 3, 0,  0 },
 930         { 153600000, P_PLL8, 1, 2,  5 },
 931         { 200000000, P_PLL2, 4, 0,  0 },
 932         { 228571000, P_PLL2, 1, 2,  7 },
 933         { 266667000, P_PLL2, 1, 1,  3 },
 934         { 320000000, P_PLL2, 1, 2,  5 },
 935         { }
 936 };
 937
 938 static struct clk_rcg ijpeg_src = {
 939         .ns_reg = 0x00a0,
 940         .md_reg = 0x009c,
 941         .mn = {
 942                 .mnctr_en_bit = 5,
 943                 .mnctr_reset_bit = 7,
 944                 .mnctr_mode_shift = 6,
 945                 .n_val_shift = 16,
 946                 .m_val_shift = 8,
 947                 .width = 8,
 948         },
 949         .p = {
 950                 .pre_div_shift = 12,
 951                 .pre_div_width = 2,
 952         },
 953         .s = {
 954                 .src_sel_shift = 0,
 955                 .parent_map = mmcc_pxo_pll8_pll2_map,
 956         },
 957         .freq_tbl = clk_tbl_ijpeg,
 958         .clkr = {
 959                 .enable_reg = 0x0098,
 960                 .enable_mask = BIT(2),
 961                 .hw.init = &(struct clk_init_data){
 962                         .name = "ijpeg_src",
 963                         .parent_names = mmcc_pxo_pll8_pll2,
 964                         .num_parents = 3,
 965                         .ops = &clk_rcg_ops,
 966                 },
 967         },
 968 };
 969
 970 static struct clk_branch ijpeg_clk = {
 971         .halt_reg = 0x01c8,
 972         .halt_bit = 24,
 973         .clkr = {
 974                 .enable_reg = 0x0098,
 975                 .enable_mask = BIT(0),
 976                 .hw.init = &(struct clk_init_data){
 977                         .name = "ijpeg_clk",
 978                         .parent_names = (const char *[]){ "ijpeg_src" },
 979                         .num_parents = 1,
 980                         .ops = &clk_branch_ops,
 981                         .flags = CLK_SET_RATE_PARENT,
 982                 },
 983         },
 984 };
 985
 986 static struct freq_tbl clk_tbl_jpegd[] = {
 987         {  64000000, P_PLL8, 6 },
 988         {  76800000, P_PLL8, 5 },
 989         {  96000000, P_PLL8, 4 },
 990         { 160000000, P_PLL2, 5 },
 991         { 200000000, P_PLL2, 4 },
 992         { }
 993 };
 994
 995 static struct clk_rcg jpegd_src = {
 996         .ns_reg = 0x00ac,
 997         .p = {
 998                 .pre_div_shift = 12,
 999                 .pre_div_width = 4,
1000         },
1001         .s = {
1002                 .src_sel_shift = 0,
1003                 .parent_map = mmcc_pxo_pll8_pll2_map,
1004         },
1005         .freq_tbl = clk_tbl_jpegd,
1006         .clkr = {
1007                 .enable_reg = 0x00a4,
1008                 .enable_mask = BIT(2),
1009                 .hw.init = &(struct clk_init_data){
1010                         .name = "jpegd_src",
1011                         .parent_names = mmcc_pxo_pll8_pll2,
1012                         .num_parents = 3,
1013                         .ops = &clk_rcg_ops,
1014                 },
1015         },
1016 };
1017
1018 static struct clk_branch jpegd_clk = {
1019         .halt_reg = 0x01c8,
1020         .halt_bit = 19,
1021         .clkr = {
1022                 .enable_reg = 0x00a4,
1023                 .enable_mask = BIT(0),
1024                 .hw.init = &(struct clk_init_data){
1025                         .name = "jpegd_clk",
1026                         .parent_names = (const char *[]){ "jpegd_src" },
1027                         .num_parents = 1,
1028                         .ops = &clk_branch_ops,
1029                         .flags = CLK_SET_RATE_PARENT,
1030                 },
1031         },
1032 };
1033
1034 static struct freq_tbl clk_tbl_mdp[] = {
1035         {   9600000, P_PLL8, 1, 1, 40 },
1036         {  13710000, P_PLL8, 1, 1, 28 },
1037         {  27000000, P_PXO,  1, 0,  0 },
1038         {  29540000, P_PLL8, 1, 1, 13 },
1039         {  34910000, P_PLL8, 1, 1, 11 },
1040         {  38400000, P_PLL8, 1, 1, 10 },
1041         {  59080000, P_PLL8, 1, 2, 13 },
1042         {  76800000, P_PLL8, 1, 1,  5 },
1043         {  85330000, P_PLL8, 1, 2,  9 },
1044         {  96000000, P_PLL8, 1, 1,  4 },
1045         { 128000000, P_PLL8, 1, 1,  3 },
1046         { 160000000, P_PLL2, 1, 1,  5 },
1047         { 177780000, P_PLL2, 1, 2,  9 },
1048         { 200000000, P_PLL2, 1, 1,  4 },
1049         { 228571000, P_PLL2, 1, 2,  7 },
1050         { 266667000, P_PLL2, 1, 1,  3 },
1051         { }
1052 };
1053
1054 static struct clk_dyn_rcg mdp_src = {
1055         .ns_reg = 0x00d0,
1056         .md_reg[0] = 0x00c4,
1057         .md_reg[1] = 0x00c8,
1058         .mn[0] = {
1059                 .mnctr_en_bit = 8,
1060                 .mnctr_reset_bit = 31,
1061                 .mnctr_mode_shift = 9,
1062                 .n_val_shift = 22,
1063                 .m_val_shift = 8,
1064                 .width = 8,
1065         },
1066         .mn[1] = {
1067                 .mnctr_en_bit = 5,
1068                 .mnctr_reset_bit = 30,
1069                 .mnctr_mode_shift = 6,
1070                 .n_val_shift = 14,
1071                 .m_val_shift = 8,
1072                 .width = 8,
1073         },
1074         .s[0] = {
1075                 .src_sel_shift = 3,
1076                 .parent_map = mmcc_pxo_pll8_pll2_map,
1077         },
1078         .s[1] = {
1079                 .src_sel_shift = 0,
1080                 .parent_map = mmcc_pxo_pll8_pll2_map,
1081         },
1082         .mux_sel_bit = 11,
1083         .freq_tbl = clk_tbl_mdp,
1084         .clkr = {
1085                 .enable_reg = 0x00c0,
1086                 .enable_mask = BIT(2),
1087                 .hw.init = &(struct clk_init_data){
1088                         .name = "mdp_src",
1089                         .parent_names = mmcc_pxo_pll8_pll2,
1090                         .num_parents = 3,
1091                         .ops = &clk_dyn_rcg_ops,
1092                 },
1093         },
1094 };
1095
1096 static struct clk_branch mdp_clk = {
1097         .halt_reg = 0x01d0,
1098         .halt_bit = 10,
1099         .clkr = {
1100                 .enable_reg = 0x00c0,
1101                 .enable_mask = BIT(0),
1102                 .hw.init = &(struct clk_init_data){
1103                         .name = "mdp_clk",
1104                         .parent_names = (const char *[]){ "mdp_src" },
1105                         .num_parents = 1,
1106                         .ops = &clk_branch_ops,
1107                         .flags = CLK_SET_RATE_PARENT,
1108                 },
1109         },
1110 };
1111
1112 static struct clk_branch mdp_lut_clk = {
1113         .halt_reg = 0x01e8,
1114         .halt_bit = 13,
1115         .clkr = {
1116                 .enable_reg = 0x016c,
1117                 .enable_mask = BIT(0),
1118                 .hw.init = &(struct clk_init_data){
1119                         .parent_names = (const char *[]){ "mdp_clk" },
1120                         .num_parents = 1,
1121                         .name = "mdp_lut_clk",
1122                         .ops = &clk_branch_ops,
1123                         .flags = CLK_SET_RATE_PARENT,
1124                 },
1125         },
1126 };
1127
1128 static struct clk_branch mdp_vsync_clk = {
1129         .halt_reg = 0x01cc,
1130         .halt_bit = 22,
1131         .clkr = {
1132                 .enable_reg = 0x0058,
1133                 .enable_mask = BIT(6),
1134                 .hw.init = &(struct clk_init_data){
1135                         .name = "mdp_vsync_clk",
1136                         .parent_names = (const char *[]){ "pxo" },
1137                         .num_parents = 1,
1138                         .ops = &clk_branch_ops
1139                 },
1140         },
1141 };
1142
1143 static struct freq_tbl clk_tbl_rot[] = {
1144         {  27000000, P_PXO,   1 },
1145         {  29540000, P_PLL8, 13 },
1146         {  32000000, P_PLL8, 12 },
1147         {  38400000, P_PLL8, 10 },
1148         {  48000000, P_PLL8,  8 },
1149         {  54860000, P_PLL8,  7 },
1150         {  64000000, P_PLL8,  6 },
1151         {  76800000, P_PLL8,  5 },
1152         {  96000000, P_PLL8,  4 },
1153         { 100000000, P_PLL2,  8 },
1154         { 114290000, P_PLL2,  7 },
1155         { 133330000, P_PLL2,  6 },
1156         { 160000000, P_PLL2,  5 },
1157         { 200000000, P_PLL2,  4 },
1158         { }
1159 };
1160
1161 static struct clk_dyn_rcg rot_src = {
1162         .ns_reg = 0x00e8,
1163         .p[0] = {
1164                 .pre_div_shift = 22,
1165                 .pre_div_width = 4,
1166         },
1167         .p[1] = {
1168                 .pre_div_shift = 26,
1169                 .pre_div_width = 4,
1170         },
1171         .s[0] = {
1172                 .src_sel_shift = 16,
1173                 .parent_map = mmcc_pxo_pll8_pll2_map,
1174         },
1175         .s[1] = {
1176                 .src_sel_shift = 19,
1177                 .parent_map = mmcc_pxo_pll8_pll2_map,
1178         },
1179         .mux_sel_bit = 30,
1180         .freq_tbl = clk_tbl_rot,
1181         .clkr = {
1182                 .enable_reg = 0x00e0,
1183                 .enable_mask = BIT(2),
1184                 .hw.init = &(struct clk_init_data){
1185                         .name = "rot_src",
1186                         .parent_names = mmcc_pxo_pll8_pll2,
1187                         .num_parents = 3,
1188                         .ops = &clk_dyn_rcg_ops,
1189                 },
1190         },
1191 };
1192
1193 static struct clk_branch rot_clk = {
1194         .halt_reg = 0x01d0,
1195         .halt_bit = 15,
1196         .clkr = {
1197                 .enable_reg = 0x00e0,
1198                 .enable_mask = BIT(0),
1199                 .hw.init = &(struct clk_init_data){
1200                         .name = "rot_clk",
1201                         .parent_names = (const char *[]){ "rot_src" },
1202                         .num_parents = 1,
1203                         .ops = &clk_branch_ops,
1204                         .flags = CLK_SET_RATE_PARENT,
1205                 },
1206         },
1207 };
1208
1209 #define P_HDMI_PLL 1
1210
1211 static u8 mmcc_pxo_hdmi_map[] = {
1212         [P_PXO]         = 0,
1213         [P_HDMI_PLL]    = 3,
1214 };
1215
1216 static const char *mmcc_pxo_hdmi[] = {
1217         "pxo",
1218         "hdmi_pll",
1219 };
1220
1221 static struct freq_tbl clk_tbl_tv[] = {
1222         {  25200000, P_HDMI_PLL, 1, 0, 0 },
1223         {  27000000, P_HDMI_PLL, 1, 0, 0 },
1224         {  27030000, P_HDMI_PLL, 1, 0, 0 },
1225         {  74250000, P_HDMI_PLL, 1, 0, 0 },
1226         { 108000000, P_HDMI_PLL, 1, 0, 0 },
1227         { 148500000, P_HDMI_PLL, 1, 0, 0 },
1228         { }
1229 };
1230
1231 static struct clk_rcg tv_src = {
1232         .ns_reg = 0x00f4,
1233         .md_reg = 0x00f0,
1234         .mn = {
1235                 .mnctr_en_bit = 5,
1236                 .mnctr_reset_bit = 7,
1237                 .mnctr_mode_shift = 6,
1238                 .n_val_shift = 16,
1239                 .m_val_shift = 8,
1240                 .width = 8,
1241         },
1242         .p = {
1243                 .pre_div_shift = 14,
1244                 .pre_div_width = 2,
1245         },
1246         .s = {
1247                 .src_sel_shift = 0,
1248                 .parent_map = mmcc_pxo_hdmi_map,
1249         },
1250         .freq_tbl = clk_tbl_tv,
1251         .clkr = {
1252                 .enable_reg = 0x00ec,
1253                 .enable_mask = BIT(2),
1254                 .hw.init = &(struct clk_init_data){
1255                         .name = "tv_src",
1256                         .parent_names = mmcc_pxo_hdmi,
1257                         .num_parents = 2,
1258                         .ops = &clk_rcg_ops,
1259                         .flags = CLK_SET_RATE_PARENT,
1260                 },
1261         },
1262 };
1263
1264 static const char *tv_src_name[] = { "tv_src" };
1265
1266 static struct clk_branch tv_enc_clk = {
1267         .halt_reg = 0x01d4,
1268         .halt_bit = 9,
1269         .clkr = {
1270                 .enable_reg = 0x00ec,
1271                 .enable_mask = BIT(8),
1272                 .hw.init = &(struct clk_init_data){
1273                         .parent_names = tv_src_name,
1274                         .num_parents = 1,
1275                         .name = "tv_enc_clk",
1276                         .ops = &clk_branch_ops,
1277                         .flags = CLK_SET_RATE_PARENT,
1278                 },
1279         },
1280 };
1281
1282 static struct clk_branch tv_dac_clk = {
1283         .halt_reg = 0x01d4,
1284         .halt_bit = 10,
1285         .clkr = {
1286                 .enable_reg = 0x00ec,
1287                 .enable_mask = BIT(10),
1288                 .hw.init = &(struct clk_init_data){
1289                         .parent_names = tv_src_name,
1290                         .num_parents = 1,
1291                         .name = "tv_dac_clk",
1292                         .ops = &clk_branch_ops,
1293                         .flags = CLK_SET_RATE_PARENT,
1294                 },
1295         },
1296 };
1297
1298 static struct clk_branch mdp_tv_clk = {
1299         .halt_reg = 0x01d4,
1300         .halt_bit = 12,
1301         .clkr = {
1302                 .enable_reg = 0x00ec,
1303                 .enable_mask = BIT(0),
1304                 .hw.init = &(struct clk_init_data){
1305                         .parent_names = tv_src_name,
1306                         .num_parents = 1,
1307                         .name = "mdp_tv_clk",
1308                         .ops = &clk_branch_ops,
1309                         .flags = CLK_SET_RATE_PARENT,
1310                 },
1311         },
1312 };
1313
1314 static struct clk_branch hdmi_tv_clk = {
1315         .halt_reg = 0x01d4,
1316         .halt_bit = 11,
1317         .clkr = {
1318                 .enable_reg = 0x00ec,
1319                 .enable_mask = BIT(12),
1320                 .hw.init = &(struct clk_init_data){
1321                         .parent_names = tv_src_name,
1322                         .num_parents = 1,
1323                         .name = "hdmi_tv_clk",
1324                         .ops = &clk_branch_ops,
1325                         .flags = CLK_SET_RATE_PARENT,
1326                 },
1327         },
1328 };
1329
1330 static struct clk_branch hdmi_app_clk = {
1331         .halt_reg = 0x01cc,
1332         .halt_bit = 25,
1333         .clkr = {
1334                 .enable_reg = 0x005c,
1335                 .enable_mask = BIT(11),
1336                 .hw.init = &(struct clk_init_data){
1337                         .parent_names = (const char *[]){ "pxo" },
1338                         .num_parents = 1,
1339                         .name = "hdmi_app_clk",
1340                         .ops = &clk_branch_ops,
1341                 },
1342         },
1343 };
1344
1345 static struct freq_tbl clk_tbl_vcodec[] = {
1346         F_MN( 27000000, P_PXO,  1,  0),
1347         F_MN( 32000000, P_PLL8, 1, 12),
1348         F_MN( 48000000, P_PLL8, 1,  8),
1349         F_MN( 54860000, P_PLL8, 1,  7),
1350         F_MN( 96000000, P_PLL8, 1,  4),
1351         F_MN(133330000, P_PLL2, 1,  6),
1352         F_MN(200000000, P_PLL2, 1,  4),
1353         F_MN(228570000, P_PLL2, 2,  7),
1354         F_MN(266670000, P_PLL2, 1,  3),
1355         { }
1356 };
1357
1358 static struct clk_dyn_rcg vcodec_src = {
1359         .ns_reg = 0x0100,
1360         .md_reg[0] = 0x00fc,
1361         .md_reg[1] = 0x0128,
1362         .mn[0] = {
1363                 .mnctr_en_bit = 5,
1364                 .mnctr_reset_bit = 31,
1365                 .mnctr_mode_shift = 6,
1366                 .n_val_shift = 11,
1367                 .m_val_shift = 8,
1368                 .width = 8,
1369         },
1370         .mn[1] = {
1371                 .mnctr_en_bit = 10,
1372                 .mnctr_reset_bit = 30,
1373                 .mnctr_mode_shift = 11,
1374                 .n_val_shift = 19,
1375                 .m_val_shift = 8,
1376                 .width = 8,
1377         },
1378         .s[0] = {
1379                 .src_sel_shift = 27,
1380                 .parent_map = mmcc_pxo_pll8_pll2_map,
1381         },
1382         .s[1] = {
1383                 .src_sel_shift = 0,
1384                 .parent_map = mmcc_pxo_pll8_pll2_map,
1385         },
1386         .mux_sel_bit = 13,
1387         .freq_tbl = clk_tbl_vcodec,
1388         .clkr = {
1389                 .enable_reg = 0x00f8,
1390                 .enable_mask = BIT(2),
1391                 .hw.init = &(struct clk_init_data){
1392                         .name = "vcodec_src",
1393                         .parent_names = mmcc_pxo_pll8_pll2,
1394                         .num_parents = 3,
1395                         .ops = &clk_dyn_rcg_ops,
1396                 },
1397         },
1398 };
1399
1400 static struct clk_branch vcodec_clk = {
1401         .halt_reg = 0x01d0,
1402         .halt_bit = 29,
1403         .clkr = {
1404                 .enable_reg = 0x00f8,
1405                 .enable_mask = BIT(0),
1406                 .hw.init = &(struct clk_init_data){
1407                         .name = "vcodec_clk",
1408                         .parent_names = (const char *[]){ "vcodec_src" },
1409                         .num_parents = 1,
1410                         .ops = &clk_branch_ops,
1411                         .flags = CLK_SET_RATE_PARENT,
1412                 },
1413         },
1414 };
1415
1416 static struct freq_tbl clk_tbl_vpe[] = {
1417         {  27000000, P_PXO,   1 },
1418         {  34909000, P_PLL8, 11 },
1419         {  38400000, P_PLL8, 10 },
1420         {  64000000, P_PLL8,  6 },
1421         {  76800000, P_PLL8,  5 },
1422         {  96000000, P_PLL8,  4 },
1423         { 100000000, P_PLL2,  8 },
1424         { 160000000, P_PLL2,  5 },
1425         { }
1426 };
1427
1428 static struct clk_rcg vpe_src = {
1429         .ns_reg = 0x0118,
1430         .p = {
1431                 .pre_div_shift = 12,
1432                 .pre_div_width = 4,
1433         },
1434         .s = {
1435                 .src_sel_shift = 0,
1436                 .parent_map = mmcc_pxo_pll8_pll2_map,
1437         },
1438         .freq_tbl = clk_tbl_vpe,
1439         .clkr = {
1440                 .enable_reg = 0x0110,
1441                 .enable_mask = BIT(2),
1442                 .hw.init = &(struct clk_init_data){
1443                         .name = "vpe_src",
1444                         .parent_names = mmcc_pxo_pll8_pll2,
1445                         .num_parents = 3,
1446                         .ops = &clk_rcg_ops,
1447                 },
1448         },
1449 };
1450
1451 static struct clk_branch vpe_clk = {
1452         .halt_reg = 0x01c8,
1453         .halt_bit = 28,
1454         .clkr = {
1455                 .enable_reg = 0x0110,
1456                 .enable_mask = BIT(0),
1457                 .hw.init = &(struct clk_init_data){
1458                         .name = "vpe_clk",
1459                         .parent_names = (const char *[]){ "vpe_src" },
1460                         .num_parents = 1,
1461                         .ops = &clk_branch_ops,
1462                         .flags = CLK_SET_RATE_PARENT,
1463                 },
1464         },
1465 };
1466
1467 static struct freq_tbl clk_tbl_vfe[] = {
1468         {  13960000, P_PLL8,  1, 2, 55 },
1469         {  27000000, P_PXO,   1, 0,  0 },
1470         {  36570000, P_PLL8,  1, 2, 21 },
1471         {  38400000, P_PLL8,  2, 1,  5 },
1472         {  45180000, P_PLL8,  1, 2, 17 },
1473         {  48000000, P_PLL8,  2, 1,  4 },
1474         {  54860000, P_PLL8,  1, 1,  7 },
1475         {  64000000, P_PLL8,  2, 1,  3 },
1476         {  76800000, P_PLL8,  1, 1,  5 },
1477         {  96000000, P_PLL8,  2, 1,  2 },
1478         { 109710000, P_PLL8,  1, 2,  7 },
1479         { 128000000, P_PLL8,  1, 1,  3 },
1480         { 153600000, P_PLL8,  1, 2,  5 },
1481         { 200000000, P_PLL2,  2, 1,  2 },
1482         { 228570000, P_PLL2,  1, 2,  7 },
1483         { 266667000, P_PLL2,  1, 1,  3 },
1484         { 320000000, P_PLL2,  1, 2,  5 },
1485         { }
1486 };
1487
1488 static struct clk_rcg vfe_src = {
1489         .ns_reg = 0x0108,
1490         .mn = {
1491                 .mnctr_en_bit = 5,
1492                 .mnctr_reset_bit = 7,
1493                 .mnctr_mode_shift = 6,
1494                 .n_val_shift = 16,
1495                 .m_val_shift = 8,
1496                 .width = 8,
1497         },
1498         .p = {
1499                 .pre_div_shift = 10,
1500                 .pre_div_width = 1,
1501         },
1502         .s = {
1503                 .src_sel_shift = 0,
1504                 .parent_map = mmcc_pxo_pll8_pll2_map,
1505         },
1506         .freq_tbl = clk_tbl_vfe,
1507         .clkr = {
1508                 .enable_reg = 0x0104,
1509                 .enable_mask = BIT(2),
1510                 .hw.init = &(struct clk_init_data){
1511                         .name = "vfe_src",
1512                         .parent_names = mmcc_pxo_pll8_pll2,
1513                         .num_parents = 3,
1514                         .ops = &clk_rcg_ops,
1515                 },
1516         },
1517 };
1518
1519 static struct clk_branch vfe_clk = {
1520         .halt_reg = 0x01cc,
1521         .halt_bit = 6,
1522         .clkr = {
1523                 .enable_reg = 0x0104,
1524                 .enable_mask = BIT(0),
1525                 .hw.init = &(struct clk_init_data){
1526                         .name = "vfe_clk",
1527                         .parent_names = (const char *[]){ "vfe_src" },
1528                         .num_parents = 1,
1529                         .ops = &clk_branch_ops,
1530                         .flags = CLK_SET_RATE_PARENT,
1531                 },
1532         },
1533 };
1534
1535 static struct clk_branch vfe_csi_clk = {
1536         .halt_reg = 0x01cc,
1537         .halt_bit = 8,
1538         .clkr = {
1539                 .enable_reg = 0x0104,
1540                 .enable_mask = BIT(12),
1541                 .hw.init = &(struct clk_init_data){
1542                         .parent_names = (const char *[]){ "vfe_src" },
1543                         .num_parents = 1,
1544                         .name = "vfe_csi_clk",
1545                         .ops = &clk_branch_ops,
1546                         .flags = CLK_SET_RATE_PARENT,
1547                 },
1548         },
1549 };
1550
1551 static struct clk_branch gmem_axi_clk = {
1552         .halt_reg = 0x01d8,
1553         .halt_bit = 6,
1554         .clkr = {
1555                 .enable_reg = 0x0018,
1556                 .enable_mask = BIT(24),
1557                 .hw.init = &(struct clk_init_data){
1558                         .name = "gmem_axi_clk",
1559                         .ops = &clk_branch_ops,
1560                         .flags = CLK_IS_ROOT,
1561                 },
1562         },
1563 };
1564
1565 static struct clk_branch ijpeg_axi_clk = {
1566         .hwcg_reg = 0x0018,
1567         .hwcg_bit = 11,
1568         .halt_reg = 0x01d8,
1569         .halt_bit = 4,
1570         .clkr = {
1571                 .enable_reg = 0x0018,
1572                 .enable_mask = BIT(21),
1573                 .hw.init = &(struct clk_init_data){
1574                         .name = "ijpeg_axi_clk",
1575                         .ops = &clk_branch_ops,
1576                         .flags = CLK_IS_ROOT,
1577                 },
1578         },
1579 };
1580
1581 static struct clk_branch mmss_imem_axi_clk = {
1582         .hwcg_reg = 0x0018,
1583         .hwcg_bit = 15,
1584         .halt_reg = 0x01d8,
1585         .halt_bit = 7,
1586         .clkr = {
1587                 .enable_reg = 0x0018,
1588                 .enable_mask = BIT(22),
1589                 .hw.init = &(struct clk_init_data){
1590                         .name = "mmss_imem_axi_clk",
1591                         .ops = &clk_branch_ops,
1592                         .flags = CLK_IS_ROOT,
1593                 },
1594         },
1595 };
1596
1597 static struct clk_branch jpegd_axi_clk = {
1598         .halt_reg = 0x01d8,
1599         .halt_bit = 5,
1600         .clkr = {
1601                 .enable_reg = 0x0018,
1602                 .enable_mask = BIT(25),
1603                 .hw.init = &(struct clk_init_data){
1604                         .name = "jpegd_axi_clk",
1605                         .ops = &clk_branch_ops,
1606                         .flags = CLK_IS_ROOT,
1607                 },
1608         },
1609 };
1610
1611 static struct clk_branch vcodec_axi_b_clk = {
1612         .hwcg_reg = 0x0114,
1613         .hwcg_bit = 22,
1614         .halt_reg = 0x01e8,
1615         .halt_bit = 25,
1616         .clkr = {
1617                 .enable_reg = 0x0114,
1618                 .enable_mask = BIT(23),
1619                 .hw.init = &(struct clk_init_data){
1620                         .name = "vcodec_axi_b_clk",
1621                         .ops = &clk_branch_ops,
1622                         .flags = CLK_IS_ROOT,
1623                 },
1624         },
1625 };
1626
1627 static struct clk_branch vcodec_axi_a_clk = {
1628         .hwcg_reg = 0x0114,
1629         .hwcg_bit = 24,
1630         .halt_reg = 0x01e8,
1631         .halt_bit = 26,
1632         .clkr = {
1633                 .enable_reg = 0x0114,
1634                 .enable_mask = BIT(25),
1635                 .hw.init = &(struct clk_init_data){
1636                         .name = "vcodec_axi_a_clk",
1637                         .ops = &clk_branch_ops,
1638                         .flags = CLK_IS_ROOT,
1639                 },
1640         },
1641 };
1642
1643 static struct clk_branch vcodec_axi_clk = {
1644         .hwcg_reg = 0x0018,
1645         .hwcg_bit = 13,
1646         .halt_reg = 0x01d8,
1647         .halt_bit = 3,
1648         .clkr = {
1649                 .enable_reg = 0x0018,
1650                 .enable_mask = BIT(19),
1651                 .hw.init = &(struct clk_init_data){
1652                         .name = "vcodec_axi_clk",
1653                         .ops = &clk_branch_ops,
1654                         .flags = CLK_IS_ROOT,
1655                 },
1656         },
1657 };
1658
1659 static struct clk_branch vfe_axi_clk = {
1660         .halt_reg = 0x01d8,
1661         .halt_bit = 0,
1662         .clkr = {
1663                 .enable_reg = 0x0018,
1664                 .enable_mask = BIT(18),
1665                 .hw.init = &(struct clk_init_data){
1666                         .name = "vfe_axi_clk",
1667                         .ops = &clk_branch_ops,
1668                         .flags = CLK_IS_ROOT,
1669                 },
1670         },
1671 };
1672
1673 static struct clk_branch mdp_axi_clk = {
1674         .hwcg_reg = 0x0018,
1675         .hwcg_bit = 16,
1676         .halt_reg = 0x01d8,
1677         .halt_bit = 8,
1678         .clkr = {
1679                 .enable_reg = 0x0018,
1680                 .enable_mask = BIT(23),
1681                 .hw.init = &(struct clk_init_data){
1682                         .name = "mdp_axi_clk",
1683                         .ops = &clk_branch_ops,
1684                         .flags = CLK_IS_ROOT,
1685                 },
1686         },
1687 };
1688
1689 static struct clk_branch rot_axi_clk = {
1690         .hwcg_reg = 0x0020,
1691         .hwcg_bit = 25,
1692         .halt_reg = 0x01d8,
1693         .halt_bit = 2,
1694         .clkr = {
1695                 .enable_reg = 0x0020,
1696                 .enable_mask = BIT(24),
1697                 .hw.init = &(struct clk_init_data){
1698                         .name = "rot_axi_clk",
1699                         .ops = &clk_branch_ops,
1700                         .flags = CLK_IS_ROOT,
1701                 },
1702         },
1703 };
1704
1705 static struct clk_branch vpe_axi_clk = {
1706         .hwcg_reg = 0x0020,
1707         .hwcg_bit = 27,
1708         .halt_reg = 0x01d8,
1709         .halt_bit = 1,
1710         .clkr = {
1711                 .enable_reg = 0x0020,
1712                 .enable_mask = BIT(26),
1713                 .hw.init = &(struct clk_init_data){
1714                         .name = "vpe_axi_clk",
1715                         .ops = &clk_branch_ops,
1716                         .flags = CLK_IS_ROOT,
1717                 },
1718         },
1719 };
1720
1721 static struct clk_branch gfx3d_axi_clk = {
1722         .hwcg_reg = 0x0244,
1723         .hwcg_bit = 24,
1724         .halt_reg = 0x0240,
1725         .halt_bit = 30,
1726         .clkr = {
1727                 .enable_reg = 0x0244,
1728                 .enable_mask = BIT(25),
1729                 .hw.init = &(struct clk_init_data){
1730                         .name = "gfx3d_axi_clk",
1731                         .ops = &clk_branch_ops,
1732                         .flags = CLK_IS_ROOT,
1733                 },
1734         },
1735 };
1736
1737 static struct clk_branch amp_ahb_clk = {
1738         .halt_reg = 0x01dc,
1739         .halt_bit = 18,
1740         .clkr = {
1741                 .enable_reg = 0x0008,
1742                 .enable_mask = BIT(24),
1743                 .hw.init = &(struct clk_init_data){
1744                         .name = "amp_ahb_clk",
1745                         .ops = &clk_branch_ops,
1746                         .flags = CLK_IS_ROOT,
1747                 },
1748         },
1749 };
1750
1751 static struct clk_branch csi_ahb_clk = {
1752         .halt_reg = 0x01dc,
1753         .halt_bit = 16,
1754         .clkr = {
1755                 .enable_reg = 0x0008,
1756                 .enable_mask = BIT(7),
1757                 .hw.init = &(struct clk_init_data){
1758                         .name = "csi_ahb_clk",
1759                         .ops = &clk_branch_ops,
1760                         .flags = CLK_IS_ROOT
1761                 },
1762         },
1763 };
1764
1765 static struct clk_branch dsi_m_ahb_clk = {
1766         .halt_reg = 0x01dc,
1767         .halt_bit = 19,
1768         .clkr = {
1769                 .enable_reg = 0x0008,
1770                 .enable_mask = BIT(9),
1771                 .hw.init = &(struct clk_init_data){
1772                         .name = "dsi_m_ahb_clk",
1773                         .ops = &clk_branch_ops,
1774                         .flags = CLK_IS_ROOT,
1775                 },
1776         },
1777 };
1778
1779 static struct clk_branch dsi_s_ahb_clk = {
1780         .hwcg_reg = 0x0038,
1781         .hwcg_bit = 20,
1782         .halt_reg = 0x01dc,
1783         .halt_bit = 21,
1784         .clkr = {
1785                 .enable_reg = 0x0008,
1786                 .enable_mask = BIT(18),
1787                 .hw.init = &(struct clk_init_data){
1788                         .name = "dsi_s_ahb_clk",
1789                         .ops = &clk_branch_ops,
1790                         .flags = CLK_IS_ROOT,
1791                 },
1792         },
1793 };
1794
1795 static struct clk_branch dsi2_m_ahb_clk = {
1796         .halt_reg = 0x01d8,
1797         .halt_bit = 18,
1798         .clkr = {
1799                 .enable_reg = 0x0008,
1800                 .enable_mask = BIT(17),
1801                 .hw.init = &(struct clk_init_data){
1802                         .name = "dsi2_m_ahb_clk",
1803                         .ops = &clk_branch_ops,
1804                         .flags = CLK_IS_ROOT
1805                 },
1806         },
1807 };
1808
1809 static struct clk_branch dsi2_s_ahb_clk = {
1810         .hwcg_reg = 0x0038,
1811         .hwcg_bit = 15,
1812         .halt_reg = 0x01dc,
1813         .halt_bit = 20,
1814         .clkr = {
1815                 .enable_reg = 0x0008,
1816                 .enable_mask = BIT(22),
1817                 .hw.init = &(struct clk_init_data){
1818                         .name = "dsi2_s_ahb_clk",
1819                         .ops = &clk_branch_ops,
1820                         .flags = CLK_IS_ROOT,
1821                 },
1822         },
1823 };
1824
1825 static struct clk_branch gfx2d0_ahb_clk = {
1826         .hwcg_reg = 0x0038,
1827         .hwcg_bit = 28,
1828         .halt_reg = 0x01dc,
1829         .halt_bit = 2,
1830         .clkr = {
1831                 .enable_reg = 0x0008,
1832                 .enable_mask = BIT(19),
1833                 .hw.init = &(struct clk_init_data){
1834                         .name = "gfx2d0_ahb_clk",
1835                         .ops = &clk_branch_ops,
1836                         .flags = CLK_IS_ROOT,
1837                 },
1838         },
1839 };
1840
1841 static struct clk_branch gfx2d1_ahb_clk = {
1842         .hwcg_reg = 0x0038,
1843         .hwcg_bit = 29,
1844         .halt_reg = 0x01dc,
1845         .halt_bit = 3,
1846         .clkr = {
1847                 .enable_reg = 0x0008,
1848                 .enable_mask = BIT(2),
1849                 .hw.init = &(struct clk_init_data){
1850                         .name = "gfx2d1_ahb_clk",
1851                         .ops = &clk_branch_ops,
1852                         .flags = CLK_IS_ROOT,
1853                 },
1854         },
1855 };
1856
1857 static struct clk_branch gfx3d_ahb_clk = {
1858         .hwcg_reg = 0x0038,
1859         .hwcg_bit = 27,
1860         .halt_reg = 0x01dc,
1861         .halt_bit = 4,
1862         .clkr = {
1863                 .enable_reg = 0x0008,
1864                 .enable_mask = BIT(3),
1865                 .hw.init = &(struct clk_init_data){
1866                         .name = "gfx3d_ahb_clk",
1867                         .ops = &clk_branch_ops,
1868                         .flags = CLK_IS_ROOT,
1869                 },
1870         },
1871 };
1872
1873 static struct clk_branch hdmi_m_ahb_clk = {
1874         .hwcg_reg = 0x0038,
1875         .hwcg_bit = 21,
1876         .halt_reg = 0x01dc,
1877         .halt_bit = 5,
1878         .clkr = {
1879                 .enable_reg = 0x0008,
1880                 .enable_mask = BIT(14),
1881                 .hw.init = &(struct clk_init_data){
1882                         .name = "hdmi_m_ahb_clk",
1883                         .ops = &clk_branch_ops,
1884                         .flags = CLK_IS_ROOT,
1885                 },
1886         },
1887 };
1888
1889 static struct clk_branch hdmi_s_ahb_clk = {
1890         .hwcg_reg = 0x0038,
1891         .hwcg_bit = 22,
1892         .halt_reg = 0x01dc,
1893         .halt_bit = 6,
1894         .clkr = {
1895                 .enable_reg = 0x0008,
1896                 .enable_mask = BIT(4),
1897                 .hw.init = &(struct clk_init_data){
1898                         .name = "hdmi_s_ahb_clk",
1899                         .ops = &clk_branch_ops,
1900                         .flags = CLK_IS_ROOT,
1901                 },
1902         },
1903 };
1904
1905 static struct clk_branch ijpeg_ahb_clk = {
1906         .halt_reg = 0x01dc,
1907         .halt_bit = 9,
1908         .clkr = {
1909                 .enable_reg = 0x0008,
1910                 .enable_mask = BIT(5),
1911                 .hw.init = &(struct clk_init_data){
1912                         .name = "ijpeg_ahb_clk",
1913                         .ops = &clk_branch_ops,
1914                         .flags = CLK_IS_ROOT
1915                 },
1916         },
1917 };
1918
1919 static struct clk_branch mmss_imem_ahb_clk = {
1920         .hwcg_reg = 0x0038,
1921         .hwcg_bit = 12,
1922         .halt_reg = 0x01dc,
1923         .halt_bit = 10,
1924         .clkr = {
1925                 .enable_reg = 0x0008,
1926                 .enable_mask = BIT(6),
1927                 .hw.init = &(struct clk_init_data){
1928                         .name = "mmss_imem_ahb_clk",
1929                         .ops = &clk_branch_ops,
1930                         .flags = CLK_IS_ROOT
1931                 },
1932         },
1933 };
1934
1935 static struct clk_branch jpegd_ahb_clk = {
1936         .halt_reg = 0x01dc,
1937         .halt_bit = 7,
1938         .clkr = {
1939                 .enable_reg = 0x0008,
1940                 .enable_mask = BIT(21),
1941                 .hw.init = &(struct clk_init_data){
1942                         .name = "jpegd_ahb_clk",
1943                         .ops = &clk_branch_ops,
1944                         .flags = CLK_IS_ROOT,
1945                 },
1946         },
1947 };
1948
1949 static struct clk_branch mdp_ahb_clk = {
1950         .halt_reg = 0x01dc,
1951         .halt_bit = 11,
1952         .clkr = {
1953                 .enable_reg = 0x0008,
1954                 .enable_mask = BIT(10),
1955                 .hw.init = &(struct clk_init_data){
1956                         .name = "mdp_ahb_clk",
1957                         .ops = &clk_branch_ops,
1958                         .flags = CLK_IS_ROOT,
1959                 },
1960         },
1961 };
1962
1963 static struct clk_branch rot_ahb_clk = {
1964         .halt_reg = 0x01dc,
1965         .halt_bit = 13,
1966         .clkr = {
1967                 .enable_reg = 0x0008,
1968                 .enable_mask = BIT(12),
1969                 .hw.init = &(struct clk_init_data){
1970                         .name = "rot_ahb_clk",
1971                         .ops = &clk_branch_ops,
1972                         .flags = CLK_IS_ROOT
1973                 },
1974         },
1975 };
1976
1977 static struct clk_branch smmu_ahb_clk = {
1978         .hwcg_reg = 0x0008,
1979         .hwcg_bit = 26,
1980         .halt_reg = 0x01dc,
1981         .halt_bit = 22,
1982         .clkr = {
1983                 .enable_reg = 0x0008,
1984                 .enable_mask = BIT(15),
1985                 .hw.init = &(struct clk_init_data){
1986                         .name = "smmu_ahb_clk",
1987                         .ops = &clk_branch_ops,
1988                         .flags = CLK_IS_ROOT,
1989                 },
1990         },
1991 };
1992
1993 static struct clk_branch tv_enc_ahb_clk = {
1994         .halt_reg = 0x01dc,
1995         .halt_bit = 23,
1996         .clkr = {
1997                 .enable_reg = 0x0008,
1998                 .enable_mask = BIT(25),
1999                 .hw.init = &(struct clk_init_data){
2000                         .name = "tv_enc_ahb_clk",
2001                         .ops = &clk_branch_ops,
2002                         .flags = CLK_IS_ROOT,
2003                 },
2004         },
2005 };
2006
2007 static struct clk_branch vcodec_ahb_clk = {
2008         .hwcg_reg = 0x0038,
2009         .hwcg_bit = 26,
2010         .halt_reg = 0x01dc,
2011         .halt_bit = 12,
2012         .clkr = {
2013                 .enable_reg = 0x0008,
2014                 .enable_mask = BIT(11),
2015                 .hw.init = &(struct clk_init_data){
2016                         .name = "vcodec_ahb_clk",
2017                         .ops = &clk_branch_ops,
2018                         .flags = CLK_IS_ROOT,
2019                 },
2020         },
2021 };
2022
2023 static struct clk_branch vfe_ahb_clk = {
2024         .halt_reg = 0x01dc,
2025         .halt_bit = 14,
2026         .clkr = {
2027                 .enable_reg = 0x0008,
2028                 .enable_mask = BIT(13),
2029                 .hw.init = &(struct clk_init_data){
2030                         .name = "vfe_ahb_clk",
2031                         .ops = &clk_branch_ops,
2032                         .flags = CLK_IS_ROOT,
2033                 },
2034         },
2035 };
2036
2037 static struct clk_branch vpe_ahb_clk = {
2038         .halt_reg = 0x01dc,
2039         .halt_bit = 15,
2040         .clkr = {
2041                 .enable_reg = 0x0008,
2042                 .enable_mask = BIT(16),
2043                 .hw.init = &(struct clk_init_data){
2044                         .name = "vpe_ahb_clk",
2045                         .ops = &clk_branch_ops,
2046                         .flags = CLK_IS_ROOT,
2047                 },
2048         },
2049 };
2050
2051 static struct clk_regmap *mmcc_msm8960_clks[] = {
2052         [TV_ENC_AHB_CLK] = &tv_enc_ahb_clk.clkr,
2053         [AMP_AHB_CLK] = &amp_ahb_clk.clkr,
2054         [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr,
2055         [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr,
2056         [GFX2D0_AHB_CLK] = &gfx2d0_ahb_clk.clkr,
2057         [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr,
2058         [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr,
2059         [VPE_AHB_CLK] = &vpe_ahb_clk.clkr,
2060         [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr,
2061         [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr,
2062         [VFE_AHB_CLK] = &vfe_ahb_clk.clkr,
2063         [ROT_AHB_CLK] = &rot_ahb_clk.clkr,
2064         [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr,
2065         [MDP_AHB_CLK] = &mdp_ahb_clk.clkr,
2066         [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr,
2067         [CSI_AHB_CLK] = &csi_ahb_clk.clkr,
2068         [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr,
2069         [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr,
2070         [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr,
2071         [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr,
2072         [GFX2D1_AHB_CLK] = &gfx2d1_ahb_clk.clkr,
2073         [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr,
2074         [GMEM_AXI_CLK] = &gmem_axi_clk.clkr,
2075         [MDP_AXI_CLK] = &mdp_axi_clk.clkr,
2076         [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr,
2077         [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr,
2078         [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr,
2079         [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr,
2080         [VFE_AXI_CLK] = &vfe_axi_clk.clkr,
2081         [VPE_AXI_CLK] = &vpe_axi_clk.clkr,
2082         [ROT_AXI_CLK] = &rot_axi_clk.clkr,
2083         [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr,
2084         [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr,
2085         [CSI0_SRC] = &csi0_src.clkr,
2086         [CSI0_CLK] = &csi0_clk.clkr,
2087         [CSI0_PHY_CLK] = &csi0_phy_clk.clkr,
2088         [CSI1_SRC] = &csi1_src.clkr,
2089         [CSI1_CLK] = &csi1_clk.clkr,
2090         [CSI1_PHY_CLK] = &csi1_phy_clk.clkr,
2091         [CSI2_SRC] = &csi2_src.clkr,
2092         [CSI2_CLK] = &csi2_clk.clkr,
2093         [CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
2094         [CSI_PIX_CLK] = &csi_pix_clk.clkr,
2095         [CSI_RDI_CLK] = &csi_rdi_clk.clkr,
2096         [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
2097         [HDMI_APP_CLK] = &hdmi_app_clk.clkr,
2098         [CSI_PIX1_CLK] = &csi_pix1_clk.clkr,
2099         [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr,
2100         [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr,
2101         [GFX2D0_SRC] = &gfx2d0_src.clkr,
2102         [GFX2D0_CLK] = &gfx2d0_clk.clkr,
2103         [GFX2D1_SRC] = &gfx2d1_src.clkr,
2104         [GFX2D1_CLK] = &gfx2d1_clk.clkr,
2105         [GFX3D_SRC] = &gfx3d_src.clkr,
2106         [GFX3D_CLK] = &gfx3d_clk.clkr,
2107         [IJPEG_SRC] = &ijpeg_src.clkr,
2108         [IJPEG_CLK] = &ijpeg_clk.clkr,
2109         [JPEGD_SRC] = &jpegd_src.clkr,
2110         [JPEGD_CLK] = &jpegd_clk.clkr,
2111         [MDP_SRC] = &mdp_src.clkr,
2112         [MDP_CLK] = &mdp_clk.clkr,
2113         [MDP_LUT_CLK] = &mdp_lut_clk.clkr,
2114         [ROT_SRC] = &rot_src.clkr,
2115         [ROT_CLK] = &rot_clk.clkr,
2116         [TV_ENC_CLK] = &tv_enc_clk.clkr,
2117         [TV_DAC_CLK] = &tv_dac_clk.clkr,
2118         [HDMI_TV_CLK] = &hdmi_tv_clk.clkr,
2119         [MDP_TV_CLK] = &mdp_tv_clk.clkr,
2120         [TV_SRC] = &tv_src.clkr,
2121         [VCODEC_SRC] = &vcodec_src.clkr,
2122         [VCODEC_CLK] = &vcodec_clk.clkr,
2123         [VFE_SRC] = &vfe_src.clkr,
2124         [VFE_CLK] = &vfe_clk.clkr,
2125         [VFE_CSI_CLK] = &vfe_csi_clk.clkr,
2126         [VPE_SRC] = &vpe_src.clkr,
2127         [VPE_CLK] = &vpe_clk.clkr,
2128         [CAMCLK0_SRC] = &camclk0_src.clkr,
2129         [CAMCLK0_CLK] = &camclk0_clk.clkr,
2130         [CAMCLK1_SRC] = &camclk1_src.clkr,
2131         [CAMCLK1_CLK] = &camclk1_clk.clkr,
2132         [CAMCLK2_SRC] = &camclk2_src.clkr,
2133         [CAMCLK2_CLK] = &camclk2_clk.clkr,
2134         [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr,
2135         [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr,
2136         [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr,
2137         [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr,
2138         [PLL2] = &pll2.clkr,
2139 };
2140
2141 static const struct qcom_reset_map mmcc_msm8960_resets[] = {
2142         [VPE_AXI_RESET] = { 0x0208, 15 },
2143         [IJPEG_AXI_RESET] = { 0x0208, 14 },
2144         [MPD_AXI_RESET] = { 0x0208, 13 },
2145         [VFE_AXI_RESET] = { 0x0208, 9 },
2146         [SP_AXI_RESET] = { 0x0208, 8 },
2147         [VCODEC_AXI_RESET] = { 0x0208, 7 },
2148         [ROT_AXI_RESET] = { 0x0208, 6 },
2149         [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
2150         [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
2151         [FAB_S3_AXI_RESET] = { 0x0208, 3 },
2152         [FAB_S2_AXI_RESET] = { 0x0208, 2 },
2153         [FAB_S1_AXI_RESET] = { 0x0208, 1 },
2154         [FAB_S0_AXI_RESET] = { 0x0208 },
2155         [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
2156         [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
2157         [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
2158         [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
2159         [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
2160         [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
2161         [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
2162         [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
2163         [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
2164         [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
2165         [SMMU_GFX2D0_AHB_RESET] = { 0x020c, 21 },
2166         [SMMU_GFX2D1_AHB_RESET] = { 0x020c, 20 },
2167         [APU_AHB_RESET] = { 0x020c, 18 },
2168         [CSI_AHB_RESET] = { 0x020c, 17 },
2169         [TV_ENC_AHB_RESET] = { 0x020c, 15 },
2170         [VPE_AHB_RESET] = { 0x020c, 14 },
2171         [FABRIC_AHB_RESET] = { 0x020c, 13 },
2172         [GFX2D0_AHB_RESET] = { 0x020c, 12 },
2173         [GFX2D1_AHB_RESET] = { 0x020c, 11 },
2174         [GFX3D_AHB_RESET] = { 0x020c, 10 },
2175         [HDMI_AHB_RESET] = { 0x020c, 9 },
2176         [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
2177         [IJPEG_AHB_RESET] = { 0x020c, 7 },
2178         [DSI_M_AHB_RESET] = { 0x020c, 6 },
2179         [DSI_S_AHB_RESET] = { 0x020c, 5 },
2180         [JPEGD_AHB_RESET] = { 0x020c, 4 },
2181         [MDP_AHB_RESET] = { 0x020c, 3 },
2182         [ROT_AHB_RESET] = { 0x020c, 2 },
2183         [VCODEC_AHB_RESET] = { 0x020c, 1 },
2184         [VFE_AHB_RESET] = { 0x020c, 0 },
2185         [DSI2_M_AHB_RESET] = { 0x0210, 31 },
2186         [DSI2_S_AHB_RESET] = { 0x0210, 30 },
2187         [CSIPHY2_RESET] = { 0x0210, 29 },
2188         [CSI_PIX1_RESET] = { 0x0210, 28 },
2189         [CSIPHY0_RESET] = { 0x0210, 27 },
2190         [CSIPHY1_RESET] = { 0x0210, 26 },
2191         [DSI2_RESET] = { 0x0210, 25 },
2192         [VFE_CSI_RESET] = { 0x0210, 24 },
2193         [MDP_RESET] = { 0x0210, 21 },
2194         [AMP_RESET] = { 0x0210, 20 },
2195         [JPEGD_RESET] = { 0x0210, 19 },
2196         [CSI1_RESET] = { 0x0210, 18 },
2197         [VPE_RESET] = { 0x0210, 17 },
2198         [MMSS_FABRIC_RESET] = { 0x0210, 16 },
2199         [VFE_RESET] = { 0x0210, 15 },
2200         [GFX2D0_RESET] = { 0x0210, 14 },
2201         [GFX2D1_RESET] = { 0x0210, 13 },
2202         [GFX3D_RESET] = { 0x0210, 12 },
2203         [HDMI_RESET] = { 0x0210, 11 },
2204         [MMSS_IMEM_RESET] = { 0x0210, 10 },
2205         [IJPEG_RESET] = { 0x0210, 9 },
2206         [CSI0_RESET] = { 0x0210, 8 },
2207         [DSI_RESET] = { 0x0210, 7 },
2208         [VCODEC_RESET] = { 0x0210, 6 },
2209         [MDP_TV_RESET] = { 0x0210, 4 },
2210         [MDP_VSYNC_RESET] = { 0x0210, 3 },
2211         [ROT_RESET] = { 0x0210, 2 },
2212         [TV_HDMI_RESET] = { 0x0210, 1 },
2213         [TV_ENC_RESET] = { 0x0210 },
2214         [CSI2_RESET] = { 0x0214, 2 },
2215         [CSI_RDI1_RESET] = { 0x0214, 1 },
2216         [CSI_RDI2_RESET] = { 0x0214 },
2217 };
2218
2219 static const struct regmap_config mmcc_msm8960_regmap_config = {
2220         .reg_bits       = 32,
2221         .reg_stride     = 4,
2222         .val_bits       = 32,
2223         .max_register   = 0x334,
2224         .fast_io        = true,
2225 };
2226
2227 static const struct of_device_id mmcc_msm8960_match_table[] = {
2228         { .compatible = "qcom,mmcc-msm8960" },
2229         { }
2230 };
2231 MODULE_DEVICE_TABLE(of, mmcc_msm8960_match_table);
2232
2233 struct qcom_cc {
2234         struct qcom_reset_controller reset;
2235         struct clk_onecell_data data;
2236         struct clk *clks[];
2237 };
2238
2239 static int mmcc_msm8960_probe(struct platform_device *pdev)
2240 {
2241         void __iomem *base;
2242         struct resource *res;
2243         int i, ret;
2244         struct device *dev = &pdev->dev;
2245         struct clk *clk;
2246         struct clk_onecell_data *data;
2247         struct clk **clks;
2248         struct regmap *regmap;
2249         size_t num_clks;
2250         struct qcom_reset_controller *reset;
2251         struct qcom_cc *cc;
2252
2253         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2254         base = devm_ioremap_resource(dev, res);
2255         if (IS_ERR(base))
2256                 return PTR_ERR(base);
2257
2258         regmap = devm_regmap_init_mmio(dev, base, &mmcc_msm8960_regmap_config);
2259         if (IS_ERR(regmap))
2260                 return PTR_ERR(regmap);
2261
2262         num_clks = ARRAY_SIZE(mmcc_msm8960_clks);
2263         cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks,
2264                           GFP_KERNEL);
2265         if (!cc)
2266                 return -ENOMEM;
2267
2268         clks = cc->clks;
2269         data = &cc->data;
2270         data->clks = clks;
2271         data->clk_num = num_clks;
2272
2273         for (i = 0; i < num_clks; i++) {
2274                 if (!mmcc_msm8960_clks[i])
2275                         continue;
2276                 clk = devm_clk_register_regmap(dev, mmcc_msm8960_clks[i]);
2277                 if (IS_ERR(clk))
2278                         return PTR_ERR(clk);
2279                 clks[i] = clk;
2280         }
2281
2282         ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, data);
2283         if (ret)
2284                 return ret;
2285
2286         reset = &cc->reset;
2287         reset->rcdev.of_node = dev->of_node;
2288         reset->rcdev.ops = &qcom_reset_ops,
2289         reset->rcdev.owner = THIS_MODULE,
2290         reset->rcdev.nr_resets = ARRAY_SIZE(mmcc_msm8960_resets),
2291         reset->regmap = regmap;
2292         reset->reset_map = mmcc_msm8960_resets,
2293         platform_set_drvdata(pdev, &reset->rcdev);
2294
2295         ret = reset_controller_register(&reset->rcdev);
2296         if (ret)
2297                 of_clk_del_provider(dev->of_node);
2298
2299         return ret;
2300 }
2301
2302 static int mmcc_msm8960_remove(struct platform_device *pdev)
2303 {
2304         of_clk_del_provider(pdev->dev.of_node);
2305         reset_controller_unregister(platform_get_drvdata(pdev));
2306         return 0;
2307 }
2308
2309 static struct platform_driver mmcc_msm8960_driver = {
2310         .probe          = mmcc_msm8960_probe,
2311         .remove         = mmcc_msm8960_remove,
2312         .driver         = {
2313                 .name   = "mmcc-msm8960",
2314                 .owner  = THIS_MODULE,
2315                 .of_match_table = mmcc_msm8960_match_table,
2316         },
2317 };
2318
2319 module_platform_driver(mmcc_msm8960_driver);
2320
2321 MODULE_DESCRIPTION("QCOM MMCC MSM8960 Driver");
2322 MODULE_LICENSE("GPL v2");
2323 MODULE_ALIAS("platform:mmcc-msm8960");