2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/delay.h>
18 #include <linux/platform_device.h>
19 #include <linux/module.h>
21 #include <linux/of_device.h>
22 #include <linux/clk-provider.h>
23 #include <linux/regmap.h>
24 #include <linux/reset-controller.h>
26 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
27 #include <dt-bindings/reset/qcom,mmcc-msm8960.h>
29 #include "clk-regmap.h"
32 #include "clk-branch.h"
40 #define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n }
42 static u8 mmcc_pxo_pll8_pll2_map[] = {
48 static const char *mmcc_pxo_pll8_pll2[] = {
54 static u8 mmcc_pxo_pll8_pll2_pll3_map[] = {
61 static const char *mmcc_pxo_pll8_pll2_pll3[] = {
68 static struct clk_pll pll2 = {
76 .clkr.hw.init = &(struct clk_init_data){
78 .parent_names = (const char *[]){ "pxo" },
84 static struct freq_tbl clk_tbl_cam[] = {
85 { 6000000, P_PLL8, 4, 1, 16 },
86 { 8000000, P_PLL8, 4, 1, 12 },
87 { 12000000, P_PLL8, 4, 1, 8 },
88 { 16000000, P_PLL8, 4, 1, 6 },
89 { 19200000, P_PLL8, 4, 1, 5 },
90 { 24000000, P_PLL8, 4, 1, 4 },
91 { 32000000, P_PLL8, 4, 1, 3 },
92 { 48000000, P_PLL8, 4, 1, 2 },
93 { 64000000, P_PLL8, 3, 1, 2 },
94 { 96000000, P_PLL8, 4, 0, 0 },
95 { 128000000, P_PLL8, 3, 0, 0 },
99 static struct clk_rcg camclk0_src = {
104 .mnctr_reset_bit = 8,
106 .mnctr_mode_shift = 6,
117 .parent_map = mmcc_pxo_pll8_pll2_map,
119 .freq_tbl = clk_tbl_cam,
121 .enable_reg = 0x0140,
122 .enable_mask = BIT(2),
123 .hw.init = &(struct clk_init_data){
124 .name = "camclk0_src",
125 .parent_names = mmcc_pxo_pll8_pll2,
132 static struct clk_branch camclk0_clk = {
136 .enable_reg = 0x0140,
137 .enable_mask = BIT(0),
138 .hw.init = &(struct clk_init_data){
139 .name = "camclk0_clk",
140 .parent_names = (const char *[]){ "camclk0_src" },
142 .ops = &clk_branch_ops,
148 static struct clk_rcg camclk1_src = {
153 .mnctr_reset_bit = 8,
155 .mnctr_mode_shift = 6,
166 .parent_map = mmcc_pxo_pll8_pll2_map,
168 .freq_tbl = clk_tbl_cam,
170 .enable_reg = 0x0154,
171 .enable_mask = BIT(2),
172 .hw.init = &(struct clk_init_data){
173 .name = "camclk1_src",
174 .parent_names = mmcc_pxo_pll8_pll2,
181 static struct clk_branch camclk1_clk = {
185 .enable_reg = 0x0154,
186 .enable_mask = BIT(0),
187 .hw.init = &(struct clk_init_data){
188 .name = "camclk1_clk",
189 .parent_names = (const char *[]){ "camclk1_src" },
191 .ops = &clk_branch_ops,
197 static struct clk_rcg camclk2_src = {
202 .mnctr_reset_bit = 8,
204 .mnctr_mode_shift = 6,
215 .parent_map = mmcc_pxo_pll8_pll2_map,
217 .freq_tbl = clk_tbl_cam,
219 .enable_reg = 0x0220,
220 .enable_mask = BIT(2),
221 .hw.init = &(struct clk_init_data){
222 .name = "camclk2_src",
223 .parent_names = mmcc_pxo_pll8_pll2,
230 static struct clk_branch camclk2_clk = {
234 .enable_reg = 0x0220,
235 .enable_mask = BIT(0),
236 .hw.init = &(struct clk_init_data){
237 .name = "camclk2_clk",
238 .parent_names = (const char *[]){ "camclk2_src" },
240 .ops = &clk_branch_ops,
246 static struct freq_tbl clk_tbl_csi[] = {
247 { 27000000, P_PXO, 1, 0, 0 },
248 { 85330000, P_PLL8, 1, 2, 9 },
249 { 177780000, P_PLL2, 1, 2, 9 },
253 static struct clk_rcg csi0_src = {
258 .mnctr_reset_bit = 7,
259 .mnctr_mode_shift = 6,
270 .parent_map = mmcc_pxo_pll8_pll2_map,
272 .freq_tbl = clk_tbl_csi,
274 .enable_reg = 0x0040,
275 .enable_mask = BIT(2),
276 .hw.init = &(struct clk_init_data){
278 .parent_names = mmcc_pxo_pll8_pll2,
285 static struct clk_branch csi0_clk = {
289 .enable_reg = 0x0040,
290 .enable_mask = BIT(0),
291 .hw.init = &(struct clk_init_data){
292 .parent_names = (const char *[]){ "csi0_src" },
295 .ops = &clk_branch_ops,
296 .flags = CLK_SET_RATE_PARENT,
301 static struct clk_branch csi0_phy_clk = {
305 .enable_reg = 0x0040,
306 .enable_mask = BIT(8),
307 .hw.init = &(struct clk_init_data){
308 .parent_names = (const char *[]){ "csi0_src" },
310 .name = "csi0_phy_clk",
311 .ops = &clk_branch_ops,
312 .flags = CLK_SET_RATE_PARENT,
317 static struct clk_rcg csi1_src = {
322 .mnctr_reset_bit = 7,
323 .mnctr_mode_shift = 6,
334 .parent_map = mmcc_pxo_pll8_pll2_map,
336 .freq_tbl = clk_tbl_csi,
338 .enable_reg = 0x0024,
339 .enable_mask = BIT(2),
340 .hw.init = &(struct clk_init_data){
342 .parent_names = mmcc_pxo_pll8_pll2,
349 static struct clk_branch csi1_clk = {
353 .enable_reg = 0x0024,
354 .enable_mask = BIT(0),
355 .hw.init = &(struct clk_init_data){
356 .parent_names = (const char *[]){ "csi1_src" },
359 .ops = &clk_branch_ops,
360 .flags = CLK_SET_RATE_PARENT,
365 static struct clk_branch csi1_phy_clk = {
369 .enable_reg = 0x0024,
370 .enable_mask = BIT(8),
371 .hw.init = &(struct clk_init_data){
372 .parent_names = (const char *[]){ "csi1_src" },
374 .name = "csi1_phy_clk",
375 .ops = &clk_branch_ops,
376 .flags = CLK_SET_RATE_PARENT,
381 static struct clk_rcg csi2_src = {
386 .mnctr_reset_bit = 7,
387 .mnctr_mode_shift = 6,
398 .parent_map = mmcc_pxo_pll8_pll2_map,
400 .freq_tbl = clk_tbl_csi,
402 .enable_reg = 0x022c,
403 .enable_mask = BIT(2),
404 .hw.init = &(struct clk_init_data){
406 .parent_names = mmcc_pxo_pll8_pll2,
413 static struct clk_branch csi2_clk = {
417 .enable_reg = 0x022c,
418 .enable_mask = BIT(0),
419 .hw.init = &(struct clk_init_data){
420 .parent_names = (const char *[]){ "csi2_src" },
423 .ops = &clk_branch_ops,
424 .flags = CLK_SET_RATE_PARENT,
429 static struct clk_branch csi2_phy_clk = {
433 .enable_reg = 0x022c,
434 .enable_mask = BIT(8),
435 .hw.init = &(struct clk_init_data){
436 .parent_names = (const char *[]){ "csi2_src" },
438 .name = "csi2_phy_clk",
439 .ops = &clk_branch_ops,
440 .flags = CLK_SET_RATE_PARENT,
450 struct clk_regmap clkr;
453 #define to_clk_pix_rdi(_hw) \
454 container_of(to_clk_regmap(_hw), struct clk_pix_rdi, clkr)
456 static int pix_rdi_set_parent(struct clk_hw *hw, u8 index)
461 struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
462 struct clk *clk = hw->clk;
463 int num_parents = __clk_get_num_parents(hw->clk);
466 * These clocks select three inputs via two muxes. One mux selects
467 * between csi0 and csi1 and the second mux selects between that mux's
468 * output and csi2. The source and destination selections for each
469 * mux must be clocking for the switch to succeed so just turn on
470 * all three sources because it's easier than figuring out what source
471 * needs to be on at what time.
473 for (i = 0; i < num_parents; i++) {
474 ret = clk_prepare_enable(clk_get_parent_by_index(clk, i));
483 regmap_update_bits(rdi->clkr.regmap, rdi->s2_reg, rdi->s2_mask, val);
485 * Wait at least 6 cycles of slowest clock
486 * for the glitch-free MUX to fully switch sources.
494 regmap_update_bits(rdi->clkr.regmap, rdi->s_reg, rdi->s_mask, val);
496 * Wait at least 6 cycles of slowest clock
497 * for the glitch-free MUX to fully switch sources.
502 for (i--; i >= 0; i--)
503 clk_disable_unprepare(clk_get_parent_by_index(clk, i));
508 static u8 pix_rdi_get_parent(struct clk_hw *hw)
511 struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
514 regmap_read(rdi->clkr.regmap, rdi->s2_reg, &val);
515 if (val & rdi->s2_mask)
518 regmap_read(rdi->clkr.regmap, rdi->s_reg, &val);
519 if (val & rdi->s_mask)
525 static const struct clk_ops clk_ops_pix_rdi = {
526 .enable = clk_enable_regmap,
527 .disable = clk_disable_regmap,
528 .set_parent = pix_rdi_set_parent,
529 .get_parent = pix_rdi_get_parent,
530 .determine_rate = __clk_mux_determine_rate,
533 static const char *pix_rdi_parents[] = {
539 static struct clk_pix_rdi csi_pix_clk = {
545 .enable_reg = 0x0058,
546 .enable_mask = BIT(26),
547 .hw.init = &(struct clk_init_data){
548 .name = "csi_pix_clk",
549 .parent_names = pix_rdi_parents,
551 .ops = &clk_ops_pix_rdi,
556 static struct clk_pix_rdi csi_pix1_clk = {
562 .enable_reg = 0x0238,
563 .enable_mask = BIT(10),
564 .hw.init = &(struct clk_init_data){
565 .name = "csi_pix1_clk",
566 .parent_names = pix_rdi_parents,
568 .ops = &clk_ops_pix_rdi,
573 static struct clk_pix_rdi csi_rdi_clk = {
579 .enable_reg = 0x0058,
580 .enable_mask = BIT(13),
581 .hw.init = &(struct clk_init_data){
582 .name = "csi_rdi_clk",
583 .parent_names = pix_rdi_parents,
585 .ops = &clk_ops_pix_rdi,
590 static struct clk_pix_rdi csi_rdi1_clk = {
596 .enable_reg = 0x0238,
597 .enable_mask = BIT(2),
598 .hw.init = &(struct clk_init_data){
599 .name = "csi_rdi1_clk",
600 .parent_names = pix_rdi_parents,
602 .ops = &clk_ops_pix_rdi,
607 static struct clk_pix_rdi csi_rdi2_clk = {
613 .enable_reg = 0x0238,
614 .enable_mask = BIT(6),
615 .hw.init = &(struct clk_init_data){
616 .name = "csi_rdi2_clk",
617 .parent_names = pix_rdi_parents,
619 .ops = &clk_ops_pix_rdi,
624 static struct freq_tbl clk_tbl_csiphytimer[] = {
625 { 85330000, P_PLL8, 1, 2, 9 },
626 { 177780000, P_PLL2, 1, 2, 9 },
630 static struct clk_rcg csiphytimer_src = {
635 .mnctr_reset_bit = 8,
637 .mnctr_mode_shift = 6,
648 .parent_map = mmcc_pxo_pll8_pll2_map,
650 .freq_tbl = clk_tbl_csiphytimer,
652 .enable_reg = 0x0160,
653 .enable_mask = BIT(2),
654 .hw.init = &(struct clk_init_data){
655 .name = "csiphytimer_src",
656 .parent_names = mmcc_pxo_pll8_pll2,
663 static const char *csixphy_timer_src[] = { "csiphytimer_src" };
665 static struct clk_branch csiphy0_timer_clk = {
669 .enable_reg = 0x0160,
670 .enable_mask = BIT(0),
671 .hw.init = &(struct clk_init_data){
672 .parent_names = csixphy_timer_src,
674 .name = "csiphy0_timer_clk",
675 .ops = &clk_branch_ops,
676 .flags = CLK_SET_RATE_PARENT,
681 static struct clk_branch csiphy1_timer_clk = {
685 .enable_reg = 0x0160,
686 .enable_mask = BIT(9),
687 .hw.init = &(struct clk_init_data){
688 .parent_names = csixphy_timer_src,
690 .name = "csiphy1_timer_clk",
691 .ops = &clk_branch_ops,
692 .flags = CLK_SET_RATE_PARENT,
697 static struct clk_branch csiphy2_timer_clk = {
701 .enable_reg = 0x0160,
702 .enable_mask = BIT(11),
703 .hw.init = &(struct clk_init_data){
704 .parent_names = csixphy_timer_src,
706 .name = "csiphy2_timer_clk",
707 .ops = &clk_branch_ops,
708 .flags = CLK_SET_RATE_PARENT,
713 static struct freq_tbl clk_tbl_gfx2d[] = {
714 F_MN( 27000000, P_PXO, 1, 0),
715 F_MN( 48000000, P_PLL8, 1, 8),
716 F_MN( 54857000, P_PLL8, 1, 7),
717 F_MN( 64000000, P_PLL8, 1, 6),
718 F_MN( 76800000, P_PLL8, 1, 5),
719 F_MN( 96000000, P_PLL8, 1, 4),
720 F_MN(128000000, P_PLL8, 1, 3),
721 F_MN(145455000, P_PLL2, 2, 11),
722 F_MN(160000000, P_PLL2, 1, 5),
723 F_MN(177778000, P_PLL2, 2, 9),
724 F_MN(200000000, P_PLL2, 1, 4),
725 F_MN(228571000, P_PLL2, 2, 7),
729 static struct clk_dyn_rcg gfx2d0_src = {
735 .mnctr_reset_bit = 25,
736 .mnctr_mode_shift = 9,
743 .mnctr_reset_bit = 24,
744 .mnctr_mode_shift = 6,
751 .parent_map = mmcc_pxo_pll8_pll2_map,
755 .parent_map = mmcc_pxo_pll8_pll2_map,
758 .freq_tbl = clk_tbl_gfx2d,
760 .enable_reg = 0x0060,
761 .enable_mask = BIT(2),
762 .hw.init = &(struct clk_init_data){
763 .name = "gfx2d0_src",
764 .parent_names = mmcc_pxo_pll8_pll2,
766 .ops = &clk_dyn_rcg_ops,
771 static struct clk_branch gfx2d0_clk = {
775 .enable_reg = 0x0060,
776 .enable_mask = BIT(0),
777 .hw.init = &(struct clk_init_data){
778 .name = "gfx2d0_clk",
779 .parent_names = (const char *[]){ "gfx2d0_src" },
781 .ops = &clk_branch_ops,
782 .flags = CLK_SET_RATE_PARENT,
787 static struct clk_dyn_rcg gfx2d1_src = {
793 .mnctr_reset_bit = 25,
794 .mnctr_mode_shift = 9,
801 .mnctr_reset_bit = 24,
802 .mnctr_mode_shift = 6,
809 .parent_map = mmcc_pxo_pll8_pll2_map,
813 .parent_map = mmcc_pxo_pll8_pll2_map,
816 .freq_tbl = clk_tbl_gfx2d,
818 .enable_reg = 0x0074,
819 .enable_mask = BIT(2),
820 .hw.init = &(struct clk_init_data){
821 .name = "gfx2d1_src",
822 .parent_names = mmcc_pxo_pll8_pll2,
824 .ops = &clk_dyn_rcg_ops,
829 static struct clk_branch gfx2d1_clk = {
833 .enable_reg = 0x0074,
834 .enable_mask = BIT(0),
835 .hw.init = &(struct clk_init_data){
836 .name = "gfx2d1_clk",
837 .parent_names = (const char *[]){ "gfx2d1_src" },
839 .ops = &clk_branch_ops,
840 .flags = CLK_SET_RATE_PARENT,
845 static struct freq_tbl clk_tbl_gfx3d[] = {
846 F_MN( 27000000, P_PXO, 1, 0),
847 F_MN( 48000000, P_PLL8, 1, 8),
848 F_MN( 54857000, P_PLL8, 1, 7),
849 F_MN( 64000000, P_PLL8, 1, 6),
850 F_MN( 76800000, P_PLL8, 1, 5),
851 F_MN( 96000000, P_PLL8, 1, 4),
852 F_MN(128000000, P_PLL8, 1, 3),
853 F_MN(145455000, P_PLL2, 2, 11),
854 F_MN(160000000, P_PLL2, 1, 5),
855 F_MN(177778000, P_PLL2, 2, 9),
856 F_MN(200000000, P_PLL2, 1, 4),
857 F_MN(228571000, P_PLL2, 2, 7),
858 F_MN(266667000, P_PLL2, 1, 3),
859 F_MN(300000000, P_PLL3, 1, 4),
860 F_MN(320000000, P_PLL2, 2, 5),
861 F_MN(400000000, P_PLL2, 1, 2),
865 static struct clk_dyn_rcg gfx3d_src = {
871 .mnctr_reset_bit = 25,
872 .mnctr_mode_shift = 9,
879 .mnctr_reset_bit = 24,
880 .mnctr_mode_shift = 6,
887 .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
891 .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
894 .freq_tbl = clk_tbl_gfx3d,
896 .enable_reg = 0x0080,
897 .enable_mask = BIT(2),
898 .hw.init = &(struct clk_init_data){
900 .parent_names = mmcc_pxo_pll8_pll2_pll3,
902 .ops = &clk_dyn_rcg_ops,
907 static struct clk_branch gfx3d_clk = {
911 .enable_reg = 0x0080,
912 .enable_mask = BIT(0),
913 .hw.init = &(struct clk_init_data){
915 .parent_names = (const char *[]){ "gfx3d_src" },
917 .ops = &clk_branch_ops,
918 .flags = CLK_SET_RATE_PARENT,
923 static struct freq_tbl clk_tbl_ijpeg[] = {
924 { 27000000, P_PXO, 1, 0, 0 },
925 { 36570000, P_PLL8, 1, 2, 21 },
926 { 54860000, P_PLL8, 7, 0, 0 },
927 { 96000000, P_PLL8, 4, 0, 0 },
928 { 109710000, P_PLL8, 1, 2, 7 },
929 { 128000000, P_PLL8, 3, 0, 0 },
930 { 153600000, P_PLL8, 1, 2, 5 },
931 { 200000000, P_PLL2, 4, 0, 0 },
932 { 228571000, P_PLL2, 1, 2, 7 },
933 { 266667000, P_PLL2, 1, 1, 3 },
934 { 320000000, P_PLL2, 1, 2, 5 },
938 static struct clk_rcg ijpeg_src = {
943 .mnctr_reset_bit = 7,
944 .mnctr_mode_shift = 6,
955 .parent_map = mmcc_pxo_pll8_pll2_map,
957 .freq_tbl = clk_tbl_ijpeg,
959 .enable_reg = 0x0098,
960 .enable_mask = BIT(2),
961 .hw.init = &(struct clk_init_data){
963 .parent_names = mmcc_pxo_pll8_pll2,
970 static struct clk_branch ijpeg_clk = {
974 .enable_reg = 0x0098,
975 .enable_mask = BIT(0),
976 .hw.init = &(struct clk_init_data){
978 .parent_names = (const char *[]){ "ijpeg_src" },
980 .ops = &clk_branch_ops,
981 .flags = CLK_SET_RATE_PARENT,
986 static struct freq_tbl clk_tbl_jpegd[] = {
987 { 64000000, P_PLL8, 6 },
988 { 76800000, P_PLL8, 5 },
989 { 96000000, P_PLL8, 4 },
990 { 160000000, P_PLL2, 5 },
991 { 200000000, P_PLL2, 4 },
995 static struct clk_rcg jpegd_src = {
1003 .parent_map = mmcc_pxo_pll8_pll2_map,
1005 .freq_tbl = clk_tbl_jpegd,
1007 .enable_reg = 0x00a4,
1008 .enable_mask = BIT(2),
1009 .hw.init = &(struct clk_init_data){
1010 .name = "jpegd_src",
1011 .parent_names = mmcc_pxo_pll8_pll2,
1013 .ops = &clk_rcg_ops,
1018 static struct clk_branch jpegd_clk = {
1022 .enable_reg = 0x00a4,
1023 .enable_mask = BIT(0),
1024 .hw.init = &(struct clk_init_data){
1025 .name = "jpegd_clk",
1026 .parent_names = (const char *[]){ "jpegd_src" },
1028 .ops = &clk_branch_ops,
1029 .flags = CLK_SET_RATE_PARENT,
1034 static struct freq_tbl clk_tbl_mdp[] = {
1035 { 9600000, P_PLL8, 1, 1, 40 },
1036 { 13710000, P_PLL8, 1, 1, 28 },
1037 { 27000000, P_PXO, 1, 0, 0 },
1038 { 29540000, P_PLL8, 1, 1, 13 },
1039 { 34910000, P_PLL8, 1, 1, 11 },
1040 { 38400000, P_PLL8, 1, 1, 10 },
1041 { 59080000, P_PLL8, 1, 2, 13 },
1042 { 76800000, P_PLL8, 1, 1, 5 },
1043 { 85330000, P_PLL8, 1, 2, 9 },
1044 { 96000000, P_PLL8, 1, 1, 4 },
1045 { 128000000, P_PLL8, 1, 1, 3 },
1046 { 160000000, P_PLL2, 1, 1, 5 },
1047 { 177780000, P_PLL2, 1, 2, 9 },
1048 { 200000000, P_PLL2, 1, 1, 4 },
1049 { 228571000, P_PLL2, 1, 2, 7 },
1050 { 266667000, P_PLL2, 1, 1, 3 },
1054 static struct clk_dyn_rcg mdp_src = {
1056 .md_reg[0] = 0x00c4,
1057 .md_reg[1] = 0x00c8,
1060 .mnctr_reset_bit = 31,
1061 .mnctr_mode_shift = 9,
1068 .mnctr_reset_bit = 30,
1069 .mnctr_mode_shift = 6,
1076 .parent_map = mmcc_pxo_pll8_pll2_map,
1080 .parent_map = mmcc_pxo_pll8_pll2_map,
1083 .freq_tbl = clk_tbl_mdp,
1085 .enable_reg = 0x00c0,
1086 .enable_mask = BIT(2),
1087 .hw.init = &(struct clk_init_data){
1089 .parent_names = mmcc_pxo_pll8_pll2,
1091 .ops = &clk_dyn_rcg_ops,
1096 static struct clk_branch mdp_clk = {
1100 .enable_reg = 0x00c0,
1101 .enable_mask = BIT(0),
1102 .hw.init = &(struct clk_init_data){
1104 .parent_names = (const char *[]){ "mdp_src" },
1106 .ops = &clk_branch_ops,
1107 .flags = CLK_SET_RATE_PARENT,
1112 static struct clk_branch mdp_lut_clk = {
1116 .enable_reg = 0x016c,
1117 .enable_mask = BIT(0),
1118 .hw.init = &(struct clk_init_data){
1119 .parent_names = (const char *[]){ "mdp_clk" },
1121 .name = "mdp_lut_clk",
1122 .ops = &clk_branch_ops,
1123 .flags = CLK_SET_RATE_PARENT,
1128 static struct clk_branch mdp_vsync_clk = {
1132 .enable_reg = 0x0058,
1133 .enable_mask = BIT(6),
1134 .hw.init = &(struct clk_init_data){
1135 .name = "mdp_vsync_clk",
1136 .parent_names = (const char *[]){ "pxo" },
1138 .ops = &clk_branch_ops
1143 static struct freq_tbl clk_tbl_rot[] = {
1144 { 27000000, P_PXO, 1 },
1145 { 29540000, P_PLL8, 13 },
1146 { 32000000, P_PLL8, 12 },
1147 { 38400000, P_PLL8, 10 },
1148 { 48000000, P_PLL8, 8 },
1149 { 54860000, P_PLL8, 7 },
1150 { 64000000, P_PLL8, 6 },
1151 { 76800000, P_PLL8, 5 },
1152 { 96000000, P_PLL8, 4 },
1153 { 100000000, P_PLL2, 8 },
1154 { 114290000, P_PLL2, 7 },
1155 { 133330000, P_PLL2, 6 },
1156 { 160000000, P_PLL2, 5 },
1157 { 200000000, P_PLL2, 4 },
1161 static struct clk_dyn_rcg rot_src = {
1164 .pre_div_shift = 22,
1168 .pre_div_shift = 26,
1172 .src_sel_shift = 16,
1173 .parent_map = mmcc_pxo_pll8_pll2_map,
1176 .src_sel_shift = 19,
1177 .parent_map = mmcc_pxo_pll8_pll2_map,
1180 .freq_tbl = clk_tbl_rot,
1182 .enable_reg = 0x00e0,
1183 .enable_mask = BIT(2),
1184 .hw.init = &(struct clk_init_data){
1186 .parent_names = mmcc_pxo_pll8_pll2,
1188 .ops = &clk_dyn_rcg_ops,
1193 static struct clk_branch rot_clk = {
1197 .enable_reg = 0x00e0,
1198 .enable_mask = BIT(0),
1199 .hw.init = &(struct clk_init_data){
1201 .parent_names = (const char *[]){ "rot_src" },
1203 .ops = &clk_branch_ops,
1204 .flags = CLK_SET_RATE_PARENT,
1209 #define P_HDMI_PLL 1
1211 static u8 mmcc_pxo_hdmi_map[] = {
1216 static const char *mmcc_pxo_hdmi[] = {
1221 static struct freq_tbl clk_tbl_tv[] = {
1222 { 25200000, P_HDMI_PLL, 1, 0, 0 },
1223 { 27000000, P_HDMI_PLL, 1, 0, 0 },
1224 { 27030000, P_HDMI_PLL, 1, 0, 0 },
1225 { 74250000, P_HDMI_PLL, 1, 0, 0 },
1226 { 108000000, P_HDMI_PLL, 1, 0, 0 },
1227 { 148500000, P_HDMI_PLL, 1, 0, 0 },
1231 static struct clk_rcg tv_src = {
1236 .mnctr_reset_bit = 7,
1237 .mnctr_mode_shift = 6,
1243 .pre_div_shift = 14,
1248 .parent_map = mmcc_pxo_hdmi_map,
1250 .freq_tbl = clk_tbl_tv,
1252 .enable_reg = 0x00ec,
1253 .enable_mask = BIT(2),
1254 .hw.init = &(struct clk_init_data){
1256 .parent_names = mmcc_pxo_hdmi,
1258 .ops = &clk_rcg_ops,
1259 .flags = CLK_SET_RATE_PARENT,
1264 static const char *tv_src_name[] = { "tv_src" };
1266 static struct clk_branch tv_enc_clk = {
1270 .enable_reg = 0x00ec,
1271 .enable_mask = BIT(8),
1272 .hw.init = &(struct clk_init_data){
1273 .parent_names = tv_src_name,
1275 .name = "tv_enc_clk",
1276 .ops = &clk_branch_ops,
1277 .flags = CLK_SET_RATE_PARENT,
1282 static struct clk_branch tv_dac_clk = {
1286 .enable_reg = 0x00ec,
1287 .enable_mask = BIT(10),
1288 .hw.init = &(struct clk_init_data){
1289 .parent_names = tv_src_name,
1291 .name = "tv_dac_clk",
1292 .ops = &clk_branch_ops,
1293 .flags = CLK_SET_RATE_PARENT,
1298 static struct clk_branch mdp_tv_clk = {
1302 .enable_reg = 0x00ec,
1303 .enable_mask = BIT(0),
1304 .hw.init = &(struct clk_init_data){
1305 .parent_names = tv_src_name,
1307 .name = "mdp_tv_clk",
1308 .ops = &clk_branch_ops,
1309 .flags = CLK_SET_RATE_PARENT,
1314 static struct clk_branch hdmi_tv_clk = {
1318 .enable_reg = 0x00ec,
1319 .enable_mask = BIT(12),
1320 .hw.init = &(struct clk_init_data){
1321 .parent_names = tv_src_name,
1323 .name = "hdmi_tv_clk",
1324 .ops = &clk_branch_ops,
1325 .flags = CLK_SET_RATE_PARENT,
1330 static struct clk_branch hdmi_app_clk = {
1334 .enable_reg = 0x005c,
1335 .enable_mask = BIT(11),
1336 .hw.init = &(struct clk_init_data){
1337 .parent_names = (const char *[]){ "pxo" },
1339 .name = "hdmi_app_clk",
1340 .ops = &clk_branch_ops,
1345 static struct freq_tbl clk_tbl_vcodec[] = {
1346 F_MN( 27000000, P_PXO, 1, 0),
1347 F_MN( 32000000, P_PLL8, 1, 12),
1348 F_MN( 48000000, P_PLL8, 1, 8),
1349 F_MN( 54860000, P_PLL8, 1, 7),
1350 F_MN( 96000000, P_PLL8, 1, 4),
1351 F_MN(133330000, P_PLL2, 1, 6),
1352 F_MN(200000000, P_PLL2, 1, 4),
1353 F_MN(228570000, P_PLL2, 2, 7),
1354 F_MN(266670000, P_PLL2, 1, 3),
1358 static struct clk_dyn_rcg vcodec_src = {
1360 .md_reg[0] = 0x00fc,
1361 .md_reg[1] = 0x0128,
1364 .mnctr_reset_bit = 31,
1365 .mnctr_mode_shift = 6,
1372 .mnctr_reset_bit = 30,
1373 .mnctr_mode_shift = 11,
1379 .src_sel_shift = 27,
1380 .parent_map = mmcc_pxo_pll8_pll2_map,
1384 .parent_map = mmcc_pxo_pll8_pll2_map,
1387 .freq_tbl = clk_tbl_vcodec,
1389 .enable_reg = 0x00f8,
1390 .enable_mask = BIT(2),
1391 .hw.init = &(struct clk_init_data){
1392 .name = "vcodec_src",
1393 .parent_names = mmcc_pxo_pll8_pll2,
1395 .ops = &clk_dyn_rcg_ops,
1400 static struct clk_branch vcodec_clk = {
1404 .enable_reg = 0x00f8,
1405 .enable_mask = BIT(0),
1406 .hw.init = &(struct clk_init_data){
1407 .name = "vcodec_clk",
1408 .parent_names = (const char *[]){ "vcodec_src" },
1410 .ops = &clk_branch_ops,
1411 .flags = CLK_SET_RATE_PARENT,
1416 static struct freq_tbl clk_tbl_vpe[] = {
1417 { 27000000, P_PXO, 1 },
1418 { 34909000, P_PLL8, 11 },
1419 { 38400000, P_PLL8, 10 },
1420 { 64000000, P_PLL8, 6 },
1421 { 76800000, P_PLL8, 5 },
1422 { 96000000, P_PLL8, 4 },
1423 { 100000000, P_PLL2, 8 },
1424 { 160000000, P_PLL2, 5 },
1428 static struct clk_rcg vpe_src = {
1431 .pre_div_shift = 12,
1436 .parent_map = mmcc_pxo_pll8_pll2_map,
1438 .freq_tbl = clk_tbl_vpe,
1440 .enable_reg = 0x0110,
1441 .enable_mask = BIT(2),
1442 .hw.init = &(struct clk_init_data){
1444 .parent_names = mmcc_pxo_pll8_pll2,
1446 .ops = &clk_rcg_ops,
1451 static struct clk_branch vpe_clk = {
1455 .enable_reg = 0x0110,
1456 .enable_mask = BIT(0),
1457 .hw.init = &(struct clk_init_data){
1459 .parent_names = (const char *[]){ "vpe_src" },
1461 .ops = &clk_branch_ops,
1462 .flags = CLK_SET_RATE_PARENT,
1467 static struct freq_tbl clk_tbl_vfe[] = {
1468 { 13960000, P_PLL8, 1, 2, 55 },
1469 { 27000000, P_PXO, 1, 0, 0 },
1470 { 36570000, P_PLL8, 1, 2, 21 },
1471 { 38400000, P_PLL8, 2, 1, 5 },
1472 { 45180000, P_PLL8, 1, 2, 17 },
1473 { 48000000, P_PLL8, 2, 1, 4 },
1474 { 54860000, P_PLL8, 1, 1, 7 },
1475 { 64000000, P_PLL8, 2, 1, 3 },
1476 { 76800000, P_PLL8, 1, 1, 5 },
1477 { 96000000, P_PLL8, 2, 1, 2 },
1478 { 109710000, P_PLL8, 1, 2, 7 },
1479 { 128000000, P_PLL8, 1, 1, 3 },
1480 { 153600000, P_PLL8, 1, 2, 5 },
1481 { 200000000, P_PLL2, 2, 1, 2 },
1482 { 228570000, P_PLL2, 1, 2, 7 },
1483 { 266667000, P_PLL2, 1, 1, 3 },
1484 { 320000000, P_PLL2, 1, 2, 5 },
1488 static struct clk_rcg vfe_src = {
1492 .mnctr_reset_bit = 7,
1493 .mnctr_mode_shift = 6,
1499 .pre_div_shift = 10,
1504 .parent_map = mmcc_pxo_pll8_pll2_map,
1506 .freq_tbl = clk_tbl_vfe,
1508 .enable_reg = 0x0104,
1509 .enable_mask = BIT(2),
1510 .hw.init = &(struct clk_init_data){
1512 .parent_names = mmcc_pxo_pll8_pll2,
1514 .ops = &clk_rcg_ops,
1519 static struct clk_branch vfe_clk = {
1523 .enable_reg = 0x0104,
1524 .enable_mask = BIT(0),
1525 .hw.init = &(struct clk_init_data){
1527 .parent_names = (const char *[]){ "vfe_src" },
1529 .ops = &clk_branch_ops,
1530 .flags = CLK_SET_RATE_PARENT,
1535 static struct clk_branch vfe_csi_clk = {
1539 .enable_reg = 0x0104,
1540 .enable_mask = BIT(12),
1541 .hw.init = &(struct clk_init_data){
1542 .parent_names = (const char *[]){ "vfe_src" },
1544 .name = "vfe_csi_clk",
1545 .ops = &clk_branch_ops,
1546 .flags = CLK_SET_RATE_PARENT,
1551 static struct clk_branch gmem_axi_clk = {
1555 .enable_reg = 0x0018,
1556 .enable_mask = BIT(24),
1557 .hw.init = &(struct clk_init_data){
1558 .name = "gmem_axi_clk",
1559 .ops = &clk_branch_ops,
1560 .flags = CLK_IS_ROOT,
1565 static struct clk_branch ijpeg_axi_clk = {
1571 .enable_reg = 0x0018,
1572 .enable_mask = BIT(21),
1573 .hw.init = &(struct clk_init_data){
1574 .name = "ijpeg_axi_clk",
1575 .ops = &clk_branch_ops,
1576 .flags = CLK_IS_ROOT,
1581 static struct clk_branch mmss_imem_axi_clk = {
1587 .enable_reg = 0x0018,
1588 .enable_mask = BIT(22),
1589 .hw.init = &(struct clk_init_data){
1590 .name = "mmss_imem_axi_clk",
1591 .ops = &clk_branch_ops,
1592 .flags = CLK_IS_ROOT,
1597 static struct clk_branch jpegd_axi_clk = {
1601 .enable_reg = 0x0018,
1602 .enable_mask = BIT(25),
1603 .hw.init = &(struct clk_init_data){
1604 .name = "jpegd_axi_clk",
1605 .ops = &clk_branch_ops,
1606 .flags = CLK_IS_ROOT,
1611 static struct clk_branch vcodec_axi_b_clk = {
1617 .enable_reg = 0x0114,
1618 .enable_mask = BIT(23),
1619 .hw.init = &(struct clk_init_data){
1620 .name = "vcodec_axi_b_clk",
1621 .ops = &clk_branch_ops,
1622 .flags = CLK_IS_ROOT,
1627 static struct clk_branch vcodec_axi_a_clk = {
1633 .enable_reg = 0x0114,
1634 .enable_mask = BIT(25),
1635 .hw.init = &(struct clk_init_data){
1636 .name = "vcodec_axi_a_clk",
1637 .ops = &clk_branch_ops,
1638 .flags = CLK_IS_ROOT,
1643 static struct clk_branch vcodec_axi_clk = {
1649 .enable_reg = 0x0018,
1650 .enable_mask = BIT(19),
1651 .hw.init = &(struct clk_init_data){
1652 .name = "vcodec_axi_clk",
1653 .ops = &clk_branch_ops,
1654 .flags = CLK_IS_ROOT,
1659 static struct clk_branch vfe_axi_clk = {
1663 .enable_reg = 0x0018,
1664 .enable_mask = BIT(18),
1665 .hw.init = &(struct clk_init_data){
1666 .name = "vfe_axi_clk",
1667 .ops = &clk_branch_ops,
1668 .flags = CLK_IS_ROOT,
1673 static struct clk_branch mdp_axi_clk = {
1679 .enable_reg = 0x0018,
1680 .enable_mask = BIT(23),
1681 .hw.init = &(struct clk_init_data){
1682 .name = "mdp_axi_clk",
1683 .ops = &clk_branch_ops,
1684 .flags = CLK_IS_ROOT,
1689 static struct clk_branch rot_axi_clk = {
1695 .enable_reg = 0x0020,
1696 .enable_mask = BIT(24),
1697 .hw.init = &(struct clk_init_data){
1698 .name = "rot_axi_clk",
1699 .ops = &clk_branch_ops,
1700 .flags = CLK_IS_ROOT,
1705 static struct clk_branch vpe_axi_clk = {
1711 .enable_reg = 0x0020,
1712 .enable_mask = BIT(26),
1713 .hw.init = &(struct clk_init_data){
1714 .name = "vpe_axi_clk",
1715 .ops = &clk_branch_ops,
1716 .flags = CLK_IS_ROOT,
1721 static struct clk_branch gfx3d_axi_clk = {
1727 .enable_reg = 0x0244,
1728 .enable_mask = BIT(25),
1729 .hw.init = &(struct clk_init_data){
1730 .name = "gfx3d_axi_clk",
1731 .ops = &clk_branch_ops,
1732 .flags = CLK_IS_ROOT,
1737 static struct clk_branch amp_ahb_clk = {
1741 .enable_reg = 0x0008,
1742 .enable_mask = BIT(24),
1743 .hw.init = &(struct clk_init_data){
1744 .name = "amp_ahb_clk",
1745 .ops = &clk_branch_ops,
1746 .flags = CLK_IS_ROOT,
1751 static struct clk_branch csi_ahb_clk = {
1755 .enable_reg = 0x0008,
1756 .enable_mask = BIT(7),
1757 .hw.init = &(struct clk_init_data){
1758 .name = "csi_ahb_clk",
1759 .ops = &clk_branch_ops,
1760 .flags = CLK_IS_ROOT
1765 static struct clk_branch dsi_m_ahb_clk = {
1769 .enable_reg = 0x0008,
1770 .enable_mask = BIT(9),
1771 .hw.init = &(struct clk_init_data){
1772 .name = "dsi_m_ahb_clk",
1773 .ops = &clk_branch_ops,
1774 .flags = CLK_IS_ROOT,
1779 static struct clk_branch dsi_s_ahb_clk = {
1785 .enable_reg = 0x0008,
1786 .enable_mask = BIT(18),
1787 .hw.init = &(struct clk_init_data){
1788 .name = "dsi_s_ahb_clk",
1789 .ops = &clk_branch_ops,
1790 .flags = CLK_IS_ROOT,
1795 static struct clk_branch dsi2_m_ahb_clk = {
1799 .enable_reg = 0x0008,
1800 .enable_mask = BIT(17),
1801 .hw.init = &(struct clk_init_data){
1802 .name = "dsi2_m_ahb_clk",
1803 .ops = &clk_branch_ops,
1804 .flags = CLK_IS_ROOT
1809 static struct clk_branch dsi2_s_ahb_clk = {
1815 .enable_reg = 0x0008,
1816 .enable_mask = BIT(22),
1817 .hw.init = &(struct clk_init_data){
1818 .name = "dsi2_s_ahb_clk",
1819 .ops = &clk_branch_ops,
1820 .flags = CLK_IS_ROOT,
1825 static struct clk_branch gfx2d0_ahb_clk = {
1831 .enable_reg = 0x0008,
1832 .enable_mask = BIT(19),
1833 .hw.init = &(struct clk_init_data){
1834 .name = "gfx2d0_ahb_clk",
1835 .ops = &clk_branch_ops,
1836 .flags = CLK_IS_ROOT,
1841 static struct clk_branch gfx2d1_ahb_clk = {
1847 .enable_reg = 0x0008,
1848 .enable_mask = BIT(2),
1849 .hw.init = &(struct clk_init_data){
1850 .name = "gfx2d1_ahb_clk",
1851 .ops = &clk_branch_ops,
1852 .flags = CLK_IS_ROOT,
1857 static struct clk_branch gfx3d_ahb_clk = {
1863 .enable_reg = 0x0008,
1864 .enable_mask = BIT(3),
1865 .hw.init = &(struct clk_init_data){
1866 .name = "gfx3d_ahb_clk",
1867 .ops = &clk_branch_ops,
1868 .flags = CLK_IS_ROOT,
1873 static struct clk_branch hdmi_m_ahb_clk = {
1879 .enable_reg = 0x0008,
1880 .enable_mask = BIT(14),
1881 .hw.init = &(struct clk_init_data){
1882 .name = "hdmi_m_ahb_clk",
1883 .ops = &clk_branch_ops,
1884 .flags = CLK_IS_ROOT,
1889 static struct clk_branch hdmi_s_ahb_clk = {
1895 .enable_reg = 0x0008,
1896 .enable_mask = BIT(4),
1897 .hw.init = &(struct clk_init_data){
1898 .name = "hdmi_s_ahb_clk",
1899 .ops = &clk_branch_ops,
1900 .flags = CLK_IS_ROOT,
1905 static struct clk_branch ijpeg_ahb_clk = {
1909 .enable_reg = 0x0008,
1910 .enable_mask = BIT(5),
1911 .hw.init = &(struct clk_init_data){
1912 .name = "ijpeg_ahb_clk",
1913 .ops = &clk_branch_ops,
1914 .flags = CLK_IS_ROOT
1919 static struct clk_branch mmss_imem_ahb_clk = {
1925 .enable_reg = 0x0008,
1926 .enable_mask = BIT(6),
1927 .hw.init = &(struct clk_init_data){
1928 .name = "mmss_imem_ahb_clk",
1929 .ops = &clk_branch_ops,
1930 .flags = CLK_IS_ROOT
1935 static struct clk_branch jpegd_ahb_clk = {
1939 .enable_reg = 0x0008,
1940 .enable_mask = BIT(21),
1941 .hw.init = &(struct clk_init_data){
1942 .name = "jpegd_ahb_clk",
1943 .ops = &clk_branch_ops,
1944 .flags = CLK_IS_ROOT,
1949 static struct clk_branch mdp_ahb_clk = {
1953 .enable_reg = 0x0008,
1954 .enable_mask = BIT(10),
1955 .hw.init = &(struct clk_init_data){
1956 .name = "mdp_ahb_clk",
1957 .ops = &clk_branch_ops,
1958 .flags = CLK_IS_ROOT,
1963 static struct clk_branch rot_ahb_clk = {
1967 .enable_reg = 0x0008,
1968 .enable_mask = BIT(12),
1969 .hw.init = &(struct clk_init_data){
1970 .name = "rot_ahb_clk",
1971 .ops = &clk_branch_ops,
1972 .flags = CLK_IS_ROOT
1977 static struct clk_branch smmu_ahb_clk = {
1983 .enable_reg = 0x0008,
1984 .enable_mask = BIT(15),
1985 .hw.init = &(struct clk_init_data){
1986 .name = "smmu_ahb_clk",
1987 .ops = &clk_branch_ops,
1988 .flags = CLK_IS_ROOT,
1993 static struct clk_branch tv_enc_ahb_clk = {
1997 .enable_reg = 0x0008,
1998 .enable_mask = BIT(25),
1999 .hw.init = &(struct clk_init_data){
2000 .name = "tv_enc_ahb_clk",
2001 .ops = &clk_branch_ops,
2002 .flags = CLK_IS_ROOT,
2007 static struct clk_branch vcodec_ahb_clk = {
2013 .enable_reg = 0x0008,
2014 .enable_mask = BIT(11),
2015 .hw.init = &(struct clk_init_data){
2016 .name = "vcodec_ahb_clk",
2017 .ops = &clk_branch_ops,
2018 .flags = CLK_IS_ROOT,
2023 static struct clk_branch vfe_ahb_clk = {
2027 .enable_reg = 0x0008,
2028 .enable_mask = BIT(13),
2029 .hw.init = &(struct clk_init_data){
2030 .name = "vfe_ahb_clk",
2031 .ops = &clk_branch_ops,
2032 .flags = CLK_IS_ROOT,
2037 static struct clk_branch vpe_ahb_clk = {
2041 .enable_reg = 0x0008,
2042 .enable_mask = BIT(16),
2043 .hw.init = &(struct clk_init_data){
2044 .name = "vpe_ahb_clk",
2045 .ops = &clk_branch_ops,
2046 .flags = CLK_IS_ROOT,
2051 static struct clk_regmap *mmcc_msm8960_clks[] = {
2052 [TV_ENC_AHB_CLK] = &tv_enc_ahb_clk.clkr,
2053 [AMP_AHB_CLK] = &_ahb_clk.clkr,
2054 [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr,
2055 [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr,
2056 [GFX2D0_AHB_CLK] = &gfx2d0_ahb_clk.clkr,
2057 [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr,
2058 [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr,
2059 [VPE_AHB_CLK] = &vpe_ahb_clk.clkr,
2060 [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr,
2061 [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr,
2062 [VFE_AHB_CLK] = &vfe_ahb_clk.clkr,
2063 [ROT_AHB_CLK] = &rot_ahb_clk.clkr,
2064 [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr,
2065 [MDP_AHB_CLK] = &mdp_ahb_clk.clkr,
2066 [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr,
2067 [CSI_AHB_CLK] = &csi_ahb_clk.clkr,
2068 [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr,
2069 [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr,
2070 [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr,
2071 [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr,
2072 [GFX2D1_AHB_CLK] = &gfx2d1_ahb_clk.clkr,
2073 [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr,
2074 [GMEM_AXI_CLK] = &gmem_axi_clk.clkr,
2075 [MDP_AXI_CLK] = &mdp_axi_clk.clkr,
2076 [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr,
2077 [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr,
2078 [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr,
2079 [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr,
2080 [VFE_AXI_CLK] = &vfe_axi_clk.clkr,
2081 [VPE_AXI_CLK] = &vpe_axi_clk.clkr,
2082 [ROT_AXI_CLK] = &rot_axi_clk.clkr,
2083 [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr,
2084 [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr,
2085 [CSI0_SRC] = &csi0_src.clkr,
2086 [CSI0_CLK] = &csi0_clk.clkr,
2087 [CSI0_PHY_CLK] = &csi0_phy_clk.clkr,
2088 [CSI1_SRC] = &csi1_src.clkr,
2089 [CSI1_CLK] = &csi1_clk.clkr,
2090 [CSI1_PHY_CLK] = &csi1_phy_clk.clkr,
2091 [CSI2_SRC] = &csi2_src.clkr,
2092 [CSI2_CLK] = &csi2_clk.clkr,
2093 [CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
2094 [CSI_PIX_CLK] = &csi_pix_clk.clkr,
2095 [CSI_RDI_CLK] = &csi_rdi_clk.clkr,
2096 [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
2097 [HDMI_APP_CLK] = &hdmi_app_clk.clkr,
2098 [CSI_PIX1_CLK] = &csi_pix1_clk.clkr,
2099 [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr,
2100 [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr,
2101 [GFX2D0_SRC] = &gfx2d0_src.clkr,
2102 [GFX2D0_CLK] = &gfx2d0_clk.clkr,
2103 [GFX2D1_SRC] = &gfx2d1_src.clkr,
2104 [GFX2D1_CLK] = &gfx2d1_clk.clkr,
2105 [GFX3D_SRC] = &gfx3d_src.clkr,
2106 [GFX3D_CLK] = &gfx3d_clk.clkr,
2107 [IJPEG_SRC] = &ijpeg_src.clkr,
2108 [IJPEG_CLK] = &ijpeg_clk.clkr,
2109 [JPEGD_SRC] = &jpegd_src.clkr,
2110 [JPEGD_CLK] = &jpegd_clk.clkr,
2111 [MDP_SRC] = &mdp_src.clkr,
2112 [MDP_CLK] = &mdp_clk.clkr,
2113 [MDP_LUT_CLK] = &mdp_lut_clk.clkr,
2114 [ROT_SRC] = &rot_src.clkr,
2115 [ROT_CLK] = &rot_clk.clkr,
2116 [TV_ENC_CLK] = &tv_enc_clk.clkr,
2117 [TV_DAC_CLK] = &tv_dac_clk.clkr,
2118 [HDMI_TV_CLK] = &hdmi_tv_clk.clkr,
2119 [MDP_TV_CLK] = &mdp_tv_clk.clkr,
2120 [TV_SRC] = &tv_src.clkr,
2121 [VCODEC_SRC] = &vcodec_src.clkr,
2122 [VCODEC_CLK] = &vcodec_clk.clkr,
2123 [VFE_SRC] = &vfe_src.clkr,
2124 [VFE_CLK] = &vfe_clk.clkr,
2125 [VFE_CSI_CLK] = &vfe_csi_clk.clkr,
2126 [VPE_SRC] = &vpe_src.clkr,
2127 [VPE_CLK] = &vpe_clk.clkr,
2128 [CAMCLK0_SRC] = &camclk0_src.clkr,
2129 [CAMCLK0_CLK] = &camclk0_clk.clkr,
2130 [CAMCLK1_SRC] = &camclk1_src.clkr,
2131 [CAMCLK1_CLK] = &camclk1_clk.clkr,
2132 [CAMCLK2_SRC] = &camclk2_src.clkr,
2133 [CAMCLK2_CLK] = &camclk2_clk.clkr,
2134 [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr,
2135 [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr,
2136 [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr,
2137 [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr,
2138 [PLL2] = &pll2.clkr,
2141 static const struct qcom_reset_map mmcc_msm8960_resets[] = {
2142 [VPE_AXI_RESET] = { 0x0208, 15 },
2143 [IJPEG_AXI_RESET] = { 0x0208, 14 },
2144 [MPD_AXI_RESET] = { 0x0208, 13 },
2145 [VFE_AXI_RESET] = { 0x0208, 9 },
2146 [SP_AXI_RESET] = { 0x0208, 8 },
2147 [VCODEC_AXI_RESET] = { 0x0208, 7 },
2148 [ROT_AXI_RESET] = { 0x0208, 6 },
2149 [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
2150 [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
2151 [FAB_S3_AXI_RESET] = { 0x0208, 3 },
2152 [FAB_S2_AXI_RESET] = { 0x0208, 2 },
2153 [FAB_S1_AXI_RESET] = { 0x0208, 1 },
2154 [FAB_S0_AXI_RESET] = { 0x0208 },
2155 [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
2156 [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
2157 [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
2158 [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
2159 [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
2160 [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
2161 [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
2162 [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
2163 [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
2164 [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
2165 [SMMU_GFX2D0_AHB_RESET] = { 0x020c, 21 },
2166 [SMMU_GFX2D1_AHB_RESET] = { 0x020c, 20 },
2167 [APU_AHB_RESET] = { 0x020c, 18 },
2168 [CSI_AHB_RESET] = { 0x020c, 17 },
2169 [TV_ENC_AHB_RESET] = { 0x020c, 15 },
2170 [VPE_AHB_RESET] = { 0x020c, 14 },
2171 [FABRIC_AHB_RESET] = { 0x020c, 13 },
2172 [GFX2D0_AHB_RESET] = { 0x020c, 12 },
2173 [GFX2D1_AHB_RESET] = { 0x020c, 11 },
2174 [GFX3D_AHB_RESET] = { 0x020c, 10 },
2175 [HDMI_AHB_RESET] = { 0x020c, 9 },
2176 [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
2177 [IJPEG_AHB_RESET] = { 0x020c, 7 },
2178 [DSI_M_AHB_RESET] = { 0x020c, 6 },
2179 [DSI_S_AHB_RESET] = { 0x020c, 5 },
2180 [JPEGD_AHB_RESET] = { 0x020c, 4 },
2181 [MDP_AHB_RESET] = { 0x020c, 3 },
2182 [ROT_AHB_RESET] = { 0x020c, 2 },
2183 [VCODEC_AHB_RESET] = { 0x020c, 1 },
2184 [VFE_AHB_RESET] = { 0x020c, 0 },
2185 [DSI2_M_AHB_RESET] = { 0x0210, 31 },
2186 [DSI2_S_AHB_RESET] = { 0x0210, 30 },
2187 [CSIPHY2_RESET] = { 0x0210, 29 },
2188 [CSI_PIX1_RESET] = { 0x0210, 28 },
2189 [CSIPHY0_RESET] = { 0x0210, 27 },
2190 [CSIPHY1_RESET] = { 0x0210, 26 },
2191 [DSI2_RESET] = { 0x0210, 25 },
2192 [VFE_CSI_RESET] = { 0x0210, 24 },
2193 [MDP_RESET] = { 0x0210, 21 },
2194 [AMP_RESET] = { 0x0210, 20 },
2195 [JPEGD_RESET] = { 0x0210, 19 },
2196 [CSI1_RESET] = { 0x0210, 18 },
2197 [VPE_RESET] = { 0x0210, 17 },
2198 [MMSS_FABRIC_RESET] = { 0x0210, 16 },
2199 [VFE_RESET] = { 0x0210, 15 },
2200 [GFX2D0_RESET] = { 0x0210, 14 },
2201 [GFX2D1_RESET] = { 0x0210, 13 },
2202 [GFX3D_RESET] = { 0x0210, 12 },
2203 [HDMI_RESET] = { 0x0210, 11 },
2204 [MMSS_IMEM_RESET] = { 0x0210, 10 },
2205 [IJPEG_RESET] = { 0x0210, 9 },
2206 [CSI0_RESET] = { 0x0210, 8 },
2207 [DSI_RESET] = { 0x0210, 7 },
2208 [VCODEC_RESET] = { 0x0210, 6 },
2209 [MDP_TV_RESET] = { 0x0210, 4 },
2210 [MDP_VSYNC_RESET] = { 0x0210, 3 },
2211 [ROT_RESET] = { 0x0210, 2 },
2212 [TV_HDMI_RESET] = { 0x0210, 1 },
2213 [TV_ENC_RESET] = { 0x0210 },
2214 [CSI2_RESET] = { 0x0214, 2 },
2215 [CSI_RDI1_RESET] = { 0x0214, 1 },
2216 [CSI_RDI2_RESET] = { 0x0214 },
2219 static const struct regmap_config mmcc_msm8960_regmap_config = {
2223 .max_register = 0x334,
2227 static const struct of_device_id mmcc_msm8960_match_table[] = {
2228 { .compatible = "qcom,mmcc-msm8960" },
2231 MODULE_DEVICE_TABLE(of, mmcc_msm8960_match_table);
2234 struct qcom_reset_controller reset;
2235 struct clk_onecell_data data;
2239 static int mmcc_msm8960_probe(struct platform_device *pdev)
2242 struct resource *res;
2244 struct device *dev = &pdev->dev;
2246 struct clk_onecell_data *data;
2248 struct regmap *regmap;
2250 struct qcom_reset_controller *reset;
2253 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2254 base = devm_ioremap_resource(dev, res);
2256 return PTR_ERR(base);
2258 regmap = devm_regmap_init_mmio(dev, base, &mmcc_msm8960_regmap_config);
2260 return PTR_ERR(regmap);
2262 num_clks = ARRAY_SIZE(mmcc_msm8960_clks);
2263 cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks,
2271 data->clk_num = num_clks;
2273 for (i = 0; i < num_clks; i++) {
2274 if (!mmcc_msm8960_clks[i])
2276 clk = devm_clk_register_regmap(dev, mmcc_msm8960_clks[i]);
2278 return PTR_ERR(clk);
2282 ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, data);
2287 reset->rcdev.of_node = dev->of_node;
2288 reset->rcdev.ops = &qcom_reset_ops,
2289 reset->rcdev.owner = THIS_MODULE,
2290 reset->rcdev.nr_resets = ARRAY_SIZE(mmcc_msm8960_resets),
2291 reset->regmap = regmap;
2292 reset->reset_map = mmcc_msm8960_resets,
2293 platform_set_drvdata(pdev, &reset->rcdev);
2295 ret = reset_controller_register(&reset->rcdev);
2297 of_clk_del_provider(dev->of_node);
2302 static int mmcc_msm8960_remove(struct platform_device *pdev)
2304 of_clk_del_provider(pdev->dev.of_node);
2305 reset_controller_unregister(platform_get_drvdata(pdev));
2309 static struct platform_driver mmcc_msm8960_driver = {
2310 .probe = mmcc_msm8960_probe,
2311 .remove = mmcc_msm8960_remove,
2313 .name = "mmcc-msm8960",
2314 .owner = THIS_MODULE,
2315 .of_match_table = mmcc_msm8960_match_table,
2319 module_platform_driver(mmcc_msm8960_driver);
2321 MODULE_DESCRIPTION("QCOM MMCC MSM8960 Driver");
2322 MODULE_LICENSE("GPL v2");
2323 MODULE_ALIAS("platform:mmcc-msm8960");