drivers/clk/qcom/lpasscc-sc7280.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2021, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk-provider.h>
   7 #include <linux/platform_device.h>
   8 #include <linux/pm_clock.h>
   9 #include <linux/pm_runtime.h>
  10 #include <linux/module.h>
  11 #include <linux/of_address.h>
  12 #include <linux/regmap.h>
  13
  14 #include <dt-bindings/clock/qcom,lpass-sc7280.h>
  15
  16 #include "clk-regmap.h"
  17 #include "clk-branch.h"
  18 #include "common.h"
  19
  20 static struct clk_branch lpass_q6ss_ahbm_clk = {
  21         .halt_reg = 0x1c,
  22         .halt_check = BRANCH_HALT,
  23         .clkr = {
  24                 .enable_reg = 0x1c,
  25                 .enable_mask = BIT(0),
  26                 .hw.init = &(struct clk_init_data){
  27                         .name = "lpass_q6ss_ahbm_clk",
  28                         .ops = &clk_branch2_ops,
  29                 },
  30         },
  31 };
  32
  33 static struct clk_branch lpass_q6ss_ahbs_clk = {
  34         .halt_reg = 0x20,
  35         .halt_check = BRANCH_HALT_VOTED,
  36         .clkr = {
  37                 .enable_reg = 0x20,
  38                 .enable_mask = BIT(0),
  39                 .hw.init = &(struct clk_init_data){
  40                         .name = "lpass_q6ss_ahbs_clk",
  41                         .ops = &clk_branch2_ops,
  42                 },
  43         },
  44 };
  45
  46 static struct clk_branch lpass_top_cc_lpi_q6_axim_hs_clk = {
  47         .halt_reg = 0x0,
  48         .halt_check = BRANCH_HALT,
  49         .clkr = {
  50                 .enable_reg = 0x0,
  51                 .enable_mask = BIT(0),
  52                 .hw.init = &(struct clk_init_data){
  53                         .name = "lpass_top_cc_lpi_q6_axim_hs_clk",
  54                         .ops = &clk_branch2_ops,
  55                 },
  56         },
  57 };
  58
  59 static struct clk_branch lpass_qdsp6ss_core_clk = {
  60         .halt_reg = 0x20,
  61         /* CLK_OFF would not toggle until LPASS is out of reset */
  62         .halt_check = BRANCH_HALT_SKIP,
  63         .clkr = {
  64                 .enable_reg = 0x20,
  65                 .enable_mask = BIT(0),
  66                 .hw.init = &(struct clk_init_data){
  67                         .name = "lpass_qdsp6ss_core_clk",
  68                         .ops = &clk_branch2_ops,
  69                 },
  70         },
  71 };
  72
  73 static struct clk_branch lpass_qdsp6ss_xo_clk = {
  74         .halt_reg = 0x38,
  75         /* CLK_OFF would not toggle until LPASS is out of reset */
  76         .halt_check = BRANCH_HALT_SKIP,
  77         .clkr = {
  78                 .enable_reg = 0x38,
  79                 .enable_mask = BIT(0),
  80                 .hw.init = &(struct clk_init_data){
  81                         .name = "lpass_qdsp6ss_xo_clk",
  82                         .ops = &clk_branch2_ops,
  83                 },
  84         },
  85 };
  86
  87 static struct clk_branch lpass_qdsp6ss_sleep_clk = {
  88         .halt_reg = 0x3c,
  89         /* CLK_OFF would not toggle until LPASS is out of reset */
  90         .halt_check = BRANCH_HALT_SKIP,
  91         .clkr = {
  92                 .enable_reg = 0x3c,
  93                 .enable_mask = BIT(0),
  94                 .hw.init = &(struct clk_init_data){
  95                         .name = "lpass_qdsp6ss_sleep_clk",
  96                         .ops = &clk_branch2_ops,
  97                 },
  98         },
  99 };
 100
 101 static struct regmap_config lpass_regmap_config = {
 102         .reg_bits       = 32,
 103         .reg_stride     = 4,
 104         .val_bits       = 32,
 105         .fast_io        = true,
 106 };
 107
 108 static struct clk_regmap *lpass_cc_sc7280_clocks[] = {
 109         [LPASS_Q6SS_AHBM_CLK] = &lpass_q6ss_ahbm_clk.clkr,
 110         [LPASS_Q6SS_AHBS_CLK] = &lpass_q6ss_ahbs_clk.clkr,
 111 };
 112
 113 static const struct qcom_cc_desc lpass_cc_sc7280_desc = {
 114         .config = &lpass_regmap_config,
 115         .clks = lpass_cc_sc7280_clocks,
 116         .num_clks = ARRAY_SIZE(lpass_cc_sc7280_clocks),
 117 };
 118
 119 static struct clk_regmap *lpass_cc_top_sc7280_clocks[] = {
 120         [LPASS_TOP_CC_LPI_Q6_AXIM_HS_CLK] =
 121                                 &lpass_top_cc_lpi_q6_axim_hs_clk.clkr,
 122 };
 123
 124 static const struct qcom_cc_desc lpass_cc_top_sc7280_desc = {
 125         .config = &lpass_regmap_config,
 126         .clks = lpass_cc_top_sc7280_clocks,
 127         .num_clks = ARRAY_SIZE(lpass_cc_top_sc7280_clocks),
 128 };
 129
 130 static struct clk_regmap *lpass_qdsp6ss_sc7280_clocks[] = {
 131         [LPASS_QDSP6SS_XO_CLK] = &lpass_qdsp6ss_xo_clk.clkr,
 132         [LPASS_QDSP6SS_SLEEP_CLK] = &lpass_qdsp6ss_sleep_clk.clkr,
 133         [LPASS_QDSP6SS_CORE_CLK] = &lpass_qdsp6ss_core_clk.clkr,
 134 };
 135
 136 static const struct qcom_cc_desc lpass_qdsp6ss_sc7280_desc = {
 137         .config = &lpass_regmap_config,
 138         .clks = lpass_qdsp6ss_sc7280_clocks,
 139         .num_clks = ARRAY_SIZE(lpass_qdsp6ss_sc7280_clocks),
 140 };
 141
 142 static int lpass_cc_sc7280_probe(struct platform_device *pdev)
 143 {
 144         const struct qcom_cc_desc *desc;
 145         int ret;
 146
 147         pm_runtime_enable(&pdev->dev);
 148         ret = pm_clk_create(&pdev->dev);
 149         if (ret)
 150                 goto disable_pm_runtime;
 151
 152         ret = pm_clk_add(&pdev->dev, "iface");
 153         if (ret < 0) {
 154                 dev_err(&pdev->dev, "failed to acquire iface clock\n");
 155                 goto destroy_pm_clk;
 156         }
 157
 158         lpass_regmap_config.name = "qdsp6ss";
 159         desc = &lpass_qdsp6ss_sc7280_desc;
 160
 161         ret = qcom_cc_probe_by_index(pdev, 0, desc);
 162         if (ret)
 163                 goto destroy_pm_clk;
 164
 165         lpass_regmap_config.name = "top_cc";
 166         desc = &lpass_cc_top_sc7280_desc;
 167
 168         ret = qcom_cc_probe_by_index(pdev, 1, desc);
 169         if (ret)
 170                 goto destroy_pm_clk;
 171
 172         lpass_regmap_config.name = "cc";
 173         desc = &lpass_cc_sc7280_desc;
 174
 175         ret = qcom_cc_probe_by_index(pdev, 2, desc);
 176         if (ret)
 177                 goto destroy_pm_clk;
 178
 179         return 0;
 180
 181 destroy_pm_clk:
 182         pm_clk_destroy(&pdev->dev);
 183
 184 disable_pm_runtime:
 185         pm_runtime_disable(&pdev->dev);
 186
 187         return ret;
 188 }
 189
 190 static const struct of_device_id lpass_cc_sc7280_match_table[] = {
 191         { .compatible = "qcom,sc7280-lpasscc" },
 192         { }
 193 };
 194 MODULE_DEVICE_TABLE(of, lpass_cc_sc7280_match_table);
 195
 196 static struct platform_driver lpass_cc_sc7280_driver = {
 197         .probe          = lpass_cc_sc7280_probe,
 198         .driver         = {
 199                 .name   = "sc7280-lpasscc",
 200                 .of_match_table = lpass_cc_sc7280_match_table,
 201         },
 202 };
 203
 204 static int __init lpass_cc_sc7280_init(void)
 205 {
 206         return platform_driver_register(&lpass_cc_sc7280_driver);
 207 }
 208 subsys_initcall(lpass_cc_sc7280_init);
 209
 210 static void __exit lpass_cc_sc7280_exit(void)
 211 {
 212         platform_driver_unregister(&lpass_cc_sc7280_driver);
 213 }
 214 module_exit(lpass_cc_sc7280_exit);
 215
 216 MODULE_DESCRIPTION("QTI LPASS_CC SC7280 Driver");
 217 MODULE_LICENSE("GPL v2");