drivers/clk/qcom/lpasscc-sc7280.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2021, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk-provider.h>
   7 #include <linux/platform_device.h>
   8 #include <linux/pm_clock.h>
   9 #include <linux/pm_runtime.h>
  10 #include <linux/module.h>
  11 #include <linux/of_address.h>
  12 #include <linux/regmap.h>
  13
  14 #include <dt-bindings/clock/qcom,lpass-sc7280.h>
  15
  16 #include "clk-regmap.h"
  17 #include "clk-branch.h"
  18 #include "common.h"
  19
  20 static struct clk_branch lpass_top_cc_lpi_q6_axim_hs_clk = {
  21         .halt_reg = 0x0,
  22         .halt_check = BRANCH_HALT,
  23         .clkr = {
  24                 .enable_reg = 0x0,
  25                 .enable_mask = BIT(0),
  26                 .hw.init = &(struct clk_init_data){
  27                         .name = "lpass_top_cc_lpi_q6_axim_hs_clk",
  28                         .ops = &clk_branch2_ops,
  29                 },
  30         },
  31 };
  32
  33 static struct clk_branch lpass_qdsp6ss_core_clk = {
  34         .halt_reg = 0x20,
  35         /* CLK_OFF would not toggle until LPASS is out of reset */
  36         .halt_check = BRANCH_HALT_SKIP,
  37         .clkr = {
  38                 .enable_reg = 0x20,
  39                 .enable_mask = BIT(0),
  40                 .hw.init = &(struct clk_init_data){
  41                         .name = "lpass_qdsp6ss_core_clk",
  42                         .ops = &clk_branch2_ops,
  43                 },
  44         },
  45 };
  46
  47 static struct clk_branch lpass_qdsp6ss_xo_clk = {
  48         .halt_reg = 0x38,
  49         /* CLK_OFF would not toggle until LPASS is out of reset */
  50         .halt_check = BRANCH_HALT_SKIP,
  51         .clkr = {
  52                 .enable_reg = 0x38,
  53                 .enable_mask = BIT(0),
  54                 .hw.init = &(struct clk_init_data){
  55                         .name = "lpass_qdsp6ss_xo_clk",
  56                         .ops = &clk_branch2_ops,
  57                 },
  58         },
  59 };
  60
  61 static struct clk_branch lpass_qdsp6ss_sleep_clk = {
  62         .halt_reg = 0x3c,
  63         /* CLK_OFF would not toggle until LPASS is out of reset */
  64         .halt_check = BRANCH_HALT_SKIP,
  65         .clkr = {
  66                 .enable_reg = 0x3c,
  67                 .enable_mask = BIT(0),
  68                 .hw.init = &(struct clk_init_data){
  69                         .name = "lpass_qdsp6ss_sleep_clk",
  70                         .ops = &clk_branch2_ops,
  71                 },
  72         },
  73 };
  74
  75 static struct regmap_config lpass_regmap_config = {
  76         .reg_bits       = 32,
  77         .reg_stride     = 4,
  78         .val_bits       = 32,
  79         .fast_io        = true,
  80 };
  81
  82 static struct clk_regmap *lpass_cc_top_sc7280_clocks[] = {
  83         [LPASS_TOP_CC_LPI_Q6_AXIM_HS_CLK] =
  84                                 &lpass_top_cc_lpi_q6_axim_hs_clk.clkr,
  85 };
  86
  87 static const struct qcom_cc_desc lpass_cc_top_sc7280_desc = {
  88         .config = &lpass_regmap_config,
  89         .clks = lpass_cc_top_sc7280_clocks,
  90         .num_clks = ARRAY_SIZE(lpass_cc_top_sc7280_clocks),
  91 };
  92
  93 static struct clk_regmap *lpass_qdsp6ss_sc7280_clocks[] = {
  94         [LPASS_QDSP6SS_XO_CLK] = &lpass_qdsp6ss_xo_clk.clkr,
  95         [LPASS_QDSP6SS_SLEEP_CLK] = &lpass_qdsp6ss_sleep_clk.clkr,
  96         [LPASS_QDSP6SS_CORE_CLK] = &lpass_qdsp6ss_core_clk.clkr,
  97 };
  98
  99 static const struct qcom_cc_desc lpass_qdsp6ss_sc7280_desc = {
 100         .config = &lpass_regmap_config,
 101         .clks = lpass_qdsp6ss_sc7280_clocks,
 102         .num_clks = ARRAY_SIZE(lpass_qdsp6ss_sc7280_clocks),
 103 };
 104
 105 static int lpass_cc_sc7280_probe(struct platform_device *pdev)
 106 {
 107         const struct qcom_cc_desc *desc;
 108         int ret;
 109
 110         pm_runtime_enable(&pdev->dev);
 111         ret = pm_clk_create(&pdev->dev);
 112         if (ret)
 113                 goto disable_pm_runtime;
 114
 115         ret = pm_clk_add(&pdev->dev, "iface");
 116         if (ret < 0) {
 117                 dev_err(&pdev->dev, "failed to acquire iface clock\n");
 118                 goto destroy_pm_clk;
 119         }
 120
 121         lpass_regmap_config.name = "qdsp6ss";
 122         desc = &lpass_qdsp6ss_sc7280_desc;
 123
 124         ret = qcom_cc_probe_by_index(pdev, 0, desc);
 125         if (ret)
 126                 goto destroy_pm_clk;
 127
 128         lpass_regmap_config.name = "top_cc";
 129         desc = &lpass_cc_top_sc7280_desc;
 130
 131         ret = qcom_cc_probe_by_index(pdev, 1, desc);
 132         if (ret)
 133                 goto destroy_pm_clk;
 134
 135         return 0;
 136
 137 destroy_pm_clk:
 138         pm_clk_destroy(&pdev->dev);
 139
 140 disable_pm_runtime:
 141         pm_runtime_disable(&pdev->dev);
 142
 143         return ret;
 144 }
 145
 146 static const struct of_device_id lpass_cc_sc7280_match_table[] = {
 147         { .compatible = "qcom,sc7280-lpasscc" },
 148         { }
 149 };
 150 MODULE_DEVICE_TABLE(of, lpass_cc_sc7280_match_table);
 151
 152 static struct platform_driver lpass_cc_sc7280_driver = {
 153         .probe          = lpass_cc_sc7280_probe,
 154         .driver         = {
 155                 .name   = "sc7280-lpasscc",
 156                 .of_match_table = lpass_cc_sc7280_match_table,
 157         },
 158 };
 159
 160 static int __init lpass_cc_sc7280_init(void)
 161 {
 162         return platform_driver_register(&lpass_cc_sc7280_driver);
 163 }
 164 subsys_initcall(lpass_cc_sc7280_init);
 165
 166 static void __exit lpass_cc_sc7280_exit(void)
 167 {
 168         platform_driver_unregister(&lpass_cc_sc7280_driver);
 169 }
 170 module_exit(lpass_cc_sc7280_exit);
 171
 172 MODULE_DESCRIPTION("QTI LPASS_CC SC7280 Driver");
 173 MODULE_LICENSE("GPL v2");