drivers/clk/qcom/gcc-sm8150.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
   3
   4 #include <linux/kernel.h>
   5 #include <linux/bitops.h>
   6 #include <linux/err.h>
   7 #include <linux/platform_device.h>
   8 #include <linux/module.h>
   9 #include <linux/of.h>
  10 #include <linux/of_device.h>
  11 #include <linux/clk-provider.h>
  12 #include <linux/regmap.h>
  13 #include <linux/reset-controller.h>
  14
  15 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
  16
  17 #include "common.h"
  18 #include "clk-alpha-pll.h"
  19 #include "clk-branch.h"
  20 #include "clk-pll.h"
  21 #include "clk-rcg.h"
  22 #include "clk-regmap.h"
  23 #include "reset.h"
  24 #include "gdsc.h"
  25
  26 enum {
  27         P_BI_TCXO,
  28         P_AUD_REF_CLK,
  29         P_CORE_BI_PLL_TEST_SE,
  30         P_GPLL0_OUT_EVEN,
  31         P_GPLL0_OUT_MAIN,
  32         P_GPLL7_OUT_MAIN,
  33         P_GPLL9_OUT_MAIN,
  34         P_SLEEP_CLK,
  35 };
  36
  37 static const struct pll_vco trion_vco[] = {
  38         { 249600000, 2000000000, 0 },
  39 };
  40
  41 static struct clk_alpha_pll gpll0 = {
  42         .offset = 0x0,
  43         .vco_table = trion_vco,
  44         .num_vco = ARRAY_SIZE(trion_vco),
  45         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
  46         .clkr = {
  47                 .enable_reg = 0x52000,
  48                 .enable_mask = BIT(0),
  49                 .hw.init = &(struct clk_init_data){
  50                         .name = "gpll0",
  51                         .parent_data = &(const struct clk_parent_data){
  52                                 .fw_name = "bi_tcxo",
  53                                 .name = "bi_tcxo",
  54                         },
  55                         .num_parents = 1,
  56                         .ops = &clk_trion_fixed_pll_ops,
  57                 },
  58         },
  59 };
  60
  61 static const struct clk_div_table post_div_table_trion_even[] = {
  62         { 0x0, 1 },
  63         { 0x1, 2 },
  64         { 0x3, 4 },
  65         { 0x7, 8 },
  66         { }
  67 };
  68
  69 static struct clk_alpha_pll_postdiv gpll0_out_even = {
  70         .offset = 0x0,
  71         .post_div_shift = 8,
  72         .post_div_table = post_div_table_trion_even,
  73         .num_post_div = ARRAY_SIZE(post_div_table_trion_even),
  74         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
  75         .width = 4,
  76         .clkr.hw.init = &(struct clk_init_data){
  77                 .name = "gpll0_out_even",
  78                 .parent_data = &(const struct clk_parent_data){
  79                         .hw = &gpll0.clkr.hw,
  80                 },
  81                 .num_parents = 1,
  82                 .ops = &clk_trion_pll_postdiv_ops,
  83         },
  84 };
  85
  86 static struct clk_alpha_pll gpll7 = {
  87         .offset = 0x1a000,
  88         .vco_table = trion_vco,
  89         .num_vco = ARRAY_SIZE(trion_vco),
  90         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
  91         .clkr = {
  92                 .enable_reg = 0x52000,
  93                 .enable_mask = BIT(7),
  94                 .hw.init = &(struct clk_init_data){
  95                         .name = "gpll7",
  96                         .parent_data = &(const struct clk_parent_data){
  97                                 .fw_name = "bi_tcxo",
  98                                 .name = "bi_tcxo",
  99                         },
 100                         .num_parents = 1,
 101                         .ops = &clk_trion_fixed_pll_ops,
 102                 },
 103         },
 104 };
 105
 106 static struct clk_alpha_pll gpll9 = {
 107         .offset = 0x1c000,
 108         .vco_table = trion_vco,
 109         .num_vco = ARRAY_SIZE(trion_vco),
 110         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
 111         .clkr = {
 112                 .enable_reg = 0x52000,
 113                 .enable_mask = BIT(9),
 114                 .hw.init = &(struct clk_init_data){
 115                         .name = "gpll9",
 116                         .parent_data = &(const struct clk_parent_data){
 117                                 .fw_name = "bi_tcxo",
 118                                 .name = "bi_tcxo",
 119                         },
 120                         .num_parents = 1,
 121                         .ops = &clk_trion_fixed_pll_ops,
 122                 },
 123         },
 124 };
 125
 126 static const struct parent_map gcc_parent_map_0[] = {
 127         { P_BI_TCXO, 0 },
 128         { P_GPLL0_OUT_MAIN, 1 },
 129         { P_GPLL0_OUT_EVEN, 6 },
 130         { P_CORE_BI_PLL_TEST_SE, 7 },
 131 };
 132
 133 static const struct clk_parent_data gcc_parents_0[] = {
 134         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 135         { .hw = &gpll0.clkr.hw },
 136         { .hw = &gpll0_out_even.clkr.hw },
 137         { .fw_name = "core_bi_pll_test_se" },
 138 };
 139
 140 static const struct parent_map gcc_parent_map_1[] = {
 141         { P_BI_TCXO, 0 },
 142         { P_GPLL0_OUT_MAIN, 1 },
 143         { P_SLEEP_CLK, 5 },
 144         { P_GPLL0_OUT_EVEN, 6 },
 145         { P_CORE_BI_PLL_TEST_SE, 7 },
 146 };
 147
 148 static const struct clk_parent_data gcc_parents_1[] = {
 149         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 150         { .hw = &gpll0.clkr.hw },
 151         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 152         { .hw = &gpll0_out_even.clkr.hw },
 153         { .fw_name = "core_bi_pll_test_se" },
 154 };
 155
 156 static const struct parent_map gcc_parent_map_2[] = {
 157         { P_BI_TCXO, 0 },
 158         { P_SLEEP_CLK, 5 },
 159         { P_CORE_BI_PLL_TEST_SE, 7 },
 160 };
 161
 162 static const struct clk_parent_data gcc_parents_2[] = {
 163         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 164         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 165         { .fw_name = "core_bi_pll_test_se" },
 166 };
 167
 168 static const struct parent_map gcc_parent_map_3[] = {
 169         { P_BI_TCXO, 0 },
 170         { P_GPLL0_OUT_MAIN, 1 },
 171         { P_CORE_BI_PLL_TEST_SE, 7 },
 172 };
 173
 174 static const struct clk_parent_data gcc_parents_3[] = {
 175         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 176         { .hw = &gpll0.clkr.hw },
 177         { .fw_name = "core_bi_pll_test_se"},
 178 };
 179
 180 static const struct parent_map gcc_parent_map_4[] = {
 181         { P_BI_TCXO, 0 },
 182         { P_CORE_BI_PLL_TEST_SE, 7 },
 183 };
 184
 185 static const struct clk_parent_data gcc_parents_4[] = {
 186         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 187         { .fw_name = "core_bi_pll_test_se" },
 188 };
 189
 190 static const struct parent_map gcc_parent_map_5[] = {
 191         { P_BI_TCXO, 0 },
 192         { P_GPLL0_OUT_MAIN, 1 },
 193         { P_GPLL7_OUT_MAIN, 3 },
 194         { P_GPLL0_OUT_EVEN, 6 },
 195         { P_CORE_BI_PLL_TEST_SE, 7 },
 196 };
 197
 198 static const struct clk_parent_data gcc_parents_5[] = {
 199         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 200         { .hw = &gpll0.clkr.hw },
 201         { .hw = &gpll7.clkr.hw },
 202         { .hw = &gpll0_out_even.clkr.hw },
 203         { .fw_name = "core_bi_pll_test_se" },
 204 };
 205
 206 static const struct parent_map gcc_parent_map_6[] = {
 207         { P_BI_TCXO, 0 },
 208         { P_GPLL0_OUT_MAIN, 1 },
 209         { P_GPLL9_OUT_MAIN, 2 },
 210         { P_GPLL0_OUT_EVEN, 6 },
 211         { P_CORE_BI_PLL_TEST_SE, 7 },
 212 };
 213
 214 static const struct clk_parent_data gcc_parents_6[] = {
 215         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 216         { .hw = &gpll0.clkr.hw },
 217         { .hw = &gpll9.clkr.hw },
 218         { .hw = &gpll0_out_even.clkr.hw },
 219         { .fw_name = "core_bi_pll_test_se" },
 220 };
 221
 222 static const struct parent_map gcc_parent_map_7[] = {
 223         { P_BI_TCXO, 0 },
 224         { P_GPLL0_OUT_MAIN, 1 },
 225         { P_AUD_REF_CLK, 2 },
 226         { P_GPLL0_OUT_EVEN, 6 },
 227         { P_CORE_BI_PLL_TEST_SE, 7 },
 228 };
 229
 230 static const struct clk_parent_data gcc_parents_7[] = {
 231         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 232         { .hw = &gpll0.clkr.hw },
 233         { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" },
 234         { .hw = &gpll0_out_even.clkr.hw },
 235         { .fw_name = "core_bi_pll_test_se" },
 236 };
 237
 238 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
 239         F(19200000, P_BI_TCXO, 1, 0, 0),
 240         F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
 241         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 242         { }
 243 };
 244
 245 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
 246         .cmd_rcgr = 0x48014,
 247         .mnd_width = 0,
 248         .hid_width = 5,
 249         .parent_map = gcc_parent_map_0,
 250         .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
 251         .clkr.hw.init = &(struct clk_init_data){
 252                 .name = "gcc_cpuss_ahb_clk_src",
 253                 .parent_data = gcc_parents_0,
 254                 .num_parents = 4,
 255                 .flags = CLK_SET_RATE_PARENT,
 256                 .ops = &clk_rcg2_ops,
 257         },
 258 };
 259
 260 static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = {
 261         F(19200000, P_BI_TCXO, 1, 0, 0),
 262         F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
 263         F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
 264         F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
 265         { }
 266 };
 267
 268 static struct clk_rcg2 gcc_emac_ptp_clk_src = {
 269         .cmd_rcgr = 0x6038,
 270         .mnd_width = 0,
 271         .hid_width = 5,
 272         .parent_map = gcc_parent_map_5,
 273         .freq_tbl = ftbl_gcc_emac_ptp_clk_src,
 274         .clkr.hw.init = &(struct clk_init_data){
 275                 .name = "gcc_emac_ptp_clk_src",
 276                 .parent_data = gcc_parents_5,
 277                 .num_parents = 5,
 278                 .flags = CLK_SET_RATE_PARENT,
 279                 .ops = &clk_rcg2_ops,
 280         },
 281 };
 282
 283 static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = {
 284         F(2500000, P_BI_TCXO, 1, 25, 192),
 285         F(5000000, P_BI_TCXO, 1, 25, 96),
 286         F(19200000, P_BI_TCXO, 1, 0, 0),
 287         F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
 288         F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
 289         F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
 290         F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
 291         { }
 292 };
 293
 294 static struct clk_rcg2 gcc_emac_rgmii_clk_src = {
 295         .cmd_rcgr = 0x601c,
 296         .mnd_width = 8,
 297         .hid_width = 5,
 298         .parent_map = gcc_parent_map_5,
 299         .freq_tbl = ftbl_gcc_emac_rgmii_clk_src,
 300         .clkr.hw.init = &(struct clk_init_data){
 301                 .name = "gcc_emac_rgmii_clk_src",
 302                 .parent_data = gcc_parents_5,
 303                 .num_parents = 5,
 304                 .flags = CLK_SET_RATE_PARENT,
 305                 .ops = &clk_rcg2_ops,
 306         },
 307 };
 308
 309 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
 310         F(19200000, P_BI_TCXO, 1, 0, 0),
 311         F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
 312         F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
 313         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 314         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
 315         { }
 316 };
 317
 318 static struct clk_rcg2 gcc_gp1_clk_src = {
 319         .cmd_rcgr = 0x64004,
 320         .mnd_width = 8,
 321         .hid_width = 5,
 322         .parent_map = gcc_parent_map_1,
 323         .freq_tbl = ftbl_gcc_gp1_clk_src,
 324         .clkr.hw.init = &(struct clk_init_data){
 325                 .name = "gcc_gp1_clk_src",
 326                 .parent_data = gcc_parents_1,
 327                 .num_parents = 5,
 328                 .flags = CLK_SET_RATE_PARENT,
 329                 .ops = &clk_rcg2_ops,
 330         },
 331 };
 332
 333 static struct clk_rcg2 gcc_gp2_clk_src = {
 334         .cmd_rcgr = 0x65004,
 335         .mnd_width = 8,
 336         .hid_width = 5,
 337         .parent_map = gcc_parent_map_1,
 338         .freq_tbl = ftbl_gcc_gp1_clk_src,
 339         .clkr.hw.init = &(struct clk_init_data){
 340                 .name = "gcc_gp2_clk_src",
 341                 .parent_data = gcc_parents_1,
 342                 .num_parents = 5,
 343                 .flags = CLK_SET_RATE_PARENT,
 344                 .ops = &clk_rcg2_ops,
 345         },
 346 };
 347
 348 static struct clk_rcg2 gcc_gp3_clk_src = {
 349         .cmd_rcgr = 0x66004,
 350         .mnd_width = 8,
 351         .hid_width = 5,
 352         .parent_map = gcc_parent_map_1,
 353         .freq_tbl = ftbl_gcc_gp1_clk_src,
 354         .clkr.hw.init = &(struct clk_init_data){
 355                 .name = "gcc_gp3_clk_src",
 356                 .parent_data = gcc_parents_1,
 357                 .num_parents = 5,
 358                 .flags = CLK_SET_RATE_PARENT,
 359                 .ops = &clk_rcg2_ops,
 360         },
 361 };
 362
 363 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
 364         F(9600000, P_BI_TCXO, 2, 0, 0),
 365         F(19200000, P_BI_TCXO, 1, 0, 0),
 366         { }
 367 };
 368
 369 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
 370         .cmd_rcgr = 0x6b02c,
 371         .mnd_width = 16,
 372         .hid_width = 5,
 373         .parent_map = gcc_parent_map_2,
 374         .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 375         .clkr.hw.init = &(struct clk_init_data){
 376                 .name = "gcc_pcie_0_aux_clk_src",
 377                 .parent_data = gcc_parents_2,
 378                 .num_parents = 3,
 379                 .flags = CLK_SET_RATE_PARENT,
 380                 .ops = &clk_rcg2_ops,
 381         },
 382 };
 383
 384 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
 385         .cmd_rcgr = 0x8d02c,
 386         .mnd_width = 16,
 387         .hid_width = 5,
 388         .parent_map = gcc_parent_map_2,
 389         .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 390         .clkr.hw.init = &(struct clk_init_data){
 391                 .name = "gcc_pcie_1_aux_clk_src",
 392                 .parent_data = gcc_parents_2,
 393                 .num_parents = 3,
 394                 .flags = CLK_SET_RATE_PARENT,
 395                 .ops = &clk_rcg2_ops,
 396         },
 397 };
 398
 399 static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {
 400         F(19200000, P_BI_TCXO, 1, 0, 0),
 401         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 402         { }
 403 };
 404
 405 static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
 406         .cmd_rcgr = 0x6f014,
 407         .mnd_width = 0,
 408         .hid_width = 5,
 409         .parent_map = gcc_parent_map_0,
 410         .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
 411         .clkr.hw.init = &(struct clk_init_data){
 412                 .name = "gcc_pcie_phy_refgen_clk_src",
 413                 .parent_data = gcc_parents_0,
 414                 .num_parents = 4,
 415                 .flags = CLK_SET_RATE_PARENT,
 416                 .ops = &clk_rcg2_ops,
 417         },
 418 };
 419
 420 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
 421         F(9600000, P_BI_TCXO, 2, 0, 0),
 422         F(19200000, P_BI_TCXO, 1, 0, 0),
 423         F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
 424         { }
 425 };
 426
 427 static struct clk_rcg2 gcc_pdm2_clk_src = {
 428         .cmd_rcgr = 0x33010,
 429         .mnd_width = 0,
 430         .hid_width = 5,
 431         .parent_map = gcc_parent_map_0,
 432         .freq_tbl = ftbl_gcc_pdm2_clk_src,
 433         .clkr.hw.init = &(struct clk_init_data){
 434                 .name = "gcc_pdm2_clk_src",
 435                 .parent_data = gcc_parents_0,
 436                 .num_parents = 4,
 437                 .flags = CLK_SET_RATE_PARENT,
 438                 .ops = &clk_rcg2_ops,
 439         },
 440 };
 441
 442 static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
 443         F(19200000, P_BI_TCXO, 1, 0, 0),
 444         F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
 445         F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 446         F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
 447         { }
 448 };
 449
 450 static struct clk_rcg2 gcc_qspi_core_clk_src = {
 451         .cmd_rcgr = 0x4b008,
 452         .mnd_width = 0,
 453         .hid_width = 5,
 454         .parent_map = gcc_parent_map_0,
 455         .freq_tbl = ftbl_gcc_qspi_core_clk_src,
 456         .clkr.hw.init = &(struct clk_init_data){
 457                 .name = "gcc_qspi_core_clk_src",
 458                 .parent_data = gcc_parents_0,
 459                 .num_parents = 4,
 460                 .flags = CLK_SET_RATE_PARENT,
 461                 .ops = &clk_rcg2_ops,
 462         },
 463 };
 464
 465 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
 466         F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
 467         F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
 468         F(19200000, P_BI_TCXO, 1, 0, 0),
 469         F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
 470         F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
 471         F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
 472         F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
 473         F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
 474         F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
 475         F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
 476         F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
 477         F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
 478         F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
 479         F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
 480         F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75),
 481         { }
 482 };
 483
 484 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
 485         .cmd_rcgr = 0x17148,
 486         .mnd_width = 16,
 487         .hid_width = 5,
 488         .parent_map = gcc_parent_map_0,
 489         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 490         .clkr.hw.init = &(struct clk_init_data){
 491                 .name = "gcc_qupv3_wrap0_s0_clk_src",
 492                 .parent_data = gcc_parents_0,
 493                 .num_parents = 4,
 494                 .flags = CLK_SET_RATE_PARENT,
 495                 .ops = &clk_rcg2_ops,
 496         },
 497 };
 498
 499 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
 500         .cmd_rcgr = 0x17278,
 501         .mnd_width = 16,
 502         .hid_width = 5,
 503         .parent_map = gcc_parent_map_0,
 504         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 505         .clkr.hw.init = &(struct clk_init_data){
 506                 .name = "gcc_qupv3_wrap0_s1_clk_src",
 507                 .parent_data = gcc_parents_0,
 508                 .num_parents = 4,
 509                 .flags = CLK_SET_RATE_PARENT,
 510                 .ops = &clk_rcg2_ops,
 511         },
 512 };
 513
 514 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
 515         .cmd_rcgr = 0x173a8,
 516         .mnd_width = 16,
 517         .hid_width = 5,
 518         .parent_map = gcc_parent_map_0,
 519         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 520         .clkr.hw.init = &(struct clk_init_data){
 521                 .name = "gcc_qupv3_wrap0_s2_clk_src",
 522                 .parent_data = gcc_parents_0,
 523                 .num_parents = 4,
 524                 .flags = CLK_SET_RATE_PARENT,
 525                 .ops = &clk_rcg2_ops,
 526         },
 527 };
 528
 529 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
 530         .cmd_rcgr = 0x174d8,
 531         .mnd_width = 16,
 532         .hid_width = 5,
 533         .parent_map = gcc_parent_map_0,
 534         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 535         .clkr.hw.init = &(struct clk_init_data){
 536                 .name = "gcc_qupv3_wrap0_s3_clk_src",
 537                 .parent_data = gcc_parents_0,
 538                 .num_parents = 4,
 539                 .flags = CLK_SET_RATE_PARENT,
 540                 .ops = &clk_rcg2_ops,
 541         },
 542 };
 543
 544 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
 545         .cmd_rcgr = 0x17608,
 546         .mnd_width = 16,
 547         .hid_width = 5,
 548         .parent_map = gcc_parent_map_0,
 549         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 550         .clkr.hw.init = &(struct clk_init_data){
 551                 .name = "gcc_qupv3_wrap0_s4_clk_src",
 552                 .parent_data = gcc_parents_0,
 553                 .num_parents = 4,
 554                 .flags = CLK_SET_RATE_PARENT,
 555                 .ops = &clk_rcg2_ops,
 556         },
 557 };
 558
 559 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
 560         .cmd_rcgr = 0x17738,
 561         .mnd_width = 16,
 562         .hid_width = 5,
 563         .parent_map = gcc_parent_map_0,
 564         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 565         .clkr.hw.init = &(struct clk_init_data){
 566                 .name = "gcc_qupv3_wrap0_s5_clk_src",
 567                 .parent_data = gcc_parents_0,
 568                 .num_parents = 4,
 569                 .flags = CLK_SET_RATE_PARENT,
 570                 .ops = &clk_rcg2_ops,
 571         },
 572 };
 573
 574 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
 575         .cmd_rcgr = 0x17868,
 576         .mnd_width = 16,
 577         .hid_width = 5,
 578         .parent_map = gcc_parent_map_0,
 579         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 580         .clkr.hw.init = &(struct clk_init_data){
 581                 .name = "gcc_qupv3_wrap0_s6_clk_src",
 582                 .parent_data = gcc_parents_0,
 583                 .num_parents = 4,
 584                 .flags = CLK_SET_RATE_PARENT,
 585                 .ops = &clk_rcg2_ops,
 586         },
 587 };
 588
 589 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
 590         .cmd_rcgr = 0x17998,
 591         .mnd_width = 16,
 592         .hid_width = 5,
 593         .parent_map = gcc_parent_map_0,
 594         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 595         .clkr.hw.init = &(struct clk_init_data){
 596                 .name = "gcc_qupv3_wrap0_s7_clk_src",
 597                 .parent_data = gcc_parents_0,
 598                 .num_parents = 4,
 599                 .flags = CLK_SET_RATE_PARENT,
 600                 .ops = &clk_rcg2_ops,
 601         },
 602 };
 603
 604 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
 605         .cmd_rcgr = 0x18148,
 606         .mnd_width = 16,
 607         .hid_width = 5,
 608         .parent_map = gcc_parent_map_0,
 609         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 610         .clkr.hw.init = &(struct clk_init_data){
 611                 .name = "gcc_qupv3_wrap1_s0_clk_src",
 612                 .parent_data = gcc_parents_0,
 613                 .num_parents = 4,
 614                 .flags = CLK_SET_RATE_PARENT,
 615                 .ops = &clk_rcg2_ops,
 616         },
 617 };
 618
 619 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
 620         .cmd_rcgr = 0x18278,
 621         .mnd_width = 16,
 622         .hid_width = 5,
 623         .parent_map = gcc_parent_map_0,
 624         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 625         .clkr.hw.init = &(struct clk_init_data){
 626                 .name = "gcc_qupv3_wrap1_s1_clk_src",
 627                 .parent_data = gcc_parents_0,
 628                 .num_parents = 4,
 629                 .flags = CLK_SET_RATE_PARENT,
 630                 .ops = &clk_rcg2_ops,
 631         },
 632 };
 633
 634 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
 635         .cmd_rcgr = 0x183a8,
 636         .mnd_width = 16,
 637         .hid_width = 5,
 638         .parent_map = gcc_parent_map_0,
 639         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 640         .clkr.hw.init = &(struct clk_init_data){
 641                 .name = "gcc_qupv3_wrap1_s2_clk_src",
 642                 .parent_data = gcc_parents_0,
 643                 .num_parents = 4,
 644                 .flags = CLK_SET_RATE_PARENT,
 645                 .ops = &clk_rcg2_ops,
 646         },
 647 };
 648
 649 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
 650         .cmd_rcgr = 0x184d8,
 651         .mnd_width = 16,
 652         .hid_width = 5,
 653         .parent_map = gcc_parent_map_0,
 654         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 655         .clkr.hw.init = &(struct clk_init_data){
 656                 .name = "gcc_qupv3_wrap1_s3_clk_src",
 657                 .parent_data = gcc_parents_0,
 658                 .num_parents = 4,
 659                 .flags = CLK_SET_RATE_PARENT,
 660                 .ops = &clk_rcg2_ops,
 661         },
 662 };
 663
 664 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
 665         .cmd_rcgr = 0x18608,
 666         .mnd_width = 16,
 667         .hid_width = 5,
 668         .parent_map = gcc_parent_map_0,
 669         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 670         .clkr.hw.init = &(struct clk_init_data){
 671                 .name = "gcc_qupv3_wrap1_s4_clk_src",
 672                 .parent_data = gcc_parents_0,
 673                 .num_parents = 4,
 674                 .flags = CLK_SET_RATE_PARENT,
 675                 .ops = &clk_rcg2_ops,
 676         },
 677 };
 678
 679 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
 680         .cmd_rcgr = 0x18738,
 681         .mnd_width = 16,
 682         .hid_width = 5,
 683         .parent_map = gcc_parent_map_0,
 684         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 685         .clkr.hw.init = &(struct clk_init_data){
 686                 .name = "gcc_qupv3_wrap1_s5_clk_src",
 687                 .parent_data = gcc_parents_0,
 688                 .num_parents = 4,
 689                 .flags = CLK_SET_RATE_PARENT,
 690                 .ops = &clk_rcg2_ops,
 691         },
 692 };
 693
 694 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
 695         .cmd_rcgr = 0x1e148,
 696         .mnd_width = 16,
 697         .hid_width = 5,
 698         .parent_map = gcc_parent_map_0,
 699         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 700         .clkr.hw.init = &(struct clk_init_data){
 701                 .name = "gcc_qupv3_wrap2_s0_clk_src",
 702                 .parent_data = gcc_parents_0,
 703                 .num_parents = 4,
 704                 .flags = CLK_SET_RATE_PARENT,
 705                 .ops = &clk_rcg2_ops,
 706         },
 707 };
 708
 709 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
 710         .cmd_rcgr = 0x1e278,
 711         .mnd_width = 16,
 712         .hid_width = 5,
 713         .parent_map = gcc_parent_map_0,
 714         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 715         .clkr.hw.init = &(struct clk_init_data){
 716                 .name = "gcc_qupv3_wrap2_s1_clk_src",
 717                 .parent_data = gcc_parents_0,
 718                 .num_parents = 4,
 719                 .flags = CLK_SET_RATE_PARENT,
 720                 .ops = &clk_rcg2_ops,
 721         },
 722 };
 723
 724 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
 725         .cmd_rcgr = 0x1e3a8,
 726         .mnd_width = 16,
 727         .hid_width = 5,
 728         .parent_map = gcc_parent_map_0,
 729         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 730         .clkr.hw.init = &(struct clk_init_data){
 731                 .name = "gcc_qupv3_wrap2_s2_clk_src",
 732                 .parent_data = gcc_parents_0,
 733                 .num_parents = 4,
 734                 .flags = CLK_SET_RATE_PARENT,
 735                 .ops = &clk_rcg2_ops,
 736         },
 737 };
 738
 739 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
 740         .cmd_rcgr = 0x1e4d8,
 741         .mnd_width = 16,
 742         .hid_width = 5,
 743         .parent_map = gcc_parent_map_0,
 744         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 745         .clkr.hw.init = &(struct clk_init_data){
 746                 .name = "gcc_qupv3_wrap2_s3_clk_src",
 747                 .parent_data = gcc_parents_0,
 748                 .num_parents = 4,
 749                 .flags = CLK_SET_RATE_PARENT,
 750                 .ops = &clk_rcg2_ops,
 751         },
 752 };
 753
 754 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
 755         .cmd_rcgr = 0x1e608,
 756         .mnd_width = 16,
 757         .hid_width = 5,
 758         .parent_map = gcc_parent_map_0,
 759         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 760         .clkr.hw.init = &(struct clk_init_data){
 761                 .name = "gcc_qupv3_wrap2_s4_clk_src",
 762                 .parent_data = gcc_parents_0,
 763                 .num_parents = 4,
 764                 .flags = CLK_SET_RATE_PARENT,
 765                 .ops = &clk_rcg2_ops,
 766         },
 767 };
 768
 769 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
 770         .cmd_rcgr = 0x1e738,
 771         .mnd_width = 16,
 772         .hid_width = 5,
 773         .parent_map = gcc_parent_map_0,
 774         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 775         .clkr.hw.init = &(struct clk_init_data){
 776                 .name = "gcc_qupv3_wrap2_s5_clk_src",
 777                 .parent_data = gcc_parents_0,
 778                 .num_parents = 4,
 779                 .flags = CLK_SET_RATE_PARENT,
 780                 .ops = &clk_rcg2_ops,
 781         },
 782 };
 783
 784 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
 785         F(400000, P_BI_TCXO, 12, 1, 4),
 786         F(9600000, P_BI_TCXO, 2, 0, 0),
 787         F(19200000, P_BI_TCXO, 1, 0, 0),
 788         F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
 789         F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
 790         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 791         F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0),
 792         { }
 793 };
 794
 795 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
 796         .cmd_rcgr = 0x1400c,
 797         .mnd_width = 8,
 798         .hid_width = 5,
 799         .parent_map = gcc_parent_map_6,
 800         .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
 801         .clkr.hw.init = &(struct clk_init_data){
 802                 .name = "gcc_sdcc2_apps_clk_src",
 803                 .parent_data = gcc_parents_6,
 804                 .num_parents = 5,
 805                 .flags = CLK_SET_RATE_PARENT,
 806                 .ops = &clk_rcg2_floor_ops,
 807         },
 808 };
 809
 810 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
 811         F(400000, P_BI_TCXO, 12, 1, 4),
 812         F(9600000, P_BI_TCXO, 2, 0, 0),
 813         F(19200000, P_BI_TCXO, 1, 0, 0),
 814         F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
 815         F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
 816         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 817         { }
 818 };
 819
 820 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
 821         .cmd_rcgr = 0x1600c,
 822         .mnd_width = 8,
 823         .hid_width = 5,
 824         .parent_map = gcc_parent_map_3,
 825         .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
 826         .clkr.hw.init = &(struct clk_init_data){
 827                 .name = "gcc_sdcc4_apps_clk_src",
 828                 .parent_data = gcc_parents_3,
 829                 .num_parents = 3,
 830                 .flags = CLK_SET_RATE_PARENT,
 831                 .ops = &clk_rcg2_floor_ops,
 832         },
 833 };
 834
 835 static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {
 836         F(105495, P_BI_TCXO, 2, 1, 91),
 837         { }
 838 };
 839
 840 static struct clk_rcg2 gcc_tsif_ref_clk_src = {
 841         .cmd_rcgr = 0x36010,
 842         .mnd_width = 8,
 843         .hid_width = 5,
 844         .parent_map = gcc_parent_map_7,
 845         .freq_tbl = ftbl_gcc_tsif_ref_clk_src,
 846         .clkr.hw.init = &(struct clk_init_data){
 847                 .name = "gcc_tsif_ref_clk_src",
 848                 .parent_data = gcc_parents_7,
 849                 .num_parents = 5,
 850                 .flags = CLK_SET_RATE_PARENT,
 851                 .ops = &clk_rcg2_ops,
 852         },
 853 };
 854
 855 static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
 856         F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
 857         F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
 858         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 859         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
 860         F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
 861         { }
 862 };
 863
 864 static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
 865         .cmd_rcgr = 0x75020,
 866         .mnd_width = 8,
 867         .hid_width = 5,
 868         .parent_map = gcc_parent_map_0,
 869         .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
 870         .clkr.hw.init = &(struct clk_init_data){
 871                 .name = "gcc_ufs_card_axi_clk_src",
 872                 .parent_data = gcc_parents_0,
 873                 .num_parents = 4,
 874                 .flags = CLK_SET_RATE_PARENT,
 875                 .ops = &clk_rcg2_ops,
 876         },
 877 };
 878
 879 static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
 880         F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
 881         F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
 882         F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 883         F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
 884         { }
 885 };
 886
 887 static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
 888         .cmd_rcgr = 0x75060,
 889         .mnd_width = 0,
 890         .hid_width = 5,
 891         .parent_map = gcc_parent_map_0,
 892         .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
 893         .clkr.hw.init = &(struct clk_init_data){
 894                 .name = "gcc_ufs_card_ice_core_clk_src",
 895                 .parent_data = gcc_parents_0,
 896                 .num_parents = 4,
 897                 .flags = CLK_SET_RATE_PARENT,
 898                 .ops = &clk_rcg2_ops,
 899         },
 900 };
 901
 902 static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = {
 903         F(19200000, P_BI_TCXO, 1, 0, 0),
 904         { }
 905 };
 906
 907 static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
 908         .cmd_rcgr = 0x75094,
 909         .mnd_width = 0,
 910         .hid_width = 5,
 911         .parent_map = gcc_parent_map_4,
 912         .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
 913         .clkr.hw.init = &(struct clk_init_data){
 914                 .name = "gcc_ufs_card_phy_aux_clk_src",
 915                 .parent_data = gcc_parents_4,
 916                 .num_parents = 2,
 917                 .flags = CLK_SET_RATE_PARENT,
 918                 .ops = &clk_rcg2_ops,
 919         },
 920 };
 921
 922 static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = {
 923         F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
 924         F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
 925         F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 926         { }
 927 };
 928
 929 static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
 930         .cmd_rcgr = 0x75078,
 931         .mnd_width = 0,
 932         .hid_width = 5,
 933         .parent_map = gcc_parent_map_0,
 934         .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
 935         .clkr.hw.init = &(struct clk_init_data){
 936                 .name = "gcc_ufs_card_unipro_core_clk_src",
 937                 .parent_data = gcc_parents_0,
 938                 .num_parents = 4,
 939                 .flags = CLK_SET_RATE_PARENT,
 940                 .ops = &clk_rcg2_ops,
 941         },
 942 };
 943
 944 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
 945         F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
 946         F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
 947         F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
 948         F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 949         F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
 950         { }
 951 };
 952
 953 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
 954         .cmd_rcgr = 0x77020,
 955         .mnd_width = 8,
 956         .hid_width = 5,
 957         .parent_map = gcc_parent_map_0,
 958         .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
 959         .clkr.hw.init = &(struct clk_init_data){
 960                 .name = "gcc_ufs_phy_axi_clk_src",
 961                 .parent_data = gcc_parents_0,
 962                 .num_parents = 4,
 963                 .flags = CLK_SET_RATE_PARENT,
 964                 .ops = &clk_rcg2_ops,
 965         },
 966 };
 967
 968 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
 969         .cmd_rcgr = 0x77060,
 970         .mnd_width = 0,
 971         .hid_width = 5,
 972         .parent_map = gcc_parent_map_0,
 973         .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
 974         .clkr.hw.init = &(struct clk_init_data){
 975                 .name = "gcc_ufs_phy_ice_core_clk_src",
 976                 .parent_data = gcc_parents_0,
 977                 .num_parents = 4,
 978                 .flags = CLK_SET_RATE_PARENT,
 979                 .ops = &clk_rcg2_ops,
 980         },
 981 };
 982
 983 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
 984         .cmd_rcgr = 0x77094,
 985         .mnd_width = 0,
 986         .hid_width = 5,
 987         .parent_map = gcc_parent_map_4,
 988         .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 989         .clkr.hw.init = &(struct clk_init_data){
 990                 .name = "gcc_ufs_phy_phy_aux_clk_src",
 991                 .parent_data = gcc_parents_4,
 992                 .num_parents = 2,
 993                 .flags = CLK_SET_RATE_PARENT,
 994                 .ops = &clk_rcg2_ops,
 995         },
 996 };
 997
 998 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
 999         .cmd_rcgr = 0x77078,
1000         .mnd_width = 0,
1001         .hid_width = 5,
1002         .parent_map = gcc_parent_map_0,
1003         .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1004         .clkr.hw.init = &(struct clk_init_data){
1005                 .name = "gcc_ufs_phy_unipro_core_clk_src",
1006                 .parent_data = gcc_parents_0,
1007                 .num_parents = 4,
1008                 .flags = CLK_SET_RATE_PARENT,
1009                 .ops = &clk_rcg2_ops,
1010         },
1011 };
1012
1013 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1014         F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
1015         F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
1016         F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1017         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1018         F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1019         { }
1020 };
1021
1022 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1023         .cmd_rcgr = 0xf01c,
1024         .mnd_width = 8,
1025         .hid_width = 5,
1026         .parent_map = gcc_parent_map_0,
1027         .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1028         .clkr.hw.init = &(struct clk_init_data){
1029                 .name = "gcc_usb30_prim_master_clk_src",
1030                 .parent_data = gcc_parents_0,
1031                 .num_parents = 4,
1032                 .flags = CLK_SET_RATE_PARENT,
1033                 .ops = &clk_rcg2_ops,
1034         },
1035 };
1036
1037 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
1038         F(19200000, P_BI_TCXO, 1, 0, 0),
1039         F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
1040         F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
1041         { }
1042 };
1043
1044 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1045         .cmd_rcgr = 0xf034,
1046         .mnd_width = 0,
1047         .hid_width = 5,
1048         .parent_map = gcc_parent_map_0,
1049         .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1050         .clkr.hw.init = &(struct clk_init_data){
1051                 .name = "gcc_usb30_prim_mock_utmi_clk_src",
1052                 .parent_data = gcc_parents_0,
1053                 .num_parents = 4,
1054                 .flags = CLK_SET_RATE_PARENT,
1055                 .ops = &clk_rcg2_ops,
1056         },
1057 };
1058
1059 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
1060         .cmd_rcgr = 0x1001c,
1061         .mnd_width = 8,
1062         .hid_width = 5,
1063         .parent_map = gcc_parent_map_0,
1064         .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1065         .clkr.hw.init = &(struct clk_init_data){
1066                 .name = "gcc_usb30_sec_master_clk_src",
1067                 .parent_data = gcc_parents_0,
1068                 .num_parents = 4,
1069                 .flags = CLK_SET_RATE_PARENT,
1070                 .ops = &clk_rcg2_ops,
1071         },
1072 };
1073
1074 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
1075         .cmd_rcgr = 0x10034,
1076         .mnd_width = 0,
1077         .hid_width = 5,
1078         .parent_map = gcc_parent_map_0,
1079         .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1080         .clkr.hw.init = &(struct clk_init_data){
1081                 .name = "gcc_usb30_sec_mock_utmi_clk_src",
1082                 .parent_data = gcc_parents_0,
1083                 .num_parents = 4,
1084                 .flags = CLK_SET_RATE_PARENT,
1085                 .ops = &clk_rcg2_ops,
1086         },
1087 };
1088
1089 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1090         .cmd_rcgr = 0xf060,
1091         .mnd_width = 0,
1092         .hid_width = 5,
1093         .parent_map = gcc_parent_map_2,
1094         .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1095         .clkr.hw.init = &(struct clk_init_data){
1096                 .name = "gcc_usb3_prim_phy_aux_clk_src",
1097                 .parent_data = gcc_parents_2,
1098                 .num_parents = 3,
1099                 .flags = CLK_SET_RATE_PARENT,
1100                 .ops = &clk_rcg2_ops,
1101         },
1102 };
1103
1104 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
1105         .cmd_rcgr = 0x10060,
1106         .mnd_width = 0,
1107         .hid_width = 5,
1108         .parent_map = gcc_parent_map_2,
1109         .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1110         .clkr.hw.init = &(struct clk_init_data){
1111                 .name = "gcc_usb3_sec_phy_aux_clk_src",
1112                 .parent_data = gcc_parents_2,
1113                 .num_parents = 3,
1114                 .flags = CLK_SET_RATE_PARENT,
1115                 .ops = &clk_rcg2_ops,
1116         },
1117 };
1118
1119 static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
1120         .halt_reg = 0x90018,
1121         .halt_check = BRANCH_HALT,
1122         .clkr = {
1123                 .enable_reg = 0x90018,
1124                 .enable_mask = BIT(0),
1125                 .hw.init = &(struct clk_init_data){
1126                         .name = "gcc_aggre_noc_pcie_tbu_clk",
1127                         .ops = &clk_branch2_ops,
1128                 },
1129         },
1130 };
1131
1132 static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
1133         .halt_reg = 0x750c0,
1134         .halt_check = BRANCH_HALT,
1135         .hwcg_reg = 0x750c0,
1136         .hwcg_bit = 1,
1137         .clkr = {
1138                 .enable_reg = 0x750c0,
1139                 .enable_mask = BIT(0),
1140                 .hw.init = &(struct clk_init_data){
1141                         .name = "gcc_aggre_ufs_card_axi_clk",
1142                         .parent_hws = (const struct clk_hw *[]){
1143                                       &gcc_ufs_card_axi_clk_src.clkr.hw },
1144                         .num_parents = 1,
1145                         .flags = CLK_SET_RATE_PARENT,
1146                         .ops = &clk_branch2_ops,
1147                 },
1148         },
1149 };
1150
1151 static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = {
1152         .halt_reg = 0x750c0,
1153         .halt_check = BRANCH_HALT,
1154         .hwcg_reg = 0x750c0,
1155         .hwcg_bit = 1,
1156         .clkr = {
1157                 .enable_reg = 0x750c0,
1158                 .enable_mask = BIT(1),
1159                 .hw.init = &(struct clk_init_data){
1160                         .name = "gcc_aggre_ufs_card_axi_hw_ctl_clk",
1161                         .parent_hws = (const struct clk_hw *[]){
1162                                       &gcc_aggre_ufs_card_axi_clk.clkr.hw },
1163                         .num_parents = 1,
1164                         .flags = CLK_SET_RATE_PARENT,
1165                         .ops = &clk_branch_simple_ops,
1166                 },
1167         },
1168 };
1169
1170 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1171         .halt_reg = 0x770c0,
1172         .halt_check = BRANCH_HALT,
1173         .hwcg_reg = 0x770c0,
1174         .hwcg_bit = 1,
1175         .clkr = {
1176                 .enable_reg = 0x770c0,
1177                 .enable_mask = BIT(0),
1178                 .hw.init = &(struct clk_init_data){
1179                         .name = "gcc_aggre_ufs_phy_axi_clk",
1180                         .parent_hws = (const struct clk_hw *[]){
1181                                       &gcc_ufs_phy_axi_clk_src.clkr.hw },
1182                         .num_parents = 1,
1183                         .flags = CLK_SET_RATE_PARENT,
1184                         .ops = &clk_branch2_ops,
1185                 },
1186         },
1187 };
1188
1189 static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
1190         .halt_reg = 0x770c0,
1191         .halt_check = BRANCH_HALT,
1192         .hwcg_reg = 0x770c0,
1193         .hwcg_bit = 1,
1194         .clkr = {
1195                 .enable_reg = 0x770c0,
1196                 .enable_mask = BIT(1),
1197                 .hw.init = &(struct clk_init_data){
1198                         .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
1199                         .parent_hws = (const struct clk_hw *[]){
1200                                       &gcc_aggre_ufs_phy_axi_clk.clkr.hw },
1201                         .num_parents = 1,
1202                         .flags = CLK_SET_RATE_PARENT,
1203                         .ops = &clk_branch_simple_ops,
1204                 },
1205         },
1206 };
1207
1208 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1209         .halt_reg = 0xf07c,
1210         .halt_check = BRANCH_HALT,
1211         .clkr = {
1212                 .enable_reg = 0xf07c,
1213                 .enable_mask = BIT(0),
1214                 .hw.init = &(struct clk_init_data){
1215                         .name = "gcc_aggre_usb3_prim_axi_clk",
1216                         .parent_hws = (const struct clk_hw *[]){
1217                                       &gcc_usb30_prim_master_clk_src.clkr.hw },
1218                         .num_parents = 1,
1219                         .flags = CLK_SET_RATE_PARENT,
1220                         .ops = &clk_branch2_ops,
1221                 },
1222         },
1223 };
1224
1225 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
1226         .halt_reg = 0x1007c,
1227         .halt_check = BRANCH_HALT,
1228         .clkr = {
1229                 .enable_reg = 0x1007c,
1230                 .enable_mask = BIT(0),
1231                 .hw.init = &(struct clk_init_data){
1232                         .name = "gcc_aggre_usb3_sec_axi_clk",
1233                         .parent_hws = (const struct clk_hw *[]){
1234                                       &gcc_usb30_sec_master_clk_src.clkr.hw },
1235                         .num_parents = 1,
1236                         .flags = CLK_SET_RATE_PARENT,
1237                         .ops = &clk_branch2_ops,
1238                 },
1239         },
1240 };
1241
1242 static struct clk_branch gcc_boot_rom_ahb_clk = {
1243         .halt_reg = 0x38004,
1244         .halt_check = BRANCH_HALT_VOTED,
1245         .hwcg_reg = 0x38004,
1246         .hwcg_bit = 1,
1247         .clkr = {
1248                 .enable_reg = 0x52004,
1249                 .enable_mask = BIT(10),
1250                 .hw.init = &(struct clk_init_data){
1251                         .name = "gcc_boot_rom_ahb_clk",
1252                         .ops = &clk_branch2_ops,
1253                 },
1254         },
1255 };
1256
1257 /*
1258  * Clock ON depends on external parent 'config noc', so cant poll
1259  * delay and also mark as crtitical for camss boot
1260  */
1261 static struct clk_branch gcc_camera_ahb_clk = {
1262         .halt_reg = 0xb008,
1263         .halt_check = BRANCH_HALT_DELAY,
1264         .hwcg_reg = 0xb008,
1265         .hwcg_bit = 1,
1266         .clkr = {
1267                 .enable_reg = 0xb008,
1268                 .enable_mask = BIT(0),
1269                 .hw.init = &(struct clk_init_data){
1270                         .name = "gcc_camera_ahb_clk",
1271                         .flags = CLK_IS_CRITICAL,
1272                         .ops = &clk_branch2_ops,
1273                 },
1274         },
1275 };
1276
1277 static struct clk_branch gcc_camera_hf_axi_clk = {
1278         .halt_reg = 0xb030,
1279         .halt_check = BRANCH_HALT,
1280         .clkr = {
1281                 .enable_reg = 0xb030,
1282                 .enable_mask = BIT(0),
1283                 .hw.init = &(struct clk_init_data){
1284                         .name = "gcc_camera_hf_axi_clk",
1285                         .ops = &clk_branch2_ops,
1286                 },
1287         },
1288 };
1289
1290 static struct clk_branch gcc_camera_sf_axi_clk = {
1291         .halt_reg = 0xb034,
1292         .halt_check = BRANCH_HALT,
1293         .clkr = {
1294                 .enable_reg = 0xb034,
1295                 .enable_mask = BIT(0),
1296                 .hw.init = &(struct clk_init_data){
1297                         .name = "gcc_camera_sf_axi_clk",
1298                         .ops = &clk_branch2_ops,
1299                 },
1300         },
1301 };
1302
1303 /* XO critical input to camss, so no need to poll */
1304 static struct clk_branch gcc_camera_xo_clk = {
1305         .halt_reg = 0xb044,
1306         .halt_check = BRANCH_HALT_DELAY,
1307         .clkr = {
1308                 .enable_reg = 0xb044,
1309                 .enable_mask = BIT(0),
1310                 .hw.init = &(struct clk_init_data){
1311                         .name = "gcc_camera_xo_clk",
1312                         .flags = CLK_IS_CRITICAL,
1313                         .ops = &clk_branch2_ops,
1314                 },
1315         },
1316 };
1317
1318 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1319         .halt_reg = 0xf078,
1320         .halt_check = BRANCH_HALT,
1321         .clkr = {
1322                 .enable_reg = 0xf078,
1323                 .enable_mask = BIT(0),
1324                 .hw.init = &(struct clk_init_data){
1325                         .name = "gcc_cfg_noc_usb3_prim_axi_clk",
1326                         .parent_hws = (const struct clk_hw *[]){
1327                                       &gcc_usb30_prim_master_clk_src.clkr.hw },
1328                         .num_parents = 1,
1329                         .flags = CLK_SET_RATE_PARENT,
1330                         .ops = &clk_branch2_ops,
1331                 },
1332         },
1333 };
1334
1335 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
1336         .halt_reg = 0x10078,
1337         .halt_check = BRANCH_HALT,
1338         .clkr = {
1339                 .enable_reg = 0x10078,
1340                 .enable_mask = BIT(0),
1341                 .hw.init = &(struct clk_init_data){
1342                         .name = "gcc_cfg_noc_usb3_sec_axi_clk",
1343                         .parent_hws = (const struct clk_hw *[]){
1344                                       &gcc_usb30_sec_master_clk_src.clkr.hw },
1345                         .num_parents = 1,
1346                         .flags = CLK_SET_RATE_PARENT,
1347                         .ops = &clk_branch2_ops,
1348                 },
1349         },
1350 };
1351
1352 static struct clk_branch gcc_cpuss_ahb_clk = {
1353         .halt_reg = 0x48000,
1354         .halt_check = BRANCH_HALT_VOTED,
1355         .clkr = {
1356                 .enable_reg = 0x52004,
1357                 .enable_mask = BIT(21),
1358                 .hw.init = &(struct clk_init_data){
1359                         .name = "gcc_cpuss_ahb_clk",
1360                         .parent_hws = (const struct clk_hw *[]){
1361                                       &gcc_cpuss_ahb_clk_src.clkr.hw },
1362                         .num_parents = 1,
1363                          /* required for cpuss */
1364                         .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1365                         .ops = &clk_branch2_ops,
1366                 },
1367         },
1368 };
1369
1370 static struct clk_branch gcc_cpuss_dvm_bus_clk = {
1371         .halt_reg = 0x48190,
1372         .halt_check = BRANCH_HALT,
1373         .clkr = {
1374                 .enable_reg = 0x48190,
1375                 .enable_mask = BIT(0),
1376                 .hw.init = &(struct clk_init_data){
1377                         .name = "gcc_cpuss_dvm_bus_clk",
1378                          /* required for cpuss */
1379                         .flags = CLK_IS_CRITICAL,
1380                         .ops = &clk_branch2_ops,
1381                 },
1382         },
1383 };
1384
1385 static struct clk_branch gcc_cpuss_gnoc_clk = {
1386         .halt_reg = 0x48004,
1387         .halt_check = BRANCH_HALT_VOTED,
1388         .hwcg_reg = 0x48004,
1389         .hwcg_bit = 1,
1390         .clkr = {
1391                 .enable_reg = 0x52004,
1392                 .enable_mask = BIT(22),
1393                 .hw.init = &(struct clk_init_data){
1394                         .name = "gcc_cpuss_gnoc_clk",
1395                          /* required for cpuss */
1396                         .flags = CLK_IS_CRITICAL,
1397                         .ops = &clk_branch2_ops,
1398                 },
1399         },
1400 };
1401
1402 static struct clk_branch gcc_cpuss_rbcpr_clk = {
1403         .halt_reg = 0x48008,
1404         .halt_check = BRANCH_HALT,
1405         .clkr = {
1406                 .enable_reg = 0x48008,
1407                 .enable_mask = BIT(0),
1408                 .hw.init = &(struct clk_init_data){
1409                         .name = "gcc_cpuss_rbcpr_clk",
1410                         .ops = &clk_branch2_ops,
1411                 },
1412         },
1413 };
1414
1415 static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1416         .halt_reg = 0x71154,
1417         .halt_check = BRANCH_VOTED,
1418         .clkr = {
1419                 .enable_reg = 0x71154,
1420                 .enable_mask = BIT(0),
1421                 .hw.init = &(struct clk_init_data){
1422                         .name = "gcc_ddrss_gpu_axi_clk",
1423                         .ops = &clk_branch2_ops,
1424                 },
1425         },
1426 };
1427
1428 /*
1429  * Clock ON depends on external parent 'config noc', so cant poll
1430  * delay and also mark as crtitical for disp boot
1431  */
1432 static struct clk_branch gcc_disp_ahb_clk = {
1433         .halt_reg = 0xb00c,
1434         .halt_check = BRANCH_HALT_DELAY,
1435         .hwcg_reg = 0xb00c,
1436         .hwcg_bit = 1,
1437         .clkr = {
1438                 .enable_reg = 0xb00c,
1439                 .enable_mask = BIT(0),
1440                 .hw.init = &(struct clk_init_data){
1441                         .name = "gcc_disp_ahb_clk",
1442                         .flags = CLK_IS_CRITICAL,
1443                         .ops = &clk_branch2_ops,
1444                 },
1445         },
1446 };
1447
1448 static struct clk_branch gcc_disp_hf_axi_clk = {
1449         .halt_reg = 0xb038,
1450         .halt_check = BRANCH_HALT,
1451         .clkr = {
1452                 .enable_reg = 0xb038,
1453                 .enable_mask = BIT(0),
1454                 .hw.init = &(struct clk_init_data){
1455                         .name = "gcc_disp_hf_axi_clk",
1456                         .ops = &clk_branch2_ops,
1457                 },
1458         },
1459 };
1460
1461 static struct clk_branch gcc_disp_sf_axi_clk = {
1462         .halt_reg = 0xb03c,
1463         .halt_check = BRANCH_HALT,
1464         .clkr = {
1465                 .enable_reg = 0xb03c,
1466                 .enable_mask = BIT(0),
1467                 .hw.init = &(struct clk_init_data){
1468                         .name = "gcc_disp_sf_axi_clk",
1469                         .ops = &clk_branch2_ops,
1470                 },
1471         },
1472 };
1473
1474 /* XO critical input to disp, so no need to poll */
1475 static struct clk_branch gcc_disp_xo_clk = {
1476         .halt_reg = 0xb048,
1477         .halt_check = BRANCH_HALT_DELAY,
1478         .clkr = {
1479                 .enable_reg = 0xb048,
1480                 .enable_mask = BIT(0),
1481                 .hw.init = &(struct clk_init_data){
1482                         .name = "gcc_disp_xo_clk",
1483                         .flags = CLK_IS_CRITICAL,
1484                         .ops = &clk_branch2_ops,
1485                 },
1486         },
1487 };
1488
1489 static struct clk_branch gcc_emac_axi_clk = {
1490         .halt_reg = 0x6010,
1491         .halt_check = BRANCH_HALT,
1492         .clkr = {
1493                 .enable_reg = 0x6010,
1494                 .enable_mask = BIT(0),
1495                 .hw.init = &(struct clk_init_data){
1496                         .name = "gcc_emac_axi_clk",
1497                         .ops = &clk_branch2_ops,
1498                 },
1499         },
1500 };
1501
1502 static struct clk_branch gcc_emac_ptp_clk = {
1503         .halt_reg = 0x6034,
1504         .halt_check = BRANCH_HALT,
1505         .clkr = {
1506                 .enable_reg = 0x6034,
1507                 .enable_mask = BIT(0),
1508                 .hw.init = &(struct clk_init_data){
1509                         .name = "gcc_emac_ptp_clk",
1510                         .parent_hws = (const struct clk_hw *[]){
1511                                       &gcc_emac_ptp_clk_src.clkr.hw },
1512                         .num_parents = 1,
1513                         .flags = CLK_SET_RATE_PARENT,
1514                         .ops = &clk_branch2_ops,
1515                 },
1516         },
1517 };
1518
1519 static struct clk_branch gcc_emac_rgmii_clk = {
1520         .halt_reg = 0x6018,
1521         .halt_check = BRANCH_HALT,
1522         .clkr = {
1523                 .enable_reg = 0x6018,
1524                 .enable_mask = BIT(0),
1525                 .hw.init = &(struct clk_init_data){
1526                         .name = "gcc_emac_rgmii_clk",
1527                         .parent_hws = (const struct clk_hw *[]){
1528                                       &gcc_emac_rgmii_clk_src.clkr.hw },
1529                         .num_parents = 1,
1530                         .flags = CLK_SET_RATE_PARENT,
1531                         .ops = &clk_branch2_ops,
1532                 },
1533         },
1534 };
1535
1536 static struct clk_branch gcc_emac_slv_ahb_clk = {
1537         .halt_reg = 0x6014,
1538         .halt_check = BRANCH_HALT,
1539         .hwcg_reg = 0x6014,
1540         .hwcg_bit = 1,
1541         .clkr = {
1542                 .enable_reg = 0x6014,
1543                 .enable_mask = BIT(0),
1544                 .hw.init = &(struct clk_init_data){
1545                         .name = "gcc_emac_slv_ahb_clk",
1546                         .ops = &clk_branch2_ops,
1547                 },
1548         },
1549 };
1550
1551 static struct clk_branch gcc_gp1_clk = {
1552         .halt_reg = 0x64000,
1553         .halt_check = BRANCH_HALT,
1554         .clkr = {
1555                 .enable_reg = 0x64000,
1556                 .enable_mask = BIT(0),
1557                 .hw.init = &(struct clk_init_data){
1558                         .name = "gcc_gp1_clk",
1559                         .parent_hws = (const struct clk_hw *[]){
1560                                       &gcc_gp1_clk_src.clkr.hw },
1561                         .num_parents = 1,
1562                         .flags = CLK_SET_RATE_PARENT,
1563                         .ops = &clk_branch2_ops,
1564                 },
1565         },
1566 };
1567
1568 static struct clk_branch gcc_gp2_clk = {
1569         .halt_reg = 0x65000,
1570         .halt_check = BRANCH_HALT,
1571         .clkr = {
1572                 .enable_reg = 0x65000,
1573                 .enable_mask = BIT(0),
1574                 .hw.init = &(struct clk_init_data){
1575                         .name = "gcc_gp2_clk",
1576                         .parent_hws = (const struct clk_hw *[]){
1577                                       &gcc_gp2_clk_src.clkr.hw },
1578                         .num_parents = 1,
1579                         .flags = CLK_SET_RATE_PARENT,
1580                         .ops = &clk_branch2_ops,
1581                 },
1582         },
1583 };
1584
1585 static struct clk_branch gcc_gp3_clk = {
1586         .halt_reg = 0x66000,
1587         .halt_check = BRANCH_HALT,
1588         .clkr = {
1589                 .enable_reg = 0x66000,
1590                 .enable_mask = BIT(0),
1591                 .hw.init = &(struct clk_init_data){
1592                         .name = "gcc_gp3_clk",
1593                         .parent_hws = (const struct clk_hw *[]){
1594                                       &gcc_gp3_clk_src.clkr.hw },
1595                         .num_parents = 1,
1596                         .flags = CLK_SET_RATE_PARENT,
1597                         .ops = &clk_branch2_ops,
1598                 },
1599         },
1600 };
1601
1602 static struct clk_branch gcc_gpu_cfg_ahb_clk = {
1603         .halt_reg = 0x71004,
1604         .halt_check = BRANCH_HALT,
1605         .hwcg_reg = 0x71004,
1606         .hwcg_bit = 1,
1607         .clkr = {
1608                 .enable_reg = 0x71004,
1609                 .enable_mask = BIT(0),
1610                 .hw.init = &(struct clk_init_data){
1611                         .name = "gcc_gpu_cfg_ahb_clk",
1612                          /* required for gpu */
1613                         .flags = CLK_IS_CRITICAL,
1614                         .ops = &clk_branch2_ops,
1615                 },
1616         },
1617 };
1618
1619 static struct clk_branch gcc_gpu_gpll0_clk_src = {
1620         .clkr = {
1621                 .enable_reg = 0x52004,
1622                 .enable_mask = BIT(15),
1623                 .hw.init = &(struct clk_init_data){
1624                         .name = "gcc_gpu_gpll0_clk_src",
1625                         .parent_hws = (const struct clk_hw *[]){
1626                                 &gpll0.clkr.hw },
1627                         .num_parents = 1,
1628                         .flags = CLK_SET_RATE_PARENT,
1629                         .ops = &clk_branch2_ops,
1630                 },
1631         },
1632 };
1633
1634 static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1635         .clkr = {
1636                 .enable_reg = 0x52004,
1637                 .enable_mask = BIT(16),
1638                 .hw.init = &(struct clk_init_data){
1639                         .name = "gcc_gpu_gpll0_div_clk_src",
1640                         .parent_hws = (const struct clk_hw *[]){
1641                                 &gcc_gpu_gpll0_clk_src.clkr.hw },
1642                         .num_parents = 1,
1643                         .flags = CLK_SET_RATE_PARENT,
1644                         .ops = &clk_branch2_ops,
1645                 },
1646         },
1647 };
1648
1649 static struct clk_branch gcc_gpu_iref_clk = {
1650         .halt_reg = 0x8c010,
1651         .halt_check = BRANCH_HALT,
1652         .clkr = {
1653                 .enable_reg = 0x8c010,
1654                 .enable_mask = BIT(0),
1655                 .hw.init = &(struct clk_init_data){
1656                         .name = "gcc_gpu_iref_clk",
1657                         .ops = &clk_branch2_ops,
1658                 },
1659         },
1660 };
1661
1662 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1663         .halt_reg = 0x7100c,
1664         .halt_check = BRANCH_VOTED,
1665         .clkr = {
1666                 .enable_reg = 0x7100c,
1667                 .enable_mask = BIT(0),
1668                 .hw.init = &(struct clk_init_data){
1669                         .name = "gcc_gpu_memnoc_gfx_clk",
1670                         .ops = &clk_branch2_ops,
1671                 },
1672         },
1673 };
1674
1675 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1676         .halt_reg = 0x71018,
1677         .halt_check = BRANCH_HALT,
1678         .clkr = {
1679                 .enable_reg = 0x71018,
1680                 .enable_mask = BIT(0),
1681                 .hw.init = &(struct clk_init_data){
1682                         .name = "gcc_gpu_snoc_dvm_gfx_clk",
1683                         .ops = &clk_branch2_ops,
1684                 },
1685         },
1686 };
1687
1688 static struct clk_branch gcc_npu_at_clk = {
1689         .halt_reg = 0x4d010,
1690         .halt_check = BRANCH_VOTED,
1691         .clkr = {
1692                 .enable_reg = 0x4d010,
1693                 .enable_mask = BIT(0),
1694                 .hw.init = &(struct clk_init_data){
1695                         .name = "gcc_npu_at_clk",
1696                         .ops = &clk_branch2_ops,
1697                 },
1698         },
1699 };
1700
1701 static struct clk_branch gcc_npu_axi_clk = {
1702         .halt_reg = 0x4d008,
1703         .halt_check = BRANCH_VOTED,
1704         .clkr = {
1705                 .enable_reg = 0x4d008,
1706                 .enable_mask = BIT(0),
1707                 .hw.init = &(struct clk_init_data){
1708                         .name = "gcc_npu_axi_clk",
1709                         .ops = &clk_branch2_ops,
1710                 },
1711         },
1712 };
1713
1714 static struct clk_branch gcc_npu_cfg_ahb_clk = {
1715         .halt_reg = 0x4d004,
1716         .halt_check = BRANCH_HALT,
1717         .hwcg_reg = 0x4d004,
1718         .hwcg_bit = 1,
1719         .clkr = {
1720                 .enable_reg = 0x4d004,
1721                 .enable_mask = BIT(0),
1722                 .hw.init = &(struct clk_init_data){
1723                         .name = "gcc_npu_cfg_ahb_clk",
1724                          /* required for npu */
1725                         .flags = CLK_IS_CRITICAL,
1726                         .ops = &clk_branch2_ops,
1727                 },
1728         },
1729 };
1730
1731 static struct clk_branch gcc_npu_gpll0_clk_src = {
1732         .clkr = {
1733                 .enable_reg = 0x52004,
1734                 .enable_mask = BIT(18),
1735                 .hw.init = &(struct clk_init_data){
1736                         .name = "gcc_npu_gpll0_clk_src",
1737                         .parent_hws = (const struct clk_hw *[]){
1738                                 &gpll0.clkr.hw },
1739                         .num_parents = 1,
1740                         .flags = CLK_SET_RATE_PARENT,
1741                         .ops = &clk_branch2_ops,
1742                 },
1743         },
1744 };
1745
1746 static struct clk_branch gcc_npu_gpll0_div_clk_src = {
1747         .clkr = {
1748                 .enable_reg = 0x52004,
1749                 .enable_mask = BIT(19),
1750                 .hw.init = &(struct clk_init_data){
1751                         .name = "gcc_npu_gpll0_div_clk_src",
1752                         .parent_hws = (const struct clk_hw *[]){
1753                                 &gcc_npu_gpll0_clk_src.clkr.hw },
1754                         .num_parents = 1,
1755                         .flags = CLK_SET_RATE_PARENT,
1756                         .ops = &clk_branch2_ops,
1757                 },
1758         },
1759 };
1760
1761 static struct clk_branch gcc_npu_trig_clk = {
1762         .halt_reg = 0x4d00c,
1763         .halt_check = BRANCH_VOTED,
1764         .clkr = {
1765                 .enable_reg = 0x4d00c,
1766                 .enable_mask = BIT(0),
1767                 .hw.init = &(struct clk_init_data){
1768                         .name = "gcc_npu_trig_clk",
1769                         .ops = &clk_branch2_ops,
1770                 },
1771         },
1772 };
1773
1774 static struct clk_branch gcc_pcie0_phy_refgen_clk = {
1775         .halt_reg = 0x6f02c,
1776         .halt_check = BRANCH_HALT,
1777         .clkr = {
1778                 .enable_reg = 0x6f02c,
1779                 .enable_mask = BIT(0),
1780                 .hw.init = &(struct clk_init_data){
1781                         .name = "gcc_pcie0_phy_refgen_clk",
1782                         .parent_hws = (const struct clk_hw *[]){
1783                                       &gcc_pcie_phy_refgen_clk_src.clkr.hw },
1784                         .num_parents = 1,
1785                         .flags = CLK_SET_RATE_PARENT,
1786                         .ops = &clk_branch2_ops,
1787                 },
1788         },
1789 };
1790
1791 static struct clk_branch gcc_pcie1_phy_refgen_clk = {
1792         .halt_reg = 0x6f030,
1793         .halt_check = BRANCH_HALT,
1794         .clkr = {
1795                 .enable_reg = 0x6f030,
1796                 .enable_mask = BIT(0),
1797                 .hw.init = &(struct clk_init_data){
1798                         .name = "gcc_pcie1_phy_refgen_clk",
1799                         .parent_hws = (const struct clk_hw *[]){
1800                                       &gcc_pcie_phy_refgen_clk_src.clkr.hw },
1801                         .num_parents = 1,
1802                         .flags = CLK_SET_RATE_PARENT,
1803                         .ops = &clk_branch2_ops,
1804                 },
1805         },
1806 };
1807
1808 static struct clk_branch gcc_pcie_0_aux_clk = {
1809         .halt_reg = 0x6b020,
1810         .halt_check = BRANCH_HALT_VOTED,
1811         .clkr = {
1812                 .enable_reg = 0x5200c,
1813                 .enable_mask = BIT(3),
1814                 .hw.init = &(struct clk_init_data){
1815                         .name = "gcc_pcie_0_aux_clk",
1816                         .parent_hws = (const struct clk_hw *[]){
1817                                       &gcc_pcie_0_aux_clk_src.clkr.hw },
1818                         .num_parents = 1,
1819                         .flags = CLK_SET_RATE_PARENT,
1820                         .ops = &clk_branch2_ops,
1821                 },
1822         },
1823 };
1824
1825 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1826         .halt_reg = 0x6b01c,
1827         .halt_check = BRANCH_HALT_VOTED,
1828         .hwcg_reg = 0x6b01c,
1829         .hwcg_bit = 1,
1830         .clkr = {
1831                 .enable_reg = 0x5200c,
1832                 .enable_mask = BIT(2),
1833                 .hw.init = &(struct clk_init_data){
1834                         .name = "gcc_pcie_0_cfg_ahb_clk",
1835                         .ops = &clk_branch2_ops,
1836                 },
1837         },
1838 };
1839
1840 static struct clk_branch gcc_pcie_0_clkref_clk = {
1841         .halt_reg = 0x8c00c,
1842         .halt_check = BRANCH_HALT,
1843         .clkr = {
1844                 .enable_reg = 0x8c00c,
1845                 .enable_mask = BIT(0),
1846                 .hw.init = &(struct clk_init_data){
1847                         .name = "gcc_pcie_0_clkref_clk",
1848                         .ops = &clk_branch2_ops,
1849                 },
1850         },
1851 };
1852
1853 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1854         .halt_reg = 0x6b018,
1855         .halt_check = BRANCH_HALT_VOTED,
1856         .clkr = {
1857                 .enable_reg = 0x5200c,
1858                 .enable_mask = BIT(1),
1859                 .hw.init = &(struct clk_init_data){
1860                         .name = "gcc_pcie_0_mstr_axi_clk",
1861                         .ops = &clk_branch2_ops,
1862                 },
1863         },
1864 };
1865
1866 /* Clock ON depends on external parent 'PIPE' clock, so dont poll */
1867 static struct clk_branch gcc_pcie_0_pipe_clk = {
1868         .halt_reg = 0x6b024,
1869         .halt_check = BRANCH_HALT_DELAY,
1870         .clkr = {
1871                 .enable_reg = 0x5200c,
1872                 .enable_mask = BIT(4),
1873                 .hw.init = &(struct clk_init_data){
1874                         .name = "gcc_pcie_0_pipe_clk",
1875                         .ops = &clk_branch2_ops,
1876                 },
1877         },
1878 };
1879
1880 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1881         .halt_reg = 0x6b014,
1882         .halt_check = BRANCH_HALT_VOTED,
1883         .hwcg_reg = 0x6b014,
1884         .hwcg_bit = 1,
1885         .clkr = {
1886                 .enable_reg = 0x5200c,
1887                 .enable_mask = BIT(0),
1888                 .hw.init = &(struct clk_init_data){
1889                         .name = "gcc_pcie_0_slv_axi_clk",
1890                         .ops = &clk_branch2_ops,
1891                 },
1892         },
1893 };
1894
1895 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1896         .halt_reg = 0x6b010,
1897         .halt_check = BRANCH_HALT_VOTED,
1898         .clkr = {
1899                 .enable_reg = 0x5200c,
1900                 .enable_mask = BIT(5),
1901                 .hw.init = &(struct clk_init_data){
1902                         .name = "gcc_pcie_0_slv_q2a_axi_clk",
1903                         .ops = &clk_branch2_ops,
1904                 },
1905         },
1906 };
1907
1908 static struct clk_branch gcc_pcie_1_aux_clk = {
1909         .halt_reg = 0x8d020,
1910         .halt_check = BRANCH_HALT_VOTED,
1911         .clkr = {
1912                 .enable_reg = 0x52004,
1913                 .enable_mask = BIT(29),
1914                 .hw.init = &(struct clk_init_data){
1915                         .name = "gcc_pcie_1_aux_clk",
1916                         .parent_hws = (const struct clk_hw *[]){
1917                                       &gcc_pcie_1_aux_clk_src.clkr.hw },
1918                         .num_parents = 1,
1919                         .flags = CLK_SET_RATE_PARENT,
1920                         .ops = &clk_branch2_ops,
1921                 },
1922         },
1923 };
1924
1925 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1926         .halt_reg = 0x8d01c,
1927         .halt_check = BRANCH_HALT_VOTED,
1928         .hwcg_reg = 0x8d01c,
1929         .hwcg_bit = 1,
1930         .clkr = {
1931                 .enable_reg = 0x52004,
1932                 .enable_mask = BIT(28),
1933                 .hw.init = &(struct clk_init_data){
1934                         .name = "gcc_pcie_1_cfg_ahb_clk",
1935                         .ops = &clk_branch2_ops,
1936                 },
1937         },
1938 };
1939
1940 static struct clk_branch gcc_pcie_1_clkref_clk = {
1941         .halt_reg = 0x8c02c,
1942         .halt_check = BRANCH_HALT,
1943         .clkr = {
1944                 .enable_reg = 0x8c02c,
1945                 .enable_mask = BIT(0),
1946                 .hw.init = &(struct clk_init_data){
1947                         .name = "gcc_pcie_1_clkref_clk",
1948                         .ops = &clk_branch2_ops,
1949                 },
1950         },
1951 };
1952
1953 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1954         .halt_reg = 0x8d018,
1955         .halt_check = BRANCH_HALT_VOTED,
1956         .clkr = {
1957                 .enable_reg = 0x52004,
1958                 .enable_mask = BIT(27),
1959                 .hw.init = &(struct clk_init_data){
1960                         .name = "gcc_pcie_1_mstr_axi_clk",
1961                         .ops = &clk_branch2_ops,
1962                 },
1963         },
1964 };
1965
1966 /* Clock ON depends on external parent 'PIPE' clock, so dont poll */
1967 static struct clk_branch gcc_pcie_1_pipe_clk = {
1968         .halt_reg = 0x8d024,
1969         .halt_check = BRANCH_HALT_DELAY,
1970         .clkr = {
1971                 .enable_reg = 0x52004,
1972                 .enable_mask = BIT(30),
1973                 .hw.init = &(struct clk_init_data){
1974                         .name = "gcc_pcie_1_pipe_clk",
1975                         .ops = &clk_branch2_ops,
1976                 },
1977         },
1978 };
1979
1980 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1981         .halt_reg = 0x8d014,
1982         .halt_check = BRANCH_HALT_VOTED,
1983         .hwcg_reg = 0x8d014,
1984         .hwcg_bit = 1,
1985         .clkr = {
1986                 .enable_reg = 0x52004,
1987                 .enable_mask = BIT(26),
1988                 .hw.init = &(struct clk_init_data){
1989                         .name = "gcc_pcie_1_slv_axi_clk",
1990                         .ops = &clk_branch2_ops,
1991                 },
1992         },
1993 };
1994
1995 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
1996         .halt_reg = 0x8d010,
1997         .halt_check = BRANCH_HALT_VOTED,
1998         .clkr = {
1999                 .enable_reg = 0x52004,
2000                 .enable_mask = BIT(25),
2001                 .hw.init = &(struct clk_init_data){
2002                         .name = "gcc_pcie_1_slv_q2a_axi_clk",
2003                         .ops = &clk_branch2_ops,
2004                 },
2005         },
2006 };
2007
2008 static struct clk_branch gcc_pcie_phy_aux_clk = {
2009         .halt_reg = 0x6f004,
2010         .halt_check = BRANCH_HALT,
2011         .clkr = {
2012                 .enable_reg = 0x6f004,
2013                 .enable_mask = BIT(0),
2014                 .hw.init = &(struct clk_init_data){
2015                         .name = "gcc_pcie_phy_aux_clk",
2016                         .parent_hws = (const struct clk_hw *[]){
2017                                       &gcc_pcie_0_aux_clk_src.clkr.hw },
2018                         .num_parents = 1,
2019                         .flags = CLK_SET_RATE_PARENT,
2020                         .ops = &clk_branch2_ops,
2021                 },
2022         },
2023 };
2024
2025 static struct clk_branch gcc_pdm2_clk = {
2026         .halt_reg = 0x3300c,
2027         .halt_check = BRANCH_HALT,
2028         .clkr = {
2029                 .enable_reg = 0x3300c,
2030                 .enable_mask = BIT(0),
2031                 .hw.init = &(struct clk_init_data){
2032                         .name = "gcc_pdm2_clk",
2033                         .parent_hws = (const struct clk_hw *[]){
2034                                       &gcc_pdm2_clk_src.clkr.hw },
2035                         .num_parents = 1,
2036                         .flags = CLK_SET_RATE_PARENT,
2037                         .ops = &clk_branch2_ops,
2038                 },
2039         },
2040 };
2041
2042 static struct clk_branch gcc_pdm_ahb_clk = {
2043         .halt_reg = 0x33004,
2044         .halt_check = BRANCH_HALT,
2045         .hwcg_reg = 0x33004,
2046         .hwcg_bit = 1,
2047         .clkr = {
2048                 .enable_reg = 0x33004,
2049                 .enable_mask = BIT(0),
2050                 .hw.init = &(struct clk_init_data){
2051                         .name = "gcc_pdm_ahb_clk",
2052                         .ops = &clk_branch2_ops,
2053                 },
2054         },
2055 };
2056
2057 static struct clk_branch gcc_pdm_xo4_clk = {
2058         .halt_reg = 0x33008,
2059         .halt_check = BRANCH_HALT,
2060         .clkr = {
2061                 .enable_reg = 0x33008,
2062                 .enable_mask = BIT(0),
2063                 .hw.init = &(struct clk_init_data){
2064                         .name = "gcc_pdm_xo4_clk",
2065                         .ops = &clk_branch2_ops,
2066                 },
2067         },
2068 };
2069
2070 static struct clk_branch gcc_prng_ahb_clk = {
2071         .halt_reg = 0x34004,
2072         .halt_check = BRANCH_HALT_VOTED,
2073         .clkr = {
2074                 .enable_reg = 0x52004,
2075                 .enable_mask = BIT(13),
2076                 .hw.init = &(struct clk_init_data){
2077                         .name = "gcc_prng_ahb_clk",
2078                         .ops = &clk_branch2_ops,
2079                 },
2080         },
2081 };
2082
2083 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
2084         .halt_reg = 0xb018,
2085         .halt_check = BRANCH_HALT,
2086         .hwcg_reg = 0xb018,
2087         .hwcg_bit = 1,
2088         .clkr = {
2089                 .enable_reg = 0xb018,
2090                 .enable_mask = BIT(0),
2091                 .hw.init = &(struct clk_init_data){
2092                         .name = "gcc_qmip_camera_nrt_ahb_clk",
2093                         .ops = &clk_branch2_ops,
2094                 },
2095         },
2096 };
2097
2098 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
2099         .halt_reg = 0xb01c,
2100         .halt_check = BRANCH_HALT,
2101         .hwcg_reg = 0xb01c,
2102         .hwcg_bit = 1,
2103         .clkr = {
2104                 .enable_reg = 0xb01c,
2105                 .enable_mask = BIT(0),
2106                 .hw.init = &(struct clk_init_data){
2107                         .name = "gcc_qmip_camera_rt_ahb_clk",
2108                         .ops = &clk_branch2_ops,
2109                 },
2110         },
2111 };
2112
2113 static struct clk_branch gcc_qmip_disp_ahb_clk = {
2114         .halt_reg = 0xb020,
2115         .halt_check = BRANCH_HALT,
2116         .hwcg_reg = 0xb020,
2117         .hwcg_bit = 1,
2118         .clkr = {
2119                 .enable_reg = 0xb020,
2120                 .enable_mask = BIT(0),
2121                 .hw.init = &(struct clk_init_data){
2122                         .name = "gcc_qmip_disp_ahb_clk",
2123                         .ops = &clk_branch2_ops,
2124                 },
2125         },
2126 };
2127
2128 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
2129         .halt_reg = 0xb010,
2130         .halt_check = BRANCH_HALT,
2131         .hwcg_reg = 0xb010,
2132         .hwcg_bit = 1,
2133         .clkr = {
2134                 .enable_reg = 0xb010,
2135                 .enable_mask = BIT(0),
2136                 .hw.init = &(struct clk_init_data){
2137                         .name = "gcc_qmip_video_cvp_ahb_clk",
2138                         .ops = &clk_branch2_ops,
2139                 },
2140         },
2141 };
2142
2143 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
2144         .halt_reg = 0xb014,
2145         .halt_check = BRANCH_HALT,
2146         .hwcg_reg = 0xb014,
2147         .hwcg_bit = 1,
2148         .clkr = {
2149                 .enable_reg = 0xb014,
2150                 .enable_mask = BIT(0),
2151                 .hw.init = &(struct clk_init_data){
2152                         .name = "gcc_qmip_video_vcodec_ahb_clk",
2153                         .ops = &clk_branch2_ops,
2154                 },
2155         },
2156 };
2157
2158 static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
2159         .halt_reg = 0x4b000,
2160         .halt_check = BRANCH_HALT,
2161         .clkr = {
2162                 .enable_reg = 0x4b000,
2163                 .enable_mask = BIT(0),
2164                 .hw.init = &(struct clk_init_data){
2165                         .name = "gcc_qspi_cnoc_periph_ahb_clk",
2166                         .ops = &clk_branch2_ops,
2167                 },
2168         },
2169 };
2170
2171 static struct clk_branch gcc_qspi_core_clk = {
2172         .halt_reg = 0x4b004,
2173         .halt_check = BRANCH_HALT,
2174         .clkr = {
2175                 .enable_reg = 0x4b004,
2176                 .enable_mask = BIT(0),
2177                 .hw.init = &(struct clk_init_data){
2178                         .name = "gcc_qspi_core_clk",
2179                         .parent_hws = (const struct clk_hw *[]){
2180                                       &gcc_qspi_core_clk_src.clkr.hw },
2181                         .num_parents = 1,
2182                         .flags = CLK_SET_RATE_PARENT,
2183                         .ops = &clk_branch2_ops,
2184                 },
2185         },
2186 };
2187
2188 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2189         .halt_reg = 0x17144,
2190         .halt_check = BRANCH_HALT_VOTED,
2191         .clkr = {
2192                 .enable_reg = 0x5200c,
2193                 .enable_mask = BIT(10),
2194                 .hw.init = &(struct clk_init_data){
2195                         .name = "gcc_qupv3_wrap0_s0_clk",
2196                         .parent_hws = (const struct clk_hw *[]){
2197                                       &gcc_qupv3_wrap0_s0_clk_src.clkr.hw },
2198                         .num_parents = 1,
2199                         .flags = CLK_SET_RATE_PARENT,
2200                         .ops = &clk_branch2_ops,
2201                 },
2202         },
2203 };
2204
2205 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2206         .halt_reg = 0x17274,
2207         .halt_check = BRANCH_HALT_VOTED,
2208         .clkr = {
2209                 .enable_reg = 0x5200c,
2210                 .enable_mask = BIT(11),
2211                 .hw.init = &(struct clk_init_data){
2212                         .name = "gcc_qupv3_wrap0_s1_clk",
2213                         .parent_hws = (const struct clk_hw *[]){
2214                                       &gcc_qupv3_wrap0_s1_clk_src.clkr.hw },
2215                         .num_parents = 1,
2216                         .flags = CLK_SET_RATE_PARENT,
2217                         .ops = &clk_branch2_ops,
2218                 },
2219         },
2220 };
2221
2222 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2223         .halt_reg = 0x173a4,
2224         .halt_check = BRANCH_HALT_VOTED,
2225         .clkr = {
2226                 .enable_reg = 0x5200c,
2227                 .enable_mask = BIT(12),
2228                 .hw.init = &(struct clk_init_data){
2229                         .name = "gcc_qupv3_wrap0_s2_clk",
2230                         .parent_hws = (const struct clk_hw *[]){
2231                                       &gcc_qupv3_wrap0_s2_clk_src.clkr.hw },
2232                         .num_parents = 1,
2233                         .flags = CLK_SET_RATE_PARENT,
2234                         .ops = &clk_branch2_ops,
2235                 },
2236         },
2237 };
2238
2239 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2240         .halt_reg = 0x174d4,
2241         .halt_check = BRANCH_HALT_VOTED,
2242         .clkr = {
2243                 .enable_reg = 0x5200c,
2244                 .enable_mask = BIT(13),
2245                 .hw.init = &(struct clk_init_data){
2246                         .name = "gcc_qupv3_wrap0_s3_clk",
2247                         .parent_hws = (const struct clk_hw *[]){
2248                                       &gcc_qupv3_wrap0_s3_clk_src.clkr.hw },
2249                         .num_parents = 1,
2250                         .flags = CLK_SET_RATE_PARENT,
2251                         .ops = &clk_branch2_ops,
2252                 },
2253         },
2254 };
2255
2256 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2257         .halt_reg = 0x17604,
2258         .halt_check = BRANCH_HALT_VOTED,
2259         .clkr = {
2260                 .enable_reg = 0x5200c,
2261                 .enable_mask = BIT(14),
2262                 .hw.init = &(struct clk_init_data){
2263                         .name = "gcc_qupv3_wrap0_s4_clk",
2264                         .parent_hws = (const struct clk_hw *[]){
2265                                       &gcc_qupv3_wrap0_s4_clk_src.clkr.hw },
2266                         .num_parents = 1,
2267                         .flags = CLK_SET_RATE_PARENT,
2268                         .ops = &clk_branch2_ops,
2269                 },
2270         },
2271 };
2272
2273 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2274         .halt_reg = 0x17734,
2275         .halt_check = BRANCH_HALT_VOTED,
2276         .clkr = {
2277                 .enable_reg = 0x5200c,
2278                 .enable_mask = BIT(15),
2279                 .hw.init = &(struct clk_init_data){
2280                         .name = "gcc_qupv3_wrap0_s5_clk",
2281                         .parent_hws = (const struct clk_hw *[]){
2282                                       &gcc_qupv3_wrap0_s5_clk_src.clkr.hw },
2283                         .num_parents = 1,
2284                         .flags = CLK_SET_RATE_PARENT,
2285                         .ops = &clk_branch2_ops,
2286                 },
2287         },
2288 };
2289
2290 static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2291         .halt_reg = 0x17864,
2292         .halt_check = BRANCH_HALT_VOTED,
2293         .clkr = {
2294                 .enable_reg = 0x5200c,
2295                 .enable_mask = BIT(16),
2296                 .hw.init = &(struct clk_init_data){
2297                         .name = "gcc_qupv3_wrap0_s6_clk",
2298                         .parent_hws = (const struct clk_hw *[]){
2299                                       &gcc_qupv3_wrap0_s6_clk_src.clkr.hw },
2300                         .num_parents = 1,
2301                         .flags = CLK_SET_RATE_PARENT,
2302                         .ops = &clk_branch2_ops,
2303                 },
2304         },
2305 };
2306
2307 static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2308         .halt_reg = 0x17994,
2309         .halt_check = BRANCH_HALT_VOTED,
2310         .clkr = {
2311                 .enable_reg = 0x5200c,
2312                 .enable_mask = BIT(17),
2313                 .hw.init = &(struct clk_init_data){
2314                         .name = "gcc_qupv3_wrap0_s7_clk",
2315                         .parent_hws = (const struct clk_hw *[]){
2316                                       &gcc_qupv3_wrap0_s7_clk_src.clkr.hw },
2317                         .num_parents = 1,
2318                         .flags = CLK_SET_RATE_PARENT,
2319                         .ops = &clk_branch2_ops,
2320                 },
2321         },
2322 };
2323
2324 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2325         .halt_reg = 0x18144,
2326         .halt_check = BRANCH_HALT_VOTED,
2327         .clkr = {
2328                 .enable_reg = 0x5200c,
2329                 .enable_mask = BIT(22),
2330                 .hw.init = &(struct clk_init_data){
2331                         .name = "gcc_qupv3_wrap1_s0_clk",
2332                         .parent_hws = (const struct clk_hw *[]){
2333                                       &gcc_qupv3_wrap1_s0_clk_src.clkr.hw },
2334                         .num_parents = 1,
2335                         .flags = CLK_SET_RATE_PARENT,
2336                         .ops = &clk_branch2_ops,
2337                 },
2338         },
2339 };
2340
2341 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2342         .halt_reg = 0x18274,
2343         .halt_check = BRANCH_HALT_VOTED,
2344         .clkr = {
2345                 .enable_reg = 0x5200c,
2346                 .enable_mask = BIT(23),
2347                 .hw.init = &(struct clk_init_data){
2348                         .name = "gcc_qupv3_wrap1_s1_clk",
2349                         .parent_hws = (const struct clk_hw *[]){
2350                                       &gcc_qupv3_wrap1_s1_clk_src.clkr.hw },
2351                         .num_parents = 1,
2352                         .flags = CLK_SET_RATE_PARENT,
2353                         .ops = &clk_branch2_ops,
2354                 },
2355         },
2356 };
2357
2358 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2359         .halt_reg = 0x183a4,
2360         .halt_check = BRANCH_HALT_VOTED,
2361         .clkr = {
2362                 .enable_reg = 0x5200c,
2363                 .enable_mask = BIT(24),
2364                 .hw.init = &(struct clk_init_data){
2365                         .name = "gcc_qupv3_wrap1_s2_clk",
2366                         .parent_hws = (const struct clk_hw *[]){
2367                                       &gcc_qupv3_wrap1_s2_clk_src.clkr.hw },
2368                         .num_parents = 1,
2369                         .flags = CLK_SET_RATE_PARENT,
2370                         .ops = &clk_branch2_ops,
2371                 },
2372         },
2373 };
2374
2375 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2376         .halt_reg = 0x184d4,
2377         .halt_check = BRANCH_HALT_VOTED,
2378         .clkr = {
2379                 .enable_reg = 0x5200c,
2380                 .enable_mask = BIT(25),
2381                 .hw.init = &(struct clk_init_data){
2382                         .name = "gcc_qupv3_wrap1_s3_clk",
2383                         .parent_hws = (const struct clk_hw *[]){
2384                                       &gcc_qupv3_wrap1_s3_clk_src.clkr.hw },
2385                         .num_parents = 1,
2386                         .flags = CLK_SET_RATE_PARENT,
2387                         .ops = &clk_branch2_ops,
2388                 },
2389         },
2390 };
2391
2392 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2393         .halt_reg = 0x18604,
2394         .halt_check = BRANCH_HALT_VOTED,
2395         .clkr = {
2396                 .enable_reg = 0x5200c,
2397                 .enable_mask = BIT(26),
2398                 .hw.init = &(struct clk_init_data){
2399                         .name = "gcc_qupv3_wrap1_s4_clk",
2400                         .parent_hws = (const struct clk_hw *[]){
2401                                       &gcc_qupv3_wrap1_s4_clk_src.clkr.hw },
2402                         .num_parents = 1,
2403                         .flags = CLK_SET_RATE_PARENT,
2404                         .ops = &clk_branch2_ops,
2405                 },
2406         },
2407 };
2408
2409 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2410         .halt_reg = 0x18734,
2411         .halt_check = BRANCH_HALT_VOTED,
2412         .clkr = {
2413                 .enable_reg = 0x5200c,
2414                 .enable_mask = BIT(27),
2415                 .hw.init = &(struct clk_init_data){
2416                         .name = "gcc_qupv3_wrap1_s5_clk",
2417                         .parent_hws = (const struct clk_hw *[]){
2418                                       &gcc_qupv3_wrap1_s5_clk_src.clkr.hw },
2419                         .num_parents = 1,
2420                         .flags = CLK_SET_RATE_PARENT,
2421                         .ops = &clk_branch2_ops,
2422                 },
2423         },
2424 };
2425
2426 static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
2427         .halt_reg = 0x1e144,
2428         .halt_check = BRANCH_HALT_VOTED,
2429         .clkr = {
2430                 .enable_reg = 0x52014,
2431                 .enable_mask = BIT(4),
2432                 .hw.init = &(struct clk_init_data){
2433                         .name = "gcc_qupv3_wrap2_s0_clk",
2434                         .parent_hws = (const struct clk_hw *[]){
2435                                       &gcc_qupv3_wrap2_s0_clk_src.clkr.hw },
2436                         .num_parents = 1,
2437                         .flags = CLK_SET_RATE_PARENT,
2438                         .ops = &clk_branch2_ops,
2439                 },
2440         },
2441 };
2442
2443 static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
2444         .halt_reg = 0x1e274,
2445         .halt_check = BRANCH_HALT_VOTED,
2446         .clkr = {
2447                 .enable_reg = 0x52014,
2448                 .enable_mask = BIT(5),
2449                 .hw.init = &(struct clk_init_data){
2450                         .name = "gcc_qupv3_wrap2_s1_clk",
2451                         .parent_hws = (const struct clk_hw *[]){
2452                                       &gcc_qupv3_wrap2_s1_clk_src.clkr.hw },
2453                         .num_parents = 1,
2454                         .flags = CLK_SET_RATE_PARENT,
2455                         .ops = &clk_branch2_ops,
2456                 },
2457         },
2458 };
2459
2460 static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
2461         .halt_reg = 0x1e3a4,
2462         .halt_check = BRANCH_HALT_VOTED,
2463         .clkr = {
2464                 .enable_reg = 0x52014,
2465                 .enable_mask = BIT(6),
2466                 .hw.init = &(struct clk_init_data){
2467                         .name = "gcc_qupv3_wrap2_s2_clk",
2468                         .parent_hws = (const struct clk_hw *[]){
2469                                       &gcc_qupv3_wrap2_s2_clk_src.clkr.hw },
2470                         .num_parents = 1,
2471                         .flags = CLK_SET_RATE_PARENT,
2472                         .ops = &clk_branch2_ops,
2473                 },
2474         },
2475 };
2476
2477 static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
2478         .halt_reg = 0x1e4d4,
2479         .halt_check = BRANCH_HALT_VOTED,
2480         .clkr = {
2481                 .enable_reg = 0x52014,
2482                 .enable_mask = BIT(7),
2483                 .hw.init = &(struct clk_init_data){
2484                         .name = "gcc_qupv3_wrap2_s3_clk",
2485                         .parent_hws = (const struct clk_hw *[]){
2486                                       &gcc_qupv3_wrap2_s3_clk_src.clkr.hw },
2487                         .num_parents = 1,
2488                         .flags = CLK_SET_RATE_PARENT,
2489                         .ops = &clk_branch2_ops,
2490                 },
2491         },
2492 };
2493
2494 static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
2495         .halt_reg = 0x1e604,
2496         .halt_check = BRANCH_HALT_VOTED,
2497         .clkr = {
2498                 .enable_reg = 0x52014,
2499                 .enable_mask = BIT(8),
2500                 .hw.init = &(struct clk_init_data){
2501                         .name = "gcc_qupv3_wrap2_s4_clk",
2502                         .parent_hws = (const struct clk_hw *[]){
2503                                       &gcc_qupv3_wrap2_s4_clk_src.clkr.hw },
2504                         .num_parents = 1,
2505                         .flags = CLK_SET_RATE_PARENT,
2506                         .ops = &clk_branch2_ops,
2507                 },
2508         },
2509 };
2510
2511 static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
2512         .halt_reg = 0x1e734,
2513         .halt_check = BRANCH_HALT_VOTED,
2514         .clkr = {
2515                 .enable_reg = 0x52014,
2516                 .enable_mask = BIT(9),
2517                 .hw.init = &(struct clk_init_data){
2518                         .name = "gcc_qupv3_wrap2_s5_clk",
2519                         .parent_hws = (const struct clk_hw *[]){
2520                                       &gcc_qupv3_wrap2_s5_clk_src.clkr.hw },
2521                         .num_parents = 1,
2522                         .flags = CLK_SET_RATE_PARENT,
2523                         .ops = &clk_branch2_ops,
2524                 },
2525         },
2526 };
2527
2528 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2529         .halt_reg = 0x17004,
2530         .halt_check = BRANCH_HALT_VOTED,
2531         .clkr = {
2532                 .enable_reg = 0x5200c,
2533                 .enable_mask = BIT(6),
2534                 .hw.init = &(struct clk_init_data){
2535                         .name = "gcc_qupv3_wrap_0_m_ahb_clk",
2536                         .ops = &clk_branch2_ops,
2537                 },
2538         },
2539 };
2540
2541 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2542         .halt_reg = 0x17008,
2543         .halt_check = BRANCH_HALT_VOTED,
2544         .hwcg_reg = 0x17008,
2545         .hwcg_bit = 1,
2546         .clkr = {
2547                 .enable_reg = 0x5200c,
2548                 .enable_mask = BIT(7),
2549                 .hw.init = &(struct clk_init_data){
2550                         .name = "gcc_qupv3_wrap_0_s_ahb_clk",
2551                         .ops = &clk_branch2_ops,
2552                 },
2553         },
2554 };
2555
2556 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2557         .halt_reg = 0x18004,
2558         .halt_check = BRANCH_HALT_VOTED,
2559         .clkr = {
2560                 .enable_reg = 0x5200c,
2561                 .enable_mask = BIT(20),
2562                 .hw.init = &(struct clk_init_data){
2563                         .name = "gcc_qupv3_wrap_1_m_ahb_clk",
2564                         .ops = &clk_branch2_ops,
2565                 },
2566         },
2567 };
2568
2569 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2570         .halt_reg = 0x18008,
2571         .halt_check = BRANCH_HALT_VOTED,
2572         .hwcg_reg = 0x18008,
2573         .hwcg_bit = 1,
2574         .clkr = {
2575                 .enable_reg = 0x5200c,
2576                 .enable_mask = BIT(21),
2577                 .hw.init = &(struct clk_init_data){
2578                         .name = "gcc_qupv3_wrap_1_s_ahb_clk",
2579                         .ops = &clk_branch2_ops,
2580                 },
2581         },
2582 };
2583
2584 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
2585         .halt_reg = 0x1e004,
2586         .halt_check = BRANCH_HALT_VOTED,
2587         .clkr = {
2588                 .enable_reg = 0x52014,
2589                 .enable_mask = BIT(2),
2590                 .hw.init = &(struct clk_init_data){
2591                         .name = "gcc_qupv3_wrap_2_m_ahb_clk",
2592                         .ops = &clk_branch2_ops,
2593                 },
2594         },
2595 };
2596
2597 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
2598         .halt_reg = 0x1e008,
2599         .halt_check = BRANCH_HALT_VOTED,
2600         .hwcg_reg = 0x1e008,
2601         .hwcg_bit = 1,
2602         .clkr = {
2603                 .enable_reg = 0x52014,
2604                 .enable_mask = BIT(1),
2605                 .hw.init = &(struct clk_init_data){
2606                         .name = "gcc_qupv3_wrap_2_s_ahb_clk",
2607                         .ops = &clk_branch2_ops,
2608                 },
2609         },
2610 };
2611
2612 static struct clk_branch gcc_sdcc2_ahb_clk = {
2613         .halt_reg = 0x14008,
2614         .halt_check = BRANCH_HALT,
2615         .clkr = {
2616                 .enable_reg = 0x14008,
2617                 .enable_mask = BIT(0),
2618                 .hw.init = &(struct clk_init_data){
2619                         .name = "gcc_sdcc2_ahb_clk",
2620                         .ops = &clk_branch2_ops,
2621                 },
2622         },
2623 };
2624
2625 static struct clk_branch gcc_sdcc2_apps_clk = {
2626         .halt_reg = 0x14004,
2627         .halt_check = BRANCH_HALT,
2628         .clkr = {
2629                 .enable_reg = 0x14004,
2630                 .enable_mask = BIT(0),
2631                 .hw.init = &(struct clk_init_data){
2632                         .name = "gcc_sdcc2_apps_clk",
2633                         .parent_hws = (const struct clk_hw *[]){
2634                                       &gcc_sdcc2_apps_clk_src.clkr.hw },
2635                         .num_parents = 1,
2636                         .flags = CLK_SET_RATE_PARENT,
2637                         .ops = &clk_branch2_ops,
2638                 },
2639         },
2640 };
2641
2642 static struct clk_branch gcc_sdcc4_ahb_clk = {
2643         .halt_reg = 0x16008,
2644         .halt_check = BRANCH_HALT,
2645         .clkr = {
2646                 .enable_reg = 0x16008,
2647                 .enable_mask = BIT(0),
2648                 .hw.init = &(struct clk_init_data){
2649                         .name = "gcc_sdcc4_ahb_clk",
2650                         .ops = &clk_branch2_ops,
2651                 },
2652         },
2653 };
2654
2655 static struct clk_branch gcc_sdcc4_apps_clk = {
2656         .halt_reg = 0x16004,
2657         .halt_check = BRANCH_HALT,
2658         .clkr = {
2659                 .enable_reg = 0x16004,
2660                 .enable_mask = BIT(0),
2661                 .hw.init = &(struct clk_init_data){
2662                         .name = "gcc_sdcc4_apps_clk",
2663                         .parent_hws = (const struct clk_hw *[]){
2664                                       &gcc_sdcc4_apps_clk_src.clkr.hw },
2665                         .num_parents = 1,
2666                         .flags = CLK_SET_RATE_PARENT,
2667                         .ops = &clk_branch2_ops,
2668                 },
2669         },
2670 };
2671
2672 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
2673         .halt_reg = 0x4819c,
2674         .halt_check = BRANCH_HALT_VOTED,
2675         .clkr = {
2676                 .enable_reg = 0x52004,
2677                 .enable_mask = BIT(0),
2678                 .hw.init = &(struct clk_init_data){
2679                         .name = "gcc_sys_noc_cpuss_ahb_clk",
2680                         .parent_hws = (const struct clk_hw *[]){
2681                                       &gcc_cpuss_ahb_clk_src.clkr.hw },
2682                         .num_parents = 1,
2683                         /* required for cpuss */
2684                         .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
2685                         .ops = &clk_branch2_ops,
2686                 },
2687         },
2688 };
2689
2690 static struct clk_branch gcc_tsif_ahb_clk = {
2691         .halt_reg = 0x36004,
2692         .halt_check = BRANCH_HALT,
2693         .clkr = {
2694                 .enable_reg = 0x36004,
2695                 .enable_mask = BIT(0),
2696                 .hw.init = &(struct clk_init_data){
2697                         .name = "gcc_tsif_ahb_clk",
2698                         .ops = &clk_branch2_ops,
2699                 },
2700         },
2701 };
2702
2703 static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2704         .halt_reg = 0x3600c,
2705         .halt_check = BRANCH_HALT,
2706         .clkr = {
2707                 .enable_reg = 0x3600c,
2708                 .enable_mask = BIT(0),
2709                 .hw.init = &(struct clk_init_data){
2710                         .name = "gcc_tsif_inactivity_timers_clk",
2711                         .ops = &clk_branch2_ops,
2712                 },
2713         },
2714 };
2715
2716 static struct clk_branch gcc_tsif_ref_clk = {
2717         .halt_reg = 0x36008,
2718         .halt_check = BRANCH_HALT,
2719         .clkr = {
2720                 .enable_reg = 0x36008,
2721                 .enable_mask = BIT(0),
2722                 .hw.init = &(struct clk_init_data){
2723                         .name = "gcc_tsif_ref_clk",
2724                         .parent_hws = (const struct clk_hw *[]){
2725                                       &gcc_tsif_ref_clk_src.clkr.hw },
2726                         .num_parents = 1,
2727                         .flags = CLK_SET_RATE_PARENT,
2728                         .ops = &clk_branch2_ops,
2729                 },
2730         },
2731 };
2732
2733 static struct clk_branch gcc_ufs_card_ahb_clk = {
2734         .halt_reg = 0x75014,
2735         .halt_check = BRANCH_HALT,
2736         .hwcg_reg = 0x75014,
2737         .hwcg_bit = 1,
2738         .clkr = {
2739                 .enable_reg = 0x75014,
2740                 .enable_mask = BIT(0),
2741                 .hw.init = &(struct clk_init_data){
2742                         .name = "gcc_ufs_card_ahb_clk",
2743                         .ops = &clk_branch2_ops,
2744                 },
2745         },
2746 };
2747
2748 static struct clk_branch gcc_ufs_card_axi_clk = {
2749         .halt_reg = 0x75010,
2750         .halt_check = BRANCH_HALT,
2751         .hwcg_reg = 0x75010,
2752         .hwcg_bit = 1,
2753         .clkr = {
2754                 .enable_reg = 0x75010,
2755                 .enable_mask = BIT(0),
2756                 .hw.init = &(struct clk_init_data){
2757                         .name = "gcc_ufs_card_axi_clk",
2758                         .parent_hws = (const struct clk_hw *[]){
2759                                       &gcc_ufs_card_axi_clk_src.clkr.hw },
2760                         .num_parents = 1,
2761                         .flags = CLK_SET_RATE_PARENT,
2762                         .ops = &clk_branch2_ops,
2763                 },
2764         },
2765 };
2766
2767 static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = {
2768         .halt_reg = 0x75010,
2769         .halt_check = BRANCH_HALT,
2770         .hwcg_reg = 0x75010,
2771         .hwcg_bit = 1,
2772         .clkr = {
2773                 .enable_reg = 0x75010,
2774                 .enable_mask = BIT(1),
2775                 .hw.init = &(struct clk_init_data){
2776                         .name = "gcc_ufs_card_axi_hw_ctl_clk",
2777                         .parent_hws = (const struct clk_hw *[]){
2778                                       &gcc_ufs_card_axi_clk.clkr.hw },
2779                         .num_parents = 1,
2780                         .flags = CLK_SET_RATE_PARENT,
2781                         .ops = &clk_branch_simple_ops,
2782                 },
2783         },
2784 };
2785
2786 static struct clk_branch gcc_ufs_card_clkref_clk = {
2787         .halt_reg = 0x8c004,
2788         .halt_check = BRANCH_HALT,
2789         .clkr = {
2790                 .enable_reg = 0x8c004,
2791                 .enable_mask = BIT(0),
2792                 .hw.init = &(struct clk_init_data){
2793                         .name = "gcc_ufs_card_clkref_clk",
2794                         .ops = &clk_branch2_ops,
2795                 },
2796         },
2797 };
2798
2799 static struct clk_branch gcc_ufs_card_ice_core_clk = {
2800         .halt_reg = 0x7505c,
2801         .halt_check = BRANCH_HALT,
2802         .hwcg_reg = 0x7505c,
2803         .hwcg_bit = 1,
2804         .clkr = {
2805                 .enable_reg = 0x7505c,
2806                 .enable_mask = BIT(0),
2807                 .hw.init = &(struct clk_init_data){
2808                         .name = "gcc_ufs_card_ice_core_clk",
2809                         .parent_hws = (const struct clk_hw *[]){
2810                                       &gcc_ufs_card_ice_core_clk_src.clkr.hw },
2811                         .num_parents = 1,
2812                         .flags = CLK_SET_RATE_PARENT,
2813                         .ops = &clk_branch2_ops,
2814                 },
2815         },
2816 };
2817
2818 static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = {
2819         .halt_reg = 0x7505c,
2820         .halt_check = BRANCH_HALT,
2821         .hwcg_reg = 0x7505c,
2822         .hwcg_bit = 1,
2823         .clkr = {
2824                 .enable_reg = 0x7505c,
2825                 .enable_mask = BIT(1),
2826                 .hw.init = &(struct clk_init_data){
2827                         .name = "gcc_ufs_card_ice_core_hw_ctl_clk",
2828                         .parent_hws = (const struct clk_hw *[]){
2829                                       &gcc_ufs_card_ice_core_clk.clkr.hw },
2830                         .num_parents = 1,
2831                         .flags = CLK_SET_RATE_PARENT,
2832                         .ops = &clk_branch_simple_ops,
2833                 },
2834         },
2835 };
2836
2837 static struct clk_branch gcc_ufs_card_phy_aux_clk = {
2838         .halt_reg = 0x75090,
2839         .halt_check = BRANCH_HALT,
2840         .hwcg_reg = 0x75090,
2841         .hwcg_bit = 1,
2842         .clkr = {
2843                 .enable_reg = 0x75090,
2844                 .enable_mask = BIT(0),
2845                 .hw.init = &(struct clk_init_data){
2846                         .name = "gcc_ufs_card_phy_aux_clk",
2847                         .parent_hws = (const struct clk_hw *[]){
2848                                       &gcc_ufs_card_phy_aux_clk_src.clkr.hw },
2849                         .num_parents = 1,
2850                         .flags = CLK_SET_RATE_PARENT,
2851                         .ops = &clk_branch2_ops,
2852                 },
2853         },
2854 };
2855
2856 static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {
2857         .halt_reg = 0x75090,
2858         .halt_check = BRANCH_HALT,
2859         .hwcg_reg = 0x75090,
2860         .hwcg_bit = 1,
2861         .clkr = {
2862                 .enable_reg = 0x75090,
2863                 .enable_mask = BIT(1),
2864                 .hw.init = &(struct clk_init_data){
2865                         .name = "gcc_ufs_card_phy_aux_hw_ctl_clk",
2866                         .parent_hws = (const struct clk_hw *[]){
2867                                       &gcc_ufs_card_phy_aux_clk.clkr.hw },
2868                         .num_parents = 1,
2869                         .flags = CLK_SET_RATE_PARENT,
2870                         .ops = &clk_branch_simple_ops,
2871                 },
2872         },
2873 };
2874
2875 /* external clocks so add BRANCH_HALT_SKIP */
2876 static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
2877         .halt_check = BRANCH_HALT_SKIP,
2878         .clkr = {
2879                 .enable_reg = 0x7501c,
2880                 .enable_mask = BIT(0),
2881                 .hw.init = &(struct clk_init_data){
2882                         .name = "gcc_ufs_card_rx_symbol_0_clk",
2883                         .ops = &clk_branch2_ops,
2884                 },
2885         },
2886 };
2887
2888 /* external clocks so add BRANCH_HALT_SKIP */
2889 static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
2890         .halt_check = BRANCH_HALT_SKIP,
2891         .clkr = {
2892                 .enable_reg = 0x750ac,
2893                 .enable_mask = BIT(0),
2894                 .hw.init = &(struct clk_init_data){
2895                         .name = "gcc_ufs_card_rx_symbol_1_clk",
2896                         .ops = &clk_branch2_ops,
2897                 },
2898         },
2899 };
2900
2901 /* external clocks so add BRANCH_HALT_SKIP */
2902 static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
2903         .halt_check = BRANCH_HALT_SKIP,
2904         .clkr = {
2905                 .enable_reg = 0x75018,
2906                 .enable_mask = BIT(0),
2907                 .hw.init = &(struct clk_init_data){
2908                         .name = "gcc_ufs_card_tx_symbol_0_clk",
2909                         .ops = &clk_branch2_ops,
2910                 },
2911         },
2912 };
2913
2914 static struct clk_branch gcc_ufs_card_unipro_core_clk = {
2915         .halt_reg = 0x75058,
2916         .halt_check = BRANCH_HALT,
2917         .hwcg_reg = 0x75058,
2918         .hwcg_bit = 1,
2919         .clkr = {
2920                 .enable_reg = 0x75058,
2921                 .enable_mask = BIT(0),
2922                 .hw.init = &(struct clk_init_data){
2923                         .name = "gcc_ufs_card_unipro_core_clk",
2924                         .parent_hws = (const struct clk_hw *[]){
2925                                 &gcc_ufs_card_unipro_core_clk_src.clkr.hw },
2926                         .num_parents = 1,
2927                         .flags = CLK_SET_RATE_PARENT,
2928                         .ops = &clk_branch2_ops,
2929                 },
2930         },
2931 };
2932
2933 static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = {
2934         .halt_reg = 0x75058,
2935         .halt_check = BRANCH_HALT,
2936         .hwcg_reg = 0x75058,
2937         .hwcg_bit = 1,
2938         .clkr = {
2939                 .enable_reg = 0x75058,
2940                 .enable_mask = BIT(1),
2941                 .hw.init = &(struct clk_init_data){
2942                         .name = "gcc_ufs_card_unipro_core_hw_ctl_clk",
2943                         .parent_hws = (const struct clk_hw *[]){
2944                                       &gcc_ufs_card_unipro_core_clk.clkr.hw },
2945                         .num_parents = 1,
2946                         .flags = CLK_SET_RATE_PARENT,
2947                         .ops = &clk_branch_simple_ops,
2948                 },
2949         },
2950 };
2951
2952 static struct clk_branch gcc_ufs_mem_clkref_clk = {
2953         .halt_reg = 0x8c000,
2954         .halt_check = BRANCH_HALT,
2955         .clkr = {
2956                 .enable_reg = 0x8c000,
2957                 .enable_mask = BIT(0),
2958                 .hw.init = &(struct clk_init_data){
2959                         .name = "gcc_ufs_mem_clkref_clk",
2960                         .ops = &clk_branch2_ops,
2961                 },
2962         },
2963 };
2964
2965 static struct clk_branch gcc_ufs_phy_ahb_clk = {
2966         .halt_reg = 0x77014,
2967         .halt_check = BRANCH_HALT,
2968         .hwcg_reg = 0x77014,
2969         .hwcg_bit = 1,
2970         .clkr = {
2971                 .enable_reg = 0x77014,
2972                 .enable_mask = BIT(0),
2973                 .hw.init = &(struct clk_init_data){
2974                         .name = "gcc_ufs_phy_ahb_clk",
2975                         .ops = &clk_branch2_ops,
2976                 },
2977         },
2978 };
2979
2980 static struct clk_branch gcc_ufs_phy_axi_clk = {
2981         .halt_reg = 0x77010,
2982         .halt_check = BRANCH_HALT,
2983         .hwcg_reg = 0x77010,
2984         .hwcg_bit = 1,
2985         .clkr = {
2986                 .enable_reg = 0x77010,
2987                 .enable_mask = BIT(0),
2988                 .hw.init = &(struct clk_init_data){
2989                         .name = "gcc_ufs_phy_axi_clk",
2990                         .parent_hws = (const struct clk_hw *[]){
2991                                 &gcc_ufs_phy_axi_clk_src.clkr.hw },
2992                         .num_parents = 1,
2993                         .flags = CLK_SET_RATE_PARENT,
2994                         .ops = &clk_branch2_ops,
2995                 },
2996         },
2997 };
2998
2999 static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
3000         .halt_reg = 0x77010,
3001         .halt_check = BRANCH_HALT,
3002         .hwcg_reg = 0x77010,
3003         .hwcg_bit = 1,
3004         .clkr = {
3005                 .enable_reg = 0x77010,
3006                 .enable_mask = BIT(1),
3007                 .hw.init = &(struct clk_init_data){
3008                         .name = "gcc_ufs_phy_axi_hw_ctl_clk",
3009                         .parent_hws = (const struct clk_hw *[]){
3010                                       &gcc_ufs_phy_axi_clk.clkr.hw },
3011                         .num_parents = 1,
3012                         .flags = CLK_SET_RATE_PARENT,
3013                         .ops = &clk_branch_simple_ops,
3014                 },
3015         },
3016 };
3017
3018 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
3019         .halt_reg = 0x7705c,
3020         .halt_check = BRANCH_HALT,
3021         .hwcg_reg = 0x7705c,
3022         .hwcg_bit = 1,
3023         .clkr = {
3024                 .enable_reg = 0x7705c,
3025                 .enable_mask = BIT(0),
3026                 .hw.init = &(struct clk_init_data){
3027                         .name = "gcc_ufs_phy_ice_core_clk",
3028                         .parent_hws = (const struct clk_hw *[]){
3029                                       &gcc_ufs_phy_ice_core_clk_src.clkr.hw },
3030                         .num_parents = 1,
3031                         .flags = CLK_SET_RATE_PARENT,
3032                         .ops = &clk_branch2_ops,
3033                 },
3034         },
3035 };
3036
3037 static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
3038         .halt_reg = 0x7705c,
3039         .halt_check = BRANCH_HALT,
3040         .hwcg_reg = 0x7705c,
3041         .hwcg_bit = 1,
3042         .clkr = {
3043                 .enable_reg = 0x7705c,
3044                 .enable_mask = BIT(1),
3045                 .hw.init = &(struct clk_init_data){
3046                         .name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
3047                         .parent_hws = (const struct clk_hw *[]){
3048                                       &gcc_ufs_phy_ice_core_clk.clkr.hw },
3049                         .num_parents = 1,
3050                         .flags = CLK_SET_RATE_PARENT,
3051                         .ops = &clk_branch_simple_ops,
3052                 },
3053         },
3054 };
3055
3056 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
3057         .halt_reg = 0x77090,
3058         .halt_check = BRANCH_HALT,
3059         .hwcg_reg = 0x77090,
3060         .hwcg_bit = 1,
3061         .clkr = {
3062                 .enable_reg = 0x77090,
3063                 .enable_mask = BIT(0),
3064                 .hw.init = &(struct clk_init_data){
3065                         .name = "gcc_ufs_phy_phy_aux_clk",
3066                         .parent_hws = (const struct clk_hw *[]){
3067                                       &gcc_ufs_phy_phy_aux_clk_src.clkr.hw },
3068                         .num_parents = 1,
3069                         .flags = CLK_SET_RATE_PARENT,
3070                         .ops = &clk_branch2_ops,
3071                 },
3072         },
3073 };
3074
3075 static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
3076         .halt_reg = 0x77090,
3077         .halt_check = BRANCH_HALT,
3078         .hwcg_reg = 0x77090,
3079         .hwcg_bit = 1,
3080         .clkr = {
3081                 .enable_reg = 0x77090,
3082                 .enable_mask = BIT(1),
3083                 .hw.init = &(struct clk_init_data){
3084                         .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
3085                         .parent_hws = (const struct clk_hw *[]){
3086                                       &gcc_ufs_phy_phy_aux_clk.clkr.hw },
3087                         .num_parents = 1,
3088                         .flags = CLK_SET_RATE_PARENT,
3089                         .ops = &clk_branch_simple_ops,
3090                 },
3091         },
3092 };
3093
3094 /* external clocks so add BRANCH_HALT_SKIP */
3095 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
3096         .halt_check = BRANCH_HALT_SKIP,
3097         .clkr = {
3098                 .enable_reg = 0x7701c,
3099                 .enable_mask = BIT(0),
3100                 .hw.init = &(struct clk_init_data){
3101                         .name = "gcc_ufs_phy_rx_symbol_0_clk",
3102                         .ops = &clk_branch2_ops,
3103                 },
3104         },
3105 };
3106
3107 /* external clocks so add BRANCH_HALT_SKIP */
3108 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
3109         .halt_check = BRANCH_HALT_SKIP,
3110         .clkr = {
3111                 .enable_reg = 0x770ac,
3112                 .enable_mask = BIT(0),
3113                 .hw.init = &(struct clk_init_data){
3114                         .name = "gcc_ufs_phy_rx_symbol_1_clk",
3115                         .ops = &clk_branch2_ops,
3116                 },
3117         },
3118 };
3119
3120 /* external clocks so add BRANCH_HALT_SKIP */
3121 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
3122         .halt_check = BRANCH_HALT_SKIP,
3123         .clkr = {
3124                 .enable_reg = 0x77018,
3125                 .enable_mask = BIT(0),
3126                 .hw.init = &(struct clk_init_data){
3127                         .name = "gcc_ufs_phy_tx_symbol_0_clk",
3128                         .ops = &clk_branch2_ops,
3129                 },
3130         },
3131 };
3132
3133 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
3134         .halt_reg = 0x77058,
3135         .halt_check = BRANCH_HALT,
3136         .hwcg_reg = 0x77058,
3137         .hwcg_bit = 1,
3138         .clkr = {
3139                 .enable_reg = 0x77058,
3140                 .enable_mask = BIT(0),
3141                 .hw.init = &(struct clk_init_data){
3142                         .name = "gcc_ufs_phy_unipro_core_clk",
3143                         .parent_hws = (const struct clk_hw *[]){
3144                                 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw },
3145                         .num_parents = 1,
3146                         .flags = CLK_SET_RATE_PARENT,
3147                         .ops = &clk_branch2_ops,
3148                 },
3149         },
3150 };
3151
3152 static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
3153         .halt_reg = 0x77058,
3154         .halt_check = BRANCH_HALT,
3155         .hwcg_reg = 0x77058,
3156         .hwcg_bit = 1,
3157         .clkr = {
3158                 .enable_reg = 0x77058,
3159                 .enable_mask = BIT(1),
3160                 .hw.init = &(struct clk_init_data){
3161                         .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
3162                         .parent_hws = (const struct clk_hw *[]){
3163                                       &gcc_ufs_phy_unipro_core_clk.clkr.hw },
3164                         .num_parents = 1,
3165                         .flags = CLK_SET_RATE_PARENT,
3166                         .ops = &clk_branch_simple_ops,
3167                 },
3168         },
3169 };
3170
3171 static struct clk_branch gcc_usb30_prim_master_clk = {
3172         .halt_reg = 0xf010,
3173         .halt_check = BRANCH_HALT,
3174         .clkr = {
3175                 .enable_reg = 0xf010,
3176                 .enable_mask = BIT(0),
3177                 .hw.init = &(struct clk_init_data){
3178                         .name = "gcc_usb30_prim_master_clk",
3179                         .parent_hws = (const struct clk_hw *[]){
3180                                       &gcc_usb30_prim_master_clk_src.clkr.hw },
3181                         .num_parents = 1,
3182                         .flags = CLK_SET_RATE_PARENT,
3183                         .ops = &clk_branch2_ops,
3184                 },
3185         },
3186 };
3187
3188 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
3189         .halt_reg = 0xf018,
3190         .halt_check = BRANCH_HALT,
3191         .clkr = {
3192                 .enable_reg = 0xf018,
3193                 .enable_mask = BIT(0),
3194                 .hw.init = &(struct clk_init_data){
3195                         .name = "gcc_usb30_prim_mock_utmi_clk",
3196                         .parent_hws = (const struct clk_hw *[]){
3197                                 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw },
3198                         .num_parents = 1,
3199                         .flags = CLK_SET_RATE_PARENT,
3200                         .ops = &clk_branch2_ops,
3201                 },
3202         },
3203 };
3204
3205 static struct clk_branch gcc_usb30_prim_sleep_clk = {
3206         .halt_reg = 0xf014,
3207         .halt_check = BRANCH_HALT,
3208         .clkr = {
3209                 .enable_reg = 0xf014,
3210                 .enable_mask = BIT(0),
3211                 .hw.init = &(struct clk_init_data){
3212                         .name = "gcc_usb30_prim_sleep_clk",
3213                         .ops = &clk_branch2_ops,
3214                 },
3215         },
3216 };
3217
3218 static struct clk_branch gcc_usb30_sec_master_clk = {
3219         .halt_reg = 0x10010,
3220         .halt_check = BRANCH_HALT,
3221         .clkr = {
3222                 .enable_reg = 0x10010,
3223                 .enable_mask = BIT(0),
3224                 .hw.init = &(struct clk_init_data){
3225                         .name = "gcc_usb30_sec_master_clk",
3226                         .parent_hws = (const struct clk_hw *[]){
3227                                       &gcc_usb30_sec_master_clk_src.clkr.hw },
3228                         .num_parents = 1,
3229                         .flags = CLK_SET_RATE_PARENT,
3230                         .ops = &clk_branch2_ops,
3231                 },
3232         },
3233 };
3234
3235 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
3236         .halt_reg = 0x10018,
3237         .halt_check = BRANCH_HALT,
3238         .clkr = {
3239                 .enable_reg = 0x10018,
3240                 .enable_mask = BIT(0),
3241                 .hw.init = &(struct clk_init_data){
3242                         .name = "gcc_usb30_sec_mock_utmi_clk",
3243                         .parent_hws = (const struct clk_hw *[]){
3244                                 &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw },
3245                         .num_parents = 1,
3246                         .flags = CLK_SET_RATE_PARENT,
3247                         .ops = &clk_branch2_ops,
3248                 },
3249         },
3250 };
3251
3252 static struct clk_branch gcc_usb30_sec_sleep_clk = {
3253         .halt_reg = 0x10014,
3254         .halt_check = BRANCH_HALT,
3255         .clkr = {
3256                 .enable_reg = 0x10014,
3257                 .enable_mask = BIT(0),
3258                 .hw.init = &(struct clk_init_data){
3259                         .name = "gcc_usb30_sec_sleep_clk",
3260                         .ops = &clk_branch2_ops,
3261                 },
3262         },
3263 };
3264
3265 static struct clk_branch gcc_usb3_prim_clkref_clk = {
3266         .halt_reg = 0x8c008,
3267         .halt_check = BRANCH_HALT,
3268         .clkr = {
3269                 .enable_reg = 0x8c008,
3270                 .enable_mask = BIT(0),
3271                 .hw.init = &(struct clk_init_data){
3272                         .name = "gcc_usb3_prim_clkref_clk",
3273                         .ops = &clk_branch2_ops,
3274                 },
3275         },
3276 };
3277
3278 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
3279         .halt_reg = 0xf050,
3280         .halt_check = BRANCH_HALT,
3281         .clkr = {
3282                 .enable_reg = 0xf050,
3283                 .enable_mask = BIT(0),
3284                 .hw.init = &(struct clk_init_data){
3285                         .name = "gcc_usb3_prim_phy_aux_clk",
3286                         .parent_hws = (const struct clk_hw *[]){
3287                                       &gcc_usb3_prim_phy_aux_clk_src.clkr.hw },
3288                         .num_parents = 1,
3289                         .flags = CLK_SET_RATE_PARENT,
3290                         .ops = &clk_branch2_ops,
3291                 },
3292         },
3293 };
3294
3295 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
3296         .halt_reg = 0xf054,
3297         .halt_check = BRANCH_HALT,
3298         .clkr = {
3299                 .enable_reg = 0xf054,
3300                 .enable_mask = BIT(0),
3301                 .hw.init = &(struct clk_init_data){
3302                         .name = "gcc_usb3_prim_phy_com_aux_clk",
3303                         .parent_hws = (const struct clk_hw *[]){
3304                                       &gcc_usb3_prim_phy_aux_clk_src.clkr.hw },
3305                         .num_parents = 1,
3306                         .flags = CLK_SET_RATE_PARENT,
3307                         .ops = &clk_branch2_ops,
3308                 },
3309         },
3310 };
3311
3312 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
3313         .halt_check = BRANCH_HALT_SKIP,
3314         .clkr = {
3315                 .enable_reg = 0xf058,
3316                 .enable_mask = BIT(0),
3317                 .hw.init = &(struct clk_init_data){
3318                         .name = "gcc_usb3_prim_phy_pipe_clk",
3319                         .ops = &clk_branch2_ops,
3320                 },
3321         },
3322 };
3323
3324 static struct clk_branch gcc_usb3_sec_clkref_clk = {
3325         .halt_reg = 0x8c028,
3326         .halt_check = BRANCH_HALT,
3327         .clkr = {
3328                 .enable_reg = 0x8c028,
3329                 .enable_mask = BIT(0),
3330                 .hw.init = &(struct clk_init_data){
3331                         .name = "gcc_usb3_sec_clkref_clk",
3332                         .ops = &clk_branch2_ops,
3333                 },
3334         },
3335 };
3336
3337 static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
3338         .halt_reg = 0x10050,
3339         .halt_check = BRANCH_HALT,
3340         .clkr = {
3341                 .enable_reg = 0x10050,
3342                 .enable_mask = BIT(0),
3343                 .hw.init = &(struct clk_init_data){
3344                         .name = "gcc_usb3_sec_phy_aux_clk",
3345                         .parent_hws = (const struct clk_hw *[]){
3346                                       &gcc_usb3_sec_phy_aux_clk_src.clkr.hw },
3347                         .num_parents = 1,
3348                         .flags = CLK_SET_RATE_PARENT,
3349                         .ops = &clk_branch2_ops,
3350                 },
3351         },
3352 };
3353
3354 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
3355         .halt_reg = 0x10054,
3356         .halt_check = BRANCH_HALT,
3357         .clkr = {
3358                 .enable_reg = 0x10054,
3359                 .enable_mask = BIT(0),
3360                 .hw.init = &(struct clk_init_data){
3361                         .name = "gcc_usb3_sec_phy_com_aux_clk",
3362                         .parent_hws = (const struct clk_hw *[]){
3363                                       &gcc_usb3_sec_phy_aux_clk_src.clkr.hw },
3364                         .num_parents = 1,
3365                         .flags = CLK_SET_RATE_PARENT,
3366                         .ops = &clk_branch2_ops,
3367                 },
3368         },
3369 };
3370
3371 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
3372         .halt_check = BRANCH_HALT_SKIP,
3373         .clkr = {
3374                 .enable_reg = 0x10058,
3375                 .enable_mask = BIT(0),
3376                 .hw.init = &(struct clk_init_data){
3377                         .name = "gcc_usb3_sec_phy_pipe_clk",
3378                         .ops = &clk_branch2_ops,
3379                 },
3380         },
3381 };
3382
3383 /*
3384  * Clock ON depends on external parent 'config noc', so cant poll
3385  * delay and also mark as crtitical for video boot
3386  */
3387 static struct clk_branch gcc_video_ahb_clk = {
3388         .halt_reg = 0xb004,
3389         .halt_check = BRANCH_HALT_DELAY,
3390         .hwcg_reg = 0xb004,
3391         .hwcg_bit = 1,
3392         .clkr = {
3393                 .enable_reg = 0xb004,
3394                 .enable_mask = BIT(0),
3395                 .hw.init = &(struct clk_init_data){
3396                         .name = "gcc_video_ahb_clk",
3397                         .flags = CLK_IS_CRITICAL,
3398                         .ops = &clk_branch2_ops,
3399                 },
3400         },
3401 };
3402
3403 static struct clk_branch gcc_video_axi0_clk = {
3404         .halt_reg = 0xb024,
3405         .halt_check = BRANCH_HALT,
3406         .clkr = {
3407                 .enable_reg = 0xb024,
3408                 .enable_mask = BIT(0),
3409                 .hw.init = &(struct clk_init_data){
3410                         .name = "gcc_video_axi0_clk",
3411                         .ops = &clk_branch2_ops,
3412                 },
3413         },
3414 };
3415
3416 static struct clk_branch gcc_video_axi1_clk = {
3417         .halt_reg = 0xb028,
3418         .halt_check = BRANCH_HALT,
3419         .clkr = {
3420                 .enable_reg = 0xb028,
3421                 .enable_mask = BIT(0),
3422                 .hw.init = &(struct clk_init_data){
3423                         .name = "gcc_video_axi1_clk",
3424                         .ops = &clk_branch2_ops,
3425                 },
3426         },
3427 };
3428
3429 static struct clk_branch gcc_video_axic_clk = {
3430         .halt_reg = 0xb02c,
3431         .halt_check = BRANCH_HALT,
3432         .clkr = {
3433                 .enable_reg = 0xb02c,
3434                 .enable_mask = BIT(0),
3435                 .hw.init = &(struct clk_init_data){
3436                         .name = "gcc_video_axic_clk",
3437                         .ops = &clk_branch2_ops,
3438                 },
3439         },
3440 };
3441
3442 /* XO critical input to video, so no need to poll */
3443 static struct clk_branch gcc_video_xo_clk = {
3444         .halt_reg = 0xb040,
3445         .halt_check = BRANCH_HALT_DELAY,
3446         .clkr = {
3447                 .enable_reg = 0xb040,
3448                 .enable_mask = BIT(0),
3449                 .hw.init = &(struct clk_init_data){
3450                         .name = "gcc_video_xo_clk",
3451                         .flags = CLK_IS_CRITICAL,
3452                         .ops = &clk_branch2_ops,
3453                 },
3454         },
3455 };
3456
3457 static struct gdsc usb30_prim_gdsc = {
3458                 .gdscr = 0xf004,
3459                 .pd = {
3460                         .name = "usb30_prim_gdsc",
3461                 },
3462                 .pwrsts = PWRSTS_OFF_ON,
3463                 .flags = POLL_CFG_GDSCR,
3464 };
3465
3466 static struct gdsc usb30_sec_gdsc = {
3467                 .gdscr = 0x10004,
3468                 .pd = {
3469                         .name = "usb30_sec_gdsc",
3470                 },
3471                 .pwrsts = PWRSTS_OFF_ON,
3472                 .flags = POLL_CFG_GDSCR,
3473 };
3474
3475 static struct clk_regmap *gcc_sm8150_clocks[] = {
3476         [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
3477         [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
3478         [GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] =
3479                 &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr,
3480         [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3481         [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] =
3482                 &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
3483         [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3484         [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
3485         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3486         [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
3487         [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
3488         [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
3489         [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
3490         [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3491         [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
3492         [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
3493         [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
3494         [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
3495         [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
3496         [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
3497         [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3498         [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
3499         [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
3500         [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
3501         [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
3502         [GCC_EMAC_AXI_CLK] = &gcc_emac_axi_clk.clkr,
3503         [GCC_EMAC_PTP_CLK] = &gcc_emac_ptp_clk.clkr,
3504         [GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr,
3505         [GCC_EMAC_RGMII_CLK] = &gcc_emac_rgmii_clk.clkr,
3506         [GCC_EMAC_RGMII_CLK_SRC] = &gcc_emac_rgmii_clk_src.clkr,
3507         [GCC_EMAC_SLV_AHB_CLK] = &gcc_emac_slv_ahb_clk.clkr,
3508         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3509         [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3510         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3511         [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3512         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3513         [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3514         [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
3515         [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3516         [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3517         [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
3518         [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3519         [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3520         [GCC_NPU_AT_CLK] = &gcc_npu_at_clk.clkr,
3521         [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
3522         [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
3523         [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr,
3524         [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
3525         [GCC_NPU_TRIG_CLK] = &gcc_npu_trig_clk.clkr,
3526         [GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr,
3527         [GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr,
3528         [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3529         [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
3530         [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3531         [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
3532         [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3533         [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3534         [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3535         [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3536         [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3537         [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
3538         [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3539         [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr,
3540         [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3541         [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3542         [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3543         [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
3544         [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
3545         [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,
3546         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3547         [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3548         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3549         [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3550         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3551         [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
3552         [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
3553         [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3554         [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
3555         [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
3556         [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
3557         [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
3558         [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
3559         [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3560         [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3561         [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3562         [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3563         [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3564         [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3565         [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3566         [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3567         [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3568         [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3569         [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3570         [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3571         [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3572         [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3573         [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3574         [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3575         [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3576         [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3577         [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3578         [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3579         [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3580         [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3581         [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3582         [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3583         [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3584         [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3585         [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3586         [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3587         [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
3588         [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
3589         [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
3590         [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
3591         [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
3592         [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
3593         [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
3594         [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
3595         [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
3596         [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
3597         [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
3598         [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
3599         [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3600         [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3601         [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3602         [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3603         [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
3604         [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
3605         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3606         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3607         [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3608         [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3609         [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3610         [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3611         [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
3612         [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3613         [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
3614         [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3615         [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
3616         [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
3617         [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
3618         [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
3619         [GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr,
3620         [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr,
3621         [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
3622         [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
3623         [GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] =
3624                 &gcc_ufs_card_ice_core_hw_ctl_clk.clkr,
3625         [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
3626         [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
3627         [GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] =
3628                 &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr,
3629         [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
3630         [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
3631         [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
3632         [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
3633         [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] =
3634                 &gcc_ufs_card_unipro_core_clk_src.clkr,
3635         [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] =
3636                 &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr,
3637         [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
3638         [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3639         [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3640         [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3641         [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
3642         [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3643         [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3644         [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] =
3645                 &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
3646         [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3647         [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3648         [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
3649         [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3650         [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
3651         [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3652         [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3653         [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
3654                 &gcc_ufs_phy_unipro_core_clk_src.clkr,
3655         [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] =
3656                 &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
3657         [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3658         [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3659         [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3660         [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
3661                 &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3662         [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3663         [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
3664         [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
3665         [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
3666         [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =
3667                 &gcc_usb30_sec_mock_utmi_clk_src.clkr,
3668         [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
3669         [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
3670         [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3671         [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3672         [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3673         [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3674         [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,
3675         [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
3676         [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
3677         [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
3678         [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
3679         [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
3680         [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
3681         [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
3682         [GCC_VIDEO_AXIC_CLK] = &gcc_video_axic_clk.clkr,
3683         [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
3684         [GPLL0] = &gpll0.clkr,
3685         [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
3686         [GPLL7] = &gpll7.clkr,
3687         [GPLL9] = &gpll9.clkr,
3688 };
3689
3690 static const struct qcom_reset_map gcc_sm8150_resets[] = {
3691         [GCC_EMAC_BCR] = { 0x6000 },
3692         [GCC_GPU_BCR] = { 0x71000 },
3693         [GCC_MMSS_BCR] = { 0xb000 },
3694         [GCC_NPU_BCR] = { 0x4d000 },
3695         [GCC_PCIE_0_BCR] = { 0x6b000 },
3696         [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3697         [GCC_PCIE_1_BCR] = { 0x8d000 },
3698         [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3699         [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3700         [GCC_PDM_BCR] = { 0x33000 },
3701         [GCC_PRNG_BCR] = { 0x34000 },
3702         [GCC_QSPI_BCR] = { 0x24008 },
3703         [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
3704         [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3705         [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
3706         [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3707         [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3708         [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3709         [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3710         [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3711         [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3712         [GCC_SDCC2_BCR] = { 0x14000 },
3713         [GCC_SDCC4_BCR] = { 0x16000 },
3714         [GCC_TSIF_BCR] = { 0x36000 },
3715         [GCC_UFS_CARD_BCR] = { 0x75000 },
3716         [GCC_UFS_PHY_BCR] = { 0x77000 },
3717         [GCC_USB30_PRIM_BCR] = { 0xf000 },
3718         [GCC_USB30_SEC_BCR] = { 0x10000 },
3719         [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3720 };
3721
3722 static struct gdsc *gcc_sm8150_gdscs[] = {
3723         [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
3724         [USB30_SEC_GDSC] = &usb30_sec_gdsc,
3725 };
3726
3727 static const struct regmap_config gcc_sm8150_regmap_config = {
3728         .reg_bits       = 32,
3729         .reg_stride     = 4,
3730         .val_bits       = 32,
3731         .max_register   = 0x9c040,
3732         .fast_io        = true,
3733 };
3734
3735 static const struct qcom_cc_desc gcc_sm8150_desc = {
3736         .config = &gcc_sm8150_regmap_config,
3737         .clks = gcc_sm8150_clocks,
3738         .num_clks = ARRAY_SIZE(gcc_sm8150_clocks),
3739         .resets = gcc_sm8150_resets,
3740         .num_resets = ARRAY_SIZE(gcc_sm8150_resets),
3741         .gdscs = gcc_sm8150_gdscs,
3742         .num_gdscs = ARRAY_SIZE(gcc_sm8150_gdscs),
3743 };
3744
3745 static const struct of_device_id gcc_sm8150_match_table[] = {
3746         { .compatible = "qcom,gcc-sm8150" },
3747         { }
3748 };
3749 MODULE_DEVICE_TABLE(of, gcc_sm8150_match_table);
3750
3751 static int gcc_sm8150_probe(struct platform_device *pdev)
3752 {
3753         struct regmap *regmap;
3754
3755         regmap = qcom_cc_map(pdev, &gcc_sm8150_desc);
3756         if (IS_ERR(regmap))
3757                 return PTR_ERR(regmap);
3758
3759         /* Disable the GPLL0 active input to NPU and GPU via MISC registers */
3760         regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
3761         regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
3762
3763         return qcom_cc_really_probe(pdev, &gcc_sm8150_desc, regmap);
3764 }
3765
3766 static struct platform_driver gcc_sm8150_driver = {
3767         .probe          = gcc_sm8150_probe,
3768         .driver         = {
3769                 .name   = "gcc-sm8150",
3770                 .of_match_table = gcc_sm8150_match_table,
3771         },
3772 };
3773
3774 static int __init gcc_sm8150_init(void)
3775 {
3776         return platform_driver_register(&gcc_sm8150_driver);
3777 }
3778 subsys_initcall(gcc_sm8150_init);
3779
3780 static void __exit gcc_sm8150_exit(void)
3781 {
3782         platform_driver_unregister(&gcc_sm8150_driver);
3783 }
3784 module_exit(gcc_sm8150_exit);
3785
3786 MODULE_DESCRIPTION("QTI GCC SM8150 Driver");
3787 MODULE_LICENSE("GPL v2");