1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org>
7 #include <linux/clk-provider.h>
8 #include <linux/module.h>
9 #include <linux/of_device.h>
10 #include <linux/regmap.h>
12 #include <dt-bindings/clock/qcom,sm6375-gcc.h>
14 #include "clk-alpha-pll.h"
15 #include "clk-branch.h"
17 #include "clk-regmap.h"
18 #include "clk-regmap-divider.h"
19 #include "clk-regmap-mux.h"
20 #include "clk-regmap-phy-mux.h"
52 static struct pll_vco lucid_vco[] = {
53 { 249600000, 2000000000, 0 },
56 static struct pll_vco zonda_vco[] = {
57 { 595200000, 3600000000UL, 0 },
60 static struct clk_alpha_pll gpll0 = {
62 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
64 .enable_reg = 0x79000,
65 .enable_mask = BIT(0),
66 .hw.init = &(struct clk_init_data){
68 .parent_data = &(const struct clk_parent_data){
72 .ops = &clk_alpha_pll_fixed_lucid_ops,
77 static const struct clk_div_table post_div_table_gpll0_out_even[] = {
82 static struct clk_alpha_pll_postdiv gpll0_out_even = {
85 .post_div_table = post_div_table_gpll0_out_even,
86 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even),
88 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
89 .clkr.hw.init = &(struct clk_init_data){
90 .name = "gpll0_out_even",
91 .parent_hws = (const struct clk_hw*[]){
95 .ops = &clk_alpha_pll_postdiv_lucid_ops,
99 static const struct clk_div_table post_div_table_gpll0_out_odd[] = {
104 static struct clk_alpha_pll_postdiv gpll0_out_odd = {
106 .post_div_shift = 12,
107 .post_div_table = post_div_table_gpll0_out_odd,
108 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_odd),
110 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
111 .clkr.hw.init = &(struct clk_init_data){
112 .name = "gpll0_out_odd",
113 .parent_hws = (const struct clk_hw*[]){
117 .ops = &clk_alpha_pll_postdiv_lucid_ops,
121 static struct clk_alpha_pll gpll1 = {
123 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
125 .enable_reg = 0x79000,
126 .enable_mask = BIT(1),
127 .hw.init = &(struct clk_init_data){
129 .parent_data = &(const struct clk_parent_data){
133 .ops = &clk_alpha_pll_lucid_ops,
138 /* 1152MHz Configuration */
139 static const struct alpha_pll_config gpll10_config = {
142 .config_ctl_val = 0x20485699,
143 .config_ctl_hi_val = 0x00002261,
144 .config_ctl_hi1_val = 0x329a299c,
145 .user_ctl_val = 0x00000001,
146 .user_ctl_hi_val = 0x00000805,
147 .user_ctl_hi1_val = 0x00000000,
150 static struct clk_alpha_pll gpll10 = {
152 .vco_table = lucid_vco,
153 .num_vco = ARRAY_SIZE(lucid_vco),
154 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
155 .flags = SUPPORTS_FSM_LEGACY_MODE,
157 .enable_reg = 0x79000,
158 .enable_mask = BIT(10),
159 .hw.init = &(struct clk_init_data){
161 .parent_data = &(const struct clk_parent_data){
165 .ops = &clk_alpha_pll_fixed_lucid_ops,
170 /* 532MHz Configuration */
171 static const struct alpha_pll_config gpll11_config = {
174 .config_ctl_val = 0x20485699,
175 .config_ctl_hi_val = 0x00002261,
176 .config_ctl_hi1_val = 0x329a299c,
177 .user_ctl_val = 0x00000001,
178 .user_ctl_hi_val = 0x00000805,
179 .user_ctl_hi1_val = 0x00000000,
182 static struct clk_alpha_pll gpll11 = {
184 .vco_table = lucid_vco,
185 .num_vco = ARRAY_SIZE(lucid_vco),
186 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
187 .flags = SUPPORTS_FSM_LEGACY_MODE,
189 .enable_reg = 0x79000,
190 .enable_mask = BIT(11),
191 .hw.init = &(struct clk_init_data){
193 .parent_data = &(const struct clk_parent_data){
197 .ops = &clk_alpha_pll_lucid_ops,
202 static struct clk_alpha_pll gpll3 = {
204 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
206 .enable_reg = 0x79000,
207 .enable_mask = BIT(3),
208 .hw.init = &(struct clk_init_data){
210 .parent_data = &(const struct clk_parent_data){
214 .ops = &clk_alpha_pll_fixed_lucid_ops,
219 static const struct clk_div_table post_div_table_gpll3_out_even[] = {
224 static struct clk_alpha_pll_postdiv gpll3_out_even = {
227 .post_div_table = post_div_table_gpll3_out_even,
228 .num_post_div = ARRAY_SIZE(post_div_table_gpll3_out_even),
230 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
231 .clkr.hw.init = &(struct clk_init_data){
232 .name = "gpll3_out_even",
233 .parent_hws = (const struct clk_hw*[]){
237 .ops = &clk_alpha_pll_postdiv_lucid_ops,
241 static struct clk_alpha_pll gpll4 = {
243 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
245 .enable_reg = 0x79000,
246 .enable_mask = BIT(4),
247 .hw.init = &(struct clk_init_data){
249 .parent_data = &(const struct clk_parent_data){
253 .ops = &clk_alpha_pll_fixed_lucid_ops,
258 static struct clk_alpha_pll gpll5 = {
260 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
262 .enable_reg = 0x79000,
263 .enable_mask = BIT(5),
264 .hw.init = &(struct clk_init_data){
266 .parent_data = &(const struct clk_parent_data){
270 .ops = &clk_alpha_pll_fixed_lucid_ops,
275 static struct clk_alpha_pll gpll6 = {
277 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
279 .enable_reg = 0x79000,
280 .enable_mask = BIT(6),
281 .hw.init = &(struct clk_init_data){
283 .parent_data = &(const struct clk_parent_data){
287 .ops = &clk_alpha_pll_fixed_lucid_ops,
292 static const struct clk_div_table post_div_table_gpll6_out_even[] = {
297 static struct clk_alpha_pll_postdiv gpll6_out_even = {
300 .post_div_table = post_div_table_gpll6_out_even,
301 .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_even),
303 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
304 .clkr.hw.init = &(struct clk_init_data){
305 .name = "gpll6_out_even",
306 .parent_hws = (const struct clk_hw*[]){
310 .ops = &clk_alpha_pll_postdiv_lucid_ops,
314 static struct clk_alpha_pll gpll7 = {
316 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
318 .enable_reg = 0x79000,
319 .enable_mask = BIT(7),
320 .hw.init = &(struct clk_init_data){
322 .parent_data = &(const struct clk_parent_data){
326 .ops = &clk_alpha_pll_fixed_lucid_ops,
331 /* 400MHz Configuration */
332 static const struct alpha_pll_config gpll8_config = {
335 .config_ctl_val = 0x20485699,
336 .config_ctl_hi_val = 0x00002261,
337 .config_ctl_hi1_val = 0x329a299c,
338 .user_ctl_val = 0x00000101,
339 .user_ctl_hi_val = 0x00000805,
340 .user_ctl_hi1_val = 0x00000000,
343 static struct clk_alpha_pll gpll8 = {
345 .vco_table = lucid_vco,
346 .num_vco = ARRAY_SIZE(lucid_vco),
347 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
348 .flags = SUPPORTS_FSM_LEGACY_MODE,
350 .enable_reg = 0x79000,
351 .enable_mask = BIT(8),
352 .hw.init = &(struct clk_init_data){
354 .parent_data = &(const struct clk_parent_data){
358 .ops = &clk_alpha_pll_lucid_ops,
363 static const struct clk_div_table post_div_table_gpll8_out_even[] = {
368 static struct clk_alpha_pll_postdiv gpll8_out_even = {
371 .post_div_table = post_div_table_gpll8_out_even,
372 .num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_even),
374 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
375 .clkr.hw.init = &(struct clk_init_data){
376 .name = "gpll8_out_even",
377 .parent_hws = (const struct clk_hw*[]){
381 .flags = CLK_SET_RATE_PARENT,
382 .ops = &clk_alpha_pll_postdiv_lucid_ops,
386 /* 1440MHz Configuration */
387 static const struct alpha_pll_config gpll9_config = {
390 .config_ctl_val = 0x08200800,
391 .config_ctl_hi_val = 0x05022011,
392 .config_ctl_hi1_val = 0x08000000,
393 .user_ctl_val = 0x00000301,
396 static struct clk_alpha_pll gpll9 = {
398 .vco_table = zonda_vco,
399 .num_vco = ARRAY_SIZE(zonda_vco),
400 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
402 .enable_reg = 0x79000,
403 .enable_mask = BIT(9),
404 .hw.init = &(struct clk_init_data){
406 .parent_data = &(const struct clk_parent_data){
410 .ops = &clk_alpha_pll_zonda_ops,
415 static const struct clk_div_table post_div_table_gpll9_out_main[] = {
420 static struct clk_alpha_pll_postdiv gpll9_out_main = {
423 .post_div_table = post_div_table_gpll9_out_main,
424 .num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main),
426 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
427 .clkr.hw.init = &(struct clk_init_data){
428 .name = "gpll9_out_main",
429 .parent_hws = (const struct clk_hw*[]){
433 .flags = CLK_SET_RATE_PARENT,
434 .ops = &clk_alpha_pll_postdiv_zonda_ops,
438 static const struct parent_map gcc_parent_map_0[] = {
440 { P_GPLL0_OUT_MAIN, 1 },
441 { P_GPLL0_OUT_EVEN, 2 },
444 static const struct clk_parent_data gcc_parent_data_0[] = {
445 { .index = DT_BI_TCXO },
446 { .hw = &gpll0.clkr.hw },
447 { .hw = &gpll0_out_even.clkr.hw },
450 static const struct parent_map gcc_parent_map_1[] = {
452 { P_GPLL0_OUT_MAIN, 1 },
453 { P_GPLL0_OUT_EVEN, 2 },
454 { P_GPLL6_OUT_EVEN, 4 },
457 static const struct clk_parent_data gcc_parent_data_1[] = {
458 { .index = DT_BI_TCXO },
459 { .hw = &gpll0.clkr.hw },
460 { .hw = &gpll0_out_even.clkr.hw },
461 { .hw = &gpll6_out_even.clkr.hw },
464 static const struct parent_map gcc_parent_map_2[] = {
466 { P_GPLL0_OUT_MAIN, 1 },
467 { P_GPLL0_OUT_EVEN, 2 },
468 { P_GPLL0_OUT_ODD, 4 },
471 static const struct clk_parent_data gcc_parent_data_2[] = {
472 { .index = DT_BI_TCXO },
473 { .hw = &gpll0.clkr.hw },
474 { .hw = &gpll0_out_even.clkr.hw },
475 { .hw = &gpll0_out_odd.clkr.hw },
478 static const struct clk_parent_data gcc_parent_data_2_ao[] = {
479 { .index = DT_BI_TCXO_AO },
480 { .hw = &gpll0.clkr.hw },
481 { .hw = &gpll0_out_even.clkr.hw },
482 { .hw = &gpll0_out_odd.clkr.hw },
485 static const struct parent_map gcc_parent_map_3[] = {
487 { P_GPLL0_OUT_MAIN, 1 },
488 { P_GPLL9_OUT_EARLY, 2 },
489 { P_GPLL10_OUT_EVEN, 3 },
490 { P_GPLL9_OUT_MAIN, 4 },
491 { P_GPLL3_OUT_EVEN, 6 },
494 static const struct clk_parent_data gcc_parent_data_3[] = {
495 { .index = DT_BI_TCXO },
496 { .hw = &gpll0.clkr.hw },
497 { .hw = &gpll9.clkr.hw },
498 { .hw = &gpll10.clkr.hw },
499 { .hw = &gpll9_out_main.clkr.hw },
500 { .hw = &gpll3_out_even.clkr.hw },
503 static const struct parent_map gcc_parent_map_4[] = {
505 { P_GPLL0_OUT_MAIN, 1 },
506 { P_GPLL0_OUT_EVEN, 2 },
507 { P_GPLL0_OUT_ODD, 4 },
508 { P_GPLL4_OUT_EVEN, 5 },
509 { P_GPLL3_OUT_EVEN, 6 },
512 static const struct clk_parent_data gcc_parent_data_4[] = {
513 { .index = DT_BI_TCXO },
514 { .hw = &gpll0.clkr.hw },
515 { .hw = &gpll0_out_even.clkr.hw },
516 { .hw = &gpll0_out_odd.clkr.hw },
517 { .hw = &gpll4.clkr.hw },
518 { .hw = &gpll3_out_even.clkr.hw },
521 static const struct parent_map gcc_parent_map_5[] = {
523 { P_GPLL0_OUT_MAIN, 1 },
524 { P_GPLL8_OUT_MAIN, 2 },
525 { P_GPLL10_OUT_EVEN, 3 },
526 { P_GPLL9_OUT_MAIN, 4 },
527 { P_GPLL8_OUT_EVEN, 5 },
528 { P_GPLL3_OUT_EVEN, 6 },
531 static const struct clk_parent_data gcc_parent_data_5[] = {
532 { .index = DT_BI_TCXO },
533 { .hw = &gpll0.clkr.hw },
534 { .hw = &gpll8.clkr.hw },
535 { .hw = &gpll10.clkr.hw },
536 { .hw = &gpll9_out_main.clkr.hw },
537 { .hw = &gpll8_out_even.clkr.hw },
538 { .hw = &gpll3_out_even.clkr.hw },
541 static const struct parent_map gcc_parent_map_6[] = {
543 { P_GPLL0_OUT_MAIN, 1 },
544 { P_GPLL8_OUT_MAIN, 2 },
545 { P_GPLL5_OUT_EVEN, 3 },
546 { P_GPLL9_OUT_MAIN, 4 },
547 { P_GPLL8_OUT_EVEN, 5 },
548 { P_GPLL3_OUT_MAIN, 6 },
551 static const struct clk_parent_data gcc_parent_data_6[] = {
552 { .index = DT_BI_TCXO },
553 { .hw = &gpll0.clkr.hw },
554 { .hw = &gpll8.clkr.hw },
555 { .hw = &gpll5.clkr.hw },
556 { .hw = &gpll9_out_main.clkr.hw },
557 { .hw = &gpll8_out_even.clkr.hw },
558 { .hw = &gpll3.clkr.hw },
561 static const struct parent_map gcc_parent_map_7[] = {
563 { P_GPLL0_OUT_MAIN, 1 },
564 { P_GPLL0_OUT_EVEN, 2 },
565 { P_GPLL0_OUT_ODD, 4 },
569 static const struct clk_parent_data gcc_parent_data_7[] = {
570 { .index = DT_BI_TCXO },
571 { .hw = &gpll0.clkr.hw },
572 { .hw = &gpll0_out_even.clkr.hw },
573 { .hw = &gpll0_out_odd.clkr.hw },
574 { .index = DT_SLEEP_CLK },
577 static const struct parent_map gcc_parent_map_8[] = {
579 { P_GPLL0_OUT_MAIN, 1 },
580 { P_GPLL0_OUT_EVEN, 2 },
581 { P_GPLL10_OUT_EVEN, 3 },
582 { P_GPLL4_OUT_EVEN, 5 },
583 { P_GPLL3_OUT_MAIN, 6 },
586 static const struct clk_parent_data gcc_parent_data_8[] = {
587 { .index = DT_BI_TCXO },
588 { .hw = &gpll0.clkr.hw },
589 { .hw = &gpll0_out_even.clkr.hw },
590 { .hw = &gpll10.clkr.hw },
591 { .hw = &gpll4.clkr.hw },
592 { .hw = &gpll3.clkr.hw },
595 static const struct parent_map gcc_parent_map_9[] = {
597 { P_GPLL0_OUT_MAIN, 1 },
598 { P_GPLL0_OUT_EVEN, 2 },
599 { P_GPLL10_OUT_EVEN, 3 },
600 { P_GPLL9_OUT_MAIN, 4 },
601 { P_GPLL8_OUT_EVEN, 5 },
602 { P_GPLL3_OUT_MAIN, 6 },
605 static const struct clk_parent_data gcc_parent_data_9[] = {
606 { .index = DT_BI_TCXO },
607 { .hw = &gpll0.clkr.hw },
608 { .hw = &gpll0_out_even.clkr.hw },
609 { .hw = &gpll10.clkr.hw },
610 { .hw = &gpll9_out_main.clkr.hw },
611 { .hw = &gpll8_out_even.clkr.hw },
612 { .hw = &gpll3.clkr.hw },
615 static const struct parent_map gcc_parent_map_10[] = {
617 { P_GPLL0_OUT_MAIN, 1 },
618 { P_GPLL8_OUT_MAIN, 2 },
619 { P_GPLL10_OUT_EVEN, 3 },
620 { P_GPLL9_OUT_MAIN, 4 },
621 { P_GPLL8_OUT_EVEN, 5 },
622 { P_GPLL3_OUT_MAIN, 6 },
625 static const struct clk_parent_data gcc_parent_data_10[] = {
626 { .index = DT_BI_TCXO },
627 { .hw = &gpll0.clkr.hw },
628 { .hw = &gpll8.clkr.hw },
629 { .hw = &gpll10.clkr.hw },
630 { .hw = &gpll9_out_main.clkr.hw },
631 { .hw = &gpll8_out_even.clkr.hw },
632 { .hw = &gpll3.clkr.hw },
635 static const struct parent_map gcc_parent_map_11[] = {
637 { P_GPLL0_OUT_MAIN, 1 },
638 { P_GPLL8_OUT_MAIN, 2 },
639 { P_GPLL10_OUT_EVEN, 3 },
640 { P_GPLL6_OUT_MAIN, 4 },
641 { P_GPLL3_OUT_EVEN, 6 },
644 static const struct clk_parent_data gcc_parent_data_11[] = {
645 { .index = DT_BI_TCXO },
646 { .hw = &gpll0.clkr.hw },
647 { .hw = &gpll8.clkr.hw },
648 { .hw = &gpll10.clkr.hw },
649 { .hw = &gpll6.clkr.hw },
650 { .hw = &gpll3_out_even.clkr.hw },
653 static const struct parent_map gcc_parent_map_12[] = {
655 { P_GPLL0_OUT_MAIN, 1 },
656 { P_GPLL0_OUT_EVEN, 2 },
657 { P_GPLL7_OUT_EVEN, 3 },
658 { P_GPLL4_OUT_EVEN, 5 },
661 static const struct clk_parent_data gcc_parent_data_12[] = {
662 { .index = DT_BI_TCXO },
663 { .hw = &gpll0.clkr.hw },
664 { .hw = &gpll0_out_even.clkr.hw },
665 { .hw = &gpll7.clkr.hw },
666 { .hw = &gpll4.clkr.hw },
669 static const struct parent_map gcc_parent_map_13[] = {
674 static const struct clk_parent_data gcc_parent_data_13[] = {
675 { .index = DT_BI_TCXO },
676 { .index = DT_SLEEP_CLK },
679 static const struct parent_map gcc_parent_map_14[] = {
681 { P_GPLL11_OUT_ODD, 2 },
682 { P_GPLL11_OUT_EVEN, 3 },
685 static const struct clk_parent_data gcc_parent_data_14[] = {
686 { .index = DT_BI_TCXO },
687 { .hw = &gpll11.clkr.hw },
688 { .hw = &gpll11.clkr.hw },
691 static const struct freq_tbl ftbl_gcc_camss_axi_clk_src[] = {
692 F(19200000, P_BI_TCXO, 1, 0, 0),
693 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
694 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
695 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
699 static struct clk_rcg2 gcc_camss_axi_clk_src = {
703 .parent_map = gcc_parent_map_8,
704 .freq_tbl = ftbl_gcc_camss_axi_clk_src,
705 .clkr.hw.init = &(struct clk_init_data){
706 .name = "gcc_camss_axi_clk_src",
707 .parent_data = gcc_parent_data_8,
708 .num_parents = ARRAY_SIZE(gcc_parent_data_8),
709 .ops = &clk_rcg2_shared_ops,
713 static const struct freq_tbl ftbl_gcc_camss_cci_0_clk_src[] = {
714 F(19200000, P_BI_TCXO, 1, 0, 0),
715 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
719 static struct clk_rcg2 gcc_camss_cci_0_clk_src = {
723 .parent_map = gcc_parent_map_9,
724 .freq_tbl = ftbl_gcc_camss_cci_0_clk_src,
725 .clkr.hw.init = &(struct clk_init_data){
726 .name = "gcc_camss_cci_0_clk_src",
727 .parent_data = gcc_parent_data_9,
728 .num_parents = ARRAY_SIZE(gcc_parent_data_9),
729 .ops = &clk_rcg2_shared_ops,
733 static struct clk_rcg2 gcc_camss_cci_1_clk_src = {
737 .parent_map = gcc_parent_map_9,
738 .freq_tbl = ftbl_gcc_camss_cci_0_clk_src,
739 .clkr.hw.init = &(struct clk_init_data){
740 .name = "gcc_camss_cci_1_clk_src",
741 .parent_data = gcc_parent_data_9,
742 .num_parents = ARRAY_SIZE(gcc_parent_data_9),
743 .ops = &clk_rcg2_shared_ops,
747 static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = {
748 F(19200000, P_BI_TCXO, 1, 0, 0),
749 F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
750 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
754 static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = {
758 .parent_map = gcc_parent_map_4,
759 .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
760 .clkr.hw.init = &(struct clk_init_data){
761 .name = "gcc_camss_csi0phytimer_clk_src",
762 .parent_data = gcc_parent_data_4,
763 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
764 .ops = &clk_rcg2_shared_ops,
768 static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = {
772 .parent_map = gcc_parent_map_4,
773 .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
774 .clkr.hw.init = &(struct clk_init_data){
775 .name = "gcc_camss_csi1phytimer_clk_src",
776 .parent_data = gcc_parent_data_4,
777 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
778 .ops = &clk_rcg2_shared_ops,
782 static struct clk_rcg2 gcc_camss_csi2phytimer_clk_src = {
786 .parent_map = gcc_parent_map_4,
787 .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
788 .clkr.hw.init = &(struct clk_init_data){
789 .name = "gcc_camss_csi2phytimer_clk_src",
790 .parent_data = gcc_parent_data_4,
791 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
792 .ops = &clk_rcg2_shared_ops,
796 static struct clk_rcg2 gcc_camss_csi3phytimer_clk_src = {
800 .parent_map = gcc_parent_map_4,
801 .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
802 .clkr.hw.init = &(struct clk_init_data){
803 .name = "gcc_camss_csi3phytimer_clk_src",
804 .parent_data = gcc_parent_data_4,
805 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
806 .ops = &clk_rcg2_shared_ops,
810 static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = {
811 F(19200000, P_BI_TCXO, 1, 0, 0),
812 F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 15),
813 F(65454545, P_GPLL9_OUT_EARLY, 11, 1, 2),
817 static struct clk_rcg2 gcc_camss_mclk0_clk_src = {
821 .parent_map = gcc_parent_map_3,
822 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
823 .clkr.hw.init = &(struct clk_init_data){
824 .name = "gcc_camss_mclk0_clk_src",
825 .parent_data = gcc_parent_data_3,
826 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
827 .ops = &clk_rcg2_shared_ops,
831 static struct clk_rcg2 gcc_camss_mclk1_clk_src = {
835 .parent_map = gcc_parent_map_3,
836 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
837 .clkr.hw.init = &(struct clk_init_data){
838 .name = "gcc_camss_mclk1_clk_src",
839 .parent_data = gcc_parent_data_3,
840 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
841 .ops = &clk_rcg2_shared_ops,
845 static struct clk_rcg2 gcc_camss_mclk2_clk_src = {
849 .parent_map = gcc_parent_map_3,
850 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
851 .clkr.hw.init = &(struct clk_init_data){
852 .name = "gcc_camss_mclk2_clk_src",
853 .parent_data = gcc_parent_data_3,
854 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
855 .ops = &clk_rcg2_shared_ops,
859 static struct clk_rcg2 gcc_camss_mclk3_clk_src = {
863 .parent_map = gcc_parent_map_3,
864 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
865 .clkr.hw.init = &(struct clk_init_data){
866 .name = "gcc_camss_mclk3_clk_src",
867 .parent_data = gcc_parent_data_3,
868 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
869 .ops = &clk_rcg2_shared_ops,
873 static struct clk_rcg2 gcc_camss_mclk4_clk_src = {
877 .parent_map = gcc_parent_map_3,
878 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
879 .clkr.hw.init = &(struct clk_init_data){
880 .name = "gcc_camss_mclk4_clk_src",
881 .parent_data = gcc_parent_data_3,
882 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
883 .ops = &clk_rcg2_shared_ops,
887 static const struct freq_tbl ftbl_gcc_camss_ope_ahb_clk_src[] = {
888 F(19200000, P_BI_TCXO, 1, 0, 0),
889 F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
890 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
894 static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = {
898 .parent_map = gcc_parent_map_10,
899 .freq_tbl = ftbl_gcc_camss_ope_ahb_clk_src,
900 .clkr.hw.init = &(struct clk_init_data){
901 .name = "gcc_camss_ope_ahb_clk_src",
902 .parent_data = gcc_parent_data_10,
903 .num_parents = ARRAY_SIZE(gcc_parent_data_10),
904 .ops = &clk_rcg2_shared_ops,
908 static const struct freq_tbl ftbl_gcc_camss_ope_clk_src[] = {
909 F(19200000, P_BI_TCXO, 1, 0, 0),
910 F(200000000, P_GPLL8_OUT_EVEN, 1, 0, 0),
911 F(266600000, P_GPLL8_OUT_EVEN, 1, 0, 0),
912 F(480000000, P_GPLL8_OUT_EVEN, 1, 0, 0),
913 F(580000000, P_GPLL8_OUT_EVEN, 1, 0, 0),
917 static struct clk_rcg2 gcc_camss_ope_clk_src = {
921 .parent_map = gcc_parent_map_10,
922 .freq_tbl = ftbl_gcc_camss_ope_clk_src,
923 .clkr.hw.init = &(struct clk_init_data){
924 .name = "gcc_camss_ope_clk_src",
925 .parent_data = gcc_parent_data_10,
926 .num_parents = ARRAY_SIZE(gcc_parent_data_10),
927 .flags = CLK_SET_RATE_PARENT,
928 .ops = &clk_rcg2_shared_ops,
932 static const struct freq_tbl ftbl_gcc_camss_tfe_0_clk_src[] = {
933 F(19200000, P_BI_TCXO, 1, 0, 0),
934 F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
935 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
936 F(144000000, P_GPLL9_OUT_MAIN, 2.5, 0, 0),
937 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
938 F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
939 F(180000000, P_GPLL9_OUT_MAIN, 2, 0, 0),
940 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
941 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
942 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
943 F(329142857, P_GPLL10_OUT_EVEN, 3.5, 0, 0),
944 F(384000000, P_GPLL10_OUT_EVEN, 3, 0, 0),
945 F(460800000, P_GPLL10_OUT_EVEN, 2.5, 0, 0),
946 F(576000000, P_GPLL10_OUT_EVEN, 2, 0, 0),
950 static struct clk_rcg2 gcc_camss_tfe_0_clk_src = {
954 .parent_map = gcc_parent_map_5,
955 .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src,
956 .clkr.hw.init = &(struct clk_init_data){
957 .name = "gcc_camss_tfe_0_clk_src",
958 .parent_data = gcc_parent_data_5,
959 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
960 .ops = &clk_rcg2_shared_ops,
964 static const struct freq_tbl ftbl_gcc_camss_tfe_0_csid_clk_src[] = {
965 F(19200000, P_BI_TCXO, 1, 0, 0),
966 F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
967 F(266571429, P_GPLL5_OUT_EVEN, 3.5, 0, 0),
968 F(426400000, P_GPLL3_OUT_MAIN, 2.5, 0, 0),
969 F(466500000, P_GPLL5_OUT_EVEN, 2, 0, 0),
973 static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = {
977 .parent_map = gcc_parent_map_6,
978 .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src,
979 .clkr.hw.init = &(struct clk_init_data){
980 .name = "gcc_camss_tfe_0_csid_clk_src",
981 .parent_data = gcc_parent_data_6,
982 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
983 .ops = &clk_rcg2_shared_ops,
987 static struct clk_rcg2 gcc_camss_tfe_1_clk_src = {
991 .parent_map = gcc_parent_map_5,
992 .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src,
993 .clkr.hw.init = &(struct clk_init_data){
994 .name = "gcc_camss_tfe_1_clk_src",
995 .parent_data = gcc_parent_data_5,
996 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
997 .ops = &clk_rcg2_shared_ops,
1001 static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = {
1002 .cmd_rcgr = 0x520b4,
1005 .parent_map = gcc_parent_map_6,
1006 .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src,
1007 .clkr.hw.init = &(struct clk_init_data){
1008 .name = "gcc_camss_tfe_1_csid_clk_src",
1009 .parent_data = gcc_parent_data_6,
1010 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
1011 .ops = &clk_rcg2_shared_ops,
1015 static struct clk_rcg2 gcc_camss_tfe_2_clk_src = {
1016 .cmd_rcgr = 0x52044,
1019 .parent_map = gcc_parent_map_5,
1020 .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src,
1021 .clkr.hw.init = &(struct clk_init_data){
1022 .name = "gcc_camss_tfe_2_clk_src",
1023 .parent_data = gcc_parent_data_5,
1024 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
1025 .ops = &clk_rcg2_shared_ops,
1029 static struct clk_rcg2 gcc_camss_tfe_2_csid_clk_src = {
1030 .cmd_rcgr = 0x520d4,
1033 .parent_map = gcc_parent_map_6,
1034 .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src,
1035 .clkr.hw.init = &(struct clk_init_data){
1036 .name = "gcc_camss_tfe_2_csid_clk_src",
1037 .parent_data = gcc_parent_data_6,
1038 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
1039 .ops = &clk_rcg2_shared_ops,
1043 static const struct freq_tbl ftbl_gcc_camss_tfe_cphy_rx_clk_src[] = {
1044 F(19200000, P_BI_TCXO, 1, 0, 0),
1045 F(256000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
1046 F(384000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
1050 static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = {
1051 .cmd_rcgr = 0x52064,
1054 .parent_map = gcc_parent_map_11,
1055 .freq_tbl = ftbl_gcc_camss_tfe_cphy_rx_clk_src,
1056 .clkr.hw.init = &(struct clk_init_data){
1057 .name = "gcc_camss_tfe_cphy_rx_clk_src",
1058 .parent_data = gcc_parent_data_11,
1059 .num_parents = ARRAY_SIZE(gcc_parent_data_11),
1060 .ops = &clk_rcg2_shared_ops,
1064 static const struct freq_tbl ftbl_gcc_camss_top_ahb_clk_src[] = {
1065 F(19200000, P_BI_TCXO, 1, 0, 0),
1066 F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0),
1067 F(80000000, P_GPLL0_OUT_MAIN, 7.5, 0, 0),
1071 static struct clk_rcg2 gcc_camss_top_ahb_clk_src = {
1072 .cmd_rcgr = 0x58010,
1075 .parent_map = gcc_parent_map_8,
1076 .freq_tbl = ftbl_gcc_camss_top_ahb_clk_src,
1077 .clkr.hw.init = &(struct clk_init_data){
1078 .name = "gcc_camss_top_ahb_clk_src",
1079 .parent_data = gcc_parent_data_8,
1080 .num_parents = ARRAY_SIZE(gcc_parent_data_8),
1081 .ops = &clk_rcg2_shared_ops,
1085 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
1086 F(19200000, P_BI_TCXO, 1, 0, 0),
1087 F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
1088 F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
1092 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
1093 .cmd_rcgr = 0x2b13c,
1096 .parent_map = gcc_parent_map_2,
1097 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
1098 .clkr.hw.init = &(struct clk_init_data){
1099 .name = "gcc_cpuss_ahb_clk_src",
1100 .parent_data = gcc_parent_data_2_ao,
1101 .num_parents = ARRAY_SIZE(gcc_parent_data_2_ao),
1102 .ops = &clk_rcg2_shared_ops,
1106 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
1107 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
1108 F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
1109 F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
1110 F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0),
1114 static struct clk_rcg2 gcc_gp1_clk_src = {
1115 .cmd_rcgr = 0x4d004,
1118 .parent_map = gcc_parent_map_7,
1119 .freq_tbl = ftbl_gcc_gp1_clk_src,
1120 .clkr.hw.init = &(struct clk_init_data){
1121 .name = "gcc_gp1_clk_src",
1122 .parent_data = gcc_parent_data_7,
1123 .num_parents = ARRAY_SIZE(gcc_parent_data_7),
1124 .ops = &clk_rcg2_shared_ops,
1128 static struct clk_rcg2 gcc_gp2_clk_src = {
1129 .cmd_rcgr = 0x4e004,
1132 .parent_map = gcc_parent_map_7,
1133 .freq_tbl = ftbl_gcc_gp1_clk_src,
1134 .clkr.hw.init = &(struct clk_init_data){
1135 .name = "gcc_gp2_clk_src",
1136 .parent_data = gcc_parent_data_7,
1137 .num_parents = ARRAY_SIZE(gcc_parent_data_7),
1138 .ops = &clk_rcg2_shared_ops,
1142 static struct clk_rcg2 gcc_gp3_clk_src = {
1143 .cmd_rcgr = 0x4f004,
1146 .parent_map = gcc_parent_map_7,
1147 .freq_tbl = ftbl_gcc_gp1_clk_src,
1148 .clkr.hw.init = &(struct clk_init_data){
1149 .name = "gcc_gp3_clk_src",
1150 .parent_data = gcc_parent_data_7,
1151 .num_parents = ARRAY_SIZE(gcc_parent_data_7),
1152 .ops = &clk_rcg2_shared_ops,
1156 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
1157 F(19200000, P_BI_TCXO, 1, 0, 0),
1158 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
1162 static struct clk_rcg2 gcc_pdm2_clk_src = {
1163 .cmd_rcgr = 0x20010,
1166 .parent_map = gcc_parent_map_0,
1167 .freq_tbl = ftbl_gcc_pdm2_clk_src,
1168 .clkr.hw.init = &(struct clk_init_data){
1169 .name = "gcc_pdm2_clk_src",
1170 .parent_data = gcc_parent_data_0,
1171 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1172 .ops = &clk_rcg2_shared_ops,
1176 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
1177 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
1178 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
1179 F(19200000, P_BI_TCXO, 1, 0, 0),
1180 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
1181 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
1182 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
1183 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
1184 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
1185 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
1186 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
1187 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
1188 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
1189 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
1190 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
1191 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
1192 F(128000000, P_GPLL6_OUT_EVEN, 3, 0, 0),
1196 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
1197 .name = "gcc_qupv3_wrap0_s0_clk_src",
1198 .parent_data = gcc_parent_data_1,
1199 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1200 .ops = &clk_rcg2_shared_ops,
1203 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
1204 .cmd_rcgr = 0x1f148,
1207 .parent_map = gcc_parent_map_1,
1208 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1209 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
1212 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
1213 .name = "gcc_qupv3_wrap0_s1_clk_src",
1214 .parent_data = gcc_parent_data_1,
1215 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1216 .ops = &clk_rcg2_shared_ops,
1219 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
1220 .cmd_rcgr = 0x1f278,
1223 .parent_map = gcc_parent_map_1,
1224 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1225 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
1228 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
1229 .name = "gcc_qupv3_wrap0_s2_clk_src",
1230 .parent_data = gcc_parent_data_1,
1231 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1232 .ops = &clk_rcg2_shared_ops,
1235 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
1236 .cmd_rcgr = 0x1f3a8,
1239 .parent_map = gcc_parent_map_1,
1240 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1241 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
1244 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
1245 .name = "gcc_qupv3_wrap0_s3_clk_src",
1246 .parent_data = gcc_parent_data_1,
1247 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1248 .ops = &clk_rcg2_shared_ops,
1251 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
1252 .cmd_rcgr = 0x1f4d8,
1255 .parent_map = gcc_parent_map_1,
1256 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1257 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
1260 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
1261 .name = "gcc_qupv3_wrap0_s4_clk_src",
1262 .parent_data = gcc_parent_data_1,
1263 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1264 .ops = &clk_rcg2_shared_ops,
1267 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
1268 .cmd_rcgr = 0x1f608,
1271 .parent_map = gcc_parent_map_1,
1272 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1273 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
1276 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
1277 .name = "gcc_qupv3_wrap0_s5_clk_src",
1278 .parent_data = gcc_parent_data_1,
1279 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1280 .ops = &clk_rcg2_shared_ops,
1283 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
1284 .cmd_rcgr = 0x1f738,
1287 .parent_map = gcc_parent_map_1,
1288 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1289 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
1292 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
1293 .name = "gcc_qupv3_wrap1_s0_clk_src",
1294 .parent_data = gcc_parent_data_1,
1295 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1296 .ops = &clk_rcg2_shared_ops,
1299 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
1300 .cmd_rcgr = 0x5301c,
1303 .parent_map = gcc_parent_map_1,
1304 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1305 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
1308 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
1309 .name = "gcc_qupv3_wrap1_s1_clk_src",
1310 .parent_data = gcc_parent_data_1,
1311 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1312 .ops = &clk_rcg2_shared_ops,
1315 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
1316 .cmd_rcgr = 0x5314c,
1319 .parent_map = gcc_parent_map_1,
1320 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1321 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
1324 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
1325 .name = "gcc_qupv3_wrap1_s2_clk_src",
1326 .parent_data = gcc_parent_data_1,
1327 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1328 .ops = &clk_rcg2_shared_ops,
1331 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
1332 .cmd_rcgr = 0x5327c,
1335 .parent_map = gcc_parent_map_1,
1336 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1337 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
1340 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
1341 .name = "gcc_qupv3_wrap1_s3_clk_src",
1342 .parent_data = gcc_parent_data_1,
1343 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1344 .ops = &clk_rcg2_shared_ops,
1347 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
1348 .cmd_rcgr = 0x533ac,
1351 .parent_map = gcc_parent_map_1,
1352 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1353 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
1356 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
1357 .name = "gcc_qupv3_wrap1_s4_clk_src",
1358 .parent_data = gcc_parent_data_1,
1359 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1360 .ops = &clk_rcg2_shared_ops,
1363 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
1364 .cmd_rcgr = 0x534dc,
1367 .parent_map = gcc_parent_map_1,
1368 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1369 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
1372 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
1373 .name = "gcc_qupv3_wrap1_s5_clk_src",
1374 .parent_data = gcc_parent_data_1,
1375 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1376 .ops = &clk_rcg2_shared_ops,
1379 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
1380 .cmd_rcgr = 0x5360c,
1383 .parent_map = gcc_parent_map_1,
1384 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1385 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
1388 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
1389 F(144000, P_BI_TCXO, 16, 3, 25),
1390 F(400000, P_BI_TCXO, 12, 1, 4),
1391 F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3),
1392 F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2),
1393 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
1394 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
1395 F(192000000, P_GPLL6_OUT_EVEN, 2, 0, 0),
1396 F(384000000, P_GPLL6_OUT_EVEN, 1, 0, 0),
1400 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
1401 .cmd_rcgr = 0x38028,
1404 .parent_map = gcc_parent_map_1,
1405 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
1406 .clkr.hw.init = &(struct clk_init_data){
1407 .name = "gcc_sdcc1_apps_clk_src",
1408 .parent_data = gcc_parent_data_1,
1409 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1410 .ops = &clk_rcg2_shared_ops,
1414 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
1415 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
1416 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
1417 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
1418 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1419 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
1423 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
1424 .cmd_rcgr = 0x38010,
1427 .parent_map = gcc_parent_map_0,
1428 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
1429 .clkr.hw.init = &(struct clk_init_data){
1430 .name = "gcc_sdcc1_ice_core_clk_src",
1431 .parent_data = gcc_parent_data_0,
1432 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1433 .ops = &clk_rcg2_shared_ops,
1437 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
1438 F(400000, P_BI_TCXO, 12, 1, 4),
1439 F(19200000, P_BI_TCXO, 1, 0, 0),
1440 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
1441 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
1442 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
1443 F(202000000, P_GPLL7_OUT_EVEN, 4, 0, 0),
1447 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
1448 .cmd_rcgr = 0x1e00c,
1451 .parent_map = gcc_parent_map_12,
1452 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
1453 .clkr.hw.init = &(struct clk_init_data){
1454 .name = "gcc_sdcc2_apps_clk_src",
1455 .parent_data = gcc_parent_data_12,
1456 .num_parents = ARRAY_SIZE(gcc_parent_data_12),
1457 .ops = &clk_rcg2_shared_ops,
1461 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
1462 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
1463 F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
1464 F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
1465 F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0),
1466 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1470 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
1471 .cmd_rcgr = 0x45020,
1474 .parent_map = gcc_parent_map_2,
1475 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
1476 .clkr.hw.init = &(struct clk_init_data){
1477 .name = "gcc_ufs_phy_axi_clk_src",
1478 .parent_data = gcc_parent_data_2,
1479 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1480 .ops = &clk_rcg2_shared_ops,
1484 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
1485 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
1486 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
1487 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
1488 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
1492 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
1493 .cmd_rcgr = 0x45048,
1496 .parent_map = gcc_parent_map_0,
1497 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
1498 .clkr.hw.init = &(struct clk_init_data){
1499 .name = "gcc_ufs_phy_ice_core_clk_src",
1500 .parent_data = gcc_parent_data_0,
1501 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1502 .ops = &clk_rcg2_shared_ops,
1506 static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
1507 F(9600000, P_BI_TCXO, 2, 0, 0),
1508 F(19200000, P_BI_TCXO, 1, 0, 0),
1512 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
1513 .cmd_rcgr = 0x4507c,
1516 .parent_map = gcc_parent_map_0,
1517 .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
1518 .clkr.hw.init = &(struct clk_init_data){
1519 .name = "gcc_ufs_phy_phy_aux_clk_src",
1520 .parent_data = gcc_parent_data_0,
1521 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1522 .ops = &clk_rcg2_shared_ops,
1526 static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
1527 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
1528 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
1529 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
1533 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1534 .cmd_rcgr = 0x45060,
1537 .parent_map = gcc_parent_map_0,
1538 .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
1539 .clkr.hw.init = &(struct clk_init_data){
1540 .name = "gcc_ufs_phy_unipro_core_clk_src",
1541 .parent_data = gcc_parent_data_0,
1542 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1543 .ops = &clk_rcg2_shared_ops,
1547 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1548 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
1549 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1550 F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0),
1551 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1555 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1556 .cmd_rcgr = 0x1a01c,
1559 .parent_map = gcc_parent_map_2,
1560 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1561 .clkr.hw.init = &(struct clk_init_data){
1562 .name = "gcc_usb30_prim_master_clk_src",
1563 .parent_data = gcc_parent_data_2,
1564 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1565 .ops = &clk_rcg2_shared_ops,
1569 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
1570 F(19200000, P_BI_TCXO, 1, 0, 0),
1574 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1575 .cmd_rcgr = 0x1a034,
1578 .parent_map = gcc_parent_map_0,
1579 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1580 .clkr.hw.init = &(struct clk_init_data){
1581 .name = "gcc_usb30_prim_mock_utmi_clk_src",
1582 .parent_data = gcc_parent_data_0,
1583 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1584 .ops = &clk_rcg2_shared_ops,
1588 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1589 .cmd_rcgr = 0x1a060,
1592 .parent_map = gcc_parent_map_13,
1593 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1594 .clkr.hw.init = &(struct clk_init_data){
1595 .name = "gcc_usb3_prim_phy_aux_clk_src",
1596 .parent_data = gcc_parent_data_13,
1597 .num_parents = ARRAY_SIZE(gcc_parent_data_13),
1598 .ops = &clk_rcg2_shared_ops,
1602 static const struct freq_tbl ftbl_gcc_video_venus_clk_src[] = {
1603 F(133000000, P_GPLL11_OUT_EVEN, 4, 0, 0),
1604 F(240000000, P_GPLL11_OUT_EVEN, 2.5, 0, 0),
1605 F(300000000, P_GPLL11_OUT_EVEN, 2, 0, 0),
1606 F(384000000, P_GPLL11_OUT_EVEN, 2, 0, 0),
1610 static struct clk_rcg2 gcc_video_venus_clk_src = {
1611 .cmd_rcgr = 0x58060,
1614 .parent_map = gcc_parent_map_14,
1615 .freq_tbl = ftbl_gcc_video_venus_clk_src,
1616 .clkr.hw.init = &(struct clk_init_data){
1617 .name = "gcc_video_venus_clk_src",
1618 .parent_data = gcc_parent_data_14,
1619 .num_parents = ARRAY_SIZE(gcc_parent_data_14),
1620 .flags = CLK_SET_RATE_PARENT,
1621 .ops = &clk_rcg2_shared_ops,
1625 static struct clk_regmap_div gcc_cpuss_ahb_postdiv_clk_src = {
1629 .clkr.hw.init = &(struct clk_init_data) {
1630 .name = "gcc_cpuss_ahb_postdiv_clk_src",
1631 .parent_hws = (const struct clk_hw*[]){
1632 &gcc_cpuss_ahb_clk_src.clkr.hw,
1635 .flags = CLK_SET_RATE_PARENT,
1636 .ops = &clk_regmap_div_ro_ops,
1640 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
1644 .clkr.hw.init = &(struct clk_init_data) {
1645 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
1646 .parent_hws = (const struct clk_hw*[]){
1647 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
1650 .flags = CLK_SET_RATE_PARENT,
1651 .ops = &clk_regmap_div_ro_ops,
1655 static struct clk_branch gcc_ahb2phy_csi_clk = {
1656 .halt_reg = 0x1d004,
1657 .halt_check = BRANCH_HALT_VOTED,
1658 .hwcg_reg = 0x1d004,
1661 .enable_reg = 0x1d004,
1662 .enable_mask = BIT(0),
1663 .hw.init = &(struct clk_init_data){
1664 .name = "gcc_ahb2phy_csi_clk",
1665 .ops = &clk_branch2_ops,
1670 static struct clk_branch gcc_ahb2phy_usb_clk = {
1671 .halt_reg = 0x1d008,
1672 .halt_check = BRANCH_HALT_VOTED,
1673 .hwcg_reg = 0x1d008,
1676 .enable_reg = 0x1d008,
1677 .enable_mask = BIT(0),
1678 .hw.init = &(struct clk_init_data){
1679 .name = "gcc_ahb2phy_usb_clk",
1680 .ops = &clk_branch2_ops,
1685 static struct clk_branch gcc_bimc_gpu_axi_clk = {
1686 .halt_reg = 0x71154,
1687 .halt_check = BRANCH_HALT_VOTED,
1688 .hwcg_reg = 0x71154,
1691 .enable_reg = 0x71154,
1692 .enable_mask = BIT(0),
1693 .hw.init = &(struct clk_init_data){
1694 .name = "gcc_bimc_gpu_axi_clk",
1695 .ops = &clk_branch2_ops,
1700 static struct clk_branch gcc_boot_rom_ahb_clk = {
1701 .halt_reg = 0x23004,
1702 .halt_check = BRANCH_HALT_VOTED,
1703 .hwcg_reg = 0x23004,
1706 .enable_reg = 0x79004,
1707 .enable_mask = BIT(10),
1708 .hw.init = &(struct clk_init_data){
1709 .name = "gcc_boot_rom_ahb_clk",
1710 .ops = &clk_branch2_ops,
1715 static struct clk_branch gcc_cam_throttle_nrt_clk = {
1716 .halt_reg = 0x17070,
1717 .halt_check = BRANCH_HALT_VOTED,
1718 .hwcg_reg = 0x17070,
1721 .enable_reg = 0x79004,
1722 .enable_mask = BIT(27),
1723 .hw.init = &(struct clk_init_data){
1724 .name = "gcc_cam_throttle_nrt_clk",
1725 .ops = &clk_branch2_ops,
1730 static struct clk_branch gcc_cam_throttle_rt_clk = {
1731 .halt_reg = 0x1706c,
1732 .halt_check = BRANCH_HALT_VOTED,
1733 .hwcg_reg = 0x1706c,
1736 .enable_reg = 0x79004,
1737 .enable_mask = BIT(26),
1738 .hw.init = &(struct clk_init_data){
1739 .name = "gcc_cam_throttle_rt_clk",
1740 .ops = &clk_branch2_ops,
1745 static struct clk_branch gcc_camera_ahb_clk = {
1746 .halt_reg = 0x17008,
1747 .halt_check = BRANCH_HALT_DELAY,
1748 .hwcg_reg = 0x17008,
1751 .enable_reg = 0x17008,
1752 .enable_mask = BIT(0),
1753 .hw.init = &(struct clk_init_data){
1754 .name = "gcc_camera_ahb_clk",
1755 .flags = CLK_IS_CRITICAL,
1756 .ops = &clk_branch2_ops,
1761 static struct clk_branch gcc_camss_axi_clk = {
1762 .halt_reg = 0x58044,
1763 .halt_check = BRANCH_HALT,
1765 .enable_reg = 0x58044,
1766 .enable_mask = BIT(0),
1767 .hw.init = &(struct clk_init_data){
1768 .name = "gcc_camss_axi_clk",
1769 .parent_data = &(const struct clk_parent_data){
1770 .hw = &gcc_camss_axi_clk_src.clkr.hw,
1773 .flags = CLK_SET_RATE_PARENT,
1774 .ops = &clk_branch2_ops,
1779 static struct clk_branch gcc_camss_cci_0_clk = {
1780 .halt_reg = 0x56018,
1781 .halt_check = BRANCH_HALT,
1783 .enable_reg = 0x56018,
1784 .enable_mask = BIT(0),
1785 .hw.init = &(struct clk_init_data){
1786 .name = "gcc_camss_cci_0_clk",
1787 .parent_data = &(const struct clk_parent_data){
1788 .hw = &gcc_camss_cci_0_clk_src.clkr.hw,
1791 .flags = CLK_SET_RATE_PARENT,
1792 .ops = &clk_branch2_ops,
1797 static struct clk_branch gcc_camss_cci_1_clk = {
1798 .halt_reg = 0x5c018,
1799 .halt_check = BRANCH_HALT,
1801 .enable_reg = 0x5c018,
1802 .enable_mask = BIT(0),
1803 .hw.init = &(struct clk_init_data){
1804 .name = "gcc_camss_cci_1_clk",
1805 .parent_data = &(const struct clk_parent_data){
1806 .hw = &gcc_camss_cci_1_clk_src.clkr.hw,
1809 .flags = CLK_SET_RATE_PARENT,
1810 .ops = &clk_branch2_ops,
1815 static struct clk_branch gcc_camss_cphy_0_clk = {
1816 .halt_reg = 0x52088,
1817 .halt_check = BRANCH_HALT,
1819 .enable_reg = 0x52088,
1820 .enable_mask = BIT(0),
1821 .hw.init = &(struct clk_init_data){
1822 .name = "gcc_camss_cphy_0_clk",
1823 .parent_data = &(const struct clk_parent_data){
1824 .hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
1827 .flags = CLK_SET_RATE_PARENT,
1828 .ops = &clk_branch2_ops,
1833 static struct clk_branch gcc_camss_cphy_1_clk = {
1834 .halt_reg = 0x5208c,
1835 .halt_check = BRANCH_HALT,
1837 .enable_reg = 0x5208c,
1838 .enable_mask = BIT(0),
1839 .hw.init = &(struct clk_init_data){
1840 .name = "gcc_camss_cphy_1_clk",
1841 .parent_data = &(const struct clk_parent_data){
1842 .hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
1845 .flags = CLK_SET_RATE_PARENT,
1846 .ops = &clk_branch2_ops,
1851 static struct clk_branch gcc_camss_cphy_2_clk = {
1852 .halt_reg = 0x52090,
1853 .halt_check = BRANCH_HALT,
1855 .enable_reg = 0x52090,
1856 .enable_mask = BIT(0),
1857 .hw.init = &(struct clk_init_data){
1858 .name = "gcc_camss_cphy_2_clk",
1859 .parent_data = &(const struct clk_parent_data){
1860 .hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
1863 .flags = CLK_SET_RATE_PARENT,
1864 .ops = &clk_branch2_ops,
1869 static struct clk_branch gcc_camss_cphy_3_clk = {
1870 .halt_reg = 0x520f8,
1871 .halt_check = BRANCH_HALT,
1873 .enable_reg = 0x520f8,
1874 .enable_mask = BIT(0),
1875 .hw.init = &(struct clk_init_data){
1876 .name = "gcc_camss_cphy_3_clk",
1877 .parent_data = &(const struct clk_parent_data){
1878 .hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
1881 .flags = CLK_SET_RATE_PARENT,
1882 .ops = &clk_branch2_ops,
1887 static struct clk_branch gcc_camss_csi0phytimer_clk = {
1888 .halt_reg = 0x59018,
1889 .halt_check = BRANCH_HALT,
1891 .enable_reg = 0x59018,
1892 .enable_mask = BIT(0),
1893 .hw.init = &(struct clk_init_data){
1894 .name = "gcc_camss_csi0phytimer_clk",
1895 .parent_data = &(const struct clk_parent_data){
1896 .hw = &gcc_camss_csi0phytimer_clk_src.clkr.hw,
1899 .flags = CLK_SET_RATE_PARENT,
1900 .ops = &clk_branch2_ops,
1905 static struct clk_branch gcc_camss_csi1phytimer_clk = {
1906 .halt_reg = 0x59034,
1907 .halt_check = BRANCH_HALT,
1909 .enable_reg = 0x59034,
1910 .enable_mask = BIT(0),
1911 .hw.init = &(struct clk_init_data){
1912 .name = "gcc_camss_csi1phytimer_clk",
1913 .parent_data = &(const struct clk_parent_data){
1914 .hw = &gcc_camss_csi1phytimer_clk_src.clkr.hw,
1917 .flags = CLK_SET_RATE_PARENT,
1918 .ops = &clk_branch2_ops,
1923 static struct clk_branch gcc_camss_csi2phytimer_clk = {
1924 .halt_reg = 0x59050,
1925 .halt_check = BRANCH_HALT,
1927 .enable_reg = 0x59050,
1928 .enable_mask = BIT(0),
1929 .hw.init = &(struct clk_init_data){
1930 .name = "gcc_camss_csi2phytimer_clk",
1931 .parent_data = &(const struct clk_parent_data){
1932 .hw = &gcc_camss_csi2phytimer_clk_src.clkr.hw,
1935 .flags = CLK_SET_RATE_PARENT,
1936 .ops = &clk_branch2_ops,
1941 static struct clk_branch gcc_camss_csi3phytimer_clk = {
1942 .halt_reg = 0x5906c,
1943 .halt_check = BRANCH_HALT,
1945 .enable_reg = 0x5906c,
1946 .enable_mask = BIT(0),
1947 .hw.init = &(struct clk_init_data){
1948 .name = "gcc_camss_csi3phytimer_clk",
1949 .parent_data = &(const struct clk_parent_data){
1950 .hw = &gcc_camss_csi3phytimer_clk_src.clkr.hw,
1953 .flags = CLK_SET_RATE_PARENT,
1954 .ops = &clk_branch2_ops,
1959 static struct clk_branch gcc_camss_mclk0_clk = {
1960 .halt_reg = 0x51018,
1961 .halt_check = BRANCH_HALT,
1963 .enable_reg = 0x51018,
1964 .enable_mask = BIT(0),
1965 .hw.init = &(struct clk_init_data){
1966 .name = "gcc_camss_mclk0_clk",
1967 .parent_data = &(const struct clk_parent_data){
1968 .hw = &gcc_camss_mclk0_clk_src.clkr.hw,
1971 .flags = CLK_SET_RATE_PARENT,
1972 .ops = &clk_branch2_ops,
1977 static struct clk_branch gcc_camss_mclk1_clk = {
1978 .halt_reg = 0x51034,
1979 .halt_check = BRANCH_HALT,
1981 .enable_reg = 0x51034,
1982 .enable_mask = BIT(0),
1983 .hw.init = &(struct clk_init_data){
1984 .name = "gcc_camss_mclk1_clk",
1985 .parent_data = &(const struct clk_parent_data){
1986 .hw = &gcc_camss_mclk1_clk_src.clkr.hw,
1989 .flags = CLK_SET_RATE_PARENT,
1990 .ops = &clk_branch2_ops,
1995 static struct clk_branch gcc_camss_mclk2_clk = {
1996 .halt_reg = 0x51050,
1997 .halt_check = BRANCH_HALT,
1999 .enable_reg = 0x51050,
2000 .enable_mask = BIT(0),
2001 .hw.init = &(struct clk_init_data){
2002 .name = "gcc_camss_mclk2_clk",
2003 .parent_data = &(const struct clk_parent_data){
2004 .hw = &gcc_camss_mclk2_clk_src.clkr.hw,
2007 .flags = CLK_SET_RATE_PARENT,
2008 .ops = &clk_branch2_ops,
2013 static struct clk_branch gcc_camss_mclk3_clk = {
2014 .halt_reg = 0x5106c,
2015 .halt_check = BRANCH_HALT,
2017 .enable_reg = 0x5106c,
2018 .enable_mask = BIT(0),
2019 .hw.init = &(struct clk_init_data){
2020 .name = "gcc_camss_mclk3_clk",
2021 .parent_data = &(const struct clk_parent_data){
2022 .hw = &gcc_camss_mclk3_clk_src.clkr.hw,
2025 .flags = CLK_SET_RATE_PARENT,
2026 .ops = &clk_branch2_ops,
2031 static struct clk_branch gcc_camss_mclk4_clk = {
2032 .halt_reg = 0x51088,
2033 .halt_check = BRANCH_HALT,
2035 .enable_reg = 0x51088,
2036 .enable_mask = BIT(0),
2037 .hw.init = &(struct clk_init_data){
2038 .name = "gcc_camss_mclk4_clk",
2039 .parent_data = &(const struct clk_parent_data){
2040 .hw = &gcc_camss_mclk4_clk_src.clkr.hw,
2043 .flags = CLK_SET_RATE_PARENT,
2044 .ops = &clk_branch2_ops,
2049 static struct clk_branch gcc_camss_nrt_axi_clk = {
2050 .halt_reg = 0x58054,
2051 .halt_check = BRANCH_HALT,
2053 .enable_reg = 0x58054,
2054 .enable_mask = BIT(0),
2055 .hw.init = &(struct clk_init_data){
2056 .name = "gcc_camss_nrt_axi_clk",
2057 .ops = &clk_branch2_ops,
2062 static struct clk_branch gcc_camss_ope_ahb_clk = {
2063 .halt_reg = 0x5503c,
2064 .halt_check = BRANCH_HALT,
2066 .enable_reg = 0x5503c,
2067 .enable_mask = BIT(0),
2068 .hw.init = &(struct clk_init_data){
2069 .name = "gcc_camss_ope_ahb_clk",
2070 .parent_data = &(const struct clk_parent_data){
2071 .hw = &gcc_camss_ope_ahb_clk_src.clkr.hw,
2074 .flags = CLK_SET_RATE_PARENT,
2075 .ops = &clk_branch2_ops,
2080 static struct clk_branch gcc_camss_ope_clk = {
2081 .halt_reg = 0x5501c,
2082 .halt_check = BRANCH_HALT,
2084 .enable_reg = 0x5501c,
2085 .enable_mask = BIT(0),
2086 .hw.init = &(struct clk_init_data){
2087 .name = "gcc_camss_ope_clk",
2088 .parent_data = &(const struct clk_parent_data){
2089 .hw = &gcc_camss_ope_clk_src.clkr.hw,
2092 .flags = CLK_SET_RATE_PARENT,
2093 .ops = &clk_branch2_ops,
2098 static struct clk_branch gcc_camss_rt_axi_clk = {
2099 .halt_reg = 0x5805c,
2100 .halt_check = BRANCH_HALT,
2102 .enable_reg = 0x5805c,
2103 .enable_mask = BIT(0),
2104 .hw.init = &(struct clk_init_data){
2105 .name = "gcc_camss_rt_axi_clk",
2106 .ops = &clk_branch2_ops,
2111 static struct clk_branch gcc_camss_tfe_0_clk = {
2112 .halt_reg = 0x5201c,
2113 .halt_check = BRANCH_HALT,
2115 .enable_reg = 0x5201c,
2116 .enable_mask = BIT(0),
2117 .hw.init = &(struct clk_init_data){
2118 .name = "gcc_camss_tfe_0_clk",
2119 .parent_data = &(const struct clk_parent_data){
2120 .hw = &gcc_camss_tfe_0_clk_src.clkr.hw,
2123 .flags = CLK_SET_RATE_PARENT,
2124 .ops = &clk_branch2_ops,
2129 static struct clk_branch gcc_camss_tfe_0_cphy_rx_clk = {
2130 .halt_reg = 0x5207c,
2131 .halt_check = BRANCH_HALT,
2133 .enable_reg = 0x5207c,
2134 .enable_mask = BIT(0),
2135 .hw.init = &(struct clk_init_data){
2136 .name = "gcc_camss_tfe_0_cphy_rx_clk",
2137 .parent_data = &(const struct clk_parent_data){
2138 .hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
2141 .flags = CLK_SET_RATE_PARENT,
2142 .ops = &clk_branch2_ops,
2147 static struct clk_branch gcc_camss_tfe_0_csid_clk = {
2148 .halt_reg = 0x520ac,
2149 .halt_check = BRANCH_HALT,
2151 .enable_reg = 0x520ac,
2152 .enable_mask = BIT(0),
2153 .hw.init = &(struct clk_init_data){
2154 .name = "gcc_camss_tfe_0_csid_clk",
2155 .parent_data = &(const struct clk_parent_data){
2156 .hw = &gcc_camss_tfe_0_csid_clk_src.clkr.hw,
2159 .flags = CLK_SET_RATE_PARENT,
2160 .ops = &clk_branch2_ops,
2165 static struct clk_branch gcc_camss_tfe_1_clk = {
2166 .halt_reg = 0x5203c,
2167 .halt_check = BRANCH_HALT,
2169 .enable_reg = 0x5203c,
2170 .enable_mask = BIT(0),
2171 .hw.init = &(struct clk_init_data){
2172 .name = "gcc_camss_tfe_1_clk",
2173 .parent_data = &(const struct clk_parent_data){
2174 .hw = &gcc_camss_tfe_1_clk_src.clkr.hw,
2177 .flags = CLK_SET_RATE_PARENT,
2178 .ops = &clk_branch2_ops,
2183 static struct clk_branch gcc_camss_tfe_1_cphy_rx_clk = {
2184 .halt_reg = 0x52080,
2185 .halt_check = BRANCH_HALT,
2187 .enable_reg = 0x52080,
2188 .enable_mask = BIT(0),
2189 .hw.init = &(struct clk_init_data){
2190 .name = "gcc_camss_tfe_1_cphy_rx_clk",
2191 .parent_data = &(const struct clk_parent_data){
2192 .hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
2195 .flags = CLK_SET_RATE_PARENT,
2196 .ops = &clk_branch2_ops,
2201 static struct clk_branch gcc_camss_tfe_1_csid_clk = {
2202 .halt_reg = 0x520cc,
2203 .halt_check = BRANCH_HALT,
2205 .enable_reg = 0x520cc,
2206 .enable_mask = BIT(0),
2207 .hw.init = &(struct clk_init_data){
2208 .name = "gcc_camss_tfe_1_csid_clk",
2209 .parent_data = &(const struct clk_parent_data){
2210 .hw = &gcc_camss_tfe_1_csid_clk_src.clkr.hw,
2213 .flags = CLK_SET_RATE_PARENT,
2214 .ops = &clk_branch2_ops,
2219 static struct clk_branch gcc_camss_tfe_2_clk = {
2220 .halt_reg = 0x5205c,
2221 .halt_check = BRANCH_HALT,
2223 .enable_reg = 0x5205c,
2224 .enable_mask = BIT(0),
2225 .hw.init = &(struct clk_init_data){
2226 .name = "gcc_camss_tfe_2_clk",
2227 .parent_data = &(const struct clk_parent_data){
2228 .hw = &gcc_camss_tfe_2_clk_src.clkr.hw,
2231 .flags = CLK_SET_RATE_PARENT,
2232 .ops = &clk_branch2_ops,
2237 static struct clk_branch gcc_camss_tfe_2_cphy_rx_clk = {
2238 .halt_reg = 0x52084,
2239 .halt_check = BRANCH_HALT,
2241 .enable_reg = 0x52084,
2242 .enable_mask = BIT(0),
2243 .hw.init = &(struct clk_init_data){
2244 .name = "gcc_camss_tfe_2_cphy_rx_clk",
2245 .parent_data = &(const struct clk_parent_data){
2246 .hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
2249 .flags = CLK_SET_RATE_PARENT,
2250 .ops = &clk_branch2_ops,
2255 static struct clk_branch gcc_camss_tfe_2_csid_clk = {
2256 .halt_reg = 0x520ec,
2257 .halt_check = BRANCH_HALT,
2259 .enable_reg = 0x520ec,
2260 .enable_mask = BIT(0),
2261 .hw.init = &(struct clk_init_data){
2262 .name = "gcc_camss_tfe_2_csid_clk",
2263 .parent_data = &(const struct clk_parent_data){
2264 .hw = &gcc_camss_tfe_2_csid_clk_src.clkr.hw,
2267 .flags = CLK_SET_RATE_PARENT,
2268 .ops = &clk_branch2_ops,
2273 static struct clk_branch gcc_camss_top_ahb_clk = {
2274 .halt_reg = 0x58028,
2275 .halt_check = BRANCH_HALT,
2277 .enable_reg = 0x58028,
2278 .enable_mask = BIT(0),
2279 .hw.init = &(struct clk_init_data){
2280 .name = "gcc_camss_top_ahb_clk",
2281 .parent_data = &(const struct clk_parent_data){
2282 .hw = &gcc_camss_top_ahb_clk_src.clkr.hw,
2285 .flags = CLK_SET_RATE_PARENT,
2286 .ops = &clk_branch2_ops,
2291 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
2292 .halt_reg = 0x1a084,
2293 .halt_check = BRANCH_HALT_VOTED,
2294 .hwcg_reg = 0x1a084,
2297 .enable_reg = 0x1a084,
2298 .enable_mask = BIT(0),
2299 .hw.init = &(struct clk_init_data){
2300 .name = "gcc_cfg_noc_usb3_prim_axi_clk",
2301 .parent_data = &(const struct clk_parent_data){
2302 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
2305 .flags = CLK_SET_RATE_PARENT,
2306 .ops = &clk_branch2_ops,
2311 static struct clk_branch gcc_disp_ahb_clk = {
2312 .halt_reg = 0x1700c,
2313 .halt_check = BRANCH_HALT_VOTED,
2314 .hwcg_reg = 0x1700c,
2317 .enable_reg = 0x1700c,
2318 .enable_mask = BIT(0),
2319 .hw.init = &(struct clk_init_data){
2320 .name = "gcc_disp_ahb_clk",
2321 .flags = CLK_IS_CRITICAL,
2322 .ops = &clk_branch2_ops,
2327 static struct clk_regmap_div gcc_disp_gpll0_clk_src = {
2331 .clkr.hw.init = &(struct clk_init_data) {
2332 .name = "gcc_disp_gpll0_clk_src",
2334 (const char *[]){ "gpll0" },
2336 .ops = &clk_regmap_div_ops,
2340 static struct clk_branch gcc_disp_gpll0_div_clk_src = {
2341 .halt_check = BRANCH_HALT_DELAY,
2343 .enable_reg = 0x79004,
2344 .enable_mask = BIT(20),
2345 .hw.init = &(struct clk_init_data){
2346 .name = "gcc_disp_gpll0_div_clk_src",
2347 .parent_data = &(const struct clk_parent_data){
2348 .hw = &gcc_disp_gpll0_clk_src.clkr.hw,
2351 .flags = CLK_SET_RATE_PARENT,
2352 .ops = &clk_branch2_ops,
2357 static struct clk_branch gcc_disp_hf_axi_clk = {
2358 .halt_reg = 0x17020,
2359 .halt_check = BRANCH_VOTED,
2360 .hwcg_reg = 0x17020,
2363 .enable_reg = 0x17020,
2364 .enable_mask = BIT(0),
2365 .hw.init = &(struct clk_init_data){
2366 .name = "gcc_disp_hf_axi_clk",
2367 .ops = &clk_branch2_ops,
2372 static struct clk_branch gcc_disp_sleep_clk = {
2373 .halt_reg = 0x17074,
2374 .halt_check = BRANCH_HALT_VOTED,
2375 .hwcg_reg = 0x17074,
2378 .enable_reg = 0x17074,
2379 .enable_mask = BIT(0),
2380 .hw.init = &(struct clk_init_data){
2381 .name = "gcc_disp_sleep_clk",
2382 .ops = &clk_branch2_ops,
2387 static struct clk_branch gcc_disp_throttle_core_clk = {
2388 .halt_reg = 0x17064,
2389 .halt_check = BRANCH_HALT_VOTED,
2390 .hwcg_reg = 0x17064,
2393 .enable_reg = 0x7900c,
2394 .enable_mask = BIT(5),
2395 .hw.init = &(struct clk_init_data){
2396 .name = "gcc_disp_throttle_core_clk",
2397 .ops = &clk_branch2_ops,
2402 static struct clk_branch gcc_gp1_clk = {
2403 .halt_reg = 0x4d000,
2404 .halt_check = BRANCH_HALT,
2406 .enable_reg = 0x4d000,
2407 .enable_mask = BIT(0),
2408 .hw.init = &(struct clk_init_data){
2409 .name = "gcc_gp1_clk",
2410 .parent_data = &(const struct clk_parent_data){
2411 .hw = &gcc_gp1_clk_src.clkr.hw,
2414 .flags = CLK_SET_RATE_PARENT,
2415 .ops = &clk_branch2_ops,
2420 static struct clk_branch gcc_gp2_clk = {
2421 .halt_reg = 0x4e000,
2422 .halt_check = BRANCH_HALT,
2424 .enable_reg = 0x4e000,
2425 .enable_mask = BIT(0),
2426 .hw.init = &(struct clk_init_data){
2427 .name = "gcc_gp2_clk",
2428 .parent_data = &(const struct clk_parent_data){
2429 .hw = &gcc_gp2_clk_src.clkr.hw,
2432 .flags = CLK_SET_RATE_PARENT,
2433 .ops = &clk_branch2_ops,
2438 static struct clk_branch gcc_gp3_clk = {
2439 .halt_reg = 0x4f000,
2440 .halt_check = BRANCH_HALT,
2442 .enable_reg = 0x4f000,
2443 .enable_mask = BIT(0),
2444 .hw.init = &(struct clk_init_data){
2445 .name = "gcc_gp3_clk",
2446 .parent_data = &(const struct clk_parent_data){
2447 .hw = &gcc_gp3_clk_src.clkr.hw,
2450 .flags = CLK_SET_RATE_PARENT,
2451 .ops = &clk_branch2_ops,
2456 static struct clk_branch gcc_gpu_cfg_ahb_clk = {
2457 .halt_reg = 0x36004,
2458 .halt_check = BRANCH_HALT_VOTED,
2459 .hwcg_reg = 0x36004,
2462 .enable_reg = 0x36004,
2463 .enable_mask = BIT(0),
2464 .hw.init = &(struct clk_init_data){
2465 .name = "gcc_gpu_cfg_ahb_clk",
2466 .flags = CLK_IS_CRITICAL,
2467 .ops = &clk_branch2_ops,
2472 static struct clk_branch gcc_gpu_gpll0_clk_src = {
2473 .halt_check = BRANCH_HALT_DELAY,
2475 .enable_reg = 0x79004,
2476 .enable_mask = BIT(15),
2477 .hw.init = &(struct clk_init_data){
2478 .name = "gcc_gpu_gpll0_clk_src",
2479 .parent_data = &(const struct clk_parent_data){
2480 .hw = &gpll0.clkr.hw,
2483 .flags = CLK_SET_RATE_PARENT,
2484 .ops = &clk_branch2_ops,
2489 static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
2490 .halt_check = BRANCH_HALT_DELAY,
2492 .enable_reg = 0x79004,
2493 .enable_mask = BIT(16),
2494 .hw.init = &(struct clk_init_data){
2495 .name = "gcc_gpu_gpll0_div_clk_src",
2496 .parent_data = &(const struct clk_parent_data){
2497 .hw = &gpll0_out_even.clkr.hw,
2500 .flags = CLK_SET_RATE_PARENT,
2501 .ops = &clk_branch2_ops,
2506 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
2507 .halt_reg = 0x3600c,
2508 .halt_check = BRANCH_VOTED,
2509 .hwcg_reg = 0x3600c,
2512 .enable_reg = 0x3600c,
2513 .enable_mask = BIT(0),
2514 .hw.init = &(struct clk_init_data){
2515 .name = "gcc_gpu_memnoc_gfx_clk",
2516 .ops = &clk_branch2_ops,
2521 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
2522 .halt_reg = 0x36018,
2523 .halt_check = BRANCH_HALT,
2525 .enable_reg = 0x36018,
2526 .enable_mask = BIT(0),
2527 .hw.init = &(struct clk_init_data){
2528 .name = "gcc_gpu_snoc_dvm_gfx_clk",
2529 .ops = &clk_branch2_ops,
2534 static struct clk_branch gcc_gpu_throttle_core_clk = {
2535 .halt_reg = 0x36048,
2536 .halt_check = BRANCH_HALT_VOTED,
2537 .hwcg_reg = 0x36048,
2540 .enable_reg = 0x79004,
2541 .enable_mask = BIT(31),
2542 .hw.init = &(struct clk_init_data){
2543 .name = "gcc_gpu_throttle_core_clk",
2544 .ops = &clk_branch2_ops,
2549 static struct clk_branch gcc_pdm2_clk = {
2550 .halt_reg = 0x2000c,
2551 .halt_check = BRANCH_HALT,
2553 .enable_reg = 0x2000c,
2554 .enable_mask = BIT(0),
2555 .hw.init = &(struct clk_init_data){
2556 .name = "gcc_pdm2_clk",
2557 .parent_data = &(const struct clk_parent_data){
2558 .hw = &gcc_pdm2_clk_src.clkr.hw,
2561 .flags = CLK_SET_RATE_PARENT,
2562 .ops = &clk_branch2_ops,
2567 static struct clk_branch gcc_pdm_ahb_clk = {
2568 .halt_reg = 0x20004,
2569 .halt_check = BRANCH_HALT_VOTED,
2570 .hwcg_reg = 0x20004,
2573 .enable_reg = 0x20004,
2574 .enable_mask = BIT(0),
2575 .hw.init = &(struct clk_init_data){
2576 .name = "gcc_pdm_ahb_clk",
2577 .ops = &clk_branch2_ops,
2582 static struct clk_branch gcc_pdm_xo4_clk = {
2583 .halt_reg = 0x20008,
2584 .halt_check = BRANCH_HALT,
2586 .enable_reg = 0x20008,
2587 .enable_mask = BIT(0),
2588 .hw.init = &(struct clk_init_data){
2589 .name = "gcc_pdm_xo4_clk",
2590 .ops = &clk_branch2_ops,
2595 static struct clk_branch gcc_prng_ahb_clk = {
2596 .halt_reg = 0x21004,
2597 .halt_check = BRANCH_HALT_VOTED,
2598 .hwcg_reg = 0x21004,
2601 .enable_reg = 0x79004,
2602 .enable_mask = BIT(13),
2603 .hw.init = &(struct clk_init_data){
2604 .name = "gcc_prng_ahb_clk",
2605 .ops = &clk_branch2_ops,
2610 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
2611 .halt_reg = 0x17014,
2612 .halt_check = BRANCH_HALT_VOTED,
2613 .hwcg_reg = 0x17014,
2616 .enable_reg = 0x7900c,
2617 .enable_mask = BIT(0),
2618 .hw.init = &(struct clk_init_data){
2619 .name = "gcc_qmip_camera_nrt_ahb_clk",
2620 .ops = &clk_branch2_ops,
2625 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
2626 .halt_reg = 0x17060,
2627 .halt_check = BRANCH_HALT_VOTED,
2628 .hwcg_reg = 0x17060,
2631 .enable_reg = 0x7900c,
2632 .enable_mask = BIT(2),
2633 .hw.init = &(struct clk_init_data){
2634 .name = "gcc_qmip_camera_rt_ahb_clk",
2635 .ops = &clk_branch2_ops,
2640 static struct clk_branch gcc_qmip_disp_ahb_clk = {
2641 .halt_reg = 0x17018,
2642 .halt_check = BRANCH_HALT_VOTED,
2643 .hwcg_reg = 0x17018,
2646 .enable_reg = 0x7900c,
2647 .enable_mask = BIT(1),
2648 .hw.init = &(struct clk_init_data){
2649 .name = "gcc_qmip_disp_ahb_clk",
2650 .ops = &clk_branch2_ops,
2655 static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = {
2656 .halt_reg = 0x36040,
2657 .halt_check = BRANCH_HALT_VOTED,
2658 .hwcg_reg = 0x36040,
2661 .enable_reg = 0x7900c,
2662 .enable_mask = BIT(4),
2663 .hw.init = &(struct clk_init_data){
2664 .name = "gcc_qmip_gpu_cfg_ahb_clk",
2665 .ops = &clk_branch2_ops,
2670 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
2671 .halt_reg = 0x17010,
2672 .halt_check = BRANCH_HALT_VOTED,
2673 .hwcg_reg = 0x17010,
2676 .enable_reg = 0x79004,
2677 .enable_mask = BIT(25),
2678 .hw.init = &(struct clk_init_data){
2679 .name = "gcc_qmip_video_vcodec_ahb_clk",
2680 .ops = &clk_branch2_ops,
2685 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
2686 .halt_reg = 0x1f014,
2687 .halt_check = BRANCH_HALT_VOTED,
2689 .enable_reg = 0x7900c,
2690 .enable_mask = BIT(9),
2691 .hw.init = &(struct clk_init_data){
2692 .name = "gcc_qupv3_wrap0_core_2x_clk",
2693 .ops = &clk_branch2_ops,
2698 static struct clk_branch gcc_qupv3_wrap0_core_clk = {
2699 .halt_reg = 0x1f00c,
2700 .halt_check = BRANCH_HALT_VOTED,
2702 .enable_reg = 0x7900c,
2703 .enable_mask = BIT(8),
2704 .hw.init = &(struct clk_init_data){
2705 .name = "gcc_qupv3_wrap0_core_clk",
2706 .ops = &clk_branch2_ops,
2711 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2712 .halt_reg = 0x1f144,
2713 .halt_check = BRANCH_HALT_VOTED,
2715 .enable_reg = 0x7900c,
2716 .enable_mask = BIT(10),
2717 .hw.init = &(struct clk_init_data){
2718 .name = "gcc_qupv3_wrap0_s0_clk",
2719 .parent_data = &(const struct clk_parent_data){
2720 .hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
2723 .flags = CLK_SET_RATE_PARENT,
2724 .ops = &clk_branch2_ops,
2729 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2730 .halt_reg = 0x1f274,
2731 .halt_check = BRANCH_HALT_VOTED,
2733 .enable_reg = 0x7900c,
2734 .enable_mask = BIT(11),
2735 .hw.init = &(struct clk_init_data){
2736 .name = "gcc_qupv3_wrap0_s1_clk",
2737 .parent_data = &(const struct clk_parent_data){
2738 .hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
2741 .flags = CLK_SET_RATE_PARENT,
2742 .ops = &clk_branch2_ops,
2747 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2748 .halt_reg = 0x1f3a4,
2749 .halt_check = BRANCH_HALT_VOTED,
2751 .enable_reg = 0x7900c,
2752 .enable_mask = BIT(12),
2753 .hw.init = &(struct clk_init_data){
2754 .name = "gcc_qupv3_wrap0_s2_clk",
2755 .parent_data = &(const struct clk_parent_data){
2756 .hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
2759 .flags = CLK_SET_RATE_PARENT,
2760 .ops = &clk_branch2_ops,
2765 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2766 .halt_reg = 0x1f4d4,
2767 .halt_check = BRANCH_HALT_VOTED,
2769 .enable_reg = 0x7900c,
2770 .enable_mask = BIT(13),
2771 .hw.init = &(struct clk_init_data){
2772 .name = "gcc_qupv3_wrap0_s3_clk",
2773 .parent_data = &(const struct clk_parent_data){
2774 .hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
2777 .flags = CLK_SET_RATE_PARENT,
2778 .ops = &clk_branch2_ops,
2783 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2784 .halt_reg = 0x1f604,
2785 .halt_check = BRANCH_HALT_VOTED,
2787 .enable_reg = 0x7900c,
2788 .enable_mask = BIT(14),
2789 .hw.init = &(struct clk_init_data){
2790 .name = "gcc_qupv3_wrap0_s4_clk",
2791 .parent_data = &(const struct clk_parent_data){
2792 .hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
2795 .flags = CLK_SET_RATE_PARENT,
2796 .ops = &clk_branch2_ops,
2801 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2802 .halt_reg = 0x1f734,
2803 .halt_check = BRANCH_HALT_VOTED,
2805 .enable_reg = 0x7900c,
2806 .enable_mask = BIT(15),
2807 .hw.init = &(struct clk_init_data){
2808 .name = "gcc_qupv3_wrap0_s5_clk",
2809 .parent_data = &(const struct clk_parent_data){
2810 .hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
2813 .flags = CLK_SET_RATE_PARENT,
2814 .ops = &clk_branch2_ops,
2819 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
2820 .halt_reg = 0x53014,
2821 .halt_check = BRANCH_HALT_VOTED,
2823 .enable_reg = 0x7900c,
2824 .enable_mask = BIT(20),
2825 .hw.init = &(struct clk_init_data){
2826 .name = "gcc_qupv3_wrap1_core_2x_clk",
2827 .ops = &clk_branch2_ops,
2832 static struct clk_branch gcc_qupv3_wrap1_core_clk = {
2833 .halt_reg = 0x5300c,
2834 .halt_check = BRANCH_HALT_VOTED,
2836 .enable_reg = 0x7900c,
2837 .enable_mask = BIT(19),
2838 .hw.init = &(struct clk_init_data){
2839 .name = "gcc_qupv3_wrap1_core_clk",
2840 .ops = &clk_branch2_ops,
2845 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2846 .halt_reg = 0x53018,
2847 .halt_check = BRANCH_HALT_VOTED,
2849 .enable_reg = 0x7900c,
2850 .enable_mask = BIT(21),
2851 .hw.init = &(struct clk_init_data){
2852 .name = "gcc_qupv3_wrap1_s0_clk",
2853 .parent_data = &(const struct clk_parent_data){
2854 .hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
2857 .flags = CLK_SET_RATE_PARENT,
2858 .ops = &clk_branch2_ops,
2863 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2864 .halt_reg = 0x53148,
2865 .halt_check = BRANCH_HALT_VOTED,
2867 .enable_reg = 0x7900c,
2868 .enable_mask = BIT(22),
2869 .hw.init = &(struct clk_init_data){
2870 .name = "gcc_qupv3_wrap1_s1_clk",
2871 .parent_data = &(const struct clk_parent_data){
2872 .hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
2875 .flags = CLK_SET_RATE_PARENT,
2876 .ops = &clk_branch2_ops,
2881 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2882 .halt_reg = 0x53278,
2883 .halt_check = BRANCH_HALT_VOTED,
2885 .enable_reg = 0x7900c,
2886 .enable_mask = BIT(23),
2887 .hw.init = &(struct clk_init_data){
2888 .name = "gcc_qupv3_wrap1_s2_clk",
2889 .parent_data = &(const struct clk_parent_data){
2890 .hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
2893 .flags = CLK_SET_RATE_PARENT,
2894 .ops = &clk_branch2_ops,
2899 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2900 .halt_reg = 0x533a8,
2901 .halt_check = BRANCH_HALT_VOTED,
2903 .enable_reg = 0x7900c,
2904 .enable_mask = BIT(24),
2905 .hw.init = &(struct clk_init_data){
2906 .name = "gcc_qupv3_wrap1_s3_clk",
2907 .parent_data = &(const struct clk_parent_data){
2908 .hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
2911 .flags = CLK_SET_RATE_PARENT,
2912 .ops = &clk_branch2_ops,
2917 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2918 .halt_reg = 0x534d8,
2919 .halt_check = BRANCH_HALT_VOTED,
2921 .enable_reg = 0x7900c,
2922 .enable_mask = BIT(25),
2923 .hw.init = &(struct clk_init_data){
2924 .name = "gcc_qupv3_wrap1_s4_clk",
2925 .parent_data = &(const struct clk_parent_data){
2926 .hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
2929 .flags = CLK_SET_RATE_PARENT,
2930 .ops = &clk_branch2_ops,
2935 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2936 .halt_reg = 0x53608,
2937 .halt_check = BRANCH_HALT_VOTED,
2939 .enable_reg = 0x7900c,
2940 .enable_mask = BIT(26),
2941 .hw.init = &(struct clk_init_data){
2942 .name = "gcc_qupv3_wrap1_s5_clk",
2943 .parent_data = &(const struct clk_parent_data){
2944 .hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
2947 .flags = CLK_SET_RATE_PARENT,
2948 .ops = &clk_branch2_ops,
2953 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2954 .halt_reg = 0x1f004,
2955 .halt_check = BRANCH_HALT_VOTED,
2956 .hwcg_reg = 0x1f004,
2959 .enable_reg = 0x7900c,
2960 .enable_mask = BIT(6),
2961 .hw.init = &(struct clk_init_data){
2962 .name = "gcc_qupv3_wrap_0_m_ahb_clk",
2963 .ops = &clk_branch2_ops,
2968 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2969 .halt_reg = 0x1f008,
2970 .halt_check = BRANCH_HALT_VOTED,
2971 .hwcg_reg = 0x1f008,
2974 .enable_reg = 0x7900c,
2975 .enable_mask = BIT(7),
2976 .hw.init = &(struct clk_init_data){
2977 .name = "gcc_qupv3_wrap_0_s_ahb_clk",
2978 .ops = &clk_branch2_ops,
2983 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2984 .halt_reg = 0x53004,
2985 .halt_check = BRANCH_HALT_VOTED,
2986 .hwcg_reg = 0x53004,
2989 .enable_reg = 0x7900c,
2990 .enable_mask = BIT(17),
2991 .hw.init = &(struct clk_init_data){
2992 .name = "gcc_qupv3_wrap_1_m_ahb_clk",
2993 .ops = &clk_branch2_ops,
2998 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2999 .halt_reg = 0x53008,
3000 .halt_check = BRANCH_HALT_VOTED,
3001 .hwcg_reg = 0x53008,
3004 .enable_reg = 0x7900c,
3005 .enable_mask = BIT(18),
3006 .hw.init = &(struct clk_init_data){
3007 .name = "gcc_qupv3_wrap_1_s_ahb_clk",
3008 .ops = &clk_branch2_ops,
3013 static struct clk_branch gcc_sdcc1_ahb_clk = {
3014 .halt_reg = 0x38008,
3015 .halt_check = BRANCH_HALT,
3017 .enable_reg = 0x38008,
3018 .enable_mask = BIT(0),
3019 .hw.init = &(struct clk_init_data){
3020 .name = "gcc_sdcc1_ahb_clk",
3021 .ops = &clk_branch2_ops,
3026 static struct clk_branch gcc_sdcc1_apps_clk = {
3027 .halt_reg = 0x38004,
3028 .halt_check = BRANCH_HALT,
3030 .enable_reg = 0x38004,
3031 .enable_mask = BIT(0),
3032 .hw.init = &(struct clk_init_data){
3033 .name = "gcc_sdcc1_apps_clk",
3034 .parent_data = &(const struct clk_parent_data){
3035 .hw = &gcc_sdcc1_apps_clk_src.clkr.hw,
3038 .flags = CLK_SET_RATE_PARENT,
3039 .ops = &clk_branch2_ops,
3044 static struct clk_branch gcc_sdcc1_ice_core_clk = {
3045 .halt_reg = 0x3800c,
3046 .halt_check = BRANCH_HALT_VOTED,
3047 .hwcg_reg = 0x3800c,
3050 .enable_reg = 0x3800c,
3051 .enable_mask = BIT(0),
3052 .hw.init = &(struct clk_init_data){
3053 .name = "gcc_sdcc1_ice_core_clk",
3054 .parent_data = &(const struct clk_parent_data){
3055 .hw = &gcc_sdcc1_ice_core_clk_src.clkr.hw,
3058 .flags = CLK_SET_RATE_PARENT,
3059 .ops = &clk_branch2_ops,
3064 static struct clk_branch gcc_sdcc2_ahb_clk = {
3065 .halt_reg = 0x1e008,
3066 .halt_check = BRANCH_HALT,
3068 .enable_reg = 0x1e008,
3069 .enable_mask = BIT(0),
3070 .hw.init = &(struct clk_init_data){
3071 .name = "gcc_sdcc2_ahb_clk",
3072 .ops = &clk_branch2_ops,
3077 static struct clk_branch gcc_sdcc2_apps_clk = {
3078 .halt_reg = 0x1e004,
3079 .halt_check = BRANCH_HALT,
3081 .enable_reg = 0x1e004,
3082 .enable_mask = BIT(0),
3083 .hw.init = &(struct clk_init_data){
3084 .name = "gcc_sdcc2_apps_clk",
3085 .parent_data = &(const struct clk_parent_data){
3086 .hw = &gcc_sdcc2_apps_clk_src.clkr.hw,
3089 .flags = CLK_SET_RATE_PARENT,
3090 .ops = &clk_branch2_ops,
3095 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
3096 .halt_reg = 0x2b06c,
3097 .halt_check = BRANCH_HALT_VOTED,
3098 .hwcg_reg = 0x2b06c,
3101 .enable_reg = 0x79004,
3102 .enable_mask = BIT(0),
3103 .hw.init = &(struct clk_init_data){
3104 .name = "gcc_sys_noc_cpuss_ahb_clk",
3105 .parent_data = &(const struct clk_parent_data){
3106 .hw = &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw,
3109 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
3110 .ops = &clk_branch2_ops,
3115 static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = {
3116 .halt_reg = 0x45098,
3117 .halt_check = BRANCH_HALT,
3119 .enable_reg = 0x45098,
3120 .enable_mask = BIT(0),
3121 .hw.init = &(struct clk_init_data){
3122 .name = "gcc_sys_noc_ufs_phy_axi_clk",
3123 .parent_data = &(const struct clk_parent_data){
3124 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
3127 .flags = CLK_SET_RATE_PARENT,
3128 .ops = &clk_branch2_ops,
3133 static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = {
3134 .halt_reg = 0x1a080,
3135 .halt_check = BRANCH_HALT_VOTED,
3136 .hwcg_reg = 0x1a080,
3139 .enable_reg = 0x1a080,
3140 .enable_mask = BIT(0),
3141 .hw.init = &(struct clk_init_data){
3142 .name = "gcc_sys_noc_usb3_prim_axi_clk",
3143 .parent_data = &(const struct clk_parent_data){
3144 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
3147 .flags = CLK_SET_RATE_PARENT,
3148 .ops = &clk_branch2_ops,
3153 static struct clk_branch gcc_ufs_phy_ahb_clk = {
3154 .halt_reg = 0x45014,
3155 .halt_check = BRANCH_HALT_VOTED,
3156 .hwcg_reg = 0x45014,
3159 .enable_reg = 0x45014,
3160 .enable_mask = BIT(0),
3161 .hw.init = &(struct clk_init_data){
3162 .name = "gcc_ufs_phy_ahb_clk",
3163 .ops = &clk_branch2_ops,
3168 static struct clk_branch gcc_ufs_phy_axi_clk = {
3169 .halt_reg = 0x45010,
3170 .halt_check = BRANCH_HALT_VOTED,
3171 .hwcg_reg = 0x45010,
3174 .enable_reg = 0x45010,
3175 .enable_mask = BIT(0),
3176 .hw.init = &(struct clk_init_data){
3177 .name = "gcc_ufs_phy_axi_clk",
3178 .parent_data = &(const struct clk_parent_data){
3179 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
3182 .flags = CLK_SET_RATE_PARENT,
3183 .ops = &clk_branch2_ops,
3188 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
3189 .halt_reg = 0x45044,
3190 .halt_check = BRANCH_HALT_VOTED,
3191 .hwcg_reg = 0x45044,
3194 .enable_reg = 0x45044,
3195 .enable_mask = BIT(0),
3196 .hw.init = &(struct clk_init_data){
3197 .name = "gcc_ufs_phy_ice_core_clk",
3198 .parent_data = &(const struct clk_parent_data){
3199 .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
3202 .flags = CLK_SET_RATE_PARENT,
3203 .ops = &clk_branch2_ops,
3208 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
3209 .halt_reg = 0x45078,
3210 .halt_check = BRANCH_HALT_VOTED,
3211 .hwcg_reg = 0x45078,
3214 .enable_reg = 0x45078,
3215 .enable_mask = BIT(0),
3216 .hw.init = &(struct clk_init_data){
3217 .name = "gcc_ufs_phy_phy_aux_clk",
3218 .parent_data = &(const struct clk_parent_data){
3219 .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
3222 .flags = CLK_SET_RATE_PARENT,
3223 .ops = &clk_branch2_ops,
3228 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
3229 .halt_reg = 0x4501c,
3230 .halt_check = BRANCH_HALT_SKIP,
3232 .enable_reg = 0x4501c,
3233 .enable_mask = BIT(0),
3234 .hw.init = &(struct clk_init_data){
3235 .name = "gcc_ufs_phy_rx_symbol_0_clk",
3236 .ops = &clk_branch2_ops,
3241 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
3242 .halt_reg = 0x45018,
3243 .halt_check = BRANCH_HALT_SKIP,
3245 .enable_reg = 0x45018,
3246 .enable_mask = BIT(0),
3247 .hw.init = &(struct clk_init_data){
3248 .name = "gcc_ufs_phy_tx_symbol_0_clk",
3249 .ops = &clk_branch2_ops,
3254 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
3255 .halt_reg = 0x45040,
3256 .halt_check = BRANCH_HALT_VOTED,
3257 .hwcg_reg = 0x45040,
3260 .enable_reg = 0x45040,
3261 .enable_mask = BIT(0),
3262 .hw.init = &(struct clk_init_data){
3263 .name = "gcc_ufs_phy_unipro_core_clk",
3264 .parent_data = &(const struct clk_parent_data){
3265 .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
3268 .flags = CLK_SET_RATE_PARENT,
3269 .ops = &clk_branch2_ops,
3274 static struct clk_branch gcc_usb30_prim_master_clk = {
3275 .halt_reg = 0x1a010,
3276 .halt_check = BRANCH_HALT,
3278 .enable_reg = 0x1a010,
3279 .enable_mask = BIT(0),
3280 .hw.init = &(struct clk_init_data){
3281 .name = "gcc_usb30_prim_master_clk",
3282 .parent_data = &(const struct clk_parent_data){
3283 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
3286 .flags = CLK_SET_RATE_PARENT,
3287 .ops = &clk_branch2_ops,
3292 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
3293 .halt_reg = 0x1a018,
3294 .halt_check = BRANCH_HALT,
3296 .enable_reg = 0x1a018,
3297 .enable_mask = BIT(0),
3298 .hw.init = &(struct clk_init_data){
3299 .name = "gcc_usb30_prim_mock_utmi_clk",
3300 .parent_data = &(const struct clk_parent_data){
3301 .hw = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
3304 .flags = CLK_SET_RATE_PARENT,
3305 .ops = &clk_branch2_ops,
3310 static struct clk_branch gcc_usb30_prim_sleep_clk = {
3311 .halt_reg = 0x1a014,
3312 .halt_check = BRANCH_HALT,
3314 .enable_reg = 0x1a014,
3315 .enable_mask = BIT(0),
3316 .hw.init = &(struct clk_init_data){
3317 .name = "gcc_usb30_prim_sleep_clk",
3318 .ops = &clk_branch2_ops,
3323 static struct clk_branch gcc_ufs_mem_clkref_clk = {
3324 .halt_reg = 0x8c000,
3325 .halt_check = BRANCH_HALT,
3327 .enable_reg = 0x8c000,
3328 .enable_mask = BIT(0),
3329 .hw.init = &(struct clk_init_data){
3330 .name = "gcc_ufs_mem_clkref_clk",
3331 .ops = &clk_branch2_ops,
3336 static struct clk_branch gcc_rx5_pcie_clkref_en_clk = {
3337 .halt_reg = 0x8c00c,
3338 .halt_check = BRANCH_HALT,
3340 .enable_reg = 0x8c00c,
3341 .enable_mask = BIT(0),
3342 .hw.init = &(struct clk_init_data){
3343 .name = "gcc_rx5_pcie_clkref_en_clk",
3344 .ops = &clk_branch2_ops,
3349 static struct clk_branch gcc_usb3_prim_clkref_clk = {
3350 .halt_reg = 0x8c010,
3351 .halt_check = BRANCH_HALT,
3353 .enable_reg = 0x8c010,
3354 .enable_mask = BIT(0),
3355 .hw.init = &(struct clk_init_data){
3356 .name = "gcc_usb3_prim_clkref_clk",
3357 .ops = &clk_branch2_ops,
3362 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
3363 .halt_reg = 0x1a054,
3364 .halt_check = BRANCH_HALT,
3366 .enable_reg = 0x1a054,
3367 .enable_mask = BIT(0),
3368 .hw.init = &(struct clk_init_data){
3369 .name = "gcc_usb3_prim_phy_com_aux_clk",
3370 .parent_data = &(const struct clk_parent_data){
3371 .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
3374 .flags = CLK_SET_RATE_PARENT,
3375 .ops = &clk_branch2_ops,
3380 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
3381 .halt_reg = 0x1a058,
3382 .halt_check = BRANCH_HALT_SKIP,
3383 .hwcg_reg = 0x1a058,
3386 .enable_reg = 0x1a058,
3387 .enable_mask = BIT(0),
3388 .hw.init = &(struct clk_init_data){
3389 .name = "gcc_usb3_prim_phy_pipe_clk",
3390 .ops = &clk_branch2_ops,
3395 static struct clk_branch gcc_vcodec0_axi_clk = {
3396 .halt_reg = 0x6e008,
3397 .halt_check = BRANCH_HALT,
3399 .enable_reg = 0x6e008,
3400 .enable_mask = BIT(0),
3401 .hw.init = &(struct clk_init_data){
3402 .name = "gcc_vcodec0_axi_clk",
3403 .ops = &clk_branch2_ops,
3408 static struct clk_branch gcc_venus_ahb_clk = {
3409 .halt_reg = 0x6e010,
3410 .halt_check = BRANCH_HALT,
3412 .enable_reg = 0x6e010,
3413 .enable_mask = BIT(0),
3414 .hw.init = &(struct clk_init_data){
3415 .name = "gcc_venus_ahb_clk",
3416 .ops = &clk_branch2_ops,
3421 static struct clk_branch gcc_venus_ctl_axi_clk = {
3422 .halt_reg = 0x6e004,
3423 .halt_check = BRANCH_HALT,
3425 .enable_reg = 0x6e004,
3426 .enable_mask = BIT(0),
3427 .hw.init = &(struct clk_init_data){
3428 .name = "gcc_venus_ctl_axi_clk",
3429 .ops = &clk_branch2_ops,
3434 static struct clk_branch gcc_video_ahb_clk = {
3435 .halt_reg = 0x17004,
3436 .halt_check = BRANCH_HALT_DELAY,
3437 .hwcg_reg = 0x17004,
3440 .enable_reg = 0x17004,
3441 .enable_mask = BIT(0),
3442 .hw.init = &(struct clk_init_data){
3443 .name = "gcc_video_ahb_clk",
3444 .flags = CLK_IS_CRITICAL,
3445 .ops = &clk_branch2_ops,
3450 static struct clk_branch gcc_video_axi0_clk = {
3451 .halt_reg = 0x1701c,
3452 .halt_check = BRANCH_HALT_VOTED,
3453 .hwcg_reg = 0x1701c,
3456 .enable_reg = 0x1701c,
3457 .enable_mask = BIT(0),
3458 .hw.init = &(struct clk_init_data){
3459 .name = "gcc_video_axi0_clk",
3460 .ops = &clk_branch2_ops,
3465 static struct clk_branch gcc_video_throttle_core_clk = {
3466 .halt_reg = 0x17068,
3467 .halt_check = BRANCH_HALT_VOTED,
3468 .hwcg_reg = 0x17068,
3471 .enable_reg = 0x79004,
3472 .enable_mask = BIT(28),
3473 .hw.init = &(struct clk_init_data){
3474 .name = "gcc_video_throttle_core_clk",
3475 .ops = &clk_branch2_ops,
3480 static struct clk_branch gcc_video_vcodec0_sys_clk = {
3481 .halt_reg = 0x580a4,
3482 .halt_check = BRANCH_HALT_VOTED,
3483 .hwcg_reg = 0x580a4,
3486 .enable_reg = 0x580a4,
3487 .enable_mask = BIT(0),
3488 .hw.init = &(struct clk_init_data){
3489 .name = "gcc_video_vcodec0_sys_clk",
3490 .parent_data = &(const struct clk_parent_data){
3491 .hw = &gcc_video_venus_clk_src.clkr.hw,
3494 .flags = CLK_SET_RATE_PARENT,
3495 .ops = &clk_branch2_ops,
3500 static struct clk_branch gcc_video_venus_ctl_clk = {
3501 .halt_reg = 0x5808c,
3502 .halt_check = BRANCH_HALT,
3504 .enable_reg = 0x5808c,
3505 .enable_mask = BIT(0),
3506 .hw.init = &(struct clk_init_data){
3507 .name = "gcc_video_venus_ctl_clk",
3508 .parent_data = &(const struct clk_parent_data){
3509 .hw = &gcc_video_venus_clk_src.clkr.hw,
3512 .flags = CLK_SET_RATE_PARENT,
3513 .ops = &clk_branch2_ops,
3518 static struct clk_branch gcc_video_xo_clk = {
3519 .halt_reg = 0x17024,
3520 .halt_check = BRANCH_HALT,
3522 .enable_reg = 0x17024,
3523 .enable_mask = BIT(0),
3524 .hw.init = &(struct clk_init_data){
3525 .name = "gcc_video_xo_clk",
3526 .ops = &clk_branch2_ops,
3531 static struct gdsc usb30_prim_gdsc = {
3534 .name = "usb30_prim_gdsc",
3536 .pwrsts = PWRSTS_OFF_ON,
3539 static struct gdsc ufs_phy_gdsc = {
3542 .name = "ufs_phy_gdsc",
3544 .pwrsts = PWRSTS_OFF_ON,
3547 static struct gdsc camss_top_gdsc = {
3550 .name = "camss_top_gdsc",
3552 .pwrsts = PWRSTS_OFF_ON,
3555 static struct gdsc venus_gdsc = {
3558 .name = "venus_gdsc",
3560 .pwrsts = PWRSTS_OFF_ON,
3563 static struct gdsc vcodec0_gdsc = {
3566 .name = "vcodec0_gdsc",
3568 .pwrsts = PWRSTS_OFF_ON,
3572 static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc = {
3575 .name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc",
3577 .pwrsts = PWRSTS_OFF_ON,
3581 static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc = {
3584 .name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc",
3586 .pwrsts = PWRSTS_OFF_ON,
3590 static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = {
3593 .name = "hlos1_vote_turing_mmu_tbu1_gdsc",
3595 .pwrsts = PWRSTS_OFF_ON,
3599 static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = {
3602 .name = "hlos1_vote_turing_mmu_tbu0_gdsc",
3604 .pwrsts = PWRSTS_OFF_ON,
3608 static struct clk_regmap *gcc_sm6375_clocks[] = {
3609 [GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr,
3610 [GCC_AHB2PHY_USB_CLK] = &gcc_ahb2phy_usb_clk.clkr,
3611 [GCC_BIMC_GPU_AXI_CLK] = &gcc_bimc_gpu_axi_clk.clkr,
3612 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3613 [GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr,
3614 [GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr,
3615 [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
3616 [GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr,
3617 [GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr,
3618 [GCC_CAMSS_CCI_0_CLK] = &gcc_camss_cci_0_clk.clkr,
3619 [GCC_CAMSS_CCI_0_CLK_SRC] = &gcc_camss_cci_0_clk_src.clkr,
3620 [GCC_CAMSS_CCI_1_CLK] = &gcc_camss_cci_1_clk.clkr,
3621 [GCC_CAMSS_CCI_1_CLK_SRC] = &gcc_camss_cci_1_clk_src.clkr,
3622 [GCC_CAMSS_CPHY_0_CLK] = &gcc_camss_cphy_0_clk.clkr,
3623 [GCC_CAMSS_CPHY_1_CLK] = &gcc_camss_cphy_1_clk.clkr,
3624 [GCC_CAMSS_CPHY_2_CLK] = &gcc_camss_cphy_2_clk.clkr,
3625 [GCC_CAMSS_CPHY_3_CLK] = &gcc_camss_cphy_3_clk.clkr,
3626 [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
3627 [GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr,
3628 [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
3629 [GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr,
3630 [GCC_CAMSS_CSI2PHYTIMER_CLK] = &gcc_camss_csi2phytimer_clk.clkr,
3631 [GCC_CAMSS_CSI2PHYTIMER_CLK_SRC] = &gcc_camss_csi2phytimer_clk_src.clkr,
3632 [GCC_CAMSS_CSI3PHYTIMER_CLK] = &gcc_camss_csi3phytimer_clk.clkr,
3633 [GCC_CAMSS_CSI3PHYTIMER_CLK_SRC] = &gcc_camss_csi3phytimer_clk_src.clkr,
3634 [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
3635 [GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr,
3636 [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
3637 [GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr,
3638 [GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr,
3639 [GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr,
3640 [GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr,
3641 [GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr,
3642 [GCC_CAMSS_MCLK4_CLK] = &gcc_camss_mclk4_clk.clkr,
3643 [GCC_CAMSS_MCLK4_CLK_SRC] = &gcc_camss_mclk4_clk_src.clkr,
3644 [GCC_CAMSS_NRT_AXI_CLK] = &gcc_camss_nrt_axi_clk.clkr,
3645 [GCC_CAMSS_OPE_AHB_CLK] = &gcc_camss_ope_ahb_clk.clkr,
3646 [GCC_CAMSS_OPE_AHB_CLK_SRC] = &gcc_camss_ope_ahb_clk_src.clkr,
3647 [GCC_CAMSS_OPE_CLK] = &gcc_camss_ope_clk.clkr,
3648 [GCC_CAMSS_OPE_CLK_SRC] = &gcc_camss_ope_clk_src.clkr,
3649 [GCC_CAMSS_RT_AXI_CLK] = &gcc_camss_rt_axi_clk.clkr,
3650 [GCC_CAMSS_TFE_0_CLK] = &gcc_camss_tfe_0_clk.clkr,
3651 [GCC_CAMSS_TFE_0_CLK_SRC] = &gcc_camss_tfe_0_clk_src.clkr,
3652 [GCC_CAMSS_TFE_0_CPHY_RX_CLK] = &gcc_camss_tfe_0_cphy_rx_clk.clkr,
3653 [GCC_CAMSS_TFE_0_CSID_CLK] = &gcc_camss_tfe_0_csid_clk.clkr,
3654 [GCC_CAMSS_TFE_0_CSID_CLK_SRC] = &gcc_camss_tfe_0_csid_clk_src.clkr,
3655 [GCC_CAMSS_TFE_1_CLK] = &gcc_camss_tfe_1_clk.clkr,
3656 [GCC_CAMSS_TFE_1_CLK_SRC] = &gcc_camss_tfe_1_clk_src.clkr,
3657 [GCC_CAMSS_TFE_1_CPHY_RX_CLK] = &gcc_camss_tfe_1_cphy_rx_clk.clkr,
3658 [GCC_CAMSS_TFE_1_CSID_CLK] = &gcc_camss_tfe_1_csid_clk.clkr,
3659 [GCC_CAMSS_TFE_1_CSID_CLK_SRC] = &gcc_camss_tfe_1_csid_clk_src.clkr,
3660 [GCC_CAMSS_TFE_2_CLK] = &gcc_camss_tfe_2_clk.clkr,
3661 [GCC_CAMSS_TFE_2_CLK_SRC] = &gcc_camss_tfe_2_clk_src.clkr,
3662 [GCC_CAMSS_TFE_2_CPHY_RX_CLK] = &gcc_camss_tfe_2_cphy_rx_clk.clkr,
3663 [GCC_CAMSS_TFE_2_CSID_CLK] = &gcc_camss_tfe_2_csid_clk.clkr,
3664 [GCC_CAMSS_TFE_2_CSID_CLK_SRC] = &gcc_camss_tfe_2_csid_clk_src.clkr,
3665 [GCC_CAMSS_TFE_CPHY_RX_CLK_SRC] = &gcc_camss_tfe_cphy_rx_clk_src.clkr,
3666 [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
3667 [GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr,
3668 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3669 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
3670 [GCC_CPUSS_AHB_POSTDIV_CLK_SRC] = &gcc_cpuss_ahb_postdiv_clk_src.clkr,
3671 [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
3672 [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
3673 [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
3674 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
3675 [GCC_DISP_SLEEP_CLK] = &gcc_disp_sleep_clk.clkr,
3676 [GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr,
3677 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3678 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3679 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3680 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3681 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3682 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3683 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
3684 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3685 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3686 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3687 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3688 [GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr,
3689 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3690 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3691 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3692 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3693 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3694 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
3695 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
3696 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3697 [GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr,
3698 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
3699 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
3700 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
3701 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3702 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3703 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3704 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3705 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3706 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3707 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3708 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3709 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3710 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3711 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3712 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3713 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
3714 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
3715 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3716 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3717 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3718 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3719 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3720 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3721 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3722 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3723 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3724 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3725 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3726 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3727 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3728 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3729 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3730 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3731 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3732 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3733 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
3734 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3735 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
3736 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3737 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3738 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3739 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
3740 [GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr,
3741 [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr,
3742 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3743 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3744 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3745 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3746 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3747 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3748 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3749 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3750 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3751 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3752 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
3753 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3754 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3755 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3756 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3757 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
3758 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3759 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
3760 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3761 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3762 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3763 [GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr,
3764 [GCC_VENUS_AHB_CLK] = &gcc_venus_ahb_clk.clkr,
3765 [GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr,
3766 [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
3767 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
3768 [GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr,
3769 [GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr,
3770 [GCC_VIDEO_VENUS_CLK_SRC] = &gcc_video_venus_clk_src.clkr,
3771 [GCC_VIDEO_VENUS_CTL_CLK] = &gcc_video_venus_ctl_clk.clkr,
3772 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
3773 [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
3774 [GCC_RX5_PCIE_CLKREF_EN_CLK] = &gcc_rx5_pcie_clkref_en_clk.clkr,
3775 [GPLL0] = &gpll0.clkr,
3776 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
3777 [GPLL0_OUT_ODD] = &gpll0_out_odd.clkr,
3778 [GPLL1] = &gpll1.clkr,
3779 [GPLL10] = &gpll10.clkr,
3780 [GPLL11] = &gpll11.clkr,
3781 [GPLL3] = &gpll3.clkr,
3782 [GPLL3_OUT_EVEN] = &gpll3_out_even.clkr,
3783 [GPLL4] = &gpll4.clkr,
3784 [GPLL5] = &gpll5.clkr,
3785 [GPLL6] = &gpll6.clkr,
3786 [GPLL6_OUT_EVEN] = &gpll6_out_even.clkr,
3787 [GPLL7] = &gpll7.clkr,
3788 [GPLL8] = &gpll8.clkr,
3789 [GPLL8_OUT_EVEN] = &gpll8_out_even.clkr,
3790 [GPLL9] = &gpll9.clkr,
3791 [GPLL9_OUT_MAIN] = &gpll9_out_main.clkr,
3794 static const struct qcom_reset_map gcc_sm6375_resets[] = {
3795 [GCC_MMSS_BCR] = { 0x17000 },
3796 [GCC_USB30_PRIM_BCR] = { 0x1a000 },
3797 [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 },
3798 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x1b020 },
3799 [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 },
3800 [GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 },
3801 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 },
3802 [GCC_SDCC2_BCR] = { 0x1e000 },
3803 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x1f000 },
3804 [GCC_PDM_BCR] = { 0x20000 },
3805 [GCC_GPU_BCR] = { 0x36000 },
3806 [GCC_SDCC1_BCR] = { 0x38000 },
3807 [GCC_UFS_PHY_BCR] = { 0x45000 },
3808 [GCC_CAMSS_TFE_BCR] = { 0x52000 },
3809 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x53000 },
3810 [GCC_CAMSS_OPE_BCR] = { 0x55000 },
3811 [GCC_CAMSS_TOP_BCR] = { 0x58000 },
3812 [GCC_VENUS_BCR] = { 0x58078 },
3813 [GCC_VCODEC0_BCR] = { 0x58094 },
3814 [GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 },
3818 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
3819 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
3820 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
3821 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
3822 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
3823 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
3824 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
3825 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
3826 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
3827 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
3828 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
3829 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
3830 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
3833 static struct gdsc *gcc_sm6375_gdscs[] = {
3834 [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
3835 [UFS_PHY_GDSC] = &ufs_phy_gdsc,
3836 [CAMSS_TOP_GDSC] = &camss_top_gdsc,
3837 [VENUS_GDSC] = &venus_gdsc,
3838 [VCODEC0_GDSC] = &vcodec0_gdsc,
3839 [HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc,
3840 [HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc,
3841 [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc,
3842 [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc,
3845 static const struct regmap_config gcc_sm6375_regmap_config = {
3849 .max_register = 0xc7000,
3853 static const struct qcom_cc_desc gcc_sm6375_desc = {
3854 .config = &gcc_sm6375_regmap_config,
3855 .clks = gcc_sm6375_clocks,
3856 .num_clks = ARRAY_SIZE(gcc_sm6375_clocks),
3857 .resets = gcc_sm6375_resets,
3858 .num_resets = ARRAY_SIZE(gcc_sm6375_resets),
3859 .gdscs = gcc_sm6375_gdscs,
3860 .num_gdscs = ARRAY_SIZE(gcc_sm6375_gdscs),
3863 static const struct of_device_id gcc_sm6375_match_table[] = {
3864 { .compatible = "qcom,sm6375-gcc" },
3867 MODULE_DEVICE_TABLE(of, gcc_sm6375_match_table);
3869 static int gcc_sm6375_probe(struct platform_device *pdev)
3871 struct regmap *regmap;
3874 regmap = qcom_cc_map(pdev, &gcc_sm6375_desc);
3876 return PTR_ERR(regmap);
3878 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks));
3883 * Keep the following clocks always on:
3884 * GCC_CAMERA_XO_CLK, GCC_CPUSS_GNOC_CLK, GCC_DISP_XO_CLK
3886 regmap_update_bits(regmap, 0x17028, BIT(0), BIT(0));
3887 regmap_update_bits(regmap, 0x2b004, BIT(0), BIT(0));
3888 regmap_update_bits(regmap, 0x1702c, BIT(0), BIT(0));
3890 clk_lucid_pll_configure(&gpll10, regmap, &gpll10_config);
3891 clk_lucid_pll_configure(&gpll11, regmap, &gpll11_config);
3892 clk_lucid_pll_configure(&gpll8, regmap, &gpll8_config);
3893 clk_zonda_pll_configure(&gpll9, regmap, &gpll9_config);
3895 return qcom_cc_really_probe(pdev, &gcc_sm6375_desc, regmap);
3898 static struct platform_driver gcc_sm6375_driver = {
3899 .probe = gcc_sm6375_probe,
3901 .name = "gcc-sm6375",
3902 .of_match_table = gcc_sm6375_match_table,
3906 static int __init gcc_sm6375_init(void)
3908 return platform_driver_register(&gcc_sm6375_driver);
3910 subsys_initcall(gcc_sm6375_init);
3912 static void __exit gcc_sm6375_exit(void)
3914 platform_driver_unregister(&gcc_sm6375_driver);
3916 module_exit(gcc_sm6375_exit);
3918 MODULE_DESCRIPTION("QTI GCC SM6375 Driver");
3919 MODULE_LICENSE("GPL");