1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/clk-provider.h>
14 #include <linux/regmap.h>
15 #include <linux/reset-controller.h>
17 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
20 #include "clk-regmap.h"
23 #include "clk-branch.h"
24 #include "clk-alpha-pll.h"
38 static struct clk_alpha_pll gpll0 = {
40 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
42 .enable_reg = 0x52000,
43 .enable_mask = BIT(0),
44 .hw.init = &(struct clk_init_data){
46 .parent_data = &(const struct clk_parent_data){
47 .fw_name = "bi_tcxo", .name = "bi_tcxo",
50 .ops = &clk_alpha_pll_fixed_fabia_ops,
55 static struct clk_alpha_pll gpll4 = {
57 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
59 .enable_reg = 0x52000,
60 .enable_mask = BIT(4),
61 .hw.init = &(struct clk_init_data){
63 .parent_data = &(const struct clk_parent_data){
64 .fw_name = "bi_tcxo", .name = "bi_tcxo",
67 .ops = &clk_alpha_pll_fixed_fabia_ops,
72 static struct clk_alpha_pll gpll6 = {
74 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
76 .enable_reg = 0x52000,
77 .enable_mask = BIT(6),
78 .hw.init = &(struct clk_init_data){
80 .parent_data = &(const struct clk_parent_data){
81 .fw_name = "bi_tcxo", .name = "bi_tcxo",
84 .ops = &clk_alpha_pll_fixed_fabia_ops,
89 static const struct clk_div_table post_div_table_fabia_even[] = {
97 static struct clk_alpha_pll_postdiv gpll0_out_even = {
100 .post_div_table = post_div_table_fabia_even,
101 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
103 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
104 .clkr.hw.init = &(struct clk_init_data){
105 .name = "gpll0_out_even",
106 .parent_hws = (const struct clk_hw*[]){
110 .ops = &clk_alpha_pll_postdiv_fabia_ops,
114 static const struct parent_map gcc_parent_map_0[] = {
116 { P_GPLL0_OUT_MAIN, 1 },
117 { P_GPLL0_OUT_EVEN, 6 },
120 static const struct clk_parent_data gcc_parent_data_0[] = {
121 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
122 { .hw = &gpll0.clkr.hw },
123 { .hw = &gpll0_out_even.clkr.hw },
126 static const struct parent_map gcc_parent_map_1[] = {
128 { P_GPLL0_OUT_MAIN, 1 },
130 { P_GPLL0_OUT_EVEN, 6 },
133 static const struct clk_parent_data gcc_parent_data_1[] = {
134 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
135 { .hw = &gpll0.clkr.hw },
136 { .fw_name = "sleep_clk", .name = "core_pi_sleep_clk" },
137 { .hw = &gpll0_out_even.clkr.hw },
140 static const struct parent_map gcc_parent_map_2[] = {
145 static const struct clk_parent_data gcc_parent_data_2[] = {
146 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
147 { .fw_name = "sleep_clk", .name = "core_pi_sleep_clk" },
150 static const struct parent_map gcc_parent_map_3[] = {
152 { P_GPLL0_OUT_MAIN, 1 },
155 static const struct clk_parent_data gcc_parent_data_3[] = {
156 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
157 { .hw = &gpll0.clkr.hw },
160 static const struct parent_map gcc_parent_map_4[] = {
164 static const struct clk_parent_data gcc_parent_data_4[] = {
165 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
168 static const struct parent_map gcc_parent_map_6[] = {
170 { P_GPLL0_OUT_MAIN, 1 },
171 { P_AUD_REF_CLK, 2 },
172 { P_GPLL0_OUT_EVEN, 6 },
175 static const struct clk_parent_data gcc_parent_data_6[] = {
176 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
177 { .hw = &gpll0.clkr.hw },
178 { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" },
179 { .hw = &gpll0_out_even.clkr.hw },
182 static const struct clk_parent_data gcc_parent_data_7_ao[] = {
183 { .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" },
184 { .hw = &gpll0.clkr.hw },
185 { .hw = &gpll0_out_even.clkr.hw },
186 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
189 static const struct clk_parent_data gcc_parent_data_8[] = {
190 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
191 { .hw = &gpll0.clkr.hw },
192 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
195 static const struct clk_parent_data gcc_parent_data_8_ao[] = {
196 { .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" },
197 { .hw = &gpll0.clkr.hw },
198 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
201 static const struct parent_map gcc_parent_map_10[] = {
203 { P_GPLL0_OUT_MAIN, 1 },
204 { P_GPLL4_OUT_MAIN, 5 },
205 { P_GPLL0_OUT_EVEN, 6 },
208 static const struct clk_parent_data gcc_parent_data_10[] = {
209 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
210 { .hw = &gpll0.clkr.hw },
211 { .hw = &gpll4.clkr.hw },
212 { .hw = &gpll0_out_even.clkr.hw },
215 static const struct parent_map gcc_parent_map_11[] = {
217 { P_GPLL0_OUT_MAIN, 1 },
218 { P_GPLL6_OUT_MAIN, 2 },
219 { P_GPLL0_OUT_EVEN, 6 },
222 static const struct clk_parent_data gcc_parent_data_11[] = {
223 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
224 { .hw = &gpll0.clkr.hw },
225 { .hw = &gpll6.clkr.hw },
226 { .hw = &gpll0_out_even.clkr.hw },
229 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
230 F(19200000, P_BI_TCXO, 1, 0, 0),
234 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
238 .parent_map = gcc_parent_map_0,
239 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
240 .clkr.hw.init = &(struct clk_init_data){
241 .name = "gcc_cpuss_ahb_clk_src",
242 .parent_data = gcc_parent_data_7_ao,
243 .num_parents = ARRAY_SIZE(gcc_parent_data_7_ao),
244 .ops = &clk_rcg2_ops,
248 static const struct freq_tbl ftbl_gcc_cpuss_rbcpr_clk_src[] = {
249 F(19200000, P_BI_TCXO, 1, 0, 0),
253 static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = {
257 .parent_map = gcc_parent_map_3,
258 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
259 .clkr.hw.init = &(struct clk_init_data){
260 .name = "gcc_cpuss_rbcpr_clk_src",
261 .parent_data = gcc_parent_data_8_ao,
262 .num_parents = ARRAY_SIZE(gcc_parent_data_8_ao),
263 .ops = &clk_rcg2_ops,
267 static const struct freq_tbl ftbl_gcc_sdm670_cpuss_rbcpr_clk_src[] = {
268 F(19200000, P_BI_TCXO, 1, 0, 0),
269 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
273 static struct clk_rcg2 gcc_sdm670_cpuss_rbcpr_clk_src = {
277 .parent_map = gcc_parent_map_3,
278 .freq_tbl = ftbl_gcc_sdm670_cpuss_rbcpr_clk_src,
279 .clkr.hw.init = &(struct clk_init_data){
280 .name = "gcc_cpuss_rbcpr_clk_src",
281 .parent_data = gcc_parent_data_8_ao,
282 .num_parents = ARRAY_SIZE(gcc_parent_data_8_ao),
283 .ops = &clk_rcg2_ops,
287 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
288 F(19200000, P_BI_TCXO, 1, 0, 0),
289 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
290 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
291 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
292 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
296 static struct clk_rcg2 gcc_gp1_clk_src = {
300 .parent_map = gcc_parent_map_1,
301 .freq_tbl = ftbl_gcc_gp1_clk_src,
302 .clkr.hw.init = &(struct clk_init_data){
303 .name = "gcc_gp1_clk_src",
304 .parent_data = gcc_parent_data_1,
305 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
306 .ops = &clk_rcg2_ops,
310 static struct clk_rcg2 gcc_gp2_clk_src = {
314 .parent_map = gcc_parent_map_1,
315 .freq_tbl = ftbl_gcc_gp1_clk_src,
316 .clkr.hw.init = &(struct clk_init_data){
317 .name = "gcc_gp2_clk_src",
318 .parent_data = gcc_parent_data_1,
319 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
320 .ops = &clk_rcg2_ops,
324 static struct clk_rcg2 gcc_gp3_clk_src = {
328 .parent_map = gcc_parent_map_1,
329 .freq_tbl = ftbl_gcc_gp1_clk_src,
330 .clkr.hw.init = &(struct clk_init_data){
331 .name = "gcc_gp3_clk_src",
332 .parent_data = gcc_parent_data_1,
333 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
334 .ops = &clk_rcg2_ops,
338 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
339 F(9600000, P_BI_TCXO, 2, 0, 0),
340 F(19200000, P_BI_TCXO, 1, 0, 0),
344 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
348 .parent_map = gcc_parent_map_2,
349 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
350 .clkr.hw.init = &(struct clk_init_data){
351 .name = "gcc_pcie_0_aux_clk_src",
352 .parent_data = gcc_parent_data_2,
353 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
354 .ops = &clk_rcg2_ops,
358 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
362 .parent_map = gcc_parent_map_2,
363 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
364 .clkr.hw.init = &(struct clk_init_data){
365 .name = "gcc_pcie_1_aux_clk_src",
366 .parent_data = gcc_parent_data_2,
367 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
368 .ops = &clk_rcg2_ops,
372 static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {
373 F(19200000, P_BI_TCXO, 1, 0, 0),
374 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
378 static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
382 .parent_map = gcc_parent_map_0,
383 .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
384 .clkr.hw.init = &(struct clk_init_data){
385 .name = "gcc_pcie_phy_refgen_clk_src",
386 .parent_data = gcc_parent_data_0,
387 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
388 .ops = &clk_rcg2_ops,
392 static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
393 F(19200000, P_BI_TCXO, 1, 0, 0),
394 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
395 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
396 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
400 static struct clk_rcg2 gcc_qspi_core_clk_src = {
404 .parent_map = gcc_parent_map_0,
405 .freq_tbl = ftbl_gcc_qspi_core_clk_src,
406 .clkr.hw.init = &(struct clk_init_data){
407 .name = "gcc_qspi_core_clk_src",
408 .parent_data = gcc_parent_data_0,
409 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
410 .ops = &clk_rcg2_floor_ops,
414 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
415 F(9600000, P_BI_TCXO, 2, 0, 0),
416 F(19200000, P_BI_TCXO, 1, 0, 0),
417 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
421 static struct clk_rcg2 gcc_pdm2_clk_src = {
425 .parent_map = gcc_parent_map_0,
426 .freq_tbl = ftbl_gcc_pdm2_clk_src,
427 .clkr.hw.init = &(struct clk_init_data){
428 .name = "gcc_pdm2_clk_src",
429 .parent_data = gcc_parent_data_0,
430 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
431 .ops = &clk_rcg2_ops,
435 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
436 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
437 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
438 F(19200000, P_BI_TCXO, 1, 0, 0),
439 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
440 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
441 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
442 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
443 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
444 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
445 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
446 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
447 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
448 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
449 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
450 F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75),
454 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
455 .name = "gcc_qupv3_wrap0_s0_clk_src",
456 .parent_data = gcc_parent_data_0,
457 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
458 .ops = &clk_rcg2_shared_ops,
461 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
465 .parent_map = gcc_parent_map_0,
466 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
467 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
470 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
471 .name = "gcc_qupv3_wrap0_s1_clk_src",
472 .parent_data = gcc_parent_data_0,
473 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
474 .ops = &clk_rcg2_shared_ops,
477 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
481 .parent_map = gcc_parent_map_0,
482 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
483 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
486 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
487 .name = "gcc_qupv3_wrap0_s2_clk_src",
488 .parent_data = gcc_parent_data_0,
489 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
490 .ops = &clk_rcg2_shared_ops,
493 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
497 .parent_map = gcc_parent_map_0,
498 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
499 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
502 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
503 .name = "gcc_qupv3_wrap0_s3_clk_src",
504 .parent_data = gcc_parent_data_0,
505 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
506 .ops = &clk_rcg2_shared_ops,
509 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
513 .parent_map = gcc_parent_map_0,
514 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
515 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
518 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
519 .name = "gcc_qupv3_wrap0_s4_clk_src",
520 .parent_data = gcc_parent_data_0,
521 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
522 .ops = &clk_rcg2_shared_ops,
525 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
529 .parent_map = gcc_parent_map_0,
530 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
531 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
534 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
535 .name = "gcc_qupv3_wrap0_s5_clk_src",
536 .parent_data = gcc_parent_data_0,
537 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
538 .ops = &clk_rcg2_shared_ops,
541 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
545 .parent_map = gcc_parent_map_0,
546 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
547 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
550 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
551 .name = "gcc_qupv3_wrap0_s6_clk_src",
552 .parent_data = gcc_parent_data_0,
553 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
554 .ops = &clk_rcg2_shared_ops,
557 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
561 .parent_map = gcc_parent_map_0,
562 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
563 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
566 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
567 .name = "gcc_qupv3_wrap0_s7_clk_src",
568 .parent_data = gcc_parent_data_0,
569 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
570 .ops = &clk_rcg2_shared_ops,
573 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
577 .parent_map = gcc_parent_map_0,
578 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
579 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
582 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
583 .name = "gcc_qupv3_wrap1_s0_clk_src",
584 .parent_data = gcc_parent_data_0,
585 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
586 .ops = &clk_rcg2_shared_ops,
589 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
593 .parent_map = gcc_parent_map_0,
594 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
595 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
598 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
599 .name = "gcc_qupv3_wrap1_s1_clk_src",
600 .parent_data = gcc_parent_data_0,
601 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
602 .ops = &clk_rcg2_shared_ops,
605 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
609 .parent_map = gcc_parent_map_0,
610 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
611 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
614 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
615 .name = "gcc_qupv3_wrap1_s2_clk_src",
616 .parent_data = gcc_parent_data_0,
617 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
618 .ops = &clk_rcg2_shared_ops,
621 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
625 .parent_map = gcc_parent_map_0,
626 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
627 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
630 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
631 .name = "gcc_qupv3_wrap1_s3_clk_src",
632 .parent_data = gcc_parent_data_0,
633 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
634 .ops = &clk_rcg2_shared_ops,
637 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
641 .parent_map = gcc_parent_map_0,
642 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
643 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
646 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
647 .name = "gcc_qupv3_wrap1_s4_clk_src",
648 .parent_data = gcc_parent_data_0,
649 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
650 .ops = &clk_rcg2_shared_ops,
653 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
657 .parent_map = gcc_parent_map_0,
658 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
659 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
662 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
663 .name = "gcc_qupv3_wrap1_s5_clk_src",
664 .parent_data = gcc_parent_data_0,
665 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
666 .ops = &clk_rcg2_shared_ops,
669 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
673 .parent_map = gcc_parent_map_0,
674 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
675 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
678 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
679 .name = "gcc_qupv3_wrap1_s6_clk_src",
680 .parent_data = gcc_parent_data_0,
681 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
682 .ops = &clk_rcg2_shared_ops,
685 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
689 .parent_map = gcc_parent_map_0,
690 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
691 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
694 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
695 .name = "gcc_qupv3_wrap1_s7_clk_src",
696 .parent_data = gcc_parent_data_0,
697 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
698 .ops = &clk_rcg2_shared_ops,
701 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
705 .parent_map = gcc_parent_map_0,
706 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
707 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
710 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
711 F(144000, P_BI_TCXO, 16, 3, 25),
712 F(400000, P_BI_TCXO, 12, 1, 4),
713 F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3),
714 F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2),
715 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
716 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
717 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
718 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
722 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
726 .parent_map = gcc_parent_map_11,
727 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
728 .clkr.hw.init = &(struct clk_init_data){
729 .name = "gcc_sdcc1_apps_clk_src",
730 .parent_data = gcc_parent_data_11,
731 .num_parents = ARRAY_SIZE(gcc_parent_data_11),
732 .ops = &clk_rcg2_floor_ops,
736 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
737 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
738 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
739 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
740 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
744 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
748 .parent_map = gcc_parent_map_0,
749 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
750 .clkr.hw.init = &(struct clk_init_data){
751 .name = "gcc_sdcc1_ice_core_clk_src",
752 .parent_data = gcc_parent_data_0,
753 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
754 .ops = &clk_rcg2_ops,
758 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
759 F(400000, P_BI_TCXO, 12, 1, 4),
760 F(9600000, P_BI_TCXO, 2, 0, 0),
761 F(19200000, P_BI_TCXO, 1, 0, 0),
762 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
763 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
764 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
765 F(201500000, P_GPLL4_OUT_MAIN, 4, 0, 0),
769 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
773 .parent_map = gcc_parent_map_10,
774 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
775 .clkr.hw.init = &(struct clk_init_data){
776 .name = "gcc_sdcc2_apps_clk_src",
777 .parent_data = gcc_parent_data_10,
778 .num_parents = ARRAY_SIZE(gcc_parent_data_10),
779 .ops = &clk_rcg2_floor_ops,
783 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
784 F(400000, P_BI_TCXO, 12, 1, 4),
785 F(9600000, P_BI_TCXO, 2, 0, 0),
786 F(19200000, P_BI_TCXO, 1, 0, 0),
787 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
788 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
789 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
793 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
797 .parent_map = gcc_parent_map_0,
798 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
799 .clkr.hw.init = &(struct clk_init_data){
800 .name = "gcc_sdcc4_apps_clk_src",
801 .parent_data = gcc_parent_data_0,
802 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
803 .ops = &clk_rcg2_floor_ops,
807 static const struct freq_tbl ftbl_gcc_sdm670_sdcc4_apps_clk_src[] = {
808 F(400000, P_BI_TCXO, 12, 1, 4),
809 F(9600000, P_BI_TCXO, 2, 0, 0),
810 F(19200000, P_BI_TCXO, 1, 0, 0),
811 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
812 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
813 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
814 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
818 static struct clk_rcg2 gcc_sdm670_sdcc4_apps_clk_src = {
822 .parent_map = gcc_parent_map_0,
823 .freq_tbl = ftbl_gcc_sdm670_sdcc4_apps_clk_src,
824 .clkr.hw.init = &(struct clk_init_data){
825 .name = "gcc_sdcc4_apps_clk_src",
826 .parent_data = gcc_parent_data_0,
827 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
828 .ops = &clk_rcg2_floor_ops,
832 static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {
833 F(105495, P_BI_TCXO, 2, 1, 91),
837 static struct clk_rcg2 gcc_tsif_ref_clk_src = {
841 .parent_map = gcc_parent_map_6,
842 .freq_tbl = ftbl_gcc_tsif_ref_clk_src,
843 .clkr.hw.init = &(struct clk_init_data){
844 .name = "gcc_tsif_ref_clk_src",
845 .parent_data = gcc_parent_data_6,
846 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
847 .ops = &clk_rcg2_ops,
851 static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
852 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
853 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
854 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
855 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
856 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
860 static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
864 .parent_map = gcc_parent_map_0,
865 .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
866 .clkr.hw.init = &(struct clk_init_data){
867 .name = "gcc_ufs_card_axi_clk_src",
868 .parent_data = gcc_parent_data_0,
869 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
870 .ops = &clk_rcg2_shared_ops,
874 static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
875 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
876 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
877 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
878 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
882 static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
886 .parent_map = gcc_parent_map_0,
887 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
888 .clkr.hw.init = &(struct clk_init_data){
889 .name = "gcc_ufs_card_ice_core_clk_src",
890 .parent_data = gcc_parent_data_0,
891 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
892 .ops = &clk_rcg2_shared_ops,
896 static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
900 .parent_map = gcc_parent_map_4,
901 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
902 .clkr.hw.init = &(struct clk_init_data){
903 .name = "gcc_ufs_card_phy_aux_clk_src",
904 .parent_data = gcc_parent_data_4,
905 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
906 .ops = &clk_rcg2_ops,
910 static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = {
911 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
912 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
913 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
917 static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
921 .parent_map = gcc_parent_map_0,
922 .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
923 .clkr.hw.init = &(struct clk_init_data){
924 .name = "gcc_ufs_card_unipro_core_clk_src",
925 .parent_data = gcc_parent_data_0,
926 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
927 .ops = &clk_rcg2_shared_ops,
931 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
932 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
933 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
934 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
935 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
936 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
940 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
944 .parent_map = gcc_parent_map_0,
945 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
946 .clkr.hw.init = &(struct clk_init_data){
947 .name = "gcc_ufs_phy_axi_clk_src",
948 .parent_data = gcc_parent_data_0,
949 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
950 .ops = &clk_rcg2_shared_ops,
954 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
958 .parent_map = gcc_parent_map_0,
959 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
960 .clkr.hw.init = &(struct clk_init_data){
961 .name = "gcc_ufs_phy_ice_core_clk_src",
962 .parent_data = gcc_parent_data_0,
963 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
964 .ops = &clk_rcg2_shared_ops,
968 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
972 .parent_map = gcc_parent_map_4,
973 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
974 .clkr.hw.init = &(struct clk_init_data){
975 .name = "gcc_ufs_phy_phy_aux_clk_src",
976 .parent_data = gcc_parent_data_4,
977 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
978 .ops = &clk_rcg2_shared_ops,
982 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
986 .parent_map = gcc_parent_map_0,
987 .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
988 .clkr.hw.init = &(struct clk_init_data){
989 .name = "gcc_ufs_phy_unipro_core_clk_src",
990 .parent_data = gcc_parent_data_0,
991 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
992 .ops = &clk_rcg2_shared_ops,
996 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
997 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
998 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
999 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1000 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1001 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1005 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1009 .parent_map = gcc_parent_map_0,
1010 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1011 .clkr.hw.init = &(struct clk_init_data){
1012 .name = "gcc_usb30_prim_master_clk_src",
1013 .parent_data = gcc_parent_data_0,
1014 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1015 .ops = &clk_rcg2_shared_ops,
1019 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
1020 F(19200000, P_BI_TCXO, 1, 0, 0),
1021 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
1022 F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0),
1023 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1027 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1031 .parent_map = gcc_parent_map_0,
1032 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1033 .clkr.hw.init = &(struct clk_init_data){
1034 .name = "gcc_usb30_prim_mock_utmi_clk_src",
1035 .parent_data = gcc_parent_data_0,
1036 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1037 .ops = &clk_rcg2_shared_ops,
1041 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
1042 .cmd_rcgr = 0x10018,
1045 .parent_map = gcc_parent_map_0,
1046 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1047 .clkr.hw.init = &(struct clk_init_data){
1048 .name = "gcc_usb30_sec_master_clk_src",
1049 .parent_data = gcc_parent_data_0,
1050 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1051 .ops = &clk_rcg2_ops,
1055 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
1056 .cmd_rcgr = 0x10030,
1059 .parent_map = gcc_parent_map_0,
1060 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1061 .clkr.hw.init = &(struct clk_init_data){
1062 .name = "gcc_usb30_sec_mock_utmi_clk_src",
1063 .parent_data = gcc_parent_data_0,
1064 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1065 .ops = &clk_rcg2_ops,
1069 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1073 .parent_map = gcc_parent_map_2,
1074 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
1075 .clkr.hw.init = &(struct clk_init_data){
1076 .name = "gcc_usb3_prim_phy_aux_clk_src",
1077 .parent_data = gcc_parent_data_2,
1078 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1079 .ops = &clk_rcg2_ops,
1083 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
1084 .cmd_rcgr = 0x1005c,
1087 .parent_map = gcc_parent_map_2,
1088 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
1089 .clkr.hw.init = &(struct clk_init_data){
1090 .name = "gcc_usb3_sec_phy_aux_clk_src",
1091 .parent_data = gcc_parent_data_2,
1092 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1093 .ops = &clk_rcg2_shared_ops,
1097 static struct clk_rcg2 gcc_vs_ctrl_clk_src = {
1098 .cmd_rcgr = 0x7a030,
1101 .parent_map = gcc_parent_map_3,
1102 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
1103 .clkr.hw.init = &(struct clk_init_data){
1104 .name = "gcc_vs_ctrl_clk_src",
1105 .parent_data = gcc_parent_data_3,
1106 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1107 .ops = &clk_rcg2_ops,
1111 static const struct freq_tbl ftbl_gcc_vsensor_clk_src[] = {
1112 F(19200000, P_BI_TCXO, 1, 0, 0),
1113 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
1114 F(600000000, P_GPLL0_OUT_MAIN, 1, 0, 0),
1118 static struct clk_rcg2 gcc_vsensor_clk_src = {
1119 .cmd_rcgr = 0x7a018,
1122 .parent_map = gcc_parent_map_3,
1123 .freq_tbl = ftbl_gcc_vsensor_clk_src,
1124 .clkr.hw.init = &(struct clk_init_data){
1125 .name = "gcc_vsensor_clk_src",
1126 .parent_data = gcc_parent_data_8,
1127 .num_parents = ARRAY_SIZE(gcc_parent_data_8),
1128 .ops = &clk_rcg2_ops,
1132 static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
1133 .halt_reg = 0x90014,
1134 .halt_check = BRANCH_HALT,
1136 .enable_reg = 0x90014,
1137 .enable_mask = BIT(0),
1138 .hw.init = &(struct clk_init_data){
1139 .name = "gcc_aggre_noc_pcie_tbu_clk",
1140 .ops = &clk_branch2_ops,
1145 static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
1146 .halt_reg = 0x82028,
1147 .halt_check = BRANCH_HALT,
1148 .hwcg_reg = 0x82028,
1151 .enable_reg = 0x82028,
1152 .enable_mask = BIT(0),
1153 .hw.init = &(struct clk_init_data){
1154 .name = "gcc_aggre_ufs_card_axi_clk",
1155 .parent_hws = (const struct clk_hw*[]){
1156 &gcc_ufs_card_axi_clk_src.clkr.hw,
1159 .flags = CLK_SET_RATE_PARENT,
1160 .ops = &clk_branch2_ops,
1165 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1166 .halt_reg = 0x82024,
1167 .halt_check = BRANCH_HALT,
1168 .hwcg_reg = 0x82024,
1171 .enable_reg = 0x82024,
1172 .enable_mask = BIT(0),
1173 .hw.init = &(struct clk_init_data){
1174 .name = "gcc_aggre_ufs_phy_axi_clk",
1175 .parent_hws = (const struct clk_hw*[]){
1176 &gcc_ufs_phy_axi_clk_src.clkr.hw,
1179 .flags = CLK_SET_RATE_PARENT,
1180 .ops = &clk_branch2_ops,
1185 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1186 .halt_reg = 0x8201c,
1187 .halt_check = BRANCH_HALT,
1189 .enable_reg = 0x8201c,
1190 .enable_mask = BIT(0),
1191 .hw.init = &(struct clk_init_data){
1192 .name = "gcc_aggre_usb3_prim_axi_clk",
1193 .parent_hws = (const struct clk_hw*[]){
1194 &gcc_usb30_prim_master_clk_src.clkr.hw,
1197 .flags = CLK_SET_RATE_PARENT,
1198 .ops = &clk_branch2_ops,
1203 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
1204 .halt_reg = 0x82020,
1205 .halt_check = BRANCH_HALT,
1207 .enable_reg = 0x82020,
1208 .enable_mask = BIT(0),
1209 .hw.init = &(struct clk_init_data){
1210 .name = "gcc_aggre_usb3_sec_axi_clk",
1211 .parent_hws = (const struct clk_hw*[]){
1212 &gcc_usb30_sec_master_clk_src.clkr.hw,
1215 .flags = CLK_SET_RATE_PARENT,
1216 .ops = &clk_branch2_ops,
1221 static struct clk_branch gcc_apc_vs_clk = {
1222 .halt_reg = 0x7a050,
1223 .halt_check = BRANCH_HALT,
1225 .enable_reg = 0x7a050,
1226 .enable_mask = BIT(0),
1227 .hw.init = &(struct clk_init_data){
1228 .name = "gcc_apc_vs_clk",
1229 .parent_hws = (const struct clk_hw*[]){
1230 &gcc_vsensor_clk_src.clkr.hw,
1233 .flags = CLK_SET_RATE_PARENT,
1234 .ops = &clk_branch2_ops,
1239 static struct clk_branch gcc_boot_rom_ahb_clk = {
1240 .halt_reg = 0x38004,
1241 .halt_check = BRANCH_HALT_VOTED,
1242 .hwcg_reg = 0x38004,
1245 .enable_reg = 0x52004,
1246 .enable_mask = BIT(10),
1247 .hw.init = &(struct clk_init_data){
1248 .name = "gcc_boot_rom_ahb_clk",
1249 .ops = &clk_branch2_ops,
1254 static struct clk_branch gcc_camera_ahb_clk = {
1256 .halt_check = BRANCH_HALT,
1260 .enable_reg = 0xb008,
1261 .enable_mask = BIT(0),
1262 .hw.init = &(struct clk_init_data){
1263 .name = "gcc_camera_ahb_clk",
1264 .flags = CLK_IS_CRITICAL,
1265 .ops = &clk_branch2_ops,
1270 static struct clk_branch gcc_camera_axi_clk = {
1272 .halt_check = BRANCH_VOTED,
1274 .enable_reg = 0xb020,
1275 .enable_mask = BIT(0),
1276 .hw.init = &(struct clk_init_data){
1277 .name = "gcc_camera_axi_clk",
1278 .ops = &clk_branch2_ops,
1283 static struct clk_branch gcc_camera_xo_clk = {
1285 .halt_check = BRANCH_HALT,
1287 .enable_reg = 0xb02c,
1288 .enable_mask = BIT(0),
1289 .hw.init = &(struct clk_init_data){
1290 .name = "gcc_camera_xo_clk",
1291 .flags = CLK_IS_CRITICAL,
1292 .ops = &clk_branch2_ops,
1297 static struct clk_branch gcc_ce1_ahb_clk = {
1298 .halt_reg = 0x4100c,
1299 .halt_check = BRANCH_HALT_VOTED,
1300 .hwcg_reg = 0x4100c,
1303 .enable_reg = 0x52004,
1304 .enable_mask = BIT(3),
1305 .hw.init = &(struct clk_init_data){
1306 .name = "gcc_ce1_ahb_clk",
1307 .ops = &clk_branch2_ops,
1312 static struct clk_branch gcc_ce1_axi_clk = {
1313 .halt_reg = 0x41008,
1314 .halt_check = BRANCH_HALT_VOTED,
1316 .enable_reg = 0x52004,
1317 .enable_mask = BIT(4),
1318 .hw.init = &(struct clk_init_data){
1319 .name = "gcc_ce1_axi_clk",
1320 .ops = &clk_branch2_ops,
1325 static struct clk_branch gcc_ce1_clk = {
1326 .halt_reg = 0x41004,
1327 .halt_check = BRANCH_HALT_VOTED,
1329 .enable_reg = 0x52004,
1330 .enable_mask = BIT(5),
1331 .hw.init = &(struct clk_init_data){
1332 .name = "gcc_ce1_clk",
1333 .ops = &clk_branch2_ops,
1338 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1340 .halt_check = BRANCH_HALT,
1342 .enable_reg = 0x502c,
1343 .enable_mask = BIT(0),
1344 .hw.init = &(struct clk_init_data){
1345 .name = "gcc_cfg_noc_usb3_prim_axi_clk",
1346 .parent_hws = (const struct clk_hw*[]){
1347 &gcc_usb30_prim_master_clk_src.clkr.hw,
1350 .flags = CLK_SET_RATE_PARENT,
1351 .ops = &clk_branch2_ops,
1356 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
1358 .halt_check = BRANCH_HALT,
1360 .enable_reg = 0x5030,
1361 .enable_mask = BIT(0),
1362 .hw.init = &(struct clk_init_data){
1363 .name = "gcc_cfg_noc_usb3_sec_axi_clk",
1364 .parent_hws = (const struct clk_hw*[]){
1365 &gcc_usb30_sec_master_clk_src.clkr.hw,
1368 .flags = CLK_SET_RATE_PARENT,
1369 .ops = &clk_branch2_ops,
1374 static struct clk_branch gcc_cpuss_ahb_clk = {
1375 .halt_reg = 0x48000,
1376 .halt_check = BRANCH_HALT_VOTED,
1378 .enable_reg = 0x52004,
1379 .enable_mask = BIT(21),
1380 .hw.init = &(struct clk_init_data){
1381 .name = "gcc_cpuss_ahb_clk",
1382 .parent_hws = (const struct clk_hw*[]){
1383 &gcc_cpuss_ahb_clk_src.clkr.hw,
1386 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1387 .ops = &clk_branch2_ops,
1392 static struct clk_branch gcc_cpuss_rbcpr_clk = {
1393 .halt_reg = 0x48008,
1394 .halt_check = BRANCH_HALT,
1396 .enable_reg = 0x48008,
1397 .enable_mask = BIT(0),
1398 .hw.init = &(struct clk_init_data){
1399 .name = "gcc_cpuss_rbcpr_clk",
1400 .parent_hws = (const struct clk_hw*[]){
1401 &gcc_cpuss_rbcpr_clk_src.clkr.hw,
1404 .flags = CLK_SET_RATE_PARENT,
1405 .ops = &clk_branch2_ops,
1411 * The source clock frequencies are different for SDM670; define a child clock
1412 * pointing to the source clock that uses SDM670 frequencies.
1414 static struct clk_branch gcc_sdm670_cpuss_rbcpr_clk = {
1415 .halt_reg = 0x48008,
1416 .halt_check = BRANCH_HALT,
1418 .enable_reg = 0x48008,
1419 .enable_mask = BIT(0),
1420 .hw.init = &(struct clk_init_data){
1421 .name = "gcc_cpuss_rbcpr_clk",
1422 .parent_hws = (const struct clk_hw*[]){
1423 &gcc_sdm670_cpuss_rbcpr_clk_src.clkr.hw,
1426 .flags = CLK_SET_RATE_PARENT,
1427 .ops = &clk_branch2_ops,
1432 static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1433 .halt_reg = 0x44038,
1434 .halt_check = BRANCH_VOTED,
1436 .enable_reg = 0x44038,
1437 .enable_mask = BIT(0),
1438 .hw.init = &(struct clk_init_data){
1439 .name = "gcc_ddrss_gpu_axi_clk",
1440 .ops = &clk_branch2_ops,
1445 static struct clk_branch gcc_disp_ahb_clk = {
1447 .halt_check = BRANCH_HALT,
1451 .enable_reg = 0xb00c,
1452 .enable_mask = BIT(0),
1453 .hw.init = &(struct clk_init_data){
1454 .name = "gcc_disp_ahb_clk",
1455 .flags = CLK_IS_CRITICAL,
1456 .ops = &clk_branch2_ops,
1461 static struct clk_branch gcc_disp_axi_clk = {
1463 .halt_check = BRANCH_VOTED,
1465 .enable_reg = 0xb024,
1466 .enable_mask = BIT(0),
1467 .hw.init = &(struct clk_init_data){
1468 .name = "gcc_disp_axi_clk",
1469 .ops = &clk_branch2_ops,
1474 static struct clk_branch gcc_disp_gpll0_clk_src = {
1475 .halt_check = BRANCH_HALT_DELAY,
1477 .enable_reg = 0x52004,
1478 .enable_mask = BIT(18),
1479 .hw.init = &(struct clk_init_data){
1480 .name = "gcc_disp_gpll0_clk_src",
1481 .parent_hws = (const struct clk_hw*[]){
1485 .ops = &clk_branch2_aon_ops,
1490 static struct clk_branch gcc_disp_gpll0_div_clk_src = {
1491 .halt_check = BRANCH_HALT_DELAY,
1493 .enable_reg = 0x52004,
1494 .enable_mask = BIT(19),
1495 .hw.init = &(struct clk_init_data){
1496 .name = "gcc_disp_gpll0_div_clk_src",
1497 .parent_hws = (const struct clk_hw*[]){
1498 &gpll0_out_even.clkr.hw,
1501 .ops = &clk_branch2_ops,
1506 static struct clk_branch gcc_disp_xo_clk = {
1508 .halt_check = BRANCH_HALT,
1510 .enable_reg = 0xb030,
1511 .enable_mask = BIT(0),
1512 .hw.init = &(struct clk_init_data){
1513 .name = "gcc_disp_xo_clk",
1514 .flags = CLK_IS_CRITICAL,
1515 .ops = &clk_branch2_ops,
1520 static struct clk_branch gcc_gp1_clk = {
1521 .halt_reg = 0x64000,
1522 .halt_check = BRANCH_HALT,
1524 .enable_reg = 0x64000,
1525 .enable_mask = BIT(0),
1526 .hw.init = &(struct clk_init_data){
1527 .name = "gcc_gp1_clk",
1528 .parent_hws = (const struct clk_hw*[]){
1529 &gcc_gp1_clk_src.clkr.hw,
1532 .flags = CLK_SET_RATE_PARENT,
1533 .ops = &clk_branch2_ops,
1538 static struct clk_branch gcc_gp2_clk = {
1539 .halt_reg = 0x65000,
1540 .halt_check = BRANCH_HALT,
1542 .enable_reg = 0x65000,
1543 .enable_mask = BIT(0),
1544 .hw.init = &(struct clk_init_data){
1545 .name = "gcc_gp2_clk",
1546 .parent_hws = (const struct clk_hw*[]){
1547 &gcc_gp2_clk_src.clkr.hw,
1550 .flags = CLK_SET_RATE_PARENT,
1551 .ops = &clk_branch2_ops,
1556 static struct clk_branch gcc_gp3_clk = {
1557 .halt_reg = 0x66000,
1558 .halt_check = BRANCH_HALT,
1560 .enable_reg = 0x66000,
1561 .enable_mask = BIT(0),
1562 .hw.init = &(struct clk_init_data){
1563 .name = "gcc_gp3_clk",
1564 .parent_hws = (const struct clk_hw*[]){
1565 &gcc_gp3_clk_src.clkr.hw,
1568 .flags = CLK_SET_RATE_PARENT,
1569 .ops = &clk_branch2_ops,
1574 static struct clk_branch gcc_gpu_cfg_ahb_clk = {
1575 .halt_reg = 0x71004,
1576 .halt_check = BRANCH_HALT,
1577 .hwcg_reg = 0x71004,
1580 .enable_reg = 0x71004,
1581 .enable_mask = BIT(0),
1582 .hw.init = &(struct clk_init_data){
1583 .name = "gcc_gpu_cfg_ahb_clk",
1584 .flags = CLK_IS_CRITICAL,
1585 .ops = &clk_branch2_ops,
1590 static struct clk_branch gcc_gpu_gpll0_clk_src = {
1591 .halt_check = BRANCH_HALT_DELAY,
1593 .enable_reg = 0x52004,
1594 .enable_mask = BIT(15),
1595 .hw.init = &(struct clk_init_data){
1596 .name = "gcc_gpu_gpll0_clk_src",
1597 .parent_hws = (const struct clk_hw*[]){
1601 .ops = &clk_branch2_ops,
1606 static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1607 .halt_check = BRANCH_HALT_DELAY,
1609 .enable_reg = 0x52004,
1610 .enable_mask = BIT(16),
1611 .hw.init = &(struct clk_init_data){
1612 .name = "gcc_gpu_gpll0_div_clk_src",
1613 .parent_hws = (const struct clk_hw*[]){
1614 &gpll0_out_even.clkr.hw,
1617 .ops = &clk_branch2_ops,
1622 static struct clk_branch gcc_gpu_iref_clk = {
1623 .halt_reg = 0x8c010,
1624 .halt_check = BRANCH_HALT,
1626 .enable_reg = 0x8c010,
1627 .enable_mask = BIT(0),
1628 .hw.init = &(struct clk_init_data){
1629 .name = "gcc_gpu_iref_clk",
1630 .ops = &clk_branch2_ops,
1635 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1636 .halt_reg = 0x7100c,
1637 .halt_check = BRANCH_VOTED,
1639 .enable_reg = 0x7100c,
1640 .enable_mask = BIT(0),
1641 .hw.init = &(struct clk_init_data){
1642 .name = "gcc_gpu_memnoc_gfx_clk",
1643 .ops = &clk_branch2_ops,
1648 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1649 .halt_reg = 0x71018,
1650 .halt_check = BRANCH_HALT,
1652 .enable_reg = 0x71018,
1653 .enable_mask = BIT(0),
1654 .hw.init = &(struct clk_init_data){
1655 .name = "gcc_gpu_snoc_dvm_gfx_clk",
1656 .ops = &clk_branch2_ops,
1661 static struct clk_branch gcc_gpu_vs_clk = {
1662 .halt_reg = 0x7a04c,
1663 .halt_check = BRANCH_HALT,
1665 .enable_reg = 0x7a04c,
1666 .enable_mask = BIT(0),
1667 .hw.init = &(struct clk_init_data){
1668 .name = "gcc_gpu_vs_clk",
1669 .parent_hws = (const struct clk_hw*[]){
1670 &gcc_vsensor_clk_src.clkr.hw,
1673 .flags = CLK_SET_RATE_PARENT,
1674 .ops = &clk_branch2_ops,
1679 static struct clk_branch gcc_mss_axis2_clk = {
1680 .halt_reg = 0x8a008,
1681 .halt_check = BRANCH_HALT,
1683 .enable_reg = 0x8a008,
1684 .enable_mask = BIT(0),
1685 .hw.init = &(struct clk_init_data){
1686 .name = "gcc_mss_axis2_clk",
1687 .ops = &clk_branch2_ops,
1692 static struct clk_branch gcc_mss_cfg_ahb_clk = {
1693 .halt_reg = 0x8a000,
1694 .halt_check = BRANCH_HALT,
1695 .hwcg_reg = 0x8a000,
1698 .enable_reg = 0x8a000,
1699 .enable_mask = BIT(0),
1700 .hw.init = &(struct clk_init_data){
1701 .name = "gcc_mss_cfg_ahb_clk",
1702 .ops = &clk_branch2_ops,
1707 static struct clk_branch gcc_mss_gpll0_div_clk_src = {
1708 .halt_check = BRANCH_HALT_DELAY,
1710 .enable_reg = 0x52004,
1711 .enable_mask = BIT(17),
1712 .hw.init = &(struct clk_init_data){
1713 .name = "gcc_mss_gpll0_div_clk_src",
1714 .ops = &clk_branch2_ops,
1719 static struct clk_branch gcc_mss_mfab_axis_clk = {
1720 .halt_reg = 0x8a004,
1721 .halt_check = BRANCH_VOTED,
1722 .hwcg_reg = 0x8a004,
1725 .enable_reg = 0x8a004,
1726 .enable_mask = BIT(0),
1727 .hw.init = &(struct clk_init_data){
1728 .name = "gcc_mss_mfab_axis_clk",
1729 .ops = &clk_branch2_ops,
1734 static struct clk_branch gcc_mss_q6_memnoc_axi_clk = {
1735 .halt_reg = 0x8a154,
1736 .halt_check = BRANCH_VOTED,
1738 .enable_reg = 0x8a154,
1739 .enable_mask = BIT(0),
1740 .hw.init = &(struct clk_init_data){
1741 .name = "gcc_mss_q6_memnoc_axi_clk",
1742 .ops = &clk_branch2_ops,
1747 static struct clk_branch gcc_mss_snoc_axi_clk = {
1748 .halt_reg = 0x8a150,
1749 .halt_check = BRANCH_HALT,
1751 .enable_reg = 0x8a150,
1752 .enable_mask = BIT(0),
1753 .hw.init = &(struct clk_init_data){
1754 .name = "gcc_mss_snoc_axi_clk",
1755 .ops = &clk_branch2_ops,
1760 static struct clk_branch gcc_mss_vs_clk = {
1761 .halt_reg = 0x7a048,
1762 .halt_check = BRANCH_HALT,
1764 .enable_reg = 0x7a048,
1765 .enable_mask = BIT(0),
1766 .hw.init = &(struct clk_init_data){
1767 .name = "gcc_mss_vs_clk",
1768 .parent_hws = (const struct clk_hw*[]){
1769 &gcc_vsensor_clk_src.clkr.hw,
1772 .flags = CLK_SET_RATE_PARENT,
1773 .ops = &clk_branch2_ops,
1778 static struct clk_branch gcc_pcie_0_aux_clk = {
1779 .halt_reg = 0x6b01c,
1780 .halt_check = BRANCH_HALT_VOTED,
1782 .enable_reg = 0x5200c,
1783 .enable_mask = BIT(3),
1784 .hw.init = &(struct clk_init_data){
1785 .name = "gcc_pcie_0_aux_clk",
1786 .parent_hws = (const struct clk_hw*[]){
1787 &gcc_pcie_0_aux_clk_src.clkr.hw,
1790 .flags = CLK_SET_RATE_PARENT,
1791 .ops = &clk_branch2_ops,
1796 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1797 .halt_reg = 0x6b018,
1798 .halt_check = BRANCH_HALT_VOTED,
1799 .hwcg_reg = 0x6b018,
1802 .enable_reg = 0x5200c,
1803 .enable_mask = BIT(2),
1804 .hw.init = &(struct clk_init_data){
1805 .name = "gcc_pcie_0_cfg_ahb_clk",
1806 .ops = &clk_branch2_ops,
1811 static struct clk_branch gcc_pcie_0_clkref_clk = {
1812 .halt_reg = 0x8c00c,
1813 .halt_check = BRANCH_HALT,
1815 .enable_reg = 0x8c00c,
1816 .enable_mask = BIT(0),
1817 .hw.init = &(struct clk_init_data){
1818 .name = "gcc_pcie_0_clkref_clk",
1819 .ops = &clk_branch2_ops,
1824 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1825 .halt_reg = 0x6b014,
1826 .halt_check = BRANCH_HALT_VOTED,
1828 .enable_reg = 0x5200c,
1829 .enable_mask = BIT(1),
1830 .hw.init = &(struct clk_init_data){
1831 .name = "gcc_pcie_0_mstr_axi_clk",
1832 .ops = &clk_branch2_ops,
1837 static struct clk_branch gcc_pcie_0_pipe_clk = {
1838 .halt_check = BRANCH_HALT_SKIP,
1840 .enable_reg = 0x5200c,
1841 .enable_mask = BIT(4),
1842 .hw.init = &(struct clk_init_data){
1843 .name = "gcc_pcie_0_pipe_clk",
1844 .parent_data = &(const struct clk_parent_data){
1845 .fw_name = "pcie_0_pipe_clk", .name = "pcie_0_pipe_clk",
1848 .flags = CLK_SET_RATE_PARENT,
1849 .ops = &clk_branch2_ops,
1854 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1855 .halt_reg = 0x6b010,
1856 .halt_check = BRANCH_HALT_VOTED,
1857 .hwcg_reg = 0x6b010,
1860 .enable_reg = 0x5200c,
1861 .enable_mask = BIT(0),
1862 .hw.init = &(struct clk_init_data){
1863 .name = "gcc_pcie_0_slv_axi_clk",
1864 .ops = &clk_branch2_ops,
1869 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1870 .halt_reg = 0x6b00c,
1871 .halt_check = BRANCH_HALT_VOTED,
1873 .enable_reg = 0x5200c,
1874 .enable_mask = BIT(5),
1875 .hw.init = &(struct clk_init_data){
1876 .name = "gcc_pcie_0_slv_q2a_axi_clk",
1877 .ops = &clk_branch2_ops,
1882 static struct clk_branch gcc_pcie_1_aux_clk = {
1883 .halt_reg = 0x8d01c,
1884 .halt_check = BRANCH_HALT_VOTED,
1886 .enable_reg = 0x52004,
1887 .enable_mask = BIT(29),
1888 .hw.init = &(struct clk_init_data){
1889 .name = "gcc_pcie_1_aux_clk",
1890 .parent_hws = (const struct clk_hw*[]){
1891 &gcc_pcie_1_aux_clk_src.clkr.hw,
1894 .flags = CLK_SET_RATE_PARENT,
1895 .ops = &clk_branch2_ops,
1900 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1901 .halt_reg = 0x8d018,
1902 .halt_check = BRANCH_HALT_VOTED,
1903 .hwcg_reg = 0x8d018,
1906 .enable_reg = 0x52004,
1907 .enable_mask = BIT(28),
1908 .hw.init = &(struct clk_init_data){
1909 .name = "gcc_pcie_1_cfg_ahb_clk",
1910 .ops = &clk_branch2_ops,
1915 static struct clk_branch gcc_pcie_1_clkref_clk = {
1916 .halt_reg = 0x8c02c,
1917 .halt_check = BRANCH_HALT,
1919 .enable_reg = 0x8c02c,
1920 .enable_mask = BIT(0),
1921 .hw.init = &(struct clk_init_data){
1922 .name = "gcc_pcie_1_clkref_clk",
1923 .ops = &clk_branch2_ops,
1928 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1929 .halt_reg = 0x8d014,
1930 .halt_check = BRANCH_HALT_VOTED,
1932 .enable_reg = 0x52004,
1933 .enable_mask = BIT(27),
1934 .hw.init = &(struct clk_init_data){
1935 .name = "gcc_pcie_1_mstr_axi_clk",
1936 .ops = &clk_branch2_ops,
1941 static struct clk_branch gcc_pcie_1_pipe_clk = {
1942 .halt_check = BRANCH_HALT_SKIP,
1944 .enable_reg = 0x52004,
1945 .enable_mask = BIT(30),
1946 .hw.init = &(struct clk_init_data){
1947 .name = "gcc_pcie_1_pipe_clk",
1948 .parent_data = &(const struct clk_parent_data){
1949 .fw_name = "pcie_1_pipe_clk", .name = "pcie_1_pipe_clk",
1952 .ops = &clk_branch2_ops,
1957 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1958 .halt_reg = 0x8d010,
1959 .halt_check = BRANCH_HALT_VOTED,
1960 .hwcg_reg = 0x8d010,
1963 .enable_reg = 0x52004,
1964 .enable_mask = BIT(26),
1965 .hw.init = &(struct clk_init_data){
1966 .name = "gcc_pcie_1_slv_axi_clk",
1967 .ops = &clk_branch2_ops,
1972 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
1973 .halt_reg = 0x8d00c,
1974 .halt_check = BRANCH_HALT_VOTED,
1976 .enable_reg = 0x52004,
1977 .enable_mask = BIT(25),
1978 .hw.init = &(struct clk_init_data){
1979 .name = "gcc_pcie_1_slv_q2a_axi_clk",
1980 .ops = &clk_branch2_ops,
1985 static struct clk_branch gcc_pcie_phy_aux_clk = {
1986 .halt_reg = 0x6f004,
1987 .halt_check = BRANCH_HALT,
1989 .enable_reg = 0x6f004,
1990 .enable_mask = BIT(0),
1991 .hw.init = &(struct clk_init_data){
1992 .name = "gcc_pcie_phy_aux_clk",
1993 .parent_hws = (const struct clk_hw*[]){
1994 &gcc_pcie_0_aux_clk_src.clkr.hw,
1997 .flags = CLK_SET_RATE_PARENT,
1998 .ops = &clk_branch2_ops,
2003 static struct clk_branch gcc_pcie_phy_refgen_clk = {
2004 .halt_reg = 0x6f02c,
2005 .halt_check = BRANCH_HALT,
2007 .enable_reg = 0x6f02c,
2008 .enable_mask = BIT(0),
2009 .hw.init = &(struct clk_init_data){
2010 .name = "gcc_pcie_phy_refgen_clk",
2011 .parent_hws = (const struct clk_hw*[]){
2012 &gcc_pcie_phy_refgen_clk_src.clkr.hw,
2015 .flags = CLK_SET_RATE_PARENT,
2016 .ops = &clk_branch2_ops,
2021 static struct clk_branch gcc_pdm2_clk = {
2022 .halt_reg = 0x3300c,
2023 .halt_check = BRANCH_HALT,
2025 .enable_reg = 0x3300c,
2026 .enable_mask = BIT(0),
2027 .hw.init = &(struct clk_init_data){
2028 .name = "gcc_pdm2_clk",
2029 .parent_hws = (const struct clk_hw*[]){
2030 &gcc_pdm2_clk_src.clkr.hw,
2033 .flags = CLK_SET_RATE_PARENT,
2034 .ops = &clk_branch2_ops,
2039 static struct clk_branch gcc_pdm_ahb_clk = {
2040 .halt_reg = 0x33004,
2041 .halt_check = BRANCH_HALT,
2042 .hwcg_reg = 0x33004,
2045 .enable_reg = 0x33004,
2046 .enable_mask = BIT(0),
2047 .hw.init = &(struct clk_init_data){
2048 .name = "gcc_pdm_ahb_clk",
2049 .ops = &clk_branch2_ops,
2054 static struct clk_branch gcc_pdm_xo4_clk = {
2055 .halt_reg = 0x33008,
2056 .halt_check = BRANCH_HALT,
2058 .enable_reg = 0x33008,
2059 .enable_mask = BIT(0),
2060 .hw.init = &(struct clk_init_data){
2061 .name = "gcc_pdm_xo4_clk",
2062 .ops = &clk_branch2_ops,
2067 static struct clk_branch gcc_prng_ahb_clk = {
2068 .halt_reg = 0x34004,
2069 .halt_check = BRANCH_HALT_VOTED,
2070 .hwcg_reg = 0x34004,
2073 .enable_reg = 0x52004,
2074 .enable_mask = BIT(13),
2075 .hw.init = &(struct clk_init_data){
2076 .name = "gcc_prng_ahb_clk",
2077 .ops = &clk_branch2_ops,
2082 static struct clk_branch gcc_qmip_camera_ahb_clk = {
2084 .halt_check = BRANCH_HALT,
2088 .enable_reg = 0xb014,
2089 .enable_mask = BIT(0),
2090 .hw.init = &(struct clk_init_data){
2091 .name = "gcc_qmip_camera_ahb_clk",
2092 .ops = &clk_branch2_ops,
2097 static struct clk_branch gcc_qmip_disp_ahb_clk = {
2099 .halt_check = BRANCH_HALT,
2103 .enable_reg = 0xb018,
2104 .enable_mask = BIT(0),
2105 .hw.init = &(struct clk_init_data){
2106 .name = "gcc_qmip_disp_ahb_clk",
2107 .ops = &clk_branch2_ops,
2112 static struct clk_branch gcc_qmip_video_ahb_clk = {
2114 .halt_check = BRANCH_HALT,
2118 .enable_reg = 0xb010,
2119 .enable_mask = BIT(0),
2120 .hw.init = &(struct clk_init_data){
2121 .name = "gcc_qmip_video_ahb_clk",
2122 .ops = &clk_branch2_ops,
2127 static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
2128 .halt_reg = 0x4b000,
2129 .halt_check = BRANCH_HALT,
2131 .enable_reg = 0x4b000,
2132 .enable_mask = BIT(0),
2133 .hw.init = &(struct clk_init_data){
2134 .name = "gcc_qspi_cnoc_periph_ahb_clk",
2135 .ops = &clk_branch2_ops,
2140 static struct clk_branch gcc_qspi_core_clk = {
2141 .halt_reg = 0x4b004,
2142 .halt_check = BRANCH_HALT,
2144 .enable_reg = 0x4b004,
2145 .enable_mask = BIT(0),
2146 .hw.init = &(struct clk_init_data){
2147 .name = "gcc_qspi_core_clk",
2148 .parent_hws = (const struct clk_hw*[]){
2149 &gcc_qspi_core_clk_src.clkr.hw,
2152 .flags = CLK_SET_RATE_PARENT,
2153 .ops = &clk_branch2_ops,
2158 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2159 .halt_reg = 0x17030,
2160 .halt_check = BRANCH_HALT_VOTED,
2162 .enable_reg = 0x5200c,
2163 .enable_mask = BIT(10),
2164 .hw.init = &(struct clk_init_data){
2165 .name = "gcc_qupv3_wrap0_s0_clk",
2166 .parent_hws = (const struct clk_hw*[]){
2167 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
2170 .flags = CLK_SET_RATE_PARENT,
2171 .ops = &clk_branch2_ops,
2176 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2177 .halt_reg = 0x17160,
2178 .halt_check = BRANCH_HALT_VOTED,
2180 .enable_reg = 0x5200c,
2181 .enable_mask = BIT(11),
2182 .hw.init = &(struct clk_init_data){
2183 .name = "gcc_qupv3_wrap0_s1_clk",
2184 .parent_hws = (const struct clk_hw*[]){
2185 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
2188 .flags = CLK_SET_RATE_PARENT,
2189 .ops = &clk_branch2_ops,
2194 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2195 .halt_reg = 0x17290,
2196 .halt_check = BRANCH_HALT_VOTED,
2198 .enable_reg = 0x5200c,
2199 .enable_mask = BIT(12),
2200 .hw.init = &(struct clk_init_data){
2201 .name = "gcc_qupv3_wrap0_s2_clk",
2202 .parent_hws = (const struct clk_hw*[]){
2203 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
2206 .flags = CLK_SET_RATE_PARENT,
2207 .ops = &clk_branch2_ops,
2212 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2213 .halt_reg = 0x173c0,
2214 .halt_check = BRANCH_HALT_VOTED,
2216 .enable_reg = 0x5200c,
2217 .enable_mask = BIT(13),
2218 .hw.init = &(struct clk_init_data){
2219 .name = "gcc_qupv3_wrap0_s3_clk",
2220 .parent_hws = (const struct clk_hw*[]){
2221 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
2224 .flags = CLK_SET_RATE_PARENT,
2225 .ops = &clk_branch2_ops,
2230 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2231 .halt_reg = 0x174f0,
2232 .halt_check = BRANCH_HALT_VOTED,
2234 .enable_reg = 0x5200c,
2235 .enable_mask = BIT(14),
2236 .hw.init = &(struct clk_init_data){
2237 .name = "gcc_qupv3_wrap0_s4_clk",
2238 .parent_hws = (const struct clk_hw*[]){
2239 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
2242 .flags = CLK_SET_RATE_PARENT,
2243 .ops = &clk_branch2_ops,
2248 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2249 .halt_reg = 0x17620,
2250 .halt_check = BRANCH_HALT_VOTED,
2252 .enable_reg = 0x5200c,
2253 .enable_mask = BIT(15),
2254 .hw.init = &(struct clk_init_data){
2255 .name = "gcc_qupv3_wrap0_s5_clk",
2256 .parent_hws = (const struct clk_hw*[]){
2257 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
2260 .flags = CLK_SET_RATE_PARENT,
2261 .ops = &clk_branch2_ops,
2266 static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2267 .halt_reg = 0x17750,
2268 .halt_check = BRANCH_HALT_VOTED,
2270 .enable_reg = 0x5200c,
2271 .enable_mask = BIT(16),
2272 .hw.init = &(struct clk_init_data){
2273 .name = "gcc_qupv3_wrap0_s6_clk",
2274 .parent_hws = (const struct clk_hw*[]){
2275 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
2278 .flags = CLK_SET_RATE_PARENT,
2279 .ops = &clk_branch2_ops,
2284 static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2285 .halt_reg = 0x17880,
2286 .halt_check = BRANCH_HALT_VOTED,
2288 .enable_reg = 0x5200c,
2289 .enable_mask = BIT(17),
2290 .hw.init = &(struct clk_init_data){
2291 .name = "gcc_qupv3_wrap0_s7_clk",
2292 .parent_hws = (const struct clk_hw*[]){
2293 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
2296 .flags = CLK_SET_RATE_PARENT,
2297 .ops = &clk_branch2_ops,
2302 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2303 .halt_reg = 0x18014,
2304 .halt_check = BRANCH_HALT_VOTED,
2306 .enable_reg = 0x5200c,
2307 .enable_mask = BIT(22),
2308 .hw.init = &(struct clk_init_data){
2309 .name = "gcc_qupv3_wrap1_s0_clk",
2310 .parent_hws = (const struct clk_hw*[]){
2311 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
2314 .flags = CLK_SET_RATE_PARENT,
2315 .ops = &clk_branch2_ops,
2320 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2321 .halt_reg = 0x18144,
2322 .halt_check = BRANCH_HALT_VOTED,
2324 .enable_reg = 0x5200c,
2325 .enable_mask = BIT(23),
2326 .hw.init = &(struct clk_init_data){
2327 .name = "gcc_qupv3_wrap1_s1_clk",
2328 .parent_hws = (const struct clk_hw*[]){
2329 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
2332 .flags = CLK_SET_RATE_PARENT,
2333 .ops = &clk_branch2_ops,
2338 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2339 .halt_reg = 0x18274,
2340 .halt_check = BRANCH_HALT_VOTED,
2342 .enable_reg = 0x5200c,
2343 .enable_mask = BIT(24),
2344 .hw.init = &(struct clk_init_data){
2345 .name = "gcc_qupv3_wrap1_s2_clk",
2346 .parent_hws = (const struct clk_hw*[]){
2347 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
2350 .flags = CLK_SET_RATE_PARENT,
2351 .ops = &clk_branch2_ops,
2356 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2357 .halt_reg = 0x183a4,
2358 .halt_check = BRANCH_HALT_VOTED,
2360 .enable_reg = 0x5200c,
2361 .enable_mask = BIT(25),
2362 .hw.init = &(struct clk_init_data){
2363 .name = "gcc_qupv3_wrap1_s3_clk",
2364 .parent_hws = (const struct clk_hw*[]){
2365 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
2368 .flags = CLK_SET_RATE_PARENT,
2369 .ops = &clk_branch2_ops,
2374 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2375 .halt_reg = 0x184d4,
2376 .halt_check = BRANCH_HALT_VOTED,
2378 .enable_reg = 0x5200c,
2379 .enable_mask = BIT(26),
2380 .hw.init = &(struct clk_init_data){
2381 .name = "gcc_qupv3_wrap1_s4_clk",
2382 .parent_hws = (const struct clk_hw*[]){
2383 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
2386 .flags = CLK_SET_RATE_PARENT,
2387 .ops = &clk_branch2_ops,
2392 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2393 .halt_reg = 0x18604,
2394 .halt_check = BRANCH_HALT_VOTED,
2396 .enable_reg = 0x5200c,
2397 .enable_mask = BIT(27),
2398 .hw.init = &(struct clk_init_data){
2399 .name = "gcc_qupv3_wrap1_s5_clk",
2400 .parent_hws = (const struct clk_hw*[]){
2401 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
2404 .flags = CLK_SET_RATE_PARENT,
2405 .ops = &clk_branch2_ops,
2410 static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
2411 .halt_reg = 0x18734,
2412 .halt_check = BRANCH_HALT_VOTED,
2414 .enable_reg = 0x5200c,
2415 .enable_mask = BIT(28),
2416 .hw.init = &(struct clk_init_data){
2417 .name = "gcc_qupv3_wrap1_s6_clk",
2418 .parent_hws = (const struct clk_hw*[]){
2419 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
2422 .flags = CLK_SET_RATE_PARENT,
2423 .ops = &clk_branch2_ops,
2428 static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
2429 .halt_reg = 0x18864,
2430 .halt_check = BRANCH_HALT_VOTED,
2432 .enable_reg = 0x5200c,
2433 .enable_mask = BIT(29),
2434 .hw.init = &(struct clk_init_data){
2435 .name = "gcc_qupv3_wrap1_s7_clk",
2436 .parent_hws = (const struct clk_hw*[]){
2437 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
2440 .flags = CLK_SET_RATE_PARENT,
2441 .ops = &clk_branch2_ops,
2446 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2447 .halt_reg = 0x17004,
2448 .halt_check = BRANCH_HALT_VOTED,
2450 .enable_reg = 0x5200c,
2451 .enable_mask = BIT(6),
2452 .hw.init = &(struct clk_init_data){
2453 .name = "gcc_qupv3_wrap_0_m_ahb_clk",
2454 .ops = &clk_branch2_ops,
2459 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2460 .halt_reg = 0x17008,
2461 .halt_check = BRANCH_HALT_VOTED,
2462 .hwcg_reg = 0x17008,
2465 .enable_reg = 0x5200c,
2466 .enable_mask = BIT(7),
2467 .hw.init = &(struct clk_init_data){
2468 .name = "gcc_qupv3_wrap_0_s_ahb_clk",
2469 .ops = &clk_branch2_ops,
2474 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2475 .halt_reg = 0x1800c,
2476 .halt_check = BRANCH_HALT_VOTED,
2478 .enable_reg = 0x5200c,
2479 .enable_mask = BIT(20),
2480 .hw.init = &(struct clk_init_data){
2481 .name = "gcc_qupv3_wrap_1_m_ahb_clk",
2482 .ops = &clk_branch2_ops,
2487 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2488 .halt_reg = 0x18010,
2489 .halt_check = BRANCH_HALT_VOTED,
2490 .hwcg_reg = 0x18010,
2493 .enable_reg = 0x5200c,
2494 .enable_mask = BIT(21),
2495 .hw.init = &(struct clk_init_data){
2496 .name = "gcc_qupv3_wrap_1_s_ahb_clk",
2497 .ops = &clk_branch2_ops,
2502 static struct clk_branch gcc_sdcc1_ahb_clk = {
2503 .halt_reg = 0x26008,
2504 .halt_check = BRANCH_HALT,
2506 .enable_reg = 0x26008,
2507 .enable_mask = BIT(0),
2508 .hw.init = &(struct clk_init_data){
2509 .name = "gcc_sdcc1_ahb_clk",
2510 .ops = &clk_branch2_ops,
2515 static struct clk_branch gcc_sdcc1_apps_clk = {
2516 .halt_reg = 0x26004,
2517 .halt_check = BRANCH_HALT,
2519 .enable_reg = 0x26004,
2520 .enable_mask = BIT(0),
2521 .hw.init = &(struct clk_init_data){
2522 .name = "gcc_sdcc1_apps_clk",
2523 .parent_hws = (const struct clk_hw*[]){
2524 &gcc_sdcc1_apps_clk_src.clkr.hw,
2527 .flags = CLK_SET_RATE_PARENT,
2528 .ops = &clk_branch2_ops,
2533 static struct clk_branch gcc_sdcc1_ice_core_clk = {
2534 .halt_reg = 0x2600c,
2535 .halt_check = BRANCH_HALT,
2537 .enable_reg = 0x2600c,
2538 .enable_mask = BIT(0),
2539 .hw.init = &(struct clk_init_data){
2540 .name = "gcc_sdcc1_ice_core_clk",
2541 .parent_hws = (const struct clk_hw*[]){
2542 &gcc_sdcc1_ice_core_clk_src.clkr.hw,
2545 .flags = CLK_SET_RATE_PARENT,
2546 .ops = &clk_branch2_ops,
2551 static struct clk_branch gcc_sdcc2_ahb_clk = {
2552 .halt_reg = 0x14008,
2553 .halt_check = BRANCH_HALT,
2555 .enable_reg = 0x14008,
2556 .enable_mask = BIT(0),
2557 .hw.init = &(struct clk_init_data){
2558 .name = "gcc_sdcc2_ahb_clk",
2559 .ops = &clk_branch2_ops,
2564 static struct clk_branch gcc_sdcc2_apps_clk = {
2565 .halt_reg = 0x14004,
2566 .halt_check = BRANCH_HALT,
2568 .enable_reg = 0x14004,
2569 .enable_mask = BIT(0),
2570 .hw.init = &(struct clk_init_data){
2571 .name = "gcc_sdcc2_apps_clk",
2572 .parent_hws = (const struct clk_hw*[]){
2573 &gcc_sdcc2_apps_clk_src.clkr.hw,
2576 .flags = CLK_SET_RATE_PARENT,
2577 .ops = &clk_branch2_ops,
2582 static struct clk_branch gcc_sdcc4_ahb_clk = {
2583 .halt_reg = 0x16008,
2584 .halt_check = BRANCH_HALT,
2586 .enable_reg = 0x16008,
2587 .enable_mask = BIT(0),
2588 .hw.init = &(struct clk_init_data){
2589 .name = "gcc_sdcc4_ahb_clk",
2590 .ops = &clk_branch2_ops,
2595 static struct clk_branch gcc_sdcc4_apps_clk = {
2596 .halt_reg = 0x16004,
2597 .halt_check = BRANCH_HALT,
2599 .enable_reg = 0x16004,
2600 .enable_mask = BIT(0),
2601 .hw.init = &(struct clk_init_data){
2602 .name = "gcc_sdcc4_apps_clk",
2603 .parent_hws = (const struct clk_hw*[]){
2604 &gcc_sdcc4_apps_clk_src.clkr.hw,
2607 .flags = CLK_SET_RATE_PARENT,
2608 .ops = &clk_branch2_ops,
2614 * The source clock frequencies are different for SDM670; define a child clock
2615 * pointing to the source clock that uses SDM670 frequencies.
2617 static struct clk_branch gcc_sdm670_sdcc4_apps_clk = {
2618 .halt_reg = 0x16004,
2619 .halt_check = BRANCH_HALT,
2621 .enable_reg = 0x16004,
2622 .enable_mask = BIT(0),
2623 .hw.init = &(struct clk_init_data){
2624 .name = "gcc_sdcc4_apps_clk",
2625 .parent_hws = (const struct clk_hw*[]){
2626 &gcc_sdm670_sdcc4_apps_clk_src.clkr.hw,
2629 .flags = CLK_SET_RATE_PARENT,
2630 .ops = &clk_branch2_ops,
2635 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
2637 .halt_check = BRANCH_HALT_VOTED,
2639 .enable_reg = 0x52004,
2640 .enable_mask = BIT(0),
2641 .hw.init = &(struct clk_init_data){
2642 .name = "gcc_sys_noc_cpuss_ahb_clk",
2643 .parent_hws = (const struct clk_hw*[]){
2644 &gcc_cpuss_ahb_clk_src.clkr.hw,
2647 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2648 .ops = &clk_branch2_ops,
2653 static struct clk_branch gcc_tsif_ahb_clk = {
2654 .halt_reg = 0x36004,
2655 .halt_check = BRANCH_HALT,
2657 .enable_reg = 0x36004,
2658 .enable_mask = BIT(0),
2659 .hw.init = &(struct clk_init_data){
2660 .name = "gcc_tsif_ahb_clk",
2661 .ops = &clk_branch2_ops,
2666 static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2667 .halt_reg = 0x3600c,
2668 .halt_check = BRANCH_HALT,
2670 .enable_reg = 0x3600c,
2671 .enable_mask = BIT(0),
2672 .hw.init = &(struct clk_init_data){
2673 .name = "gcc_tsif_inactivity_timers_clk",
2674 .ops = &clk_branch2_ops,
2679 static struct clk_branch gcc_tsif_ref_clk = {
2680 .halt_reg = 0x36008,
2681 .halt_check = BRANCH_HALT,
2683 .enable_reg = 0x36008,
2684 .enable_mask = BIT(0),
2685 .hw.init = &(struct clk_init_data){
2686 .name = "gcc_tsif_ref_clk",
2687 .parent_hws = (const struct clk_hw*[]){
2688 &gcc_tsif_ref_clk_src.clkr.hw,
2691 .flags = CLK_SET_RATE_PARENT,
2692 .ops = &clk_branch2_ops,
2697 static struct clk_branch gcc_ufs_card_ahb_clk = {
2698 .halt_reg = 0x75010,
2699 .halt_check = BRANCH_HALT,
2700 .hwcg_reg = 0x75010,
2703 .enable_reg = 0x75010,
2704 .enable_mask = BIT(0),
2705 .hw.init = &(struct clk_init_data){
2706 .name = "gcc_ufs_card_ahb_clk",
2707 .ops = &clk_branch2_ops,
2712 static struct clk_branch gcc_ufs_card_axi_clk = {
2713 .halt_reg = 0x7500c,
2714 .halt_check = BRANCH_HALT,
2715 .hwcg_reg = 0x7500c,
2718 .enable_reg = 0x7500c,
2719 .enable_mask = BIT(0),
2720 .hw.init = &(struct clk_init_data){
2721 .name = "gcc_ufs_card_axi_clk",
2722 .parent_hws = (const struct clk_hw*[]){
2723 &gcc_ufs_card_axi_clk_src.clkr.hw,
2726 .flags = CLK_SET_RATE_PARENT,
2727 .ops = &clk_branch2_ops,
2732 static struct clk_branch gcc_ufs_card_clkref_clk = {
2733 .halt_reg = 0x8c004,
2734 .halt_check = BRANCH_HALT,
2736 .enable_reg = 0x8c004,
2737 .enable_mask = BIT(0),
2738 .hw.init = &(struct clk_init_data){
2739 .name = "gcc_ufs_card_clkref_clk",
2740 .ops = &clk_branch2_ops,
2745 static struct clk_branch gcc_ufs_card_ice_core_clk = {
2746 .halt_reg = 0x75058,
2747 .halt_check = BRANCH_HALT,
2748 .hwcg_reg = 0x75058,
2751 .enable_reg = 0x75058,
2752 .enable_mask = BIT(0),
2753 .hw.init = &(struct clk_init_data){
2754 .name = "gcc_ufs_card_ice_core_clk",
2755 .parent_hws = (const struct clk_hw*[]){
2756 &gcc_ufs_card_ice_core_clk_src.clkr.hw,
2759 .flags = CLK_SET_RATE_PARENT,
2760 .ops = &clk_branch2_ops,
2765 static struct clk_branch gcc_ufs_card_phy_aux_clk = {
2766 .halt_reg = 0x7508c,
2767 .halt_check = BRANCH_HALT,
2768 .hwcg_reg = 0x7508c,
2771 .enable_reg = 0x7508c,
2772 .enable_mask = BIT(0),
2773 .hw.init = &(struct clk_init_data){
2774 .name = "gcc_ufs_card_phy_aux_clk",
2775 .parent_hws = (const struct clk_hw*[]){
2776 &gcc_ufs_card_phy_aux_clk_src.clkr.hw,
2779 .flags = CLK_SET_RATE_PARENT,
2780 .ops = &clk_branch2_ops,
2785 static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
2786 .halt_check = BRANCH_HALT_SKIP,
2788 .enable_reg = 0x75018,
2789 .enable_mask = BIT(0),
2790 .hw.init = &(struct clk_init_data){
2791 .name = "gcc_ufs_card_rx_symbol_0_clk",
2792 .ops = &clk_branch2_ops,
2797 static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
2798 .halt_check = BRANCH_HALT_SKIP,
2800 .enable_reg = 0x750a8,
2801 .enable_mask = BIT(0),
2802 .hw.init = &(struct clk_init_data){
2803 .name = "gcc_ufs_card_rx_symbol_1_clk",
2804 .ops = &clk_branch2_ops,
2809 static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
2810 .halt_check = BRANCH_HALT_SKIP,
2812 .enable_reg = 0x75014,
2813 .enable_mask = BIT(0),
2814 .hw.init = &(struct clk_init_data){
2815 .name = "gcc_ufs_card_tx_symbol_0_clk",
2816 .ops = &clk_branch2_ops,
2821 static struct clk_branch gcc_ufs_card_unipro_core_clk = {
2822 .halt_reg = 0x75054,
2823 .halt_check = BRANCH_HALT,
2824 .hwcg_reg = 0x75054,
2827 .enable_reg = 0x75054,
2828 .enable_mask = BIT(0),
2829 .hw.init = &(struct clk_init_data){
2830 .name = "gcc_ufs_card_unipro_core_clk",
2831 .parent_hws = (const struct clk_hw*[]){
2832 &gcc_ufs_card_unipro_core_clk_src.clkr.hw,
2835 .flags = CLK_SET_RATE_PARENT,
2836 .ops = &clk_branch2_ops,
2841 static struct clk_branch gcc_ufs_mem_clkref_clk = {
2842 .halt_reg = 0x8c000,
2843 .halt_check = BRANCH_HALT,
2845 .enable_reg = 0x8c000,
2846 .enable_mask = BIT(0),
2847 .hw.init = &(struct clk_init_data){
2848 .name = "gcc_ufs_mem_clkref_clk",
2849 .ops = &clk_branch2_ops,
2854 static struct clk_branch gcc_ufs_phy_ahb_clk = {
2855 .halt_reg = 0x77010,
2856 .halt_check = BRANCH_HALT,
2857 .hwcg_reg = 0x77010,
2860 .enable_reg = 0x77010,
2861 .enable_mask = BIT(0),
2862 .hw.init = &(struct clk_init_data){
2863 .name = "gcc_ufs_phy_ahb_clk",
2864 .ops = &clk_branch2_ops,
2869 static struct clk_branch gcc_ufs_phy_axi_clk = {
2870 .halt_reg = 0x7700c,
2871 .halt_check = BRANCH_HALT,
2872 .hwcg_reg = 0x7700c,
2875 .enable_reg = 0x7700c,
2876 .enable_mask = BIT(0),
2877 .hw.init = &(struct clk_init_data){
2878 .name = "gcc_ufs_phy_axi_clk",
2879 .parent_hws = (const struct clk_hw*[]){
2880 &gcc_ufs_phy_axi_clk_src.clkr.hw,
2883 .flags = CLK_SET_RATE_PARENT,
2884 .ops = &clk_branch2_ops,
2889 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2890 .halt_reg = 0x77058,
2891 .halt_check = BRANCH_HALT,
2892 .hwcg_reg = 0x77058,
2895 .enable_reg = 0x77058,
2896 .enable_mask = BIT(0),
2897 .hw.init = &(struct clk_init_data){
2898 .name = "gcc_ufs_phy_ice_core_clk",
2899 .parent_hws = (const struct clk_hw*[]){
2900 &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2903 .flags = CLK_SET_RATE_PARENT,
2904 .ops = &clk_branch2_ops,
2909 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2910 .halt_reg = 0x7708c,
2911 .halt_check = BRANCH_HALT,
2912 .hwcg_reg = 0x7708c,
2915 .enable_reg = 0x7708c,
2916 .enable_mask = BIT(0),
2917 .hw.init = &(struct clk_init_data){
2918 .name = "gcc_ufs_phy_phy_aux_clk",
2919 .parent_hws = (const struct clk_hw*[]){
2920 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2923 .flags = CLK_SET_RATE_PARENT,
2924 .ops = &clk_branch2_ops,
2929 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
2930 .halt_check = BRANCH_HALT_SKIP,
2932 .enable_reg = 0x77018,
2933 .enable_mask = BIT(0),
2934 .hw.init = &(struct clk_init_data){
2935 .name = "gcc_ufs_phy_rx_symbol_0_clk",
2936 .ops = &clk_branch2_ops,
2941 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
2942 .halt_check = BRANCH_HALT_SKIP,
2944 .enable_reg = 0x770a8,
2945 .enable_mask = BIT(0),
2946 .hw.init = &(struct clk_init_data){
2947 .name = "gcc_ufs_phy_rx_symbol_1_clk",
2948 .ops = &clk_branch2_ops,
2953 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
2954 .halt_check = BRANCH_HALT_SKIP,
2956 .enable_reg = 0x77014,
2957 .enable_mask = BIT(0),
2958 .hw.init = &(struct clk_init_data){
2959 .name = "gcc_ufs_phy_tx_symbol_0_clk",
2960 .ops = &clk_branch2_ops,
2965 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2966 .halt_reg = 0x77054,
2967 .halt_check = BRANCH_HALT,
2968 .hwcg_reg = 0x77054,
2971 .enable_reg = 0x77054,
2972 .enable_mask = BIT(0),
2973 .hw.init = &(struct clk_init_data){
2974 .name = "gcc_ufs_phy_unipro_core_clk",
2975 .parent_hws = (const struct clk_hw*[]){
2976 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2979 .flags = CLK_SET_RATE_PARENT,
2980 .ops = &clk_branch2_ops,
2985 static struct clk_branch gcc_usb30_prim_master_clk = {
2987 .halt_check = BRANCH_HALT,
2989 .enable_reg = 0xf00c,
2990 .enable_mask = BIT(0),
2991 .hw.init = &(struct clk_init_data){
2992 .name = "gcc_usb30_prim_master_clk",
2993 .parent_hws = (const struct clk_hw*[]){
2994 &gcc_usb30_prim_master_clk_src.clkr.hw,
2997 .flags = CLK_SET_RATE_PARENT,
2998 .ops = &clk_branch2_ops,
3003 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
3005 .halt_check = BRANCH_HALT,
3007 .enable_reg = 0xf014,
3008 .enable_mask = BIT(0),
3009 .hw.init = &(struct clk_init_data){
3010 .name = "gcc_usb30_prim_mock_utmi_clk",
3011 .parent_hws = (const struct clk_hw*[]){
3012 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
3015 .flags = CLK_SET_RATE_PARENT,
3016 .ops = &clk_branch2_ops,
3021 static struct clk_branch gcc_usb30_prim_sleep_clk = {
3023 .halt_check = BRANCH_HALT,
3025 .enable_reg = 0xf010,
3026 .enable_mask = BIT(0),
3027 .hw.init = &(struct clk_init_data){
3028 .name = "gcc_usb30_prim_sleep_clk",
3029 .ops = &clk_branch2_ops,
3034 static struct clk_branch gcc_usb30_sec_master_clk = {
3035 .halt_reg = 0x1000c,
3036 .halt_check = BRANCH_HALT,
3038 .enable_reg = 0x1000c,
3039 .enable_mask = BIT(0),
3040 .hw.init = &(struct clk_init_data){
3041 .name = "gcc_usb30_sec_master_clk",
3042 .parent_hws = (const struct clk_hw*[]){
3043 &gcc_usb30_sec_master_clk_src.clkr.hw,
3046 .flags = CLK_SET_RATE_PARENT,
3047 .ops = &clk_branch2_ops,
3052 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
3053 .halt_reg = 0x10014,
3054 .halt_check = BRANCH_HALT,
3056 .enable_reg = 0x10014,
3057 .enable_mask = BIT(0),
3058 .hw.init = &(struct clk_init_data){
3059 .name = "gcc_usb30_sec_mock_utmi_clk",
3060 .parent_hws = (const struct clk_hw*[]){
3061 &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
3064 .flags = CLK_SET_RATE_PARENT,
3065 .ops = &clk_branch2_ops,
3070 static struct clk_branch gcc_usb30_sec_sleep_clk = {
3071 .halt_reg = 0x10010,
3072 .halt_check = BRANCH_HALT,
3074 .enable_reg = 0x10010,
3075 .enable_mask = BIT(0),
3076 .hw.init = &(struct clk_init_data){
3077 .name = "gcc_usb30_sec_sleep_clk",
3078 .ops = &clk_branch2_ops,
3083 static struct clk_branch gcc_usb3_prim_clkref_clk = {
3084 .halt_reg = 0x8c008,
3085 .halt_check = BRANCH_HALT,
3087 .enable_reg = 0x8c008,
3088 .enable_mask = BIT(0),
3089 .hw.init = &(struct clk_init_data){
3090 .name = "gcc_usb3_prim_clkref_clk",
3091 .ops = &clk_branch2_ops,
3096 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
3098 .halt_check = BRANCH_HALT,
3100 .enable_reg = 0xf04c,
3101 .enable_mask = BIT(0),
3102 .hw.init = &(struct clk_init_data){
3103 .name = "gcc_usb3_prim_phy_aux_clk",
3104 .parent_hws = (const struct clk_hw*[]){
3105 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
3108 .flags = CLK_SET_RATE_PARENT,
3109 .ops = &clk_branch2_ops,
3114 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
3116 .halt_check = BRANCH_HALT,
3118 .enable_reg = 0xf050,
3119 .enable_mask = BIT(0),
3120 .hw.init = &(struct clk_init_data){
3121 .name = "gcc_usb3_prim_phy_com_aux_clk",
3122 .parent_hws = (const struct clk_hw*[]){
3123 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
3126 .flags = CLK_SET_RATE_PARENT,
3127 .ops = &clk_branch2_ops,
3132 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
3133 .halt_check = BRANCH_HALT_SKIP,
3135 .enable_reg = 0xf054,
3136 .enable_mask = BIT(0),
3137 .hw.init = &(struct clk_init_data){
3138 .name = "gcc_usb3_prim_phy_pipe_clk",
3139 .ops = &clk_branch2_ops,
3144 static struct clk_branch gcc_usb3_sec_clkref_clk = {
3145 .halt_reg = 0x8c028,
3146 .halt_check = BRANCH_HALT,
3148 .enable_reg = 0x8c028,
3149 .enable_mask = BIT(0),
3150 .hw.init = &(struct clk_init_data){
3151 .name = "gcc_usb3_sec_clkref_clk",
3152 .ops = &clk_branch2_ops,
3157 static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
3158 .halt_reg = 0x1004c,
3159 .halt_check = BRANCH_HALT,
3161 .enable_reg = 0x1004c,
3162 .enable_mask = BIT(0),
3163 .hw.init = &(struct clk_init_data){
3164 .name = "gcc_usb3_sec_phy_aux_clk",
3165 .parent_hws = (const struct clk_hw*[]){
3166 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
3169 .flags = CLK_SET_RATE_PARENT,
3170 .ops = &clk_branch2_ops,
3175 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
3176 .halt_reg = 0x10050,
3177 .halt_check = BRANCH_HALT,
3179 .enable_reg = 0x10050,
3180 .enable_mask = BIT(0),
3181 .hw.init = &(struct clk_init_data){
3182 .name = "gcc_usb3_sec_phy_com_aux_clk",
3183 .parent_hws = (const struct clk_hw*[]){
3184 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
3187 .flags = CLK_SET_RATE_PARENT,
3188 .ops = &clk_branch2_ops,
3193 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
3194 .halt_check = BRANCH_HALT_SKIP,
3196 .enable_reg = 0x10054,
3197 .enable_mask = BIT(0),
3198 .hw.init = &(struct clk_init_data){
3199 .name = "gcc_usb3_sec_phy_pipe_clk",
3200 .ops = &clk_branch2_ops,
3205 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
3206 .halt_reg = 0x6a004,
3207 .halt_check = BRANCH_HALT,
3208 .hwcg_reg = 0x6a004,
3211 .enable_reg = 0x6a004,
3212 .enable_mask = BIT(0),
3213 .hw.init = &(struct clk_init_data){
3214 .name = "gcc_usb_phy_cfg_ahb2phy_clk",
3215 .ops = &clk_branch2_ops,
3220 static struct clk_branch gcc_vdda_vs_clk = {
3221 .halt_reg = 0x7a00c,
3222 .halt_check = BRANCH_HALT,
3224 .enable_reg = 0x7a00c,
3225 .enable_mask = BIT(0),
3226 .hw.init = &(struct clk_init_data){
3227 .name = "gcc_vdda_vs_clk",
3228 .parent_hws = (const struct clk_hw*[]){
3229 &gcc_vsensor_clk_src.clkr.hw,
3232 .flags = CLK_SET_RATE_PARENT,
3233 .ops = &clk_branch2_ops,
3238 static struct clk_branch gcc_vddcx_vs_clk = {
3239 .halt_reg = 0x7a004,
3240 .halt_check = BRANCH_HALT,
3242 .enable_reg = 0x7a004,
3243 .enable_mask = BIT(0),
3244 .hw.init = &(struct clk_init_data){
3245 .name = "gcc_vddcx_vs_clk",
3246 .parent_hws = (const struct clk_hw*[]){
3247 &gcc_vsensor_clk_src.clkr.hw,
3250 .flags = CLK_SET_RATE_PARENT,
3251 .ops = &clk_branch2_ops,
3256 static struct clk_branch gcc_vddmx_vs_clk = {
3257 .halt_reg = 0x7a008,
3258 .halt_check = BRANCH_HALT,
3260 .enable_reg = 0x7a008,
3261 .enable_mask = BIT(0),
3262 .hw.init = &(struct clk_init_data){
3263 .name = "gcc_vddmx_vs_clk",
3264 .parent_hws = (const struct clk_hw*[]){
3265 &gcc_vsensor_clk_src.clkr.hw,
3268 .flags = CLK_SET_RATE_PARENT,
3269 .ops = &clk_branch2_ops,
3274 static struct clk_branch gcc_video_ahb_clk = {
3276 .halt_check = BRANCH_HALT,
3280 .enable_reg = 0xb004,
3281 .enable_mask = BIT(0),
3282 .hw.init = &(struct clk_init_data){
3283 .name = "gcc_video_ahb_clk",
3284 .flags = CLK_IS_CRITICAL,
3285 .ops = &clk_branch2_ops,
3290 static struct clk_branch gcc_video_axi_clk = {
3292 .halt_check = BRANCH_VOTED,
3294 .enable_reg = 0xb01c,
3295 .enable_mask = BIT(0),
3296 .hw.init = &(struct clk_init_data){
3297 .name = "gcc_video_axi_clk",
3298 .ops = &clk_branch2_ops,
3303 static struct clk_branch gcc_video_xo_clk = {
3305 .halt_check = BRANCH_HALT,
3307 .enable_reg = 0xb028,
3308 .enable_mask = BIT(0),
3309 .hw.init = &(struct clk_init_data){
3310 .name = "gcc_video_xo_clk",
3311 .flags = CLK_IS_CRITICAL,
3312 .ops = &clk_branch2_ops,
3317 static struct clk_branch gcc_vs_ctrl_ahb_clk = {
3318 .halt_reg = 0x7a014,
3319 .halt_check = BRANCH_HALT,
3320 .hwcg_reg = 0x7a014,
3323 .enable_reg = 0x7a014,
3324 .enable_mask = BIT(0),
3325 .hw.init = &(struct clk_init_data){
3326 .name = "gcc_vs_ctrl_ahb_clk",
3327 .ops = &clk_branch2_ops,
3332 static struct clk_branch gcc_vs_ctrl_clk = {
3333 .halt_reg = 0x7a010,
3334 .halt_check = BRANCH_HALT,
3336 .enable_reg = 0x7a010,
3337 .enable_mask = BIT(0),
3338 .hw.init = &(struct clk_init_data){
3339 .name = "gcc_vs_ctrl_clk",
3340 .parent_hws = (const struct clk_hw*[]){
3341 &gcc_vs_ctrl_clk_src.clkr.hw,
3344 .flags = CLK_SET_RATE_PARENT,
3345 .ops = &clk_branch2_ops,
3350 static struct clk_branch gcc_cpuss_dvm_bus_clk = {
3351 .halt_reg = 0x48190,
3352 .halt_check = BRANCH_HALT,
3354 .enable_reg = 0x48190,
3355 .enable_mask = BIT(0),
3356 .hw.init = &(struct clk_init_data){
3357 .name = "gcc_cpuss_dvm_bus_clk",
3358 .flags = CLK_IS_CRITICAL,
3359 .ops = &clk_branch2_ops,
3364 static struct clk_branch gcc_cpuss_gnoc_clk = {
3365 .halt_reg = 0x48004,
3366 .halt_check = BRANCH_HALT_VOTED,
3367 .hwcg_reg = 0x48004,
3370 .enable_reg = 0x52004,
3371 .enable_mask = BIT(22),
3372 .hw.init = &(struct clk_init_data){
3373 .name = "gcc_cpuss_gnoc_clk",
3374 .flags = CLK_IS_CRITICAL,
3375 .ops = &clk_branch2_ops,
3380 /* TODO: Remove after DTS updated to protect these */
3381 #ifdef CONFIG_SDM_LPASSCC_845
3382 static struct clk_branch gcc_lpass_q6_axi_clk = {
3383 .halt_reg = 0x47000,
3384 .halt_check = BRANCH_HALT,
3386 .enable_reg = 0x47000,
3387 .enable_mask = BIT(0),
3388 .hw.init = &(struct clk_init_data){
3389 .name = "gcc_lpass_q6_axi_clk",
3390 .flags = CLK_IS_CRITICAL,
3391 .ops = &clk_branch2_ops,
3396 static struct clk_branch gcc_lpass_sway_clk = {
3397 .halt_reg = 0x47008,
3398 .halt_check = BRANCH_HALT,
3400 .enable_reg = 0x47008,
3401 .enable_mask = BIT(0),
3402 .hw.init = &(struct clk_init_data){
3403 .name = "gcc_lpass_sway_clk",
3404 .flags = CLK_IS_CRITICAL,
3405 .ops = &clk_branch2_ops,
3411 static struct gdsc pcie_0_gdsc = {
3414 .name = "pcie_0_gdsc",
3416 .pwrsts = PWRSTS_OFF_ON,
3417 .flags = POLL_CFG_GDSCR,
3420 static struct gdsc pcie_1_gdsc = {
3423 .name = "pcie_1_gdsc",
3425 .pwrsts = PWRSTS_OFF_ON,
3426 .flags = POLL_CFG_GDSCR,
3429 static struct gdsc ufs_card_gdsc = {
3432 .name = "ufs_card_gdsc",
3434 .pwrsts = PWRSTS_OFF_ON,
3435 .flags = POLL_CFG_GDSCR,
3438 static struct gdsc ufs_phy_gdsc = {
3441 .name = "ufs_phy_gdsc",
3443 .pwrsts = PWRSTS_OFF_ON,
3444 .flags = POLL_CFG_GDSCR,
3447 static struct gdsc usb30_prim_gdsc = {
3450 .name = "usb30_prim_gdsc",
3452 .pwrsts = PWRSTS_OFF_ON,
3453 .flags = POLL_CFG_GDSCR,
3456 static struct gdsc usb30_sec_gdsc = {
3459 .name = "usb30_sec_gdsc",
3461 .pwrsts = PWRSTS_OFF_ON,
3462 .flags = POLL_CFG_GDSCR,
3465 static struct gdsc hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc = {
3468 .name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc",
3470 .pwrsts = PWRSTS_OFF_ON,
3474 static struct gdsc hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc = {
3477 .name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc",
3479 .pwrsts = PWRSTS_OFF_ON,
3483 static struct gdsc hlos1_vote_aggre_noc_mmu_tbu1_gdsc = {
3486 .name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc",
3488 .pwrsts = PWRSTS_OFF_ON,
3492 static struct gdsc hlos1_vote_aggre_noc_mmu_tbu2_gdsc = {
3495 .name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc",
3497 .pwrsts = PWRSTS_OFF_ON,
3501 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
3504 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
3506 .pwrsts = PWRSTS_OFF_ON,
3510 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
3513 .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
3515 .pwrsts = PWRSTS_OFF_ON,
3519 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = {
3522 .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc",
3524 .pwrsts = PWRSTS_OFF_ON,
3528 static struct clk_regmap *gcc_sdm670_clocks[] = {
3529 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3530 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3531 [GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr,
3532 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3533 [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
3534 [GCC_CAMERA_AXI_CLK] = &gcc_camera_axi_clk.clkr,
3535 [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
3536 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
3537 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
3538 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
3539 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3540 [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
3541 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
3542 [GCC_CPUSS_RBCPR_CLK] = &gcc_sdm670_cpuss_rbcpr_clk.clkr,
3543 [GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_sdm670_cpuss_rbcpr_clk_src.clkr,
3544 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3545 [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
3546 [GCC_DISP_AXI_CLK] = &gcc_disp_axi_clk.clkr,
3547 [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
3548 [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
3549 [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
3550 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3551 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3552 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3553 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3554 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3555 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3556 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
3557 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3558 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3559 [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
3560 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3561 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3562 [GCC_GPU_VS_CLK] = &gcc_gpu_vs_clk.clkr,
3563 [GCC_MSS_AXIS2_CLK] = &gcc_mss_axis2_clk.clkr,
3564 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3565 [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr,
3566 [GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr,
3567 [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
3568 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
3569 [GCC_MSS_VS_CLK] = &gcc_mss_vs_clk.clkr,
3570 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3571 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3572 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3573 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3574 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3575 [GCC_QMIP_CAMERA_AHB_CLK] = &gcc_qmip_camera_ahb_clk.clkr,
3576 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3577 [GCC_QMIP_VIDEO_AHB_CLK] = &gcc_qmip_video_ahb_clk.clkr,
3578 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3579 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3580 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3581 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3582 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3583 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3584 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3585 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3586 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3587 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3588 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3589 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3590 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3591 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3592 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3593 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3594 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3595 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3596 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3597 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3598 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3599 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3600 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3601 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3602 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3603 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3604 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3605 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3606 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
3607 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
3608 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
3609 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
3610 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3611 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3612 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3613 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3614 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3615 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3616 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
3617 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
3618 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3619 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3620 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3621 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3622 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3623 [GCC_SDCC4_APPS_CLK] = &gcc_sdm670_sdcc4_apps_clk.clkr,
3624 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdm670_sdcc4_apps_clk_src.clkr,
3625 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
3626 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3627 [GCC_TSIF_INACTIVITY_TIMERS_CLK] =
3628 &gcc_tsif_inactivity_timers_clk.clkr,
3629 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3630 [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
3631 [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
3632 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3633 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3634 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3635 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3636 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3637 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3638 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3639 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3640 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3641 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3642 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
3643 &gcc_ufs_phy_unipro_core_clk_src.clkr,
3644 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3645 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3646 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3647 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
3648 &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3649 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3650 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
3651 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3652 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3653 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3654 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3655 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
3656 [GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr,
3657 [GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr,
3658 [GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr,
3659 [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
3660 [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
3661 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
3662 [GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr,
3663 [GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr,
3664 [GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr,
3665 [GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr,
3666 [GPLL0] = &gpll0.clkr,
3667 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
3668 [GPLL4] = &gpll4.clkr,
3669 [GPLL6] = &gpll6.clkr,
3670 [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
3671 [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
3672 [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
3673 [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
3674 [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
3677 static struct clk_regmap *gcc_sdm845_clocks[] = {
3678 [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
3679 [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
3680 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3681 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3682 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
3683 [GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr,
3684 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3685 [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
3686 [GCC_CAMERA_AXI_CLK] = &gcc_camera_axi_clk.clkr,
3687 [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
3688 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
3689 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
3690 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
3691 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3692 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
3693 [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
3694 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
3695 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
3696 [GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_cpuss_rbcpr_clk_src.clkr,
3697 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3698 [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
3699 [GCC_DISP_AXI_CLK] = &gcc_disp_axi_clk.clkr,
3700 [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
3701 [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
3702 [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
3703 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3704 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3705 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3706 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3707 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3708 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3709 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
3710 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3711 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3712 [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
3713 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3714 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3715 [GCC_GPU_VS_CLK] = &gcc_gpu_vs_clk.clkr,
3716 [GCC_MSS_AXIS2_CLK] = &gcc_mss_axis2_clk.clkr,
3717 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3718 [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr,
3719 [GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr,
3720 [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
3721 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
3722 [GCC_MSS_VS_CLK] = &gcc_mss_vs_clk.clkr,
3723 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3724 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
3725 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3726 [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
3727 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3728 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3729 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3730 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3731 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3732 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
3733 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3734 [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr,
3735 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3736 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3737 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3738 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
3739 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
3740 [GCC_PCIE_PHY_REFGEN_CLK] = &gcc_pcie_phy_refgen_clk.clkr,
3741 [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,
3742 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3743 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3744 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3745 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3746 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3747 [GCC_QMIP_CAMERA_AHB_CLK] = &gcc_qmip_camera_ahb_clk.clkr,
3748 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3749 [GCC_QMIP_VIDEO_AHB_CLK] = &gcc_qmip_video_ahb_clk.clkr,
3750 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3751 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3752 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3753 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3754 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3755 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3756 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3757 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3758 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3759 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3760 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3761 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3762 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3763 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3764 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3765 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3766 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3767 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3768 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3769 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3770 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3771 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3772 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3773 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3774 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3775 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3776 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3777 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3778 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
3779 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
3780 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
3781 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
3782 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3783 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3784 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3785 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3786 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3787 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3788 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3789 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3790 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3791 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3792 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
3793 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3794 [GCC_TSIF_INACTIVITY_TIMERS_CLK] =
3795 &gcc_tsif_inactivity_timers_clk.clkr,
3796 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3797 [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
3798 [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
3799 [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
3800 [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
3801 [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr,
3802 [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
3803 [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
3804 [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
3805 [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
3806 [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
3807 [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
3808 [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
3809 [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
3810 [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] =
3811 &gcc_ufs_card_unipro_core_clk_src.clkr,
3812 [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
3813 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3814 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3815 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3816 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3817 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3818 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3819 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3820 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3821 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
3822 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3823 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3824 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
3825 &gcc_ufs_phy_unipro_core_clk_src.clkr,
3826 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3827 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3828 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3829 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
3830 &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3831 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3832 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
3833 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
3834 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
3835 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =
3836 &gcc_usb30_sec_mock_utmi_clk_src.clkr,
3837 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
3838 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
3839 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3840 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3841 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3842 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3843 [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,
3844 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
3845 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
3846 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
3847 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
3848 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
3849 [GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr,
3850 [GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr,
3851 [GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr,
3852 [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
3853 [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
3854 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
3855 [GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr,
3856 [GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr,
3857 [GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr,
3858 [GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr,
3859 [GPLL0] = &gpll0.clkr,
3860 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
3861 [GPLL4] = &gpll4.clkr,
3862 [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
3863 [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
3864 [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
3865 [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
3866 [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
3867 #ifdef CONFIG_SDM_LPASSCC_845
3868 [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
3869 [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,
3873 static const struct qcom_reset_map gcc_sdm845_resets[] = {
3874 [GCC_MMSS_BCR] = { 0xb000 },
3875 [GCC_PCIE_0_BCR] = { 0x6b000 },
3876 [GCC_PCIE_1_BCR] = { 0x8d000 },
3877 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3878 [GCC_PDM_BCR] = { 0x33000 },
3879 [GCC_PRNG_BCR] = { 0x34000 },
3880 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
3881 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3882 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3883 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3884 [GCC_SDCC2_BCR] = { 0x14000 },
3885 [GCC_SDCC4_BCR] = { 0x16000 },
3886 [GCC_TSIF_BCR] = { 0x36000 },
3887 [GCC_UFS_CARD_BCR] = { 0x75000 },
3888 [GCC_UFS_PHY_BCR] = { 0x77000 },
3889 [GCC_USB30_PRIM_BCR] = { 0xf000 },
3890 [GCC_USB30_SEC_BCR] = { 0x10000 },
3891 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3892 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3893 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3894 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3895 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3896 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
3897 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3898 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3899 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3902 static struct gdsc *gcc_sdm670_gdscs[] = {
3903 [UFS_PHY_GDSC] = &ufs_phy_gdsc,
3904 [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
3905 [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] =
3906 &hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc,
3907 [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] =
3908 &hlos1_vote_aggre_noc_mmu_tbu1_gdsc,
3909 [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] =
3910 &hlos1_vote_aggre_noc_mmu_tbu2_gdsc,
3911 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =
3912 &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
3913 [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] =
3914 &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
3915 [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc,
3918 static struct gdsc *gcc_sdm845_gdscs[] = {
3919 [PCIE_0_GDSC] = &pcie_0_gdsc,
3920 [PCIE_1_GDSC] = &pcie_1_gdsc,
3921 [UFS_CARD_GDSC] = &ufs_card_gdsc,
3922 [UFS_PHY_GDSC] = &ufs_phy_gdsc,
3923 [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
3924 [USB30_SEC_GDSC] = &usb30_sec_gdsc,
3925 [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] =
3926 &hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc,
3927 [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] =
3928 &hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc,
3929 [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] =
3930 &hlos1_vote_aggre_noc_mmu_tbu1_gdsc,
3931 [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] =
3932 &hlos1_vote_aggre_noc_mmu_tbu2_gdsc,
3933 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =
3934 &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
3935 [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] =
3936 &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
3937 [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc,
3940 static const struct regmap_config gcc_sdm845_regmap_config = {
3944 .max_register = 0x182090,
3948 static const struct qcom_cc_desc gcc_sdm670_desc = {
3949 .config = &gcc_sdm845_regmap_config,
3950 .clks = gcc_sdm670_clocks,
3951 .num_clks = ARRAY_SIZE(gcc_sdm670_clocks),
3952 /* Snapdragon 670 can function without its own exclusive resets. */
3953 .resets = gcc_sdm845_resets,
3954 .num_resets = ARRAY_SIZE(gcc_sdm845_resets),
3955 .gdscs = gcc_sdm670_gdscs,
3956 .num_gdscs = ARRAY_SIZE(gcc_sdm670_gdscs),
3959 static const struct qcom_cc_desc gcc_sdm845_desc = {
3960 .config = &gcc_sdm845_regmap_config,
3961 .clks = gcc_sdm845_clocks,
3962 .num_clks = ARRAY_SIZE(gcc_sdm845_clocks),
3963 .resets = gcc_sdm845_resets,
3964 .num_resets = ARRAY_SIZE(gcc_sdm845_resets),
3965 .gdscs = gcc_sdm845_gdscs,
3966 .num_gdscs = ARRAY_SIZE(gcc_sdm845_gdscs),
3969 static const struct of_device_id gcc_sdm845_match_table[] = {
3970 { .compatible = "qcom,gcc-sdm670", .data = &gcc_sdm670_desc },
3971 { .compatible = "qcom,gcc-sdm845", .data = &gcc_sdm845_desc },
3974 MODULE_DEVICE_TABLE(of, gcc_sdm845_match_table);
3976 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
3977 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
3978 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
3979 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
3980 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
3981 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
3982 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
3983 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
3984 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
3985 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
3986 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
3987 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
3988 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
3989 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
3990 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
3991 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
3992 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
3995 static int gcc_sdm845_probe(struct platform_device *pdev)
3997 const struct qcom_cc_desc *gcc_desc;
3998 struct regmap *regmap;
4001 regmap = qcom_cc_map(pdev, &gcc_sdm845_desc);
4003 return PTR_ERR(regmap);
4005 /* Disable the GPLL0 active input to MMSS and GPU via MISC registers */
4006 regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
4007 regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
4009 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
4010 ARRAY_SIZE(gcc_dfs_clocks));
4014 gcc_desc = of_device_get_match_data(&pdev->dev);
4015 return qcom_cc_really_probe(pdev, gcc_desc, regmap);
4018 static struct platform_driver gcc_sdm845_driver = {
4019 .probe = gcc_sdm845_probe,
4021 .name = "gcc-sdm845",
4022 .of_match_table = gcc_sdm845_match_table,
4026 static int __init gcc_sdm845_init(void)
4028 return platform_driver_register(&gcc_sdm845_driver);
4030 core_initcall(gcc_sdm845_init);
4032 static void __exit gcc_sdm845_exit(void)
4034 platform_driver_unregister(&gcc_sdm845_driver);
4036 module_exit(gcc_sdm845_exit);
4038 MODULE_DESCRIPTION("QTI GCC SDM845 Driver");
4039 MODULE_LICENSE("GPL v2");
4040 MODULE_ALIAS("platform:gcc-sdm845");