drivers/clk/qcom/gcc-sdm845.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/bitops.h>
   8 #include <linux/err.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/of_device.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/regmap.h>
  15 #include <linux/reset-controller.h>
  16
  17 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
  18
  19 #include "common.h"
  20 #include "clk-regmap.h"
  21 #include "clk-pll.h"
  22 #include "clk-rcg.h"
  23 #include "clk-branch.h"
  24 #include "clk-alpha-pll.h"
  25 #include "gdsc.h"
  26 #include "reset.h"
  27
  28 enum {
  29         P_BI_TCXO,
  30         P_AUD_REF_CLK,
  31         P_GPLL0_OUT_EVEN,
  32         P_GPLL0_OUT_MAIN,
  33         P_GPLL4_OUT_MAIN,
  34         P_SLEEP_CLK,
  35 };
  36
  37 static struct clk_alpha_pll gpll0 = {
  38         .offset = 0x0,
  39         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  40         .clkr = {
  41                 .enable_reg = 0x52000,
  42                 .enable_mask = BIT(0),
  43                 .hw.init = &(struct clk_init_data){
  44                         .name = "gpll0",
  45                         .parent_data = &(const struct clk_parent_data){
  46                                 .fw_name = "bi_tcxo", .name = "bi_tcxo",
  47                         },
  48                         .num_parents = 1,
  49                         .ops = &clk_alpha_pll_fixed_fabia_ops,
  50                 },
  51         },
  52 };
  53
  54 static struct clk_alpha_pll gpll4 = {
  55         .offset = 0x76000,
  56         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  57         .clkr = {
  58                 .enable_reg = 0x52000,
  59                 .enable_mask = BIT(4),
  60                 .hw.init = &(struct clk_init_data){
  61                         .name = "gpll4",
  62                         .parent_data = &(const struct clk_parent_data){
  63                                 .fw_name = "bi_tcxo", .name = "bi_tcxo",
  64                         },
  65                         .num_parents = 1,
  66                         .ops = &clk_alpha_pll_fixed_fabia_ops,
  67                 },
  68         },
  69 };
  70
  71 static const struct clk_div_table post_div_table_fabia_even[] = {
  72         { 0x0, 1 },
  73         { 0x1, 2 },
  74         { 0x3, 4 },
  75         { 0x7, 8 },
  76         { }
  77 };
  78
  79 static struct clk_alpha_pll_postdiv gpll0_out_even = {
  80         .offset = 0x0,
  81         .post_div_shift = 8,
  82         .post_div_table = post_div_table_fabia_even,
  83         .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
  84         .width = 4,
  85         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  86         .clkr.hw.init = &(struct clk_init_data){
  87                 .name = "gpll0_out_even",
  88                 .parent_hws = (const struct clk_hw*[]){
  89                         &gpll0.clkr.hw,
  90                 },
  91                 .num_parents = 1,
  92                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
  93         },
  94 };
  95
  96 static const struct parent_map gcc_parent_map_0[] = {
  97         { P_BI_TCXO, 0 },
  98         { P_GPLL0_OUT_MAIN, 1 },
  99         { P_GPLL0_OUT_EVEN, 6 },
 100 };
 101
 102 static const struct clk_parent_data gcc_parent_data_0[] = {
 103         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 104         { .hw = &gpll0.clkr.hw },
 105         { .hw = &gpll0_out_even.clkr.hw },
 106 };
 107
 108 static const struct parent_map gcc_parent_map_1[] = {
 109         { P_BI_TCXO, 0 },
 110         { P_GPLL0_OUT_MAIN, 1 },
 111         { P_SLEEP_CLK, 5 },
 112         { P_GPLL0_OUT_EVEN, 6 },
 113 };
 114
 115 static const struct clk_parent_data gcc_parent_data_1[] = {
 116         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 117         { .hw = &gpll0.clkr.hw },
 118         { .fw_name = "sleep_clk", .name = "core_pi_sleep_clk" },
 119         { .hw = &gpll0_out_even.clkr.hw },
 120 };
 121
 122 static const struct parent_map gcc_parent_map_2[] = {
 123         { P_BI_TCXO, 0 },
 124         { P_SLEEP_CLK, 5 },
 125 };
 126
 127 static const struct clk_parent_data gcc_parent_data_2[] = {
 128         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 129         { .fw_name = "sleep_clk", .name = "core_pi_sleep_clk" },
 130 };
 131
 132 static const struct parent_map gcc_parent_map_3[] = {
 133         { P_BI_TCXO, 0 },
 134         { P_GPLL0_OUT_MAIN, 1 },
 135 };
 136
 137 static const struct clk_parent_data gcc_parent_data_3[] = {
 138         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 139         { .hw = &gpll0.clkr.hw },
 140 };
 141
 142 static const struct parent_map gcc_parent_map_4[] = {
 143         { P_BI_TCXO, 0 },
 144 };
 145
 146 static const struct clk_parent_data gcc_parent_data_4[] = {
 147         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 148 };
 149
 150 static const struct parent_map gcc_parent_map_6[] = {
 151         { P_BI_TCXO, 0 },
 152         { P_GPLL0_OUT_MAIN, 1 },
 153         { P_AUD_REF_CLK, 2 },
 154         { P_GPLL0_OUT_EVEN, 6 },
 155 };
 156
 157 static const struct clk_parent_data gcc_parent_data_6[] = {
 158         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 159         { .hw = &gpll0.clkr.hw },
 160         { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" },
 161         { .hw = &gpll0_out_even.clkr.hw },
 162 };
 163
 164 static const struct clk_parent_data gcc_parent_data_7_ao[] = {
 165         { .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" },
 166         { .hw = &gpll0.clkr.hw },
 167         { .hw = &gpll0_out_even.clkr.hw },
 168         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 169 };
 170
 171 static const struct clk_parent_data gcc_parent_data_8[] = {
 172         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 173         { .hw = &gpll0.clkr.hw },
 174         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 175 };
 176
 177 static const struct clk_parent_data gcc_parent_data_8_ao[] = {
 178         { .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" },
 179         { .hw = &gpll0.clkr.hw },
 180         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 181 };
 182
 183 static const struct parent_map gcc_parent_map_10[] = {
 184         { P_BI_TCXO, 0 },
 185         { P_GPLL0_OUT_MAIN, 1 },
 186         { P_GPLL4_OUT_MAIN, 5 },
 187         { P_GPLL0_OUT_EVEN, 6 },
 188 };
 189
 190 static const struct clk_parent_data gcc_parent_data_10[] = {
 191         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 192         { .hw = &gpll0.clkr.hw },
 193         { .hw = &gpll4.clkr.hw },
 194         { .hw = &gpll0_out_even.clkr.hw },
 195 };
 196
 197
 198 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
 199         F(19200000, P_BI_TCXO, 1, 0, 0),
 200         { }
 201 };
 202
 203 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
 204         .cmd_rcgr = 0x48014,
 205         .mnd_width = 0,
 206         .hid_width = 5,
 207         .parent_map = gcc_parent_map_0,
 208         .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
 209         .clkr.hw.init = &(struct clk_init_data){
 210                 .name = "gcc_cpuss_ahb_clk_src",
 211                 .parent_data = gcc_parent_data_7_ao,
 212                 .num_parents = ARRAY_SIZE(gcc_parent_data_7_ao),
 213                 .ops = &clk_rcg2_ops,
 214         },
 215 };
 216
 217 static const struct freq_tbl ftbl_gcc_cpuss_rbcpr_clk_src[] = {
 218         F(19200000, P_BI_TCXO, 1, 0, 0),
 219         { }
 220 };
 221
 222 static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = {
 223         .cmd_rcgr = 0x4815c,
 224         .mnd_width = 0,
 225         .hid_width = 5,
 226         .parent_map = gcc_parent_map_3,
 227         .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
 228         .clkr.hw.init = &(struct clk_init_data){
 229                 .name = "gcc_cpuss_rbcpr_clk_src",
 230                 .parent_data = gcc_parent_data_8_ao,
 231                 .num_parents = ARRAY_SIZE(gcc_parent_data_8_ao),
 232                 .ops = &clk_rcg2_ops,
 233         },
 234 };
 235
 236 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
 237         F(19200000, P_BI_TCXO, 1, 0, 0),
 238         F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
 239         F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
 240         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 241         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
 242         { }
 243 };
 244
 245 static struct clk_rcg2 gcc_gp1_clk_src = {
 246         .cmd_rcgr = 0x64004,
 247         .mnd_width = 8,
 248         .hid_width = 5,
 249         .parent_map = gcc_parent_map_1,
 250         .freq_tbl = ftbl_gcc_gp1_clk_src,
 251         .clkr.hw.init = &(struct clk_init_data){
 252                 .name = "gcc_gp1_clk_src",
 253                 .parent_data = gcc_parent_data_1,
 254                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 255                 .ops = &clk_rcg2_ops,
 256         },
 257 };
 258
 259 static struct clk_rcg2 gcc_gp2_clk_src = {
 260         .cmd_rcgr = 0x65004,
 261         .mnd_width = 8,
 262         .hid_width = 5,
 263         .parent_map = gcc_parent_map_1,
 264         .freq_tbl = ftbl_gcc_gp1_clk_src,
 265         .clkr.hw.init = &(struct clk_init_data){
 266                 .name = "gcc_gp2_clk_src",
 267                 .parent_data = gcc_parent_data_1,
 268                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 269                 .ops = &clk_rcg2_ops,
 270         },
 271 };
 272
 273 static struct clk_rcg2 gcc_gp3_clk_src = {
 274         .cmd_rcgr = 0x66004,
 275         .mnd_width = 8,
 276         .hid_width = 5,
 277         .parent_map = gcc_parent_map_1,
 278         .freq_tbl = ftbl_gcc_gp1_clk_src,
 279         .clkr.hw.init = &(struct clk_init_data){
 280                 .name = "gcc_gp3_clk_src",
 281                 .parent_data = gcc_parent_data_1,
 282                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 283                 .ops = &clk_rcg2_ops,
 284         },
 285 };
 286
 287 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
 288         F(9600000, P_BI_TCXO, 2, 0, 0),
 289         F(19200000, P_BI_TCXO, 1, 0, 0),
 290         { }
 291 };
 292
 293 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
 294         .cmd_rcgr = 0x6b028,
 295         .mnd_width = 16,
 296         .hid_width = 5,
 297         .parent_map = gcc_parent_map_2,
 298         .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 299         .clkr.hw.init = &(struct clk_init_data){
 300                 .name = "gcc_pcie_0_aux_clk_src",
 301                 .parent_data = gcc_parent_data_2,
 302                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
 303                 .ops = &clk_rcg2_ops,
 304         },
 305 };
 306
 307 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
 308         .cmd_rcgr = 0x8d028,
 309         .mnd_width = 16,
 310         .hid_width = 5,
 311         .parent_map = gcc_parent_map_2,
 312         .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 313         .clkr.hw.init = &(struct clk_init_data){
 314                 .name = "gcc_pcie_1_aux_clk_src",
 315                 .parent_data = gcc_parent_data_2,
 316                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
 317                 .ops = &clk_rcg2_ops,
 318         },
 319 };
 320
 321 static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {
 322         F(19200000, P_BI_TCXO, 1, 0, 0),
 323         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 324         { }
 325 };
 326
 327 static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
 328         .cmd_rcgr = 0x6f014,
 329         .mnd_width = 0,
 330         .hid_width = 5,
 331         .parent_map = gcc_parent_map_0,
 332         .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
 333         .clkr.hw.init = &(struct clk_init_data){
 334                 .name = "gcc_pcie_phy_refgen_clk_src",
 335                 .parent_data = gcc_parent_data_0,
 336                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 337                 .ops = &clk_rcg2_ops,
 338         },
 339 };
 340
 341 static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
 342         F(19200000, P_BI_TCXO, 1, 0, 0),
 343         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 344         F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 345         F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
 346         { }
 347 };
 348
 349 static struct clk_rcg2 gcc_qspi_core_clk_src = {
 350         .cmd_rcgr = 0x4b008,
 351         .mnd_width = 0,
 352         .hid_width = 5,
 353         .parent_map = gcc_parent_map_0,
 354         .freq_tbl = ftbl_gcc_qspi_core_clk_src,
 355         .clkr.hw.init = &(struct clk_init_data){
 356                 .name = "gcc_qspi_core_clk_src",
 357                 .parent_data = gcc_parent_data_0,
 358                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 359                 .ops = &clk_rcg2_floor_ops,
 360         },
 361 };
 362
 363 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
 364         F(9600000, P_BI_TCXO, 2, 0, 0),
 365         F(19200000, P_BI_TCXO, 1, 0, 0),
 366         F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
 367         { }
 368 };
 369
 370 static struct clk_rcg2 gcc_pdm2_clk_src = {
 371         .cmd_rcgr = 0x33010,
 372         .mnd_width = 0,
 373         .hid_width = 5,
 374         .parent_map = gcc_parent_map_0,
 375         .freq_tbl = ftbl_gcc_pdm2_clk_src,
 376         .clkr.hw.init = &(struct clk_init_data){
 377                 .name = "gcc_pdm2_clk_src",
 378                 .parent_data = gcc_parent_data_0,
 379                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 380                 .ops = &clk_rcg2_ops,
 381         },
 382 };
 383
 384 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
 385         F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
 386         F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
 387         F(19200000, P_BI_TCXO, 1, 0, 0),
 388         F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
 389         F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
 390         F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
 391         F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
 392         F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
 393         F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
 394         F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
 395         F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
 396         F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
 397         F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
 398         F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
 399         F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75),
 400         { }
 401 };
 402
 403 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
 404         .name = "gcc_qupv3_wrap0_s0_clk_src",
 405         .parent_data = gcc_parent_data_0,
 406         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 407         .ops = &clk_rcg2_shared_ops,
 408 };
 409
 410 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
 411         .cmd_rcgr = 0x17034,
 412         .mnd_width = 16,
 413         .hid_width = 5,
 414         .parent_map = gcc_parent_map_0,
 415         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 416         .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
 417 };
 418
 419 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
 420         .name = "gcc_qupv3_wrap0_s1_clk_src",
 421         .parent_data = gcc_parent_data_0,
 422         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 423         .ops = &clk_rcg2_shared_ops,
 424 };
 425
 426 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
 427         .cmd_rcgr = 0x17164,
 428         .mnd_width = 16,
 429         .hid_width = 5,
 430         .parent_map = gcc_parent_map_0,
 431         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 432         .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
 433 };
 434
 435 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
 436         .name = "gcc_qupv3_wrap0_s2_clk_src",
 437         .parent_data = gcc_parent_data_0,
 438         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 439         .ops = &clk_rcg2_shared_ops,
 440 };
 441
 442 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
 443         .cmd_rcgr = 0x17294,
 444         .mnd_width = 16,
 445         .hid_width = 5,
 446         .parent_map = gcc_parent_map_0,
 447         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 448         .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
 449 };
 450
 451 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
 452         .name = "gcc_qupv3_wrap0_s3_clk_src",
 453         .parent_data = gcc_parent_data_0,
 454         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 455         .ops = &clk_rcg2_shared_ops,
 456 };
 457
 458 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
 459         .cmd_rcgr = 0x173c4,
 460         .mnd_width = 16,
 461         .hid_width = 5,
 462         .parent_map = gcc_parent_map_0,
 463         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 464         .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
 465 };
 466
 467 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
 468         .name = "gcc_qupv3_wrap0_s4_clk_src",
 469         .parent_data = gcc_parent_data_0,
 470         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 471         .ops = &clk_rcg2_shared_ops,
 472 };
 473
 474 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
 475         .cmd_rcgr = 0x174f4,
 476         .mnd_width = 16,
 477         .hid_width = 5,
 478         .parent_map = gcc_parent_map_0,
 479         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 480         .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
 481 };
 482
 483 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
 484         .name = "gcc_qupv3_wrap0_s5_clk_src",
 485         .parent_data = gcc_parent_data_0,
 486         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 487         .ops = &clk_rcg2_shared_ops,
 488 };
 489
 490 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
 491         .cmd_rcgr = 0x17624,
 492         .mnd_width = 16,
 493         .hid_width = 5,
 494         .parent_map = gcc_parent_map_0,
 495         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 496         .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
 497 };
 498
 499 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
 500         .name = "gcc_qupv3_wrap0_s6_clk_src",
 501         .parent_data = gcc_parent_data_0,
 502         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 503         .ops = &clk_rcg2_shared_ops,
 504 };
 505
 506 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
 507         .cmd_rcgr = 0x17754,
 508         .mnd_width = 16,
 509         .hid_width = 5,
 510         .parent_map = gcc_parent_map_0,
 511         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 512         .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
 513 };
 514
 515 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
 516         .name = "gcc_qupv3_wrap0_s7_clk_src",
 517         .parent_data = gcc_parent_data_0,
 518         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 519         .ops = &clk_rcg2_shared_ops,
 520 };
 521
 522 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
 523         .cmd_rcgr = 0x17884,
 524         .mnd_width = 16,
 525         .hid_width = 5,
 526         .parent_map = gcc_parent_map_0,
 527         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 528         .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
 529 };
 530
 531 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
 532         .name = "gcc_qupv3_wrap1_s0_clk_src",
 533         .parent_data = gcc_parent_data_0,
 534         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 535         .ops = &clk_rcg2_shared_ops,
 536 };
 537
 538 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
 539         .cmd_rcgr = 0x18018,
 540         .mnd_width = 16,
 541         .hid_width = 5,
 542         .parent_map = gcc_parent_map_0,
 543         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 544         .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
 545 };
 546
 547 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
 548         .name = "gcc_qupv3_wrap1_s1_clk_src",
 549         .parent_data = gcc_parent_data_0,
 550         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 551         .ops = &clk_rcg2_shared_ops,
 552 };
 553
 554 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
 555         .cmd_rcgr = 0x18148,
 556         .mnd_width = 16,
 557         .hid_width = 5,
 558         .parent_map = gcc_parent_map_0,
 559         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 560         .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
 561 };
 562
 563 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
 564         .name = "gcc_qupv3_wrap1_s2_clk_src",
 565         .parent_data = gcc_parent_data_0,
 566         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 567         .ops = &clk_rcg2_shared_ops,
 568 };
 569
 570 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
 571         .cmd_rcgr = 0x18278,
 572         .mnd_width = 16,
 573         .hid_width = 5,
 574         .parent_map = gcc_parent_map_0,
 575         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 576         .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
 577 };
 578
 579 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
 580         .name = "gcc_qupv3_wrap1_s3_clk_src",
 581         .parent_data = gcc_parent_data_0,
 582         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 583         .ops = &clk_rcg2_shared_ops,
 584 };
 585
 586 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
 587         .cmd_rcgr = 0x183a8,
 588         .mnd_width = 16,
 589         .hid_width = 5,
 590         .parent_map = gcc_parent_map_0,
 591         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 592         .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
 593 };
 594
 595 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
 596         .name = "gcc_qupv3_wrap1_s4_clk_src",
 597         .parent_data = gcc_parent_data_0,
 598         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 599         .ops = &clk_rcg2_shared_ops,
 600 };
 601
 602 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
 603         .cmd_rcgr = 0x184d8,
 604         .mnd_width = 16,
 605         .hid_width = 5,
 606         .parent_map = gcc_parent_map_0,
 607         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 608         .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
 609 };
 610
 611 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
 612         .name = "gcc_qupv3_wrap1_s5_clk_src",
 613         .parent_data = gcc_parent_data_0,
 614         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 615         .ops = &clk_rcg2_shared_ops,
 616 };
 617
 618 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
 619         .cmd_rcgr = 0x18608,
 620         .mnd_width = 16,
 621         .hid_width = 5,
 622         .parent_map = gcc_parent_map_0,
 623         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 624         .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
 625 };
 626
 627 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
 628         .name = "gcc_qupv3_wrap1_s6_clk_src",
 629         .parent_data = gcc_parent_data_0,
 630         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 631         .ops = &clk_rcg2_shared_ops,
 632 };
 633
 634 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
 635         .cmd_rcgr = 0x18738,
 636         .mnd_width = 16,
 637         .hid_width = 5,
 638         .parent_map = gcc_parent_map_0,
 639         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 640         .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
 641 };
 642
 643 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
 644         .name = "gcc_qupv3_wrap1_s7_clk_src",
 645         .parent_data = gcc_parent_data_0,
 646         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 647         .ops = &clk_rcg2_shared_ops,
 648 };
 649
 650 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
 651         .cmd_rcgr = 0x18868,
 652         .mnd_width = 16,
 653         .hid_width = 5,
 654         .parent_map = gcc_parent_map_0,
 655         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 656         .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
 657 };
 658
 659 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
 660         F(400000, P_BI_TCXO, 12, 1, 4),
 661         F(9600000, P_BI_TCXO, 2, 0, 0),
 662         F(19200000, P_BI_TCXO, 1, 0, 0),
 663         F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
 664         F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
 665         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 666         F(201500000, P_GPLL4_OUT_MAIN, 4, 0, 0),
 667         { }
 668 };
 669
 670 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
 671         .cmd_rcgr = 0x1400c,
 672         .mnd_width = 8,
 673         .hid_width = 5,
 674         .parent_map = gcc_parent_map_10,
 675         .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
 676         .clkr.hw.init = &(struct clk_init_data){
 677                 .name = "gcc_sdcc2_apps_clk_src",
 678                 .parent_data = gcc_parent_data_10,
 679                 .num_parents = ARRAY_SIZE(gcc_parent_data_10),
 680                 .ops = &clk_rcg2_floor_ops,
 681         },
 682 };
 683
 684 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
 685         F(400000, P_BI_TCXO, 12, 1, 4),
 686         F(9600000, P_BI_TCXO, 2, 0, 0),
 687         F(19200000, P_BI_TCXO, 1, 0, 0),
 688         F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
 689         F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
 690         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 691         { }
 692 };
 693
 694 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
 695         .cmd_rcgr = 0x1600c,
 696         .mnd_width = 8,
 697         .hid_width = 5,
 698         .parent_map = gcc_parent_map_0,
 699         .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
 700         .clkr.hw.init = &(struct clk_init_data){
 701                 .name = "gcc_sdcc4_apps_clk_src",
 702                 .parent_data = gcc_parent_data_0,
 703                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 704                 .ops = &clk_rcg2_floor_ops,
 705         },
 706 };
 707
 708 static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {
 709         F(105495, P_BI_TCXO, 2, 1, 91),
 710         { }
 711 };
 712
 713 static struct clk_rcg2 gcc_tsif_ref_clk_src = {
 714         .cmd_rcgr = 0x36010,
 715         .mnd_width = 8,
 716         .hid_width = 5,
 717         .parent_map = gcc_parent_map_6,
 718         .freq_tbl = ftbl_gcc_tsif_ref_clk_src,
 719         .clkr.hw.init = &(struct clk_init_data){
 720                 .name = "gcc_tsif_ref_clk_src",
 721                 .parent_data = gcc_parent_data_6,
 722                 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
 723                 .ops = &clk_rcg2_ops,
 724         },
 725 };
 726
 727 static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
 728         F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
 729         F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
 730         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 731         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
 732         F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
 733         { }
 734 };
 735
 736 static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
 737         .cmd_rcgr = 0x7501c,
 738         .mnd_width = 8,
 739         .hid_width = 5,
 740         .parent_map = gcc_parent_map_0,
 741         .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
 742         .clkr.hw.init = &(struct clk_init_data){
 743                 .name = "gcc_ufs_card_axi_clk_src",
 744                 .parent_data = gcc_parent_data_0,
 745                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 746                 .ops = &clk_rcg2_shared_ops,
 747         },
 748 };
 749
 750 static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
 751         F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
 752         F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
 753         F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 754         F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
 755         { }
 756 };
 757
 758 static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
 759         .cmd_rcgr = 0x7505c,
 760         .mnd_width = 0,
 761         .hid_width = 5,
 762         .parent_map = gcc_parent_map_0,
 763         .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
 764         .clkr.hw.init = &(struct clk_init_data){
 765                 .name = "gcc_ufs_card_ice_core_clk_src",
 766                 .parent_data = gcc_parent_data_0,
 767                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 768                 .ops = &clk_rcg2_shared_ops,
 769         },
 770 };
 771
 772 static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
 773         .cmd_rcgr = 0x75090,
 774         .mnd_width = 0,
 775         .hid_width = 5,
 776         .parent_map = gcc_parent_map_4,
 777         .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
 778         .clkr.hw.init = &(struct clk_init_data){
 779                 .name = "gcc_ufs_card_phy_aux_clk_src",
 780                 .parent_data = gcc_parent_data_4,
 781                 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
 782                 .ops = &clk_rcg2_ops,
 783         },
 784 };
 785
 786 static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = {
 787         F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
 788         F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
 789         F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 790         { }
 791 };
 792
 793 static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
 794         .cmd_rcgr = 0x75074,
 795         .mnd_width = 0,
 796         .hid_width = 5,
 797         .parent_map = gcc_parent_map_0,
 798         .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
 799         .clkr.hw.init = &(struct clk_init_data){
 800                 .name = "gcc_ufs_card_unipro_core_clk_src",
 801                 .parent_data = gcc_parent_data_0,
 802                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 803                 .ops = &clk_rcg2_shared_ops,
 804         },
 805 };
 806
 807 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
 808         F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
 809         F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
 810         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 811         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
 812         F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
 813         { }
 814 };
 815
 816 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
 817         .cmd_rcgr = 0x7701c,
 818         .mnd_width = 8,
 819         .hid_width = 5,
 820         .parent_map = gcc_parent_map_0,
 821         .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
 822         .clkr.hw.init = &(struct clk_init_data){
 823                 .name = "gcc_ufs_phy_axi_clk_src",
 824                 .parent_data = gcc_parent_data_0,
 825                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 826                 .ops = &clk_rcg2_shared_ops,
 827         },
 828 };
 829
 830 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
 831         .cmd_rcgr = 0x7705c,
 832         .mnd_width = 0,
 833         .hid_width = 5,
 834         .parent_map = gcc_parent_map_0,
 835         .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
 836         .clkr.hw.init = &(struct clk_init_data){
 837                 .name = "gcc_ufs_phy_ice_core_clk_src",
 838                 .parent_data = gcc_parent_data_0,
 839                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 840                 .ops = &clk_rcg2_shared_ops,
 841         },
 842 };
 843
 844 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
 845         .cmd_rcgr = 0x77090,
 846         .mnd_width = 0,
 847         .hid_width = 5,
 848         .parent_map = gcc_parent_map_4,
 849         .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 850         .clkr.hw.init = &(struct clk_init_data){
 851                 .name = "gcc_ufs_phy_phy_aux_clk_src",
 852                 .parent_data = gcc_parent_data_4,
 853                 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
 854                 .ops = &clk_rcg2_shared_ops,
 855         },
 856 };
 857
 858 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
 859         .cmd_rcgr = 0x77074,
 860         .mnd_width = 0,
 861         .hid_width = 5,
 862         .parent_map = gcc_parent_map_0,
 863         .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
 864         .clkr.hw.init = &(struct clk_init_data){
 865                 .name = "gcc_ufs_phy_unipro_core_clk_src",
 866                 .parent_data = gcc_parent_data_0,
 867                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 868                 .ops = &clk_rcg2_shared_ops,
 869         },
 870 };
 871
 872 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
 873         F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
 874         F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
 875         F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
 876         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
 877         F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
 878         { }
 879 };
 880
 881 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
 882         .cmd_rcgr = 0xf018,
 883         .mnd_width = 8,
 884         .hid_width = 5,
 885         .parent_map = gcc_parent_map_0,
 886         .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
 887         .clkr.hw.init = &(struct clk_init_data){
 888                 .name = "gcc_usb30_prim_master_clk_src",
 889                 .parent_data = gcc_parent_data_0,
 890                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 891                 .ops = &clk_rcg2_shared_ops,
 892         },
 893 };
 894
 895 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
 896         F(19200000, P_BI_TCXO, 1, 0, 0),
 897         F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
 898         F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0),
 899         F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
 900         { }
 901 };
 902
 903 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
 904         .cmd_rcgr = 0xf030,
 905         .mnd_width = 0,
 906         .hid_width = 5,
 907         .parent_map = gcc_parent_map_0,
 908         .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
 909         .clkr.hw.init = &(struct clk_init_data){
 910                 .name = "gcc_usb30_prim_mock_utmi_clk_src",
 911                 .parent_data = gcc_parent_data_0,
 912                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 913                 .ops = &clk_rcg2_shared_ops,
 914         },
 915 };
 916
 917 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
 918         .cmd_rcgr = 0x10018,
 919         .mnd_width = 8,
 920         .hid_width = 5,
 921         .parent_map = gcc_parent_map_0,
 922         .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
 923         .clkr.hw.init = &(struct clk_init_data){
 924                 .name = "gcc_usb30_sec_master_clk_src",
 925                 .parent_data = gcc_parent_data_0,
 926                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 927                 .ops = &clk_rcg2_ops,
 928         },
 929 };
 930
 931 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
 932         .cmd_rcgr = 0x10030,
 933         .mnd_width = 0,
 934         .hid_width = 5,
 935         .parent_map = gcc_parent_map_0,
 936         .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
 937         .clkr.hw.init = &(struct clk_init_data){
 938                 .name = "gcc_usb30_sec_mock_utmi_clk_src",
 939                 .parent_data = gcc_parent_data_0,
 940                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 941                 .ops = &clk_rcg2_ops,
 942         },
 943 };
 944
 945 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
 946         .cmd_rcgr = 0xf05c,
 947         .mnd_width = 0,
 948         .hid_width = 5,
 949         .parent_map = gcc_parent_map_2,
 950         .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
 951         .clkr.hw.init = &(struct clk_init_data){
 952                 .name = "gcc_usb3_prim_phy_aux_clk_src",
 953                 .parent_data = gcc_parent_data_2,
 954                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
 955                 .ops = &clk_rcg2_ops,
 956         },
 957 };
 958
 959 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
 960         .cmd_rcgr = 0x1005c,
 961         .mnd_width = 0,
 962         .hid_width = 5,
 963         .parent_map = gcc_parent_map_2,
 964         .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
 965         .clkr.hw.init = &(struct clk_init_data){
 966                 .name = "gcc_usb3_sec_phy_aux_clk_src",
 967                 .parent_data = gcc_parent_data_2,
 968                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
 969                 .ops = &clk_rcg2_shared_ops,
 970         },
 971 };
 972
 973 static struct clk_rcg2 gcc_vs_ctrl_clk_src = {
 974         .cmd_rcgr = 0x7a030,
 975         .mnd_width = 0,
 976         .hid_width = 5,
 977         .parent_map = gcc_parent_map_3,
 978         .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
 979         .clkr.hw.init = &(struct clk_init_data){
 980                 .name = "gcc_vs_ctrl_clk_src",
 981                 .parent_data = gcc_parent_data_3,
 982                 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
 983                 .ops = &clk_rcg2_ops,
 984         },
 985 };
 986
 987 static const struct freq_tbl ftbl_gcc_vsensor_clk_src[] = {
 988         F(19200000, P_BI_TCXO, 1, 0, 0),
 989         F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
 990         F(600000000, P_GPLL0_OUT_MAIN, 1, 0, 0),
 991         { }
 992 };
 993
 994 static struct clk_rcg2 gcc_vsensor_clk_src = {
 995         .cmd_rcgr = 0x7a018,
 996         .mnd_width = 0,
 997         .hid_width = 5,
 998         .parent_map = gcc_parent_map_3,
 999         .freq_tbl = ftbl_gcc_vsensor_clk_src,
1000         .clkr.hw.init = &(struct clk_init_data){
1001                 .name = "gcc_vsensor_clk_src",
1002                 .parent_data = gcc_parent_data_8,
1003                 .num_parents = ARRAY_SIZE(gcc_parent_data_8),
1004                 .ops = &clk_rcg2_ops,
1005         },
1006 };
1007
1008 static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
1009         .halt_reg = 0x90014,
1010         .halt_check = BRANCH_HALT,
1011         .clkr = {
1012                 .enable_reg = 0x90014,
1013                 .enable_mask = BIT(0),
1014                 .hw.init = &(struct clk_init_data){
1015                         .name = "gcc_aggre_noc_pcie_tbu_clk",
1016                         .ops = &clk_branch2_ops,
1017                 },
1018         },
1019 };
1020
1021 static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
1022         .halt_reg = 0x82028,
1023         .halt_check = BRANCH_HALT,
1024         .hwcg_reg = 0x82028,
1025         .hwcg_bit = 1,
1026         .clkr = {
1027                 .enable_reg = 0x82028,
1028                 .enable_mask = BIT(0),
1029                 .hw.init = &(struct clk_init_data){
1030                         .name = "gcc_aggre_ufs_card_axi_clk",
1031                         .parent_hws = (const struct clk_hw*[]){
1032                                 &gcc_ufs_card_axi_clk_src.clkr.hw,
1033                         },
1034                         .num_parents = 1,
1035                         .flags = CLK_SET_RATE_PARENT,
1036                         .ops = &clk_branch2_ops,
1037                 },
1038         },
1039 };
1040
1041 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1042         .halt_reg = 0x82024,
1043         .halt_check = BRANCH_HALT,
1044         .hwcg_reg = 0x82024,
1045         .hwcg_bit = 1,
1046         .clkr = {
1047                 .enable_reg = 0x82024,
1048                 .enable_mask = BIT(0),
1049                 .hw.init = &(struct clk_init_data){
1050                         .name = "gcc_aggre_ufs_phy_axi_clk",
1051                         .parent_hws = (const struct clk_hw*[]){
1052                                 &gcc_ufs_phy_axi_clk_src.clkr.hw,
1053                         },
1054                         .num_parents = 1,
1055                         .flags = CLK_SET_RATE_PARENT,
1056                         .ops = &clk_branch2_ops,
1057                 },
1058         },
1059 };
1060
1061 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1062         .halt_reg = 0x8201c,
1063         .halt_check = BRANCH_HALT,
1064         .clkr = {
1065                 .enable_reg = 0x8201c,
1066                 .enable_mask = BIT(0),
1067                 .hw.init = &(struct clk_init_data){
1068                         .name = "gcc_aggre_usb3_prim_axi_clk",
1069                         .parent_hws = (const struct clk_hw*[]){
1070                                 &gcc_usb30_prim_master_clk_src.clkr.hw,
1071                         },
1072                         .num_parents = 1,
1073                         .flags = CLK_SET_RATE_PARENT,
1074                         .ops = &clk_branch2_ops,
1075                 },
1076         },
1077 };
1078
1079 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
1080         .halt_reg = 0x82020,
1081         .halt_check = BRANCH_HALT,
1082         .clkr = {
1083                 .enable_reg = 0x82020,
1084                 .enable_mask = BIT(0),
1085                 .hw.init = &(struct clk_init_data){
1086                         .name = "gcc_aggre_usb3_sec_axi_clk",
1087                         .parent_hws = (const struct clk_hw*[]){
1088                                 &gcc_usb30_sec_master_clk_src.clkr.hw,
1089                         },
1090                         .num_parents = 1,
1091                         .flags = CLK_SET_RATE_PARENT,
1092                         .ops = &clk_branch2_ops,
1093                 },
1094         },
1095 };
1096
1097 static struct clk_branch gcc_apc_vs_clk = {
1098         .halt_reg = 0x7a050,
1099         .halt_check = BRANCH_HALT,
1100         .clkr = {
1101                 .enable_reg = 0x7a050,
1102                 .enable_mask = BIT(0),
1103                 .hw.init = &(struct clk_init_data){
1104                         .name = "gcc_apc_vs_clk",
1105                         .parent_hws = (const struct clk_hw*[]){
1106                                 &gcc_vsensor_clk_src.clkr.hw,
1107                         },
1108                         .num_parents = 1,
1109                         .flags = CLK_SET_RATE_PARENT,
1110                         .ops = &clk_branch2_ops,
1111                 },
1112         },
1113 };
1114
1115 static struct clk_branch gcc_boot_rom_ahb_clk = {
1116         .halt_reg = 0x38004,
1117         .halt_check = BRANCH_HALT_VOTED,
1118         .hwcg_reg = 0x38004,
1119         .hwcg_bit = 1,
1120         .clkr = {
1121                 .enable_reg = 0x52004,
1122                 .enable_mask = BIT(10),
1123                 .hw.init = &(struct clk_init_data){
1124                         .name = "gcc_boot_rom_ahb_clk",
1125                         .ops = &clk_branch2_ops,
1126                 },
1127         },
1128 };
1129
1130 static struct clk_branch gcc_camera_ahb_clk = {
1131         .halt_reg = 0xb008,
1132         .halt_check = BRANCH_HALT,
1133         .hwcg_reg = 0xb008,
1134         .hwcg_bit = 1,
1135         .clkr = {
1136                 .enable_reg = 0xb008,
1137                 .enable_mask = BIT(0),
1138                 .hw.init = &(struct clk_init_data){
1139                         .name = "gcc_camera_ahb_clk",
1140                         .flags = CLK_IS_CRITICAL,
1141                         .ops = &clk_branch2_ops,
1142                 },
1143         },
1144 };
1145
1146 static struct clk_branch gcc_camera_axi_clk = {
1147         .halt_reg = 0xb020,
1148         .halt_check = BRANCH_VOTED,
1149         .clkr = {
1150                 .enable_reg = 0xb020,
1151                 .enable_mask = BIT(0),
1152                 .hw.init = &(struct clk_init_data){
1153                         .name = "gcc_camera_axi_clk",
1154                         .ops = &clk_branch2_ops,
1155                 },
1156         },
1157 };
1158
1159 static struct clk_branch gcc_camera_xo_clk = {
1160         .halt_reg = 0xb02c,
1161         .halt_check = BRANCH_HALT,
1162         .clkr = {
1163                 .enable_reg = 0xb02c,
1164                 .enable_mask = BIT(0),
1165                 .hw.init = &(struct clk_init_data){
1166                         .name = "gcc_camera_xo_clk",
1167                         .flags = CLK_IS_CRITICAL,
1168                         .ops = &clk_branch2_ops,
1169                 },
1170         },
1171 };
1172
1173 static struct clk_branch gcc_ce1_ahb_clk = {
1174         .halt_reg = 0x4100c,
1175         .halt_check = BRANCH_HALT_VOTED,
1176         .hwcg_reg = 0x4100c,
1177         .hwcg_bit = 1,
1178         .clkr = {
1179                 .enable_reg = 0x52004,
1180                 .enable_mask = BIT(3),
1181                 .hw.init = &(struct clk_init_data){
1182                         .name = "gcc_ce1_ahb_clk",
1183                         .ops = &clk_branch2_ops,
1184                 },
1185         },
1186 };
1187
1188 static struct clk_branch gcc_ce1_axi_clk = {
1189         .halt_reg = 0x41008,
1190         .halt_check = BRANCH_HALT_VOTED,
1191         .clkr = {
1192                 .enable_reg = 0x52004,
1193                 .enable_mask = BIT(4),
1194                 .hw.init = &(struct clk_init_data){
1195                         .name = "gcc_ce1_axi_clk",
1196                         .ops = &clk_branch2_ops,
1197                 },
1198         },
1199 };
1200
1201 static struct clk_branch gcc_ce1_clk = {
1202         .halt_reg = 0x41004,
1203         .halt_check = BRANCH_HALT_VOTED,
1204         .clkr = {
1205                 .enable_reg = 0x52004,
1206                 .enable_mask = BIT(5),
1207                 .hw.init = &(struct clk_init_data){
1208                         .name = "gcc_ce1_clk",
1209                         .ops = &clk_branch2_ops,
1210                 },
1211         },
1212 };
1213
1214 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1215         .halt_reg = 0x502c,
1216         .halt_check = BRANCH_HALT,
1217         .clkr = {
1218                 .enable_reg = 0x502c,
1219                 .enable_mask = BIT(0),
1220                 .hw.init = &(struct clk_init_data){
1221                         .name = "gcc_cfg_noc_usb3_prim_axi_clk",
1222                         .parent_hws = (const struct clk_hw*[]){
1223                                 &gcc_usb30_prim_master_clk_src.clkr.hw,
1224                         },
1225                         .num_parents = 1,
1226                         .flags = CLK_SET_RATE_PARENT,
1227                         .ops = &clk_branch2_ops,
1228                 },
1229         },
1230 };
1231
1232 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
1233         .halt_reg = 0x5030,
1234         .halt_check = BRANCH_HALT,
1235         .clkr = {
1236                 .enable_reg = 0x5030,
1237                 .enable_mask = BIT(0),
1238                 .hw.init = &(struct clk_init_data){
1239                         .name = "gcc_cfg_noc_usb3_sec_axi_clk",
1240                         .parent_hws = (const struct clk_hw*[]){
1241                                 &gcc_usb30_sec_master_clk_src.clkr.hw,
1242                         },
1243                         .num_parents = 1,
1244                         .flags = CLK_SET_RATE_PARENT,
1245                         .ops = &clk_branch2_ops,
1246                 },
1247         },
1248 };
1249
1250 static struct clk_branch gcc_cpuss_ahb_clk = {
1251         .halt_reg = 0x48000,
1252         .halt_check = BRANCH_HALT_VOTED,
1253         .clkr = {
1254                 .enable_reg = 0x52004,
1255                 .enable_mask = BIT(21),
1256                 .hw.init = &(struct clk_init_data){
1257                         .name = "gcc_cpuss_ahb_clk",
1258                         .parent_hws = (const struct clk_hw*[]){
1259                                 &gcc_cpuss_ahb_clk_src.clkr.hw,
1260                         },
1261                         .num_parents = 1,
1262                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1263                         .ops = &clk_branch2_ops,
1264                 },
1265         },
1266 };
1267
1268 static struct clk_branch gcc_cpuss_rbcpr_clk = {
1269         .halt_reg = 0x48008,
1270         .halt_check = BRANCH_HALT,
1271         .clkr = {
1272                 .enable_reg = 0x48008,
1273                 .enable_mask = BIT(0),
1274                 .hw.init = &(struct clk_init_data){
1275                         .name = "gcc_cpuss_rbcpr_clk",
1276                         .parent_hws = (const struct clk_hw*[]){
1277                                 &gcc_cpuss_rbcpr_clk_src.clkr.hw,
1278                         },
1279                         .num_parents = 1,
1280                         .flags = CLK_SET_RATE_PARENT,
1281                         .ops = &clk_branch2_ops,
1282                 },
1283         },
1284 };
1285
1286 static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1287         .halt_reg = 0x44038,
1288         .halt_check = BRANCH_VOTED,
1289         .clkr = {
1290                 .enable_reg = 0x44038,
1291                 .enable_mask = BIT(0),
1292                 .hw.init = &(struct clk_init_data){
1293                         .name = "gcc_ddrss_gpu_axi_clk",
1294                         .ops = &clk_branch2_ops,
1295                 },
1296         },
1297 };
1298
1299 static struct clk_branch gcc_disp_ahb_clk = {
1300         .halt_reg = 0xb00c,
1301         .halt_check = BRANCH_HALT,
1302         .hwcg_reg = 0xb00c,
1303         .hwcg_bit = 1,
1304         .clkr = {
1305                 .enable_reg = 0xb00c,
1306                 .enable_mask = BIT(0),
1307                 .hw.init = &(struct clk_init_data){
1308                         .name = "gcc_disp_ahb_clk",
1309                         .flags = CLK_IS_CRITICAL,
1310                         .ops = &clk_branch2_ops,
1311                 },
1312         },
1313 };
1314
1315 static struct clk_branch gcc_disp_axi_clk = {
1316         .halt_reg = 0xb024,
1317         .halt_check = BRANCH_VOTED,
1318         .clkr = {
1319                 .enable_reg = 0xb024,
1320                 .enable_mask = BIT(0),
1321                 .hw.init = &(struct clk_init_data){
1322                         .name = "gcc_disp_axi_clk",
1323                         .ops = &clk_branch2_ops,
1324                 },
1325         },
1326 };
1327
1328 static struct clk_branch gcc_disp_gpll0_clk_src = {
1329         .halt_check = BRANCH_HALT_DELAY,
1330         .clkr = {
1331                 .enable_reg = 0x52004,
1332                 .enable_mask = BIT(18),
1333                 .hw.init = &(struct clk_init_data){
1334                         .name = "gcc_disp_gpll0_clk_src",
1335                         .parent_hws = (const struct clk_hw*[]){
1336                                 &gpll0.clkr.hw,
1337                         },
1338                         .num_parents = 1,
1339                         .ops = &clk_branch2_aon_ops,
1340                 },
1341         },
1342 };
1343
1344 static struct clk_branch gcc_disp_gpll0_div_clk_src = {
1345         .halt_check = BRANCH_HALT_DELAY,
1346         .clkr = {
1347                 .enable_reg = 0x52004,
1348                 .enable_mask = BIT(19),
1349                 .hw.init = &(struct clk_init_data){
1350                         .name = "gcc_disp_gpll0_div_clk_src",
1351                         .parent_hws = (const struct clk_hw*[]){
1352                                 &gpll0_out_even.clkr.hw,
1353                         },
1354                         .num_parents = 1,
1355                         .ops = &clk_branch2_ops,
1356                 },
1357         },
1358 };
1359
1360 static struct clk_branch gcc_disp_xo_clk = {
1361         .halt_reg = 0xb030,
1362         .halt_check = BRANCH_HALT,
1363         .clkr = {
1364                 .enable_reg = 0xb030,
1365                 .enable_mask = BIT(0),
1366                 .hw.init = &(struct clk_init_data){
1367                         .name = "gcc_disp_xo_clk",
1368                         .flags = CLK_IS_CRITICAL,
1369                         .ops = &clk_branch2_ops,
1370                 },
1371         },
1372 };
1373
1374 static struct clk_branch gcc_gp1_clk = {
1375         .halt_reg = 0x64000,
1376         .halt_check = BRANCH_HALT,
1377         .clkr = {
1378                 .enable_reg = 0x64000,
1379                 .enable_mask = BIT(0),
1380                 .hw.init = &(struct clk_init_data){
1381                         .name = "gcc_gp1_clk",
1382                         .parent_hws = (const struct clk_hw*[]){
1383                                 &gcc_gp1_clk_src.clkr.hw,
1384                         },
1385                         .num_parents = 1,
1386                         .flags = CLK_SET_RATE_PARENT,
1387                         .ops = &clk_branch2_ops,
1388                 },
1389         },
1390 };
1391
1392 static struct clk_branch gcc_gp2_clk = {
1393         .halt_reg = 0x65000,
1394         .halt_check = BRANCH_HALT,
1395         .clkr = {
1396                 .enable_reg = 0x65000,
1397                 .enable_mask = BIT(0),
1398                 .hw.init = &(struct clk_init_data){
1399                         .name = "gcc_gp2_clk",
1400                         .parent_hws = (const struct clk_hw*[]){
1401                                 &gcc_gp2_clk_src.clkr.hw,
1402                         },
1403                         .num_parents = 1,
1404                         .flags = CLK_SET_RATE_PARENT,
1405                         .ops = &clk_branch2_ops,
1406                 },
1407         },
1408 };
1409
1410 static struct clk_branch gcc_gp3_clk = {
1411         .halt_reg = 0x66000,
1412         .halt_check = BRANCH_HALT,
1413         .clkr = {
1414                 .enable_reg = 0x66000,
1415                 .enable_mask = BIT(0),
1416                 .hw.init = &(struct clk_init_data){
1417                         .name = "gcc_gp3_clk",
1418                         .parent_hws = (const struct clk_hw*[]){
1419                                 &gcc_gp3_clk_src.clkr.hw,
1420                         },
1421                         .num_parents = 1,
1422                         .flags = CLK_SET_RATE_PARENT,
1423                         .ops = &clk_branch2_ops,
1424                 },
1425         },
1426 };
1427
1428 static struct clk_branch gcc_gpu_cfg_ahb_clk = {
1429         .halt_reg = 0x71004,
1430         .halt_check = BRANCH_HALT,
1431         .hwcg_reg = 0x71004,
1432         .hwcg_bit = 1,
1433         .clkr = {
1434                 .enable_reg = 0x71004,
1435                 .enable_mask = BIT(0),
1436                 .hw.init = &(struct clk_init_data){
1437                         .name = "gcc_gpu_cfg_ahb_clk",
1438                         .flags = CLK_IS_CRITICAL,
1439                         .ops = &clk_branch2_ops,
1440                 },
1441         },
1442 };
1443
1444 static struct clk_branch gcc_gpu_gpll0_clk_src = {
1445         .halt_check = BRANCH_HALT_DELAY,
1446         .clkr = {
1447                 .enable_reg = 0x52004,
1448                 .enable_mask = BIT(15),
1449                 .hw.init = &(struct clk_init_data){
1450                         .name = "gcc_gpu_gpll0_clk_src",
1451                         .parent_hws = (const struct clk_hw*[]){
1452                                 &gpll0.clkr.hw,
1453                         },
1454                         .num_parents = 1,
1455                         .ops = &clk_branch2_ops,
1456                 },
1457         },
1458 };
1459
1460 static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1461         .halt_check = BRANCH_HALT_DELAY,
1462         .clkr = {
1463                 .enable_reg = 0x52004,
1464                 .enable_mask = BIT(16),
1465                 .hw.init = &(struct clk_init_data){
1466                         .name = "gcc_gpu_gpll0_div_clk_src",
1467                         .parent_hws = (const struct clk_hw*[]){
1468                                 &gpll0_out_even.clkr.hw,
1469                         },
1470                         .num_parents = 1,
1471                         .ops = &clk_branch2_ops,
1472                 },
1473         },
1474 };
1475
1476 static struct clk_branch gcc_gpu_iref_clk = {
1477         .halt_reg = 0x8c010,
1478         .halt_check = BRANCH_HALT,
1479         .clkr = {
1480                 .enable_reg = 0x8c010,
1481                 .enable_mask = BIT(0),
1482                 .hw.init = &(struct clk_init_data){
1483                         .name = "gcc_gpu_iref_clk",
1484                         .ops = &clk_branch2_ops,
1485                 },
1486         },
1487 };
1488
1489 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1490         .halt_reg = 0x7100c,
1491         .halt_check = BRANCH_VOTED,
1492         .clkr = {
1493                 .enable_reg = 0x7100c,
1494                 .enable_mask = BIT(0),
1495                 .hw.init = &(struct clk_init_data){
1496                         .name = "gcc_gpu_memnoc_gfx_clk",
1497                         .ops = &clk_branch2_ops,
1498                 },
1499         },
1500 };
1501
1502 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1503         .halt_reg = 0x71018,
1504         .halt_check = BRANCH_HALT,
1505         .clkr = {
1506                 .enable_reg = 0x71018,
1507                 .enable_mask = BIT(0),
1508                 .hw.init = &(struct clk_init_data){
1509                         .name = "gcc_gpu_snoc_dvm_gfx_clk",
1510                         .ops = &clk_branch2_ops,
1511                 },
1512         },
1513 };
1514
1515 static struct clk_branch gcc_gpu_vs_clk = {
1516         .halt_reg = 0x7a04c,
1517         .halt_check = BRANCH_HALT,
1518         .clkr = {
1519                 .enable_reg = 0x7a04c,
1520                 .enable_mask = BIT(0),
1521                 .hw.init = &(struct clk_init_data){
1522                         .name = "gcc_gpu_vs_clk",
1523                         .parent_hws = (const struct clk_hw*[]){
1524                                 &gcc_vsensor_clk_src.clkr.hw,
1525                         },
1526                         .num_parents = 1,
1527                         .flags = CLK_SET_RATE_PARENT,
1528                         .ops = &clk_branch2_ops,
1529                 },
1530         },
1531 };
1532
1533 static struct clk_branch gcc_mss_axis2_clk = {
1534         .halt_reg = 0x8a008,
1535         .halt_check = BRANCH_HALT,
1536         .clkr = {
1537                 .enable_reg = 0x8a008,
1538                 .enable_mask = BIT(0),
1539                 .hw.init = &(struct clk_init_data){
1540                         .name = "gcc_mss_axis2_clk",
1541                         .ops = &clk_branch2_ops,
1542                 },
1543         },
1544 };
1545
1546 static struct clk_branch gcc_mss_cfg_ahb_clk = {
1547         .halt_reg = 0x8a000,
1548         .halt_check = BRANCH_HALT,
1549         .hwcg_reg = 0x8a000,
1550         .hwcg_bit = 1,
1551         .clkr = {
1552                 .enable_reg = 0x8a000,
1553                 .enable_mask = BIT(0),
1554                 .hw.init = &(struct clk_init_data){
1555                         .name = "gcc_mss_cfg_ahb_clk",
1556                         .ops = &clk_branch2_ops,
1557                 },
1558         },
1559 };
1560
1561 static struct clk_branch gcc_mss_gpll0_div_clk_src = {
1562         .halt_check = BRANCH_HALT_DELAY,
1563         .clkr = {
1564                 .enable_reg = 0x52004,
1565                 .enable_mask = BIT(17),
1566                 .hw.init = &(struct clk_init_data){
1567                         .name = "gcc_mss_gpll0_div_clk_src",
1568                         .ops = &clk_branch2_ops,
1569                 },
1570         },
1571 };
1572
1573 static struct clk_branch gcc_mss_mfab_axis_clk = {
1574         .halt_reg = 0x8a004,
1575         .halt_check = BRANCH_VOTED,
1576         .hwcg_reg = 0x8a004,
1577         .hwcg_bit = 1,
1578         .clkr = {
1579                 .enable_reg = 0x8a004,
1580                 .enable_mask = BIT(0),
1581                 .hw.init = &(struct clk_init_data){
1582                         .name = "gcc_mss_mfab_axis_clk",
1583                         .ops = &clk_branch2_ops,
1584                 },
1585         },
1586 };
1587
1588 static struct clk_branch gcc_mss_q6_memnoc_axi_clk = {
1589         .halt_reg = 0x8a154,
1590         .halt_check = BRANCH_VOTED,
1591         .clkr = {
1592                 .enable_reg = 0x8a154,
1593                 .enable_mask = BIT(0),
1594                 .hw.init = &(struct clk_init_data){
1595                         .name = "gcc_mss_q6_memnoc_axi_clk",
1596                         .ops = &clk_branch2_ops,
1597                 },
1598         },
1599 };
1600
1601 static struct clk_branch gcc_mss_snoc_axi_clk = {
1602         .halt_reg = 0x8a150,
1603         .halt_check = BRANCH_HALT,
1604         .clkr = {
1605                 .enable_reg = 0x8a150,
1606                 .enable_mask = BIT(0),
1607                 .hw.init = &(struct clk_init_data){
1608                         .name = "gcc_mss_snoc_axi_clk",
1609                         .ops = &clk_branch2_ops,
1610                 },
1611         },
1612 };
1613
1614 static struct clk_branch gcc_mss_vs_clk = {
1615         .halt_reg = 0x7a048,
1616         .halt_check = BRANCH_HALT,
1617         .clkr = {
1618                 .enable_reg = 0x7a048,
1619                 .enable_mask = BIT(0),
1620                 .hw.init = &(struct clk_init_data){
1621                         .name = "gcc_mss_vs_clk",
1622                         .parent_hws = (const struct clk_hw*[]){
1623                                 &gcc_vsensor_clk_src.clkr.hw,
1624                         },
1625                         .num_parents = 1,
1626                         .flags = CLK_SET_RATE_PARENT,
1627                         .ops = &clk_branch2_ops,
1628                 },
1629         },
1630 };
1631
1632 static struct clk_branch gcc_pcie_0_aux_clk = {
1633         .halt_reg = 0x6b01c,
1634         .halt_check = BRANCH_HALT_VOTED,
1635         .clkr = {
1636                 .enable_reg = 0x5200c,
1637                 .enable_mask = BIT(3),
1638                 .hw.init = &(struct clk_init_data){
1639                         .name = "gcc_pcie_0_aux_clk",
1640                         .parent_hws = (const struct clk_hw*[]){
1641                                 &gcc_pcie_0_aux_clk_src.clkr.hw,
1642                         },
1643                         .num_parents = 1,
1644                         .flags = CLK_SET_RATE_PARENT,
1645                         .ops = &clk_branch2_ops,
1646                 },
1647         },
1648 };
1649
1650 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1651         .halt_reg = 0x6b018,
1652         .halt_check = BRANCH_HALT_VOTED,
1653         .hwcg_reg = 0x6b018,
1654         .hwcg_bit = 1,
1655         .clkr = {
1656                 .enable_reg = 0x5200c,
1657                 .enable_mask = BIT(2),
1658                 .hw.init = &(struct clk_init_data){
1659                         .name = "gcc_pcie_0_cfg_ahb_clk",
1660                         .ops = &clk_branch2_ops,
1661                 },
1662         },
1663 };
1664
1665 static struct clk_branch gcc_pcie_0_clkref_clk = {
1666         .halt_reg = 0x8c00c,
1667         .halt_check = BRANCH_HALT,
1668         .clkr = {
1669                 .enable_reg = 0x8c00c,
1670                 .enable_mask = BIT(0),
1671                 .hw.init = &(struct clk_init_data){
1672                         .name = "gcc_pcie_0_clkref_clk",
1673                         .ops = &clk_branch2_ops,
1674                 },
1675         },
1676 };
1677
1678 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1679         .halt_reg = 0x6b014,
1680         .halt_check = BRANCH_HALT_VOTED,
1681         .clkr = {
1682                 .enable_reg = 0x5200c,
1683                 .enable_mask = BIT(1),
1684                 .hw.init = &(struct clk_init_data){
1685                         .name = "gcc_pcie_0_mstr_axi_clk",
1686                         .ops = &clk_branch2_ops,
1687                 },
1688         },
1689 };
1690
1691 static struct clk_branch gcc_pcie_0_pipe_clk = {
1692         .halt_check = BRANCH_HALT_SKIP,
1693         .clkr = {
1694                 .enable_reg = 0x5200c,
1695                 .enable_mask = BIT(4),
1696                 .hw.init = &(struct clk_init_data){
1697                         .name = "gcc_pcie_0_pipe_clk",
1698                         .parent_data = &(const struct clk_parent_data){
1699                                 .fw_name = "pcie_0_pipe_clk", .name = "pcie_0_pipe_clk",
1700                         },
1701                         .num_parents = 1,
1702                         .flags = CLK_SET_RATE_PARENT,
1703                         .ops = &clk_branch2_ops,
1704                 },
1705         },
1706 };
1707
1708 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1709         .halt_reg = 0x6b010,
1710         .halt_check = BRANCH_HALT_VOTED,
1711         .hwcg_reg = 0x6b010,
1712         .hwcg_bit = 1,
1713         .clkr = {
1714                 .enable_reg = 0x5200c,
1715                 .enable_mask = BIT(0),
1716                 .hw.init = &(struct clk_init_data){
1717                         .name = "gcc_pcie_0_slv_axi_clk",
1718                         .ops = &clk_branch2_ops,
1719                 },
1720         },
1721 };
1722
1723 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1724         .halt_reg = 0x6b00c,
1725         .halt_check = BRANCH_HALT_VOTED,
1726         .clkr = {
1727                 .enable_reg = 0x5200c,
1728                 .enable_mask = BIT(5),
1729                 .hw.init = &(struct clk_init_data){
1730                         .name = "gcc_pcie_0_slv_q2a_axi_clk",
1731                         .ops = &clk_branch2_ops,
1732                 },
1733         },
1734 };
1735
1736 static struct clk_branch gcc_pcie_1_aux_clk = {
1737         .halt_reg = 0x8d01c,
1738         .halt_check = BRANCH_HALT_VOTED,
1739         .clkr = {
1740                 .enable_reg = 0x52004,
1741                 .enable_mask = BIT(29),
1742                 .hw.init = &(struct clk_init_data){
1743                         .name = "gcc_pcie_1_aux_clk",
1744                         .parent_hws = (const struct clk_hw*[]){
1745                                 &gcc_pcie_1_aux_clk_src.clkr.hw,
1746                         },
1747                         .num_parents = 1,
1748                         .flags = CLK_SET_RATE_PARENT,
1749                         .ops = &clk_branch2_ops,
1750                 },
1751         },
1752 };
1753
1754 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1755         .halt_reg = 0x8d018,
1756         .halt_check = BRANCH_HALT_VOTED,
1757         .hwcg_reg = 0x8d018,
1758         .hwcg_bit = 1,
1759         .clkr = {
1760                 .enable_reg = 0x52004,
1761                 .enable_mask = BIT(28),
1762                 .hw.init = &(struct clk_init_data){
1763                         .name = "gcc_pcie_1_cfg_ahb_clk",
1764                         .ops = &clk_branch2_ops,
1765                 },
1766         },
1767 };
1768
1769 static struct clk_branch gcc_pcie_1_clkref_clk = {
1770         .halt_reg = 0x8c02c,
1771         .halt_check = BRANCH_HALT,
1772         .clkr = {
1773                 .enable_reg = 0x8c02c,
1774                 .enable_mask = BIT(0),
1775                 .hw.init = &(struct clk_init_data){
1776                         .name = "gcc_pcie_1_clkref_clk",
1777                         .ops = &clk_branch2_ops,
1778                 },
1779         },
1780 };
1781
1782 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1783         .halt_reg = 0x8d014,
1784         .halt_check = BRANCH_HALT_VOTED,
1785         .clkr = {
1786                 .enable_reg = 0x52004,
1787                 .enable_mask = BIT(27),
1788                 .hw.init = &(struct clk_init_data){
1789                         .name = "gcc_pcie_1_mstr_axi_clk",
1790                         .ops = &clk_branch2_ops,
1791                 },
1792         },
1793 };
1794
1795 static struct clk_branch gcc_pcie_1_pipe_clk = {
1796         .halt_check = BRANCH_HALT_SKIP,
1797         .clkr = {
1798                 .enable_reg = 0x52004,
1799                 .enable_mask = BIT(30),
1800                 .hw.init = &(struct clk_init_data){
1801                         .name = "gcc_pcie_1_pipe_clk",
1802                         .parent_data = &(const struct clk_parent_data){
1803                                 .fw_name = "pcie_1_pipe_clk", .name = "pcie_1_pipe_clk",
1804                         },
1805                         .num_parents = 1,
1806                         .ops = &clk_branch2_ops,
1807                 },
1808         },
1809 };
1810
1811 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1812         .halt_reg = 0x8d010,
1813         .halt_check = BRANCH_HALT_VOTED,
1814         .hwcg_reg = 0x8d010,
1815         .hwcg_bit = 1,
1816         .clkr = {
1817                 .enable_reg = 0x52004,
1818                 .enable_mask = BIT(26),
1819                 .hw.init = &(struct clk_init_data){
1820                         .name = "gcc_pcie_1_slv_axi_clk",
1821                         .ops = &clk_branch2_ops,
1822                 },
1823         },
1824 };
1825
1826 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
1827         .halt_reg = 0x8d00c,
1828         .halt_check = BRANCH_HALT_VOTED,
1829         .clkr = {
1830                 .enable_reg = 0x52004,
1831                 .enable_mask = BIT(25),
1832                 .hw.init = &(struct clk_init_data){
1833                         .name = "gcc_pcie_1_slv_q2a_axi_clk",
1834                         .ops = &clk_branch2_ops,
1835                 },
1836         },
1837 };
1838
1839 static struct clk_branch gcc_pcie_phy_aux_clk = {
1840         .halt_reg = 0x6f004,
1841         .halt_check = BRANCH_HALT,
1842         .clkr = {
1843                 .enable_reg = 0x6f004,
1844                 .enable_mask = BIT(0),
1845                 .hw.init = &(struct clk_init_data){
1846                         .name = "gcc_pcie_phy_aux_clk",
1847                         .parent_hws = (const struct clk_hw*[]){
1848                                 &gcc_pcie_0_aux_clk_src.clkr.hw,
1849                         },
1850                         .num_parents = 1,
1851                         .flags = CLK_SET_RATE_PARENT,
1852                         .ops = &clk_branch2_ops,
1853                 },
1854         },
1855 };
1856
1857 static struct clk_branch gcc_pcie_phy_refgen_clk = {
1858         .halt_reg = 0x6f02c,
1859         .halt_check = BRANCH_HALT,
1860         .clkr = {
1861                 .enable_reg = 0x6f02c,
1862                 .enable_mask = BIT(0),
1863                 .hw.init = &(struct clk_init_data){
1864                         .name = "gcc_pcie_phy_refgen_clk",
1865                         .parent_hws = (const struct clk_hw*[]){
1866                                 &gcc_pcie_phy_refgen_clk_src.clkr.hw,
1867                         },
1868                         .num_parents = 1,
1869                         .flags = CLK_SET_RATE_PARENT,
1870                         .ops = &clk_branch2_ops,
1871                 },
1872         },
1873 };
1874
1875 static struct clk_branch gcc_pdm2_clk = {
1876         .halt_reg = 0x3300c,
1877         .halt_check = BRANCH_HALT,
1878         .clkr = {
1879                 .enable_reg = 0x3300c,
1880                 .enable_mask = BIT(0),
1881                 .hw.init = &(struct clk_init_data){
1882                         .name = "gcc_pdm2_clk",
1883                         .parent_hws = (const struct clk_hw*[]){
1884                                 &gcc_pdm2_clk_src.clkr.hw,
1885                         },
1886                         .num_parents = 1,
1887                         .flags = CLK_SET_RATE_PARENT,
1888                         .ops = &clk_branch2_ops,
1889                 },
1890         },
1891 };
1892
1893 static struct clk_branch gcc_pdm_ahb_clk = {
1894         .halt_reg = 0x33004,
1895         .halt_check = BRANCH_HALT,
1896         .hwcg_reg = 0x33004,
1897         .hwcg_bit = 1,
1898         .clkr = {
1899                 .enable_reg = 0x33004,
1900                 .enable_mask = BIT(0),
1901                 .hw.init = &(struct clk_init_data){
1902                         .name = "gcc_pdm_ahb_clk",
1903                         .ops = &clk_branch2_ops,
1904                 },
1905         },
1906 };
1907
1908 static struct clk_branch gcc_pdm_xo4_clk = {
1909         .halt_reg = 0x33008,
1910         .halt_check = BRANCH_HALT,
1911         .clkr = {
1912                 .enable_reg = 0x33008,
1913                 .enable_mask = BIT(0),
1914                 .hw.init = &(struct clk_init_data){
1915                         .name = "gcc_pdm_xo4_clk",
1916                         .ops = &clk_branch2_ops,
1917                 },
1918         },
1919 };
1920
1921 static struct clk_branch gcc_prng_ahb_clk = {
1922         .halt_reg = 0x34004,
1923         .halt_check = BRANCH_HALT_VOTED,
1924         .hwcg_reg = 0x34004,
1925         .hwcg_bit = 1,
1926         .clkr = {
1927                 .enable_reg = 0x52004,
1928                 .enable_mask = BIT(13),
1929                 .hw.init = &(struct clk_init_data){
1930                         .name = "gcc_prng_ahb_clk",
1931                         .ops = &clk_branch2_ops,
1932                 },
1933         },
1934 };
1935
1936 static struct clk_branch gcc_qmip_camera_ahb_clk = {
1937         .halt_reg = 0xb014,
1938         .halt_check = BRANCH_HALT,
1939         .hwcg_reg = 0xb014,
1940         .hwcg_bit = 1,
1941         .clkr = {
1942                 .enable_reg = 0xb014,
1943                 .enable_mask = BIT(0),
1944                 .hw.init = &(struct clk_init_data){
1945                         .name = "gcc_qmip_camera_ahb_clk",
1946                         .ops = &clk_branch2_ops,
1947                 },
1948         },
1949 };
1950
1951 static struct clk_branch gcc_qmip_disp_ahb_clk = {
1952         .halt_reg = 0xb018,
1953         .halt_check = BRANCH_HALT,
1954         .hwcg_reg = 0xb018,
1955         .hwcg_bit = 1,
1956         .clkr = {
1957                 .enable_reg = 0xb018,
1958                 .enable_mask = BIT(0),
1959                 .hw.init = &(struct clk_init_data){
1960                         .name = "gcc_qmip_disp_ahb_clk",
1961                         .ops = &clk_branch2_ops,
1962                 },
1963         },
1964 };
1965
1966 static struct clk_branch gcc_qmip_video_ahb_clk = {
1967         .halt_reg = 0xb010,
1968         .halt_check = BRANCH_HALT,
1969         .hwcg_reg = 0xb010,
1970         .hwcg_bit = 1,
1971         .clkr = {
1972                 .enable_reg = 0xb010,
1973                 .enable_mask = BIT(0),
1974                 .hw.init = &(struct clk_init_data){
1975                         .name = "gcc_qmip_video_ahb_clk",
1976                         .ops = &clk_branch2_ops,
1977                 },
1978         },
1979 };
1980
1981 static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
1982         .halt_reg = 0x4b000,
1983         .halt_check = BRANCH_HALT,
1984         .clkr = {
1985                 .enable_reg = 0x4b000,
1986                 .enable_mask = BIT(0),
1987                 .hw.init = &(struct clk_init_data){
1988                         .name = "gcc_qspi_cnoc_periph_ahb_clk",
1989                         .ops = &clk_branch2_ops,
1990                 },
1991         },
1992 };
1993
1994 static struct clk_branch gcc_qspi_core_clk = {
1995         .halt_reg = 0x4b004,
1996         .halt_check = BRANCH_HALT,
1997         .clkr = {
1998                 .enable_reg = 0x4b004,
1999                 .enable_mask = BIT(0),
2000                 .hw.init = &(struct clk_init_data){
2001                         .name = "gcc_qspi_core_clk",
2002                         .parent_hws = (const struct clk_hw*[]){
2003                                 &gcc_qspi_core_clk_src.clkr.hw,
2004                         },
2005                         .num_parents = 1,
2006                         .flags = CLK_SET_RATE_PARENT,
2007                         .ops = &clk_branch2_ops,
2008                 },
2009         },
2010 };
2011
2012 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2013         .halt_reg = 0x17030,
2014         .halt_check = BRANCH_HALT_VOTED,
2015         .clkr = {
2016                 .enable_reg = 0x5200c,
2017                 .enable_mask = BIT(10),
2018                 .hw.init = &(struct clk_init_data){
2019                         .name = "gcc_qupv3_wrap0_s0_clk",
2020                         .parent_hws = (const struct clk_hw*[]){
2021                                 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
2022                         },
2023                         .num_parents = 1,
2024                         .flags = CLK_SET_RATE_PARENT,
2025                         .ops = &clk_branch2_ops,
2026                 },
2027         },
2028 };
2029
2030 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2031         .halt_reg = 0x17160,
2032         .halt_check = BRANCH_HALT_VOTED,
2033         .clkr = {
2034                 .enable_reg = 0x5200c,
2035                 .enable_mask = BIT(11),
2036                 .hw.init = &(struct clk_init_data){
2037                         .name = "gcc_qupv3_wrap0_s1_clk",
2038                         .parent_hws = (const struct clk_hw*[]){
2039                                 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
2040                         },
2041                         .num_parents = 1,
2042                         .flags = CLK_SET_RATE_PARENT,
2043                         .ops = &clk_branch2_ops,
2044                 },
2045         },
2046 };
2047
2048 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2049         .halt_reg = 0x17290,
2050         .halt_check = BRANCH_HALT_VOTED,
2051         .clkr = {
2052                 .enable_reg = 0x5200c,
2053                 .enable_mask = BIT(12),
2054                 .hw.init = &(struct clk_init_data){
2055                         .name = "gcc_qupv3_wrap0_s2_clk",
2056                         .parent_hws = (const struct clk_hw*[]){
2057                                 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
2058                         },
2059                         .num_parents = 1,
2060                         .flags = CLK_SET_RATE_PARENT,
2061                         .ops = &clk_branch2_ops,
2062                 },
2063         },
2064 };
2065
2066 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2067         .halt_reg = 0x173c0,
2068         .halt_check = BRANCH_HALT_VOTED,
2069         .clkr = {
2070                 .enable_reg = 0x5200c,
2071                 .enable_mask = BIT(13),
2072                 .hw.init = &(struct clk_init_data){
2073                         .name = "gcc_qupv3_wrap0_s3_clk",
2074                         .parent_hws = (const struct clk_hw*[]){
2075                                 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
2076                         },
2077                         .num_parents = 1,
2078                         .flags = CLK_SET_RATE_PARENT,
2079                         .ops = &clk_branch2_ops,
2080                 },
2081         },
2082 };
2083
2084 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2085         .halt_reg = 0x174f0,
2086         .halt_check = BRANCH_HALT_VOTED,
2087         .clkr = {
2088                 .enable_reg = 0x5200c,
2089                 .enable_mask = BIT(14),
2090                 .hw.init = &(struct clk_init_data){
2091                         .name = "gcc_qupv3_wrap0_s4_clk",
2092                         .parent_hws = (const struct clk_hw*[]){
2093                                 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
2094                         },
2095                         .num_parents = 1,
2096                         .flags = CLK_SET_RATE_PARENT,
2097                         .ops = &clk_branch2_ops,
2098                 },
2099         },
2100 };
2101
2102 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2103         .halt_reg = 0x17620,
2104         .halt_check = BRANCH_HALT_VOTED,
2105         .clkr = {
2106                 .enable_reg = 0x5200c,
2107                 .enable_mask = BIT(15),
2108                 .hw.init = &(struct clk_init_data){
2109                         .name = "gcc_qupv3_wrap0_s5_clk",
2110                         .parent_hws = (const struct clk_hw*[]){
2111                                 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
2112                         },
2113                         .num_parents = 1,
2114                         .flags = CLK_SET_RATE_PARENT,
2115                         .ops = &clk_branch2_ops,
2116                 },
2117         },
2118 };
2119
2120 static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2121         .halt_reg = 0x17750,
2122         .halt_check = BRANCH_HALT_VOTED,
2123         .clkr = {
2124                 .enable_reg = 0x5200c,
2125                 .enable_mask = BIT(16),
2126                 .hw.init = &(struct clk_init_data){
2127                         .name = "gcc_qupv3_wrap0_s6_clk",
2128                         .parent_hws = (const struct clk_hw*[]){
2129                                 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
2130                         },
2131                         .num_parents = 1,
2132                         .flags = CLK_SET_RATE_PARENT,
2133                         .ops = &clk_branch2_ops,
2134                 },
2135         },
2136 };
2137
2138 static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2139         .halt_reg = 0x17880,
2140         .halt_check = BRANCH_HALT_VOTED,
2141         .clkr = {
2142                 .enable_reg = 0x5200c,
2143                 .enable_mask = BIT(17),
2144                 .hw.init = &(struct clk_init_data){
2145                         .name = "gcc_qupv3_wrap0_s7_clk",
2146                         .parent_hws = (const struct clk_hw*[]){
2147                                 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
2148                         },
2149                         .num_parents = 1,
2150                         .flags = CLK_SET_RATE_PARENT,
2151                         .ops = &clk_branch2_ops,
2152                 },
2153         },
2154 };
2155
2156 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2157         .halt_reg = 0x18014,
2158         .halt_check = BRANCH_HALT_VOTED,
2159         .clkr = {
2160                 .enable_reg = 0x5200c,
2161                 .enable_mask = BIT(22),
2162                 .hw.init = &(struct clk_init_data){
2163                         .name = "gcc_qupv3_wrap1_s0_clk",
2164                         .parent_hws = (const struct clk_hw*[]){
2165                                 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
2166                         },
2167                         .num_parents = 1,
2168                         .flags = CLK_SET_RATE_PARENT,
2169                         .ops = &clk_branch2_ops,
2170                 },
2171         },
2172 };
2173
2174 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2175         .halt_reg = 0x18144,
2176         .halt_check = BRANCH_HALT_VOTED,
2177         .clkr = {
2178                 .enable_reg = 0x5200c,
2179                 .enable_mask = BIT(23),
2180                 .hw.init = &(struct clk_init_data){
2181                         .name = "gcc_qupv3_wrap1_s1_clk",
2182                         .parent_hws = (const struct clk_hw*[]){
2183                                 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
2184                         },
2185                         .num_parents = 1,
2186                         .flags = CLK_SET_RATE_PARENT,
2187                         .ops = &clk_branch2_ops,
2188                 },
2189         },
2190 };
2191
2192 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2193         .halt_reg = 0x18274,
2194         .halt_check = BRANCH_HALT_VOTED,
2195         .clkr = {
2196                 .enable_reg = 0x5200c,
2197                 .enable_mask = BIT(24),
2198                 .hw.init = &(struct clk_init_data){
2199                         .name = "gcc_qupv3_wrap1_s2_clk",
2200                         .parent_hws = (const struct clk_hw*[]){
2201                                 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
2202                         },
2203                         .num_parents = 1,
2204                         .flags = CLK_SET_RATE_PARENT,
2205                         .ops = &clk_branch2_ops,
2206                 },
2207         },
2208 };
2209
2210 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2211         .halt_reg = 0x183a4,
2212         .halt_check = BRANCH_HALT_VOTED,
2213         .clkr = {
2214                 .enable_reg = 0x5200c,
2215                 .enable_mask = BIT(25),
2216                 .hw.init = &(struct clk_init_data){
2217                         .name = "gcc_qupv3_wrap1_s3_clk",
2218                         .parent_hws = (const struct clk_hw*[]){
2219                                 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
2220                         },
2221                         .num_parents = 1,
2222                         .flags = CLK_SET_RATE_PARENT,
2223                         .ops = &clk_branch2_ops,
2224                 },
2225         },
2226 };
2227
2228 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2229         .halt_reg = 0x184d4,
2230         .halt_check = BRANCH_HALT_VOTED,
2231         .clkr = {
2232                 .enable_reg = 0x5200c,
2233                 .enable_mask = BIT(26),
2234                 .hw.init = &(struct clk_init_data){
2235                         .name = "gcc_qupv3_wrap1_s4_clk",
2236                         .parent_hws = (const struct clk_hw*[]){
2237                                 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
2238                         },
2239                         .num_parents = 1,
2240                         .flags = CLK_SET_RATE_PARENT,
2241                         .ops = &clk_branch2_ops,
2242                 },
2243         },
2244 };
2245
2246 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2247         .halt_reg = 0x18604,
2248         .halt_check = BRANCH_HALT_VOTED,
2249         .clkr = {
2250                 .enable_reg = 0x5200c,
2251                 .enable_mask = BIT(27),
2252                 .hw.init = &(struct clk_init_data){
2253                         .name = "gcc_qupv3_wrap1_s5_clk",
2254                         .parent_hws = (const struct clk_hw*[]){
2255                                 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
2256                         },
2257                         .num_parents = 1,
2258                         .flags = CLK_SET_RATE_PARENT,
2259                         .ops = &clk_branch2_ops,
2260                 },
2261         },
2262 };
2263
2264 static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
2265         .halt_reg = 0x18734,
2266         .halt_check = BRANCH_HALT_VOTED,
2267         .clkr = {
2268                 .enable_reg = 0x5200c,
2269                 .enable_mask = BIT(28),
2270                 .hw.init = &(struct clk_init_data){
2271                         .name = "gcc_qupv3_wrap1_s6_clk",
2272                         .parent_hws = (const struct clk_hw*[]){
2273                                 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
2274                         },
2275                         .num_parents = 1,
2276                         .flags = CLK_SET_RATE_PARENT,
2277                         .ops = &clk_branch2_ops,
2278                 },
2279         },
2280 };
2281
2282 static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
2283         .halt_reg = 0x18864,
2284         .halt_check = BRANCH_HALT_VOTED,
2285         .clkr = {
2286                 .enable_reg = 0x5200c,
2287                 .enable_mask = BIT(29),
2288                 .hw.init = &(struct clk_init_data){
2289                         .name = "gcc_qupv3_wrap1_s7_clk",
2290                         .parent_hws = (const struct clk_hw*[]){
2291                                 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
2292                         },
2293                         .num_parents = 1,
2294                         .flags = CLK_SET_RATE_PARENT,
2295                         .ops = &clk_branch2_ops,
2296                 },
2297         },
2298 };
2299
2300 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2301         .halt_reg = 0x17004,
2302         .halt_check = BRANCH_HALT_VOTED,
2303         .clkr = {
2304                 .enable_reg = 0x5200c,
2305                 .enable_mask = BIT(6),
2306                 .hw.init = &(struct clk_init_data){
2307                         .name = "gcc_qupv3_wrap_0_m_ahb_clk",
2308                         .ops = &clk_branch2_ops,
2309                 },
2310         },
2311 };
2312
2313 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2314         .halt_reg = 0x17008,
2315         .halt_check = BRANCH_HALT_VOTED,
2316         .hwcg_reg = 0x17008,
2317         .hwcg_bit = 1,
2318         .clkr = {
2319                 .enable_reg = 0x5200c,
2320                 .enable_mask = BIT(7),
2321                 .hw.init = &(struct clk_init_data){
2322                         .name = "gcc_qupv3_wrap_0_s_ahb_clk",
2323                         .ops = &clk_branch2_ops,
2324                 },
2325         },
2326 };
2327
2328 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2329         .halt_reg = 0x1800c,
2330         .halt_check = BRANCH_HALT_VOTED,
2331         .clkr = {
2332                 .enable_reg = 0x5200c,
2333                 .enable_mask = BIT(20),
2334                 .hw.init = &(struct clk_init_data){
2335                         .name = "gcc_qupv3_wrap_1_m_ahb_clk",
2336                         .ops = &clk_branch2_ops,
2337                 },
2338         },
2339 };
2340
2341 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2342         .halt_reg = 0x18010,
2343         .halt_check = BRANCH_HALT_VOTED,
2344         .hwcg_reg = 0x18010,
2345         .hwcg_bit = 1,
2346         .clkr = {
2347                 .enable_reg = 0x5200c,
2348                 .enable_mask = BIT(21),
2349                 .hw.init = &(struct clk_init_data){
2350                         .name = "gcc_qupv3_wrap_1_s_ahb_clk",
2351                         .ops = &clk_branch2_ops,
2352                 },
2353         },
2354 };
2355
2356 static struct clk_branch gcc_sdcc2_ahb_clk = {
2357         .halt_reg = 0x14008,
2358         .halt_check = BRANCH_HALT,
2359         .clkr = {
2360                 .enable_reg = 0x14008,
2361                 .enable_mask = BIT(0),
2362                 .hw.init = &(struct clk_init_data){
2363                         .name = "gcc_sdcc2_ahb_clk",
2364                         .ops = &clk_branch2_ops,
2365                 },
2366         },
2367 };
2368
2369 static struct clk_branch gcc_sdcc2_apps_clk = {
2370         .halt_reg = 0x14004,
2371         .halt_check = BRANCH_HALT,
2372         .clkr = {
2373                 .enable_reg = 0x14004,
2374                 .enable_mask = BIT(0),
2375                 .hw.init = &(struct clk_init_data){
2376                         .name = "gcc_sdcc2_apps_clk",
2377                         .parent_hws = (const struct clk_hw*[]){
2378                                 &gcc_sdcc2_apps_clk_src.clkr.hw,
2379                         },
2380                         .num_parents = 1,
2381                         .flags = CLK_SET_RATE_PARENT,
2382                         .ops = &clk_branch2_ops,
2383                 },
2384         },
2385 };
2386
2387 static struct clk_branch gcc_sdcc4_ahb_clk = {
2388         .halt_reg = 0x16008,
2389         .halt_check = BRANCH_HALT,
2390         .clkr = {
2391                 .enable_reg = 0x16008,
2392                 .enable_mask = BIT(0),
2393                 .hw.init = &(struct clk_init_data){
2394                         .name = "gcc_sdcc4_ahb_clk",
2395                         .ops = &clk_branch2_ops,
2396                 },
2397         },
2398 };
2399
2400 static struct clk_branch gcc_sdcc4_apps_clk = {
2401         .halt_reg = 0x16004,
2402         .halt_check = BRANCH_HALT,
2403         .clkr = {
2404                 .enable_reg = 0x16004,
2405                 .enable_mask = BIT(0),
2406                 .hw.init = &(struct clk_init_data){
2407                         .name = "gcc_sdcc4_apps_clk",
2408                         .parent_hws = (const struct clk_hw*[]){
2409                                 &gcc_sdcc4_apps_clk_src.clkr.hw,
2410                         },
2411                         .num_parents = 1,
2412                         .flags = CLK_SET_RATE_PARENT,
2413                         .ops = &clk_branch2_ops,
2414                 },
2415         },
2416 };
2417
2418 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
2419         .halt_reg = 0x414c,
2420         .halt_check = BRANCH_HALT_VOTED,
2421         .clkr = {
2422                 .enable_reg = 0x52004,
2423                 .enable_mask = BIT(0),
2424                 .hw.init = &(struct clk_init_data){
2425                         .name = "gcc_sys_noc_cpuss_ahb_clk",
2426                         .parent_hws = (const struct clk_hw*[]){
2427                                 &gcc_cpuss_ahb_clk_src.clkr.hw,
2428                         },
2429                         .num_parents = 1,
2430                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2431                         .ops = &clk_branch2_ops,
2432                 },
2433         },
2434 };
2435
2436 static struct clk_branch gcc_tsif_ahb_clk = {
2437         .halt_reg = 0x36004,
2438         .halt_check = BRANCH_HALT,
2439         .clkr = {
2440                 .enable_reg = 0x36004,
2441                 .enable_mask = BIT(0),
2442                 .hw.init = &(struct clk_init_data){
2443                         .name = "gcc_tsif_ahb_clk",
2444                         .ops = &clk_branch2_ops,
2445                 },
2446         },
2447 };
2448
2449 static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2450         .halt_reg = 0x3600c,
2451         .halt_check = BRANCH_HALT,
2452         .clkr = {
2453                 .enable_reg = 0x3600c,
2454                 .enable_mask = BIT(0),
2455                 .hw.init = &(struct clk_init_data){
2456                         .name = "gcc_tsif_inactivity_timers_clk",
2457                         .ops = &clk_branch2_ops,
2458                 },
2459         },
2460 };
2461
2462 static struct clk_branch gcc_tsif_ref_clk = {
2463         .halt_reg = 0x36008,
2464         .halt_check = BRANCH_HALT,
2465         .clkr = {
2466                 .enable_reg = 0x36008,
2467                 .enable_mask = BIT(0),
2468                 .hw.init = &(struct clk_init_data){
2469                         .name = "gcc_tsif_ref_clk",
2470                         .parent_hws = (const struct clk_hw*[]){
2471                                 &gcc_tsif_ref_clk_src.clkr.hw,
2472                         },
2473                         .num_parents = 1,
2474                         .flags = CLK_SET_RATE_PARENT,
2475                         .ops = &clk_branch2_ops,
2476                 },
2477         },
2478 };
2479
2480 static struct clk_branch gcc_ufs_card_ahb_clk = {
2481         .halt_reg = 0x75010,
2482         .halt_check = BRANCH_HALT,
2483         .hwcg_reg = 0x75010,
2484         .hwcg_bit = 1,
2485         .clkr = {
2486                 .enable_reg = 0x75010,
2487                 .enable_mask = BIT(0),
2488                 .hw.init = &(struct clk_init_data){
2489                         .name = "gcc_ufs_card_ahb_clk",
2490                         .ops = &clk_branch2_ops,
2491                 },
2492         },
2493 };
2494
2495 static struct clk_branch gcc_ufs_card_axi_clk = {
2496         .halt_reg = 0x7500c,
2497         .halt_check = BRANCH_HALT,
2498         .hwcg_reg = 0x7500c,
2499         .hwcg_bit = 1,
2500         .clkr = {
2501                 .enable_reg = 0x7500c,
2502                 .enable_mask = BIT(0),
2503                 .hw.init = &(struct clk_init_data){
2504                         .name = "gcc_ufs_card_axi_clk",
2505                         .parent_hws = (const struct clk_hw*[]){
2506                                 &gcc_ufs_card_axi_clk_src.clkr.hw,
2507                         },
2508                         .num_parents = 1,
2509                         .flags = CLK_SET_RATE_PARENT,
2510                         .ops = &clk_branch2_ops,
2511                 },
2512         },
2513 };
2514
2515 static struct clk_branch gcc_ufs_card_clkref_clk = {
2516         .halt_reg = 0x8c004,
2517         .halt_check = BRANCH_HALT,
2518         .clkr = {
2519                 .enable_reg = 0x8c004,
2520                 .enable_mask = BIT(0),
2521                 .hw.init = &(struct clk_init_data){
2522                         .name = "gcc_ufs_card_clkref_clk",
2523                         .ops = &clk_branch2_ops,
2524                 },
2525         },
2526 };
2527
2528 static struct clk_branch gcc_ufs_card_ice_core_clk = {
2529         .halt_reg = 0x75058,
2530         .halt_check = BRANCH_HALT,
2531         .hwcg_reg = 0x75058,
2532         .hwcg_bit = 1,
2533         .clkr = {
2534                 .enable_reg = 0x75058,
2535                 .enable_mask = BIT(0),
2536                 .hw.init = &(struct clk_init_data){
2537                         .name = "gcc_ufs_card_ice_core_clk",
2538                         .parent_hws = (const struct clk_hw*[]){
2539                                 &gcc_ufs_card_ice_core_clk_src.clkr.hw,
2540                         },
2541                         .num_parents = 1,
2542                         .flags = CLK_SET_RATE_PARENT,
2543                         .ops = &clk_branch2_ops,
2544                 },
2545         },
2546 };
2547
2548 static struct clk_branch gcc_ufs_card_phy_aux_clk = {
2549         .halt_reg = 0x7508c,
2550         .halt_check = BRANCH_HALT,
2551         .hwcg_reg = 0x7508c,
2552         .hwcg_bit = 1,
2553         .clkr = {
2554                 .enable_reg = 0x7508c,
2555                 .enable_mask = BIT(0),
2556                 .hw.init = &(struct clk_init_data){
2557                         .name = "gcc_ufs_card_phy_aux_clk",
2558                         .parent_hws = (const struct clk_hw*[]){
2559                                 &gcc_ufs_card_phy_aux_clk_src.clkr.hw,
2560                         },
2561                         .num_parents = 1,
2562                         .flags = CLK_SET_RATE_PARENT,
2563                         .ops = &clk_branch2_ops,
2564                 },
2565         },
2566 };
2567
2568 static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
2569         .halt_check = BRANCH_HALT_SKIP,
2570         .clkr = {
2571                 .enable_reg = 0x75018,
2572                 .enable_mask = BIT(0),
2573                 .hw.init = &(struct clk_init_data){
2574                         .name = "gcc_ufs_card_rx_symbol_0_clk",
2575                         .ops = &clk_branch2_ops,
2576                 },
2577         },
2578 };
2579
2580 static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
2581         .halt_check = BRANCH_HALT_SKIP,
2582         .clkr = {
2583                 .enable_reg = 0x750a8,
2584                 .enable_mask = BIT(0),
2585                 .hw.init = &(struct clk_init_data){
2586                         .name = "gcc_ufs_card_rx_symbol_1_clk",
2587                         .ops = &clk_branch2_ops,
2588                 },
2589         },
2590 };
2591
2592 static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
2593         .halt_check = BRANCH_HALT_SKIP,
2594         .clkr = {
2595                 .enable_reg = 0x75014,
2596                 .enable_mask = BIT(0),
2597                 .hw.init = &(struct clk_init_data){
2598                         .name = "gcc_ufs_card_tx_symbol_0_clk",
2599                         .ops = &clk_branch2_ops,
2600                 },
2601         },
2602 };
2603
2604 static struct clk_branch gcc_ufs_card_unipro_core_clk = {
2605         .halt_reg = 0x75054,
2606         .halt_check = BRANCH_HALT,
2607         .hwcg_reg = 0x75054,
2608         .hwcg_bit = 1,
2609         .clkr = {
2610                 .enable_reg = 0x75054,
2611                 .enable_mask = BIT(0),
2612                 .hw.init = &(struct clk_init_data){
2613                         .name = "gcc_ufs_card_unipro_core_clk",
2614                         .parent_hws = (const struct clk_hw*[]){
2615                                 &gcc_ufs_card_unipro_core_clk_src.clkr.hw,
2616                         },
2617                         .num_parents = 1,
2618                         .flags = CLK_SET_RATE_PARENT,
2619                         .ops = &clk_branch2_ops,
2620                 },
2621         },
2622 };
2623
2624 static struct clk_branch gcc_ufs_mem_clkref_clk = {
2625         .halt_reg = 0x8c000,
2626         .halt_check = BRANCH_HALT,
2627         .clkr = {
2628                 .enable_reg = 0x8c000,
2629                 .enable_mask = BIT(0),
2630                 .hw.init = &(struct clk_init_data){
2631                         .name = "gcc_ufs_mem_clkref_clk",
2632                         .ops = &clk_branch2_ops,
2633                 },
2634         },
2635 };
2636
2637 static struct clk_branch gcc_ufs_phy_ahb_clk = {
2638         .halt_reg = 0x77010,
2639         .halt_check = BRANCH_HALT,
2640         .hwcg_reg = 0x77010,
2641         .hwcg_bit = 1,
2642         .clkr = {
2643                 .enable_reg = 0x77010,
2644                 .enable_mask = BIT(0),
2645                 .hw.init = &(struct clk_init_data){
2646                         .name = "gcc_ufs_phy_ahb_clk",
2647                         .ops = &clk_branch2_ops,
2648                 },
2649         },
2650 };
2651
2652 static struct clk_branch gcc_ufs_phy_axi_clk = {
2653         .halt_reg = 0x7700c,
2654         .halt_check = BRANCH_HALT,
2655         .hwcg_reg = 0x7700c,
2656         .hwcg_bit = 1,
2657         .clkr = {
2658                 .enable_reg = 0x7700c,
2659                 .enable_mask = BIT(0),
2660                 .hw.init = &(struct clk_init_data){
2661                         .name = "gcc_ufs_phy_axi_clk",
2662                         .parent_hws = (const struct clk_hw*[]){
2663                                 &gcc_ufs_phy_axi_clk_src.clkr.hw,
2664                         },
2665                         .num_parents = 1,
2666                         .flags = CLK_SET_RATE_PARENT,
2667                         .ops = &clk_branch2_ops,
2668                 },
2669         },
2670 };
2671
2672 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2673         .halt_reg = 0x77058,
2674         .halt_check = BRANCH_HALT,
2675         .hwcg_reg = 0x77058,
2676         .hwcg_bit = 1,
2677         .clkr = {
2678                 .enable_reg = 0x77058,
2679                 .enable_mask = BIT(0),
2680                 .hw.init = &(struct clk_init_data){
2681                         .name = "gcc_ufs_phy_ice_core_clk",
2682                         .parent_hws = (const struct clk_hw*[]){
2683                                 &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2684                         },
2685                         .num_parents = 1,
2686                         .flags = CLK_SET_RATE_PARENT,
2687                         .ops = &clk_branch2_ops,
2688                 },
2689         },
2690 };
2691
2692 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2693         .halt_reg = 0x7708c,
2694         .halt_check = BRANCH_HALT,
2695         .hwcg_reg = 0x7708c,
2696         .hwcg_bit = 1,
2697         .clkr = {
2698                 .enable_reg = 0x7708c,
2699                 .enable_mask = BIT(0),
2700                 .hw.init = &(struct clk_init_data){
2701                         .name = "gcc_ufs_phy_phy_aux_clk",
2702                         .parent_hws = (const struct clk_hw*[]){
2703                                 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2704                         },
2705                         .num_parents = 1,
2706                         .flags = CLK_SET_RATE_PARENT,
2707                         .ops = &clk_branch2_ops,
2708                 },
2709         },
2710 };
2711
2712 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
2713         .halt_check = BRANCH_HALT_SKIP,
2714         .clkr = {
2715                 .enable_reg = 0x77018,
2716                 .enable_mask = BIT(0),
2717                 .hw.init = &(struct clk_init_data){
2718                         .name = "gcc_ufs_phy_rx_symbol_0_clk",
2719                         .ops = &clk_branch2_ops,
2720                 },
2721         },
2722 };
2723
2724 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
2725         .halt_check = BRANCH_HALT_SKIP,
2726         .clkr = {
2727                 .enable_reg = 0x770a8,
2728                 .enable_mask = BIT(0),
2729                 .hw.init = &(struct clk_init_data){
2730                         .name = "gcc_ufs_phy_rx_symbol_1_clk",
2731                         .ops = &clk_branch2_ops,
2732                 },
2733         },
2734 };
2735
2736 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
2737         .halt_check = BRANCH_HALT_SKIP,
2738         .clkr = {
2739                 .enable_reg = 0x77014,
2740                 .enable_mask = BIT(0),
2741                 .hw.init = &(struct clk_init_data){
2742                         .name = "gcc_ufs_phy_tx_symbol_0_clk",
2743                         .ops = &clk_branch2_ops,
2744                 },
2745         },
2746 };
2747
2748 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2749         .halt_reg = 0x77054,
2750         .halt_check = BRANCH_HALT,
2751         .hwcg_reg = 0x77054,
2752         .hwcg_bit = 1,
2753         .clkr = {
2754                 .enable_reg = 0x77054,
2755                 .enable_mask = BIT(0),
2756                 .hw.init = &(struct clk_init_data){
2757                         .name = "gcc_ufs_phy_unipro_core_clk",
2758                         .parent_hws = (const struct clk_hw*[]){
2759                                 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2760                         },
2761                         .num_parents = 1,
2762                         .flags = CLK_SET_RATE_PARENT,
2763                         .ops = &clk_branch2_ops,
2764                 },
2765         },
2766 };
2767
2768 static struct clk_branch gcc_usb30_prim_master_clk = {
2769         .halt_reg = 0xf00c,
2770         .halt_check = BRANCH_HALT,
2771         .clkr = {
2772                 .enable_reg = 0xf00c,
2773                 .enable_mask = BIT(0),
2774                 .hw.init = &(struct clk_init_data){
2775                         .name = "gcc_usb30_prim_master_clk",
2776                         .parent_hws = (const struct clk_hw*[]){
2777                                 &gcc_usb30_prim_master_clk_src.clkr.hw,
2778                         },
2779                         .num_parents = 1,
2780                         .flags = CLK_SET_RATE_PARENT,
2781                         .ops = &clk_branch2_ops,
2782                 },
2783         },
2784 };
2785
2786 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
2787         .halt_reg = 0xf014,
2788         .halt_check = BRANCH_HALT,
2789         .clkr = {
2790                 .enable_reg = 0xf014,
2791                 .enable_mask = BIT(0),
2792                 .hw.init = &(struct clk_init_data){
2793                         .name = "gcc_usb30_prim_mock_utmi_clk",
2794                         .parent_hws = (const struct clk_hw*[]){
2795                                 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
2796                         },
2797                         .num_parents = 1,
2798                         .flags = CLK_SET_RATE_PARENT,
2799                         .ops = &clk_branch2_ops,
2800                 },
2801         },
2802 };
2803
2804 static struct clk_branch gcc_usb30_prim_sleep_clk = {
2805         .halt_reg = 0xf010,
2806         .halt_check = BRANCH_HALT,
2807         .clkr = {
2808                 .enable_reg = 0xf010,
2809                 .enable_mask = BIT(0),
2810                 .hw.init = &(struct clk_init_data){
2811                         .name = "gcc_usb30_prim_sleep_clk",
2812                         .ops = &clk_branch2_ops,
2813                 },
2814         },
2815 };
2816
2817 static struct clk_branch gcc_usb30_sec_master_clk = {
2818         .halt_reg = 0x1000c,
2819         .halt_check = BRANCH_HALT,
2820         .clkr = {
2821                 .enable_reg = 0x1000c,
2822                 .enable_mask = BIT(0),
2823                 .hw.init = &(struct clk_init_data){
2824                         .name = "gcc_usb30_sec_master_clk",
2825                         .parent_hws = (const struct clk_hw*[]){
2826                                 &gcc_usb30_sec_master_clk_src.clkr.hw,
2827                         },
2828                         .num_parents = 1,
2829                         .flags = CLK_SET_RATE_PARENT,
2830                         .ops = &clk_branch2_ops,
2831                 },
2832         },
2833 };
2834
2835 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
2836         .halt_reg = 0x10014,
2837         .halt_check = BRANCH_HALT,
2838         .clkr = {
2839                 .enable_reg = 0x10014,
2840                 .enable_mask = BIT(0),
2841                 .hw.init = &(struct clk_init_data){
2842                         .name = "gcc_usb30_sec_mock_utmi_clk",
2843                         .parent_hws = (const struct clk_hw*[]){
2844                                 &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
2845                         },
2846                         .num_parents = 1,
2847                         .flags = CLK_SET_RATE_PARENT,
2848                         .ops = &clk_branch2_ops,
2849                 },
2850         },
2851 };
2852
2853 static struct clk_branch gcc_usb30_sec_sleep_clk = {
2854         .halt_reg = 0x10010,
2855         .halt_check = BRANCH_HALT,
2856         .clkr = {
2857                 .enable_reg = 0x10010,
2858                 .enable_mask = BIT(0),
2859                 .hw.init = &(struct clk_init_data){
2860                         .name = "gcc_usb30_sec_sleep_clk",
2861                         .ops = &clk_branch2_ops,
2862                 },
2863         },
2864 };
2865
2866 static struct clk_branch gcc_usb3_prim_clkref_clk = {
2867         .halt_reg = 0x8c008,
2868         .halt_check = BRANCH_HALT,
2869         .clkr = {
2870                 .enable_reg = 0x8c008,
2871                 .enable_mask = BIT(0),
2872                 .hw.init = &(struct clk_init_data){
2873                         .name = "gcc_usb3_prim_clkref_clk",
2874                         .ops = &clk_branch2_ops,
2875                 },
2876         },
2877 };
2878
2879 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
2880         .halt_reg = 0xf04c,
2881         .halt_check = BRANCH_HALT,
2882         .clkr = {
2883                 .enable_reg = 0xf04c,
2884                 .enable_mask = BIT(0),
2885                 .hw.init = &(struct clk_init_data){
2886                         .name = "gcc_usb3_prim_phy_aux_clk",
2887                         .parent_hws = (const struct clk_hw*[]){
2888                                 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2889                         },
2890                         .num_parents = 1,
2891                         .flags = CLK_SET_RATE_PARENT,
2892                         .ops = &clk_branch2_ops,
2893                 },
2894         },
2895 };
2896
2897 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
2898         .halt_reg = 0xf050,
2899         .halt_check = BRANCH_HALT,
2900         .clkr = {
2901                 .enable_reg = 0xf050,
2902                 .enable_mask = BIT(0),
2903                 .hw.init = &(struct clk_init_data){
2904                         .name = "gcc_usb3_prim_phy_com_aux_clk",
2905                         .parent_hws = (const struct clk_hw*[]){
2906                                 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2907                         },
2908                         .num_parents = 1,
2909                         .flags = CLK_SET_RATE_PARENT,
2910                         .ops = &clk_branch2_ops,
2911                 },
2912         },
2913 };
2914
2915 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
2916         .halt_check = BRANCH_HALT_SKIP,
2917         .clkr = {
2918                 .enable_reg = 0xf054,
2919                 .enable_mask = BIT(0),
2920                 .hw.init = &(struct clk_init_data){
2921                         .name = "gcc_usb3_prim_phy_pipe_clk",
2922                         .ops = &clk_branch2_ops,
2923                 },
2924         },
2925 };
2926
2927 static struct clk_branch gcc_usb3_sec_clkref_clk = {
2928         .halt_reg = 0x8c028,
2929         .halt_check = BRANCH_HALT,
2930         .clkr = {
2931                 .enable_reg = 0x8c028,
2932                 .enable_mask = BIT(0),
2933                 .hw.init = &(struct clk_init_data){
2934                         .name = "gcc_usb3_sec_clkref_clk",
2935                         .ops = &clk_branch2_ops,
2936                 },
2937         },
2938 };
2939
2940 static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
2941         .halt_reg = 0x1004c,
2942         .halt_check = BRANCH_HALT,
2943         .clkr = {
2944                 .enable_reg = 0x1004c,
2945                 .enable_mask = BIT(0),
2946                 .hw.init = &(struct clk_init_data){
2947                         .name = "gcc_usb3_sec_phy_aux_clk",
2948                         .parent_hws = (const struct clk_hw*[]){
2949                                 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
2950                         },
2951                         .num_parents = 1,
2952                         .flags = CLK_SET_RATE_PARENT,
2953                         .ops = &clk_branch2_ops,
2954                 },
2955         },
2956 };
2957
2958 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
2959         .halt_reg = 0x10050,
2960         .halt_check = BRANCH_HALT,
2961         .clkr = {
2962                 .enable_reg = 0x10050,
2963                 .enable_mask = BIT(0),
2964                 .hw.init = &(struct clk_init_data){
2965                         .name = "gcc_usb3_sec_phy_com_aux_clk",
2966                         .parent_hws = (const struct clk_hw*[]){
2967                                 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
2968                         },
2969                         .num_parents = 1,
2970                         .flags = CLK_SET_RATE_PARENT,
2971                         .ops = &clk_branch2_ops,
2972                 },
2973         },
2974 };
2975
2976 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
2977         .halt_check = BRANCH_HALT_SKIP,
2978         .clkr = {
2979                 .enable_reg = 0x10054,
2980                 .enable_mask = BIT(0),
2981                 .hw.init = &(struct clk_init_data){
2982                         .name = "gcc_usb3_sec_phy_pipe_clk",
2983                         .ops = &clk_branch2_ops,
2984                 },
2985         },
2986 };
2987
2988 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
2989         .halt_reg = 0x6a004,
2990         .halt_check = BRANCH_HALT,
2991         .hwcg_reg = 0x6a004,
2992         .hwcg_bit = 1,
2993         .clkr = {
2994                 .enable_reg = 0x6a004,
2995                 .enable_mask = BIT(0),
2996                 .hw.init = &(struct clk_init_data){
2997                         .name = "gcc_usb_phy_cfg_ahb2phy_clk",
2998                         .ops = &clk_branch2_ops,
2999                 },
3000         },
3001 };
3002
3003 static struct clk_branch gcc_vdda_vs_clk = {
3004         .halt_reg = 0x7a00c,
3005         .halt_check = BRANCH_HALT,
3006         .clkr = {
3007                 .enable_reg = 0x7a00c,
3008                 .enable_mask = BIT(0),
3009                 .hw.init = &(struct clk_init_data){
3010                         .name = "gcc_vdda_vs_clk",
3011                         .parent_hws = (const struct clk_hw*[]){
3012                                 &gcc_vsensor_clk_src.clkr.hw,
3013                         },
3014                         .num_parents = 1,
3015                         .flags = CLK_SET_RATE_PARENT,
3016                         .ops = &clk_branch2_ops,
3017                 },
3018         },
3019 };
3020
3021 static struct clk_branch gcc_vddcx_vs_clk = {
3022         .halt_reg = 0x7a004,
3023         .halt_check = BRANCH_HALT,
3024         .clkr = {
3025                 .enable_reg = 0x7a004,
3026                 .enable_mask = BIT(0),
3027                 .hw.init = &(struct clk_init_data){
3028                         .name = "gcc_vddcx_vs_clk",
3029                         .parent_hws = (const struct clk_hw*[]){
3030                                 &gcc_vsensor_clk_src.clkr.hw,
3031                         },
3032                         .num_parents = 1,
3033                         .flags = CLK_SET_RATE_PARENT,
3034                         .ops = &clk_branch2_ops,
3035                 },
3036         },
3037 };
3038
3039 static struct clk_branch gcc_vddmx_vs_clk = {
3040         .halt_reg = 0x7a008,
3041         .halt_check = BRANCH_HALT,
3042         .clkr = {
3043                 .enable_reg = 0x7a008,
3044                 .enable_mask = BIT(0),
3045                 .hw.init = &(struct clk_init_data){
3046                         .name = "gcc_vddmx_vs_clk",
3047                         .parent_hws = (const struct clk_hw*[]){
3048                                 &gcc_vsensor_clk_src.clkr.hw,
3049                         },
3050                         .num_parents = 1,
3051                         .flags = CLK_SET_RATE_PARENT,
3052                         .ops = &clk_branch2_ops,
3053                 },
3054         },
3055 };
3056
3057 static struct clk_branch gcc_video_ahb_clk = {
3058         .halt_reg = 0xb004,
3059         .halt_check = BRANCH_HALT,
3060         .hwcg_reg = 0xb004,
3061         .hwcg_bit = 1,
3062         .clkr = {
3063                 .enable_reg = 0xb004,
3064                 .enable_mask = BIT(0),
3065                 .hw.init = &(struct clk_init_data){
3066                         .name = "gcc_video_ahb_clk",
3067                         .flags = CLK_IS_CRITICAL,
3068                         .ops = &clk_branch2_ops,
3069                 },
3070         },
3071 };
3072
3073 static struct clk_branch gcc_video_axi_clk = {
3074         .halt_reg = 0xb01c,
3075         .halt_check = BRANCH_VOTED,
3076         .clkr = {
3077                 .enable_reg = 0xb01c,
3078                 .enable_mask = BIT(0),
3079                 .hw.init = &(struct clk_init_data){
3080                         .name = "gcc_video_axi_clk",
3081                         .ops = &clk_branch2_ops,
3082                 },
3083         },
3084 };
3085
3086 static struct clk_branch gcc_video_xo_clk = {
3087         .halt_reg = 0xb028,
3088         .halt_check = BRANCH_HALT,
3089         .clkr = {
3090                 .enable_reg = 0xb028,
3091                 .enable_mask = BIT(0),
3092                 .hw.init = &(struct clk_init_data){
3093                         .name = "gcc_video_xo_clk",
3094                         .flags = CLK_IS_CRITICAL,
3095                         .ops = &clk_branch2_ops,
3096                 },
3097         },
3098 };
3099
3100 static struct clk_branch gcc_vs_ctrl_ahb_clk = {
3101         .halt_reg = 0x7a014,
3102         .halt_check = BRANCH_HALT,
3103         .hwcg_reg = 0x7a014,
3104         .hwcg_bit = 1,
3105         .clkr = {
3106                 .enable_reg = 0x7a014,
3107                 .enable_mask = BIT(0),
3108                 .hw.init = &(struct clk_init_data){
3109                         .name = "gcc_vs_ctrl_ahb_clk",
3110                         .ops = &clk_branch2_ops,
3111                 },
3112         },
3113 };
3114
3115 static struct clk_branch gcc_vs_ctrl_clk = {
3116         .halt_reg = 0x7a010,
3117         .halt_check = BRANCH_HALT,
3118         .clkr = {
3119                 .enable_reg = 0x7a010,
3120                 .enable_mask = BIT(0),
3121                 .hw.init = &(struct clk_init_data){
3122                         .name = "gcc_vs_ctrl_clk",
3123                         .parent_hws = (const struct clk_hw*[]){
3124                                 &gcc_vs_ctrl_clk_src.clkr.hw,
3125                         },
3126                         .num_parents = 1,
3127                         .flags = CLK_SET_RATE_PARENT,
3128                         .ops = &clk_branch2_ops,
3129                 },
3130         },
3131 };
3132
3133 static struct clk_branch gcc_cpuss_dvm_bus_clk = {
3134         .halt_reg = 0x48190,
3135         .halt_check = BRANCH_HALT,
3136         .clkr = {
3137                 .enable_reg = 0x48190,
3138                 .enable_mask = BIT(0),
3139                 .hw.init = &(struct clk_init_data){
3140                         .name = "gcc_cpuss_dvm_bus_clk",
3141                         .flags = CLK_IS_CRITICAL,
3142                         .ops = &clk_branch2_ops,
3143                 },
3144         },
3145 };
3146
3147 static struct clk_branch gcc_cpuss_gnoc_clk = {
3148         .halt_reg = 0x48004,
3149         .halt_check = BRANCH_HALT_VOTED,
3150         .hwcg_reg = 0x48004,
3151         .hwcg_bit = 1,
3152         .clkr = {
3153                 .enable_reg = 0x52004,
3154                 .enable_mask = BIT(22),
3155                 .hw.init = &(struct clk_init_data){
3156                         .name = "gcc_cpuss_gnoc_clk",
3157                         .flags = CLK_IS_CRITICAL,
3158                         .ops = &clk_branch2_ops,
3159                 },
3160         },
3161 };
3162
3163 /* TODO: Remove after DTS updated to protect these */
3164 #ifdef CONFIG_SDM_LPASSCC_845
3165 static struct clk_branch gcc_lpass_q6_axi_clk = {
3166         .halt_reg = 0x47000,
3167         .halt_check = BRANCH_HALT,
3168         .clkr = {
3169                 .enable_reg = 0x47000,
3170                 .enable_mask = BIT(0),
3171                 .hw.init = &(struct clk_init_data){
3172                         .name = "gcc_lpass_q6_axi_clk",
3173                         .flags = CLK_IS_CRITICAL,
3174                         .ops = &clk_branch2_ops,
3175                 },
3176         },
3177 };
3178
3179 static struct clk_branch gcc_lpass_sway_clk = {
3180         .halt_reg = 0x47008,
3181         .halt_check = BRANCH_HALT,
3182         .clkr = {
3183                 .enable_reg = 0x47008,
3184                 .enable_mask = BIT(0),
3185                 .hw.init = &(struct clk_init_data){
3186                         .name = "gcc_lpass_sway_clk",
3187                         .flags = CLK_IS_CRITICAL,
3188                         .ops = &clk_branch2_ops,
3189                 },
3190         },
3191 };
3192 #endif
3193
3194 static struct gdsc pcie_0_gdsc = {
3195         .gdscr = 0x6b004,
3196         .pd = {
3197                 .name = "pcie_0_gdsc",
3198         },
3199         .pwrsts = PWRSTS_OFF_ON,
3200         .flags = POLL_CFG_GDSCR,
3201 };
3202
3203 static struct gdsc pcie_1_gdsc = {
3204         .gdscr = 0x8d004,
3205         .pd = {
3206                 .name = "pcie_1_gdsc",
3207         },
3208         .pwrsts = PWRSTS_OFF_ON,
3209         .flags = POLL_CFG_GDSCR,
3210 };
3211
3212 static struct gdsc ufs_card_gdsc = {
3213         .gdscr = 0x75004,
3214         .pd = {
3215                 .name = "ufs_card_gdsc",
3216         },
3217         .pwrsts = PWRSTS_OFF_ON,
3218         .flags = POLL_CFG_GDSCR,
3219 };
3220
3221 static struct gdsc ufs_phy_gdsc = {
3222         .gdscr = 0x77004,
3223         .pd = {
3224                 .name = "ufs_phy_gdsc",
3225         },
3226         .pwrsts = PWRSTS_OFF_ON,
3227         .flags = POLL_CFG_GDSCR,
3228 };
3229
3230 static struct gdsc usb30_prim_gdsc = {
3231         .gdscr = 0xf004,
3232         .pd = {
3233                 .name = "usb30_prim_gdsc",
3234         },
3235         .pwrsts = PWRSTS_OFF_ON,
3236         .flags = POLL_CFG_GDSCR,
3237 };
3238
3239 static struct gdsc usb30_sec_gdsc = {
3240         .gdscr = 0x10004,
3241         .pd = {
3242                 .name = "usb30_sec_gdsc",
3243         },
3244         .pwrsts = PWRSTS_OFF_ON,
3245         .flags = POLL_CFG_GDSCR,
3246 };
3247
3248 static struct gdsc hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc = {
3249         .gdscr = 0x7d030,
3250         .pd = {
3251                 .name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc",
3252         },
3253         .pwrsts = PWRSTS_OFF_ON,
3254         .flags = VOTABLE,
3255 };
3256
3257 static struct gdsc hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc = {
3258         .gdscr = 0x7d03c,
3259         .pd = {
3260                 .name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc",
3261         },
3262         .pwrsts = PWRSTS_OFF_ON,
3263         .flags = VOTABLE,
3264 };
3265
3266 static struct gdsc hlos1_vote_aggre_noc_mmu_tbu1_gdsc = {
3267         .gdscr = 0x7d034,
3268         .pd = {
3269                 .name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc",
3270         },
3271         .pwrsts = PWRSTS_OFF_ON,
3272         .flags = VOTABLE,
3273 };
3274
3275 static struct gdsc hlos1_vote_aggre_noc_mmu_tbu2_gdsc = {
3276         .gdscr = 0x7d038,
3277         .pd = {
3278                 .name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc",
3279         },
3280         .pwrsts = PWRSTS_OFF_ON,
3281         .flags = VOTABLE,
3282 };
3283
3284 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
3285         .gdscr = 0x7d040,
3286         .pd = {
3287                 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
3288         },
3289         .pwrsts = PWRSTS_OFF_ON,
3290         .flags = VOTABLE,
3291 };
3292
3293 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
3294         .gdscr = 0x7d048,
3295         .pd = {
3296                 .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
3297         },
3298         .pwrsts = PWRSTS_OFF_ON,
3299         .flags = VOTABLE,
3300 };
3301
3302 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = {
3303         .gdscr = 0x7d044,
3304         .pd = {
3305                 .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc",
3306         },
3307         .pwrsts = PWRSTS_OFF_ON,
3308         .flags = VOTABLE,
3309 };
3310
3311 static struct clk_regmap *gcc_sdm845_clocks[] = {
3312         [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
3313         [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
3314         [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3315         [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3316         [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
3317         [GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr,
3318         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3319         [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
3320         [GCC_CAMERA_AXI_CLK] = &gcc_camera_axi_clk.clkr,
3321         [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
3322         [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
3323         [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
3324         [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
3325         [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3326         [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
3327         [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
3328         [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
3329         [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
3330         [GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_cpuss_rbcpr_clk_src.clkr,
3331         [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3332         [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
3333         [GCC_DISP_AXI_CLK] = &gcc_disp_axi_clk.clkr,
3334         [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
3335         [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
3336         [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
3337         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3338         [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3339         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3340         [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3341         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3342         [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3343         [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
3344         [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3345         [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3346         [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
3347         [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3348         [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3349         [GCC_GPU_VS_CLK] = &gcc_gpu_vs_clk.clkr,
3350         [GCC_MSS_AXIS2_CLK] = &gcc_mss_axis2_clk.clkr,
3351         [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3352         [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr,
3353         [GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr,
3354         [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
3355         [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
3356         [GCC_MSS_VS_CLK] = &gcc_mss_vs_clk.clkr,
3357         [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3358         [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
3359         [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3360         [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
3361         [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3362         [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3363         [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3364         [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3365         [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3366         [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
3367         [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3368         [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr,
3369         [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3370         [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3371         [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3372         [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
3373         [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
3374         [GCC_PCIE_PHY_REFGEN_CLK] = &gcc_pcie_phy_refgen_clk.clkr,
3375         [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,
3376         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3377         [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3378         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3379         [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3380         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3381         [GCC_QMIP_CAMERA_AHB_CLK] = &gcc_qmip_camera_ahb_clk.clkr,
3382         [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3383         [GCC_QMIP_VIDEO_AHB_CLK] = &gcc_qmip_video_ahb_clk.clkr,
3384         [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3385         [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3386         [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3387         [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3388         [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3389         [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3390         [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3391         [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3392         [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3393         [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3394         [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3395         [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3396         [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3397         [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3398         [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3399         [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3400         [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3401         [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3402         [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3403         [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3404         [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3405         [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3406         [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3407         [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3408         [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3409         [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3410         [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3411         [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3412         [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
3413         [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
3414         [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
3415         [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
3416         [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3417         [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3418         [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3419         [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3420         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3421         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3422         [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3423         [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3424         [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3425         [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3426         [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
3427         [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3428         [GCC_TSIF_INACTIVITY_TIMERS_CLK] =
3429                                         &gcc_tsif_inactivity_timers_clk.clkr,
3430         [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3431         [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
3432         [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
3433         [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
3434         [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
3435         [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr,
3436         [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
3437         [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
3438         [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
3439         [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
3440         [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
3441         [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
3442         [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
3443         [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
3444         [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] =
3445                                         &gcc_ufs_card_unipro_core_clk_src.clkr,
3446         [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
3447         [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3448         [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3449         [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3450         [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3451         [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3452         [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3453         [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3454         [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3455         [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
3456         [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3457         [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3458         [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
3459                                         &gcc_ufs_phy_unipro_core_clk_src.clkr,
3460         [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3461         [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3462         [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3463         [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
3464                                         &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3465         [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3466         [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
3467         [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
3468         [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
3469         [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =
3470                                         &gcc_usb30_sec_mock_utmi_clk_src.clkr,
3471         [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
3472         [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
3473         [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3474         [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3475         [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3476         [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3477         [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,
3478         [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
3479         [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
3480         [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
3481         [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
3482         [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
3483         [GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr,
3484         [GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr,
3485         [GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr,
3486         [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
3487         [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
3488         [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
3489         [GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr,
3490         [GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr,
3491         [GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr,
3492         [GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr,
3493         [GPLL0] = &gpll0.clkr,
3494         [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
3495         [GPLL4] = &gpll4.clkr,
3496         [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
3497         [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
3498         [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
3499         [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
3500         [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
3501 #ifdef CONFIG_SDM_LPASSCC_845
3502         [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
3503         [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,
3504 #endif
3505 };
3506
3507 static const struct qcom_reset_map gcc_sdm845_resets[] = {
3508         [GCC_MMSS_BCR] = { 0xb000 },
3509         [GCC_PCIE_0_BCR] = { 0x6b000 },
3510         [GCC_PCIE_1_BCR] = { 0x8d000 },
3511         [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3512         [GCC_PDM_BCR] = { 0x33000 },
3513         [GCC_PRNG_BCR] = { 0x34000 },
3514         [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
3515         [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3516         [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3517         [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3518         [GCC_SDCC2_BCR] = { 0x14000 },
3519         [GCC_SDCC4_BCR] = { 0x16000 },
3520         [GCC_TSIF_BCR] = { 0x36000 },
3521         [GCC_UFS_CARD_BCR] = { 0x75000 },
3522         [GCC_UFS_PHY_BCR] = { 0x77000 },
3523         [GCC_USB30_PRIM_BCR] = { 0xf000 },
3524         [GCC_USB30_SEC_BCR] = { 0x10000 },
3525         [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3526         [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3527         [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3528         [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3529         [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3530         [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
3531         [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3532         [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3533         [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3534 };
3535
3536 static struct gdsc *gcc_sdm845_gdscs[] = {
3537         [PCIE_0_GDSC] = &pcie_0_gdsc,
3538         [PCIE_1_GDSC] = &pcie_1_gdsc,
3539         [UFS_CARD_GDSC] = &ufs_card_gdsc,
3540         [UFS_PHY_GDSC] = &ufs_phy_gdsc,
3541         [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
3542         [USB30_SEC_GDSC] = &usb30_sec_gdsc,
3543         [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] =
3544                         &hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc,
3545         [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] =
3546                         &hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc,
3547         [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] =
3548                         &hlos1_vote_aggre_noc_mmu_tbu1_gdsc,
3549         [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] =
3550                         &hlos1_vote_aggre_noc_mmu_tbu2_gdsc,
3551         [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =
3552                         &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
3553         [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] =
3554                         &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
3555         [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc,
3556 };
3557
3558 static const struct regmap_config gcc_sdm845_regmap_config = {
3559         .reg_bits       = 32,
3560         .reg_stride     = 4,
3561         .val_bits       = 32,
3562         .max_register   = 0x182090,
3563         .fast_io        = true,
3564 };
3565
3566 static const struct qcom_cc_desc gcc_sdm845_desc = {
3567         .config = &gcc_sdm845_regmap_config,
3568         .clks = gcc_sdm845_clocks,
3569         .num_clks = ARRAY_SIZE(gcc_sdm845_clocks),
3570         .resets = gcc_sdm845_resets,
3571         .num_resets = ARRAY_SIZE(gcc_sdm845_resets),
3572         .gdscs = gcc_sdm845_gdscs,
3573         .num_gdscs = ARRAY_SIZE(gcc_sdm845_gdscs),
3574 };
3575
3576 static const struct of_device_id gcc_sdm845_match_table[] = {
3577         { .compatible = "qcom,gcc-sdm845" },
3578         { }
3579 };
3580 MODULE_DEVICE_TABLE(of, gcc_sdm845_match_table);
3581
3582 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
3583         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
3584         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
3585         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
3586         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
3587         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
3588         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
3589         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
3590         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
3591         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
3592         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
3593         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
3594         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
3595         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
3596         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
3597         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
3598         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
3599 };
3600
3601 static int gcc_sdm845_probe(struct platform_device *pdev)
3602 {
3603         struct regmap *regmap;
3604         int ret;
3605
3606         regmap = qcom_cc_map(pdev, &gcc_sdm845_desc);
3607         if (IS_ERR(regmap))
3608                 return PTR_ERR(regmap);
3609
3610         /* Disable the GPLL0 active input to MMSS and GPU via MISC registers */
3611         regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
3612         regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
3613
3614         ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
3615                                         ARRAY_SIZE(gcc_dfs_clocks));
3616         if (ret)
3617                 return ret;
3618
3619         return qcom_cc_really_probe(pdev, &gcc_sdm845_desc, regmap);
3620 }
3621
3622 static struct platform_driver gcc_sdm845_driver = {
3623         .probe          = gcc_sdm845_probe,
3624         .driver         = {
3625                 .name   = "gcc-sdm845",
3626                 .of_match_table = gcc_sdm845_match_table,
3627         },
3628 };
3629
3630 static int __init gcc_sdm845_init(void)
3631 {
3632         return platform_driver_register(&gcc_sdm845_driver);
3633 }
3634 core_initcall(gcc_sdm845_init);
3635
3636 static void __exit gcc_sdm845_exit(void)
3637 {
3638         platform_driver_unregister(&gcc_sdm845_driver);
3639 }
3640 module_exit(gcc_sdm845_exit);
3641
3642 MODULE_DESCRIPTION("QTI GCC SDM845 Driver");
3643 MODULE_LICENSE("GPL v2");
3644 MODULE_ALIAS("platform:gcc-sdm845");