1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
6 #include <linux/clk-provider.h>
7 #include <linux/kernel.h>
8 #include <linux/module.h>
9 #include <linux/of_device.h>
11 #include <linux/regmap.h>
13 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
15 #include "clk-alpha-pll.h"
16 #include "clk-branch.h"
18 #include "clk-regmap-divider.h"
19 #include "clk-regmap-mux.h"
20 #include "clk-regmap-phy-mux.h"
30 P_GCC_GPLL10_OUT_MAIN,
36 P_UFS_PHY_RX_SYMBOL_0_CLK,
37 P_UFS_PHY_RX_SYMBOL_1_CLK,
38 P_UFS_PHY_TX_SYMBOL_0_CLK,
39 P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
40 P_GCC_MSS_GPLL0_MAIN_DIV_CLK,
43 static struct clk_alpha_pll gcc_gpll0 = {
45 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
47 .enable_reg = 0x52010,
48 .enable_mask = BIT(0),
49 .hw.init = &(struct clk_init_data){
51 .parent_data = &(const struct clk_parent_data){
55 .ops = &clk_alpha_pll_fixed_lucid_ops,
60 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
65 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
68 .post_div_table = post_div_table_gcc_gpll0_out_even,
69 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
71 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
72 .clkr.hw.init = &(struct clk_init_data){
73 .name = "gcc_gpll0_out_even",
74 .parent_hws = (const struct clk_hw*[]){
78 .ops = &clk_alpha_pll_postdiv_lucid_ops,
82 static const struct clk_div_table post_div_table_gcc_gpll0_out_odd[] = {
87 static struct clk_alpha_pll_postdiv gcc_gpll0_out_odd = {
90 .post_div_table = post_div_table_gcc_gpll0_out_odd,
91 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_odd),
93 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
94 .clkr.hw.init = &(struct clk_init_data){
95 .name = "gcc_gpll0_out_odd",
96 .parent_hws = (const struct clk_hw*[]){
100 .ops = &clk_alpha_pll_postdiv_lucid_ops,
104 static struct clk_alpha_pll gcc_gpll1 = {
106 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
108 .enable_reg = 0x52010,
109 .enable_mask = BIT(1),
110 .hw.init = &(struct clk_init_data){
112 .parent_data = &(const struct clk_parent_data){
113 .fw_name = "bi_tcxo",
116 .ops = &clk_alpha_pll_fixed_lucid_ops,
121 static struct clk_alpha_pll gcc_gpll10 = {
123 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
125 .enable_reg = 0x52010,
126 .enable_mask = BIT(9),
127 .hw.init = &(struct clk_init_data){
128 .name = "gcc_gpll10",
129 .parent_data = &(const struct clk_parent_data){
130 .fw_name = "bi_tcxo",
133 .ops = &clk_alpha_pll_fixed_lucid_ops,
138 static struct clk_alpha_pll gcc_gpll4 = {
140 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
142 .enable_reg = 0x52010,
143 .enable_mask = BIT(4),
144 .hw.init = &(struct clk_init_data){
146 .parent_data = &(const struct clk_parent_data){
147 .fw_name = "bi_tcxo",
150 .ops = &clk_alpha_pll_fixed_lucid_ops,
155 static struct clk_alpha_pll gcc_gpll9 = {
157 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
159 .enable_reg = 0x52010,
160 .enable_mask = BIT(8),
161 .hw.init = &(struct clk_init_data){
163 .parent_data = &(const struct clk_parent_data){
164 .fw_name = "bi_tcxo",
167 .ops = &clk_alpha_pll_fixed_lucid_ops,
172 static struct clk_branch gcc_mss_gpll0_main_div_clk_src = {
173 .halt_check = BRANCH_HALT_DELAY,
175 .enable_reg = 0x52000,
176 .enable_mask = BIT(17),
177 .hw.init = &(struct clk_init_data){
178 .name = "gcc_mss_gpll0_main_div_clk_src",
179 .parent_hws = (const struct clk_hw*[]){
180 &gcc_gpll0_out_even.clkr.hw,
183 .flags = CLK_SET_RATE_PARENT,
184 .ops = &clk_branch2_ops,
189 static const struct parent_map gcc_parent_map_0[] = {
191 { P_GCC_GPLL0_OUT_MAIN, 1 },
192 { P_GCC_GPLL0_OUT_EVEN, 6 },
195 static const struct clk_parent_data gcc_parent_data_0[] = {
196 { .fw_name = "bi_tcxo" },
197 { .hw = &gcc_gpll0.clkr.hw },
198 { .hw = &gcc_gpll0_out_even.clkr.hw },
201 static const struct parent_map gcc_parent_map_1[] = {
203 { P_GCC_GPLL0_OUT_MAIN, 1 },
204 { P_GCC_GPLL0_OUT_ODD, 3 },
205 { P_GCC_GPLL0_OUT_EVEN, 6 },
208 static const struct clk_parent_data gcc_parent_data_1[] = {
209 { .fw_name = "bi_tcxo" },
210 { .hw = &gcc_gpll0.clkr.hw },
211 { .hw = &gcc_gpll0_out_odd.clkr.hw },
212 { .hw = &gcc_gpll0_out_even.clkr.hw },
215 static const struct parent_map gcc_parent_map_2[] = {
220 static const struct clk_parent_data gcc_parent_data_2[] = {
221 { .fw_name = "bi_tcxo" },
222 { .fw_name = "sleep_clk" },
225 static const struct parent_map gcc_parent_map_3[] = {
229 static const struct clk_parent_data gcc_parent_data_3[] = {
230 { .fw_name = "bi_tcxo" },
233 static const struct parent_map gcc_parent_map_4[] = {
235 { P_GCC_GPLL0_OUT_MAIN, 1 },
236 { P_GCC_GPLL0_OUT_ODD, 3 },
238 { P_GCC_GPLL0_OUT_EVEN, 6 },
241 static const struct clk_parent_data gcc_parent_data_4[] = {
242 { .fw_name = "bi_tcxo" },
243 { .hw = &gcc_gpll0.clkr.hw },
244 { .hw = &gcc_gpll0_out_odd.clkr.hw },
245 { .fw_name = "sleep_clk" },
246 { .hw = &gcc_gpll0_out_even.clkr.hw },
249 static const struct parent_map gcc_parent_map_5[] = {
251 { P_GCC_GPLL0_OUT_EVEN, 6 },
254 static const struct clk_parent_data gcc_parent_data_5[] = {
255 { .fw_name = "bi_tcxo" },
256 { .hw = &gcc_gpll0_out_even.clkr.hw },
259 static const struct parent_map gcc_parent_map_8[] = {
261 { P_GCC_GPLL0_OUT_MAIN, 1 },
262 { P_GCC_GPLL0_OUT_ODD, 3 },
263 { P_GCC_GPLL10_OUT_MAIN, 5 },
264 { P_GCC_GPLL0_OUT_EVEN, 6 },
267 static const struct clk_parent_data gcc_parent_data_8[] = {
268 { .fw_name = "bi_tcxo" },
269 { .hw = &gcc_gpll0.clkr.hw },
270 { .hw = &gcc_gpll0_out_odd.clkr.hw },
271 { .hw = &gcc_gpll10.clkr.hw },
272 { .hw = &gcc_gpll0_out_even.clkr.hw },
275 static const struct parent_map gcc_parent_map_9[] = {
277 { P_GCC_GPLL0_OUT_MAIN, 1 },
278 { P_GCC_GPLL9_OUT_MAIN, 2 },
279 { P_GCC_GPLL0_OUT_ODD, 3 },
280 { P_GCC_GPLL4_OUT_MAIN, 5 },
281 { P_GCC_GPLL0_OUT_EVEN, 6 },
284 static const struct clk_parent_data gcc_parent_data_9[] = {
285 { .fw_name = "bi_tcxo" },
286 { .hw = &gcc_gpll0.clkr.hw },
287 { .hw = &gcc_gpll9.clkr.hw },
288 { .hw = &gcc_gpll0_out_odd.clkr.hw },
289 { .hw = &gcc_gpll4.clkr.hw },
290 { .hw = &gcc_gpll0_out_even.clkr.hw },
293 static const struct parent_map gcc_parent_map_10[] = {
294 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
298 static const struct clk_parent_data gcc_parent_data_10[] = {
299 { .fw_name = "ufs_phy_rx_symbol_0_clk" },
300 { .fw_name = "bi_tcxo" },
303 static const struct parent_map gcc_parent_map_11[] = {
304 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
308 static const struct clk_parent_data gcc_parent_data_11[] = {
309 { .fw_name = "ufs_phy_rx_symbol_1_clk" },
310 { .fw_name = "bi_tcxo" },
313 static const struct parent_map gcc_parent_map_12[] = {
314 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
318 static const struct clk_parent_data gcc_parent_data_12[] = {
319 { .fw_name = "ufs_phy_tx_symbol_0_clk" },
320 { .fw_name = "bi_tcxo" },
323 static const struct parent_map gcc_parent_map_13[] = {
324 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
328 static const struct clk_parent_data gcc_parent_data_13[] = {
329 { .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" },
330 { .fw_name = "bi_tcxo" },
333 static const struct parent_map gcc_parent_map_14[] = {
334 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
338 static const struct clk_parent_data gcc_parent_data_14[] = {
339 { .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" },
340 { .fw_name = "bi_tcxo" },
343 static const struct parent_map gcc_parent_map_15[] = {
345 { P_GCC_MSS_GPLL0_MAIN_DIV_CLK, 1 },
348 static const struct clk_parent_data gcc_parent_data_15[] = {
349 { .fw_name = "bi_tcxo" },
350 { .hw = &gcc_mss_gpll0_main_div_clk_src.clkr.hw },
353 static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
356 .hw.init = &(struct clk_init_data){
357 .name = "gcc_pcie_0_pipe_clk_src",
358 .parent_data = &(const struct clk_parent_data){
359 .fw_name = "pcie_0_pipe_clk",
360 .name = "pcie_0_pipe_clk",
363 .ops = &clk_regmap_phy_mux_ops,
368 static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {
371 .hw.init = &(struct clk_init_data){
372 .name = "gcc_pcie_1_pipe_clk_src",
373 .parent_data = &(const struct clk_parent_data){
374 .fw_name = "pcie_1_pipe_clk",
375 .name = "pcie_1_pipe_clk",
378 .ops = &clk_regmap_phy_mux_ops,
383 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
387 .parent_map = gcc_parent_map_10,
389 .hw.init = &(struct clk_init_data){
390 .name = "gcc_ufs_phy_rx_symbol_0_clk_src",
391 .parent_data = gcc_parent_data_10,
392 .num_parents = ARRAY_SIZE(gcc_parent_data_10),
393 .ops = &clk_regmap_mux_closest_ops,
398 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
402 .parent_map = gcc_parent_map_11,
404 .hw.init = &(struct clk_init_data){
405 .name = "gcc_ufs_phy_rx_symbol_1_clk_src",
406 .parent_data = gcc_parent_data_11,
407 .num_parents = ARRAY_SIZE(gcc_parent_data_11),
408 .ops = &clk_regmap_mux_closest_ops,
413 static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
417 .parent_map = gcc_parent_map_12,
419 .hw.init = &(struct clk_init_data){
420 .name = "gcc_ufs_phy_tx_symbol_0_clk_src",
421 .parent_data = gcc_parent_data_12,
422 .num_parents = ARRAY_SIZE(gcc_parent_data_12),
423 .ops = &clk_regmap_mux_closest_ops,
428 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
432 .parent_map = gcc_parent_map_13,
434 .hw.init = &(struct clk_init_data){
435 .name = "gcc_usb3_prim_phy_pipe_clk_src",
436 .parent_data = gcc_parent_data_13,
437 .num_parents = ARRAY_SIZE(gcc_parent_data_13),
438 .ops = &clk_regmap_mux_closest_ops,
443 static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = {
447 .parent_map = gcc_parent_map_14,
449 .hw.init = &(struct clk_init_data){
450 .name = "gcc_usb3_sec_phy_pipe_clk_src",
451 .parent_data = gcc_parent_data_14,
452 .num_parents = ARRAY_SIZE(gcc_parent_data_14),
453 .ops = &clk_regmap_mux_closest_ops,
458 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
459 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
460 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
461 F(200000000, P_GCC_GPLL0_OUT_ODD, 1, 0, 0),
465 static struct clk_rcg2 gcc_gp1_clk_src = {
469 .parent_map = gcc_parent_map_4,
470 .freq_tbl = ftbl_gcc_gp1_clk_src,
471 .clkr.hw.init = &(struct clk_init_data){
472 .name = "gcc_gp1_clk_src",
473 .parent_data = gcc_parent_data_4,
474 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
475 .ops = &clk_rcg2_ops,
479 static struct clk_rcg2 gcc_gp2_clk_src = {
483 .parent_map = gcc_parent_map_4,
484 .freq_tbl = ftbl_gcc_gp1_clk_src,
485 .clkr.hw.init = &(struct clk_init_data){
486 .name = "gcc_gp2_clk_src",
487 .parent_data = gcc_parent_data_4,
488 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
489 .ops = &clk_rcg2_ops,
493 static struct clk_rcg2 gcc_gp3_clk_src = {
497 .parent_map = gcc_parent_map_4,
498 .freq_tbl = ftbl_gcc_gp1_clk_src,
499 .clkr.hw.init = &(struct clk_init_data){
500 .name = "gcc_gp3_clk_src",
501 .parent_data = gcc_parent_data_4,
502 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
503 .ops = &clk_rcg2_ops,
507 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
508 F(9600000, P_BI_TCXO, 2, 0, 0),
509 F(19200000, P_BI_TCXO, 1, 0, 0),
513 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
517 .parent_map = gcc_parent_map_2,
518 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
519 .clkr.hw.init = &(struct clk_init_data){
520 .name = "gcc_pcie_0_aux_clk_src",
521 .parent_data = gcc_parent_data_2,
522 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
523 .ops = &clk_rcg2_ops,
527 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
528 F(19200000, P_BI_TCXO, 1, 0, 0),
529 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
533 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
537 .parent_map = gcc_parent_map_0,
538 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
539 .clkr.hw.init = &(struct clk_init_data){
540 .name = "gcc_pcie_0_phy_rchng_clk_src",
541 .parent_data = gcc_parent_data_0,
542 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
543 .ops = &clk_rcg2_ops,
547 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
551 .parent_map = gcc_parent_map_2,
552 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
553 .clkr.hw.init = &(struct clk_init_data){
554 .name = "gcc_pcie_1_aux_clk_src",
555 .parent_data = gcc_parent_data_2,
556 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
557 .ops = &clk_rcg2_ops,
561 static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
565 .parent_map = gcc_parent_map_0,
566 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
567 .clkr.hw.init = &(struct clk_init_data){
568 .name = "gcc_pcie_1_phy_rchng_clk_src",
569 .parent_data = gcc_parent_data_0,
570 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
571 .flags = CLK_SET_RATE_PARENT,
572 .ops = &clk_rcg2_ops,
576 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
577 F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0),
581 static struct clk_rcg2 gcc_pdm2_clk_src = {
585 .parent_map = gcc_parent_map_0,
586 .freq_tbl = ftbl_gcc_pdm2_clk_src,
587 .clkr.hw.init = &(struct clk_init_data){
588 .name = "gcc_pdm2_clk_src",
589 .parent_data = gcc_parent_data_0,
590 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
591 .flags = CLK_SET_RATE_PARENT,
592 .ops = &clk_rcg2_ops,
596 static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
597 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
598 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
599 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
600 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
604 static struct clk_rcg2 gcc_qspi_core_clk_src = {
608 .parent_map = gcc_parent_map_0,
609 .freq_tbl = ftbl_gcc_qspi_core_clk_src,
610 .clkr.hw.init = &(struct clk_init_data){
611 .name = "gcc_qspi_core_clk_src",
612 .parent_data = gcc_parent_data_0,
613 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
614 .ops = &clk_rcg2_floor_ops,
618 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
619 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
620 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
621 F(19200000, P_BI_TCXO, 1, 0, 0),
622 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
623 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
624 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
625 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
626 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
627 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
628 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
629 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
630 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
631 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
632 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
633 F(120000000, P_GCC_GPLL0_OUT_EVEN, 2.5, 0, 0),
637 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
638 .name = "gcc_qupv3_wrap0_s0_clk_src",
639 .parent_data = gcc_parent_data_0,
640 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
641 .ops = &clk_rcg2_ops,
644 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
648 .parent_map = gcc_parent_map_0,
649 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
650 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
653 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
654 .name = "gcc_qupv3_wrap0_s1_clk_src",
655 .parent_data = gcc_parent_data_0,
656 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
657 .ops = &clk_rcg2_ops,
660 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
664 .parent_map = gcc_parent_map_0,
665 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
666 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
669 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = {
670 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
671 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
672 F(19200000, P_BI_TCXO, 1, 0, 0),
673 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
674 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
675 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
676 F(52174000, P_GCC_GPLL0_OUT_MAIN, 1, 2, 23),
677 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
678 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
679 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
680 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
681 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
685 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
686 .name = "gcc_qupv3_wrap0_s2_clk_src",
687 .parent_data = gcc_parent_data_0,
688 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
689 .ops = &clk_rcg2_ops,
692 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
696 .parent_map = gcc_parent_map_0,
697 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
698 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
701 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
702 .name = "gcc_qupv3_wrap0_s3_clk_src",
703 .parent_data = gcc_parent_data_0,
704 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
705 .ops = &clk_rcg2_ops,
708 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
712 .parent_map = gcc_parent_map_0,
713 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
714 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
717 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
718 .name = "gcc_qupv3_wrap0_s4_clk_src",
719 .parent_data = gcc_parent_data_0,
720 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
721 .ops = &clk_rcg2_ops,
724 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
728 .parent_map = gcc_parent_map_0,
729 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
730 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
733 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
734 .name = "gcc_qupv3_wrap0_s5_clk_src",
735 .parent_data = gcc_parent_data_0,
736 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
737 .ops = &clk_rcg2_ops,
740 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
744 .parent_map = gcc_parent_map_0,
745 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
746 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
749 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
750 .name = "gcc_qupv3_wrap0_s6_clk_src",
751 .parent_data = gcc_parent_data_0,
752 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
753 .ops = &clk_rcg2_ops,
756 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
760 .parent_map = gcc_parent_map_0,
761 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
762 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
765 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
766 .name = "gcc_qupv3_wrap0_s7_clk_src",
767 .parent_data = gcc_parent_data_0,
768 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
769 .ops = &clk_rcg2_ops,
772 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
776 .parent_map = gcc_parent_map_0,
777 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
778 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
781 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
782 .name = "gcc_qupv3_wrap1_s0_clk_src",
783 .parent_data = gcc_parent_data_0,
784 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
785 .ops = &clk_rcg2_ops,
788 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
792 .parent_map = gcc_parent_map_0,
793 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
794 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
797 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
798 .name = "gcc_qupv3_wrap1_s1_clk_src",
799 .parent_data = gcc_parent_data_0,
800 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
801 .ops = &clk_rcg2_ops,
804 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
808 .parent_map = gcc_parent_map_0,
809 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
810 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
813 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
814 .name = "gcc_qupv3_wrap1_s2_clk_src",
815 .parent_data = gcc_parent_data_0,
816 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
817 .ops = &clk_rcg2_ops,
820 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
824 .parent_map = gcc_parent_map_0,
825 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
826 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
829 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
830 .name = "gcc_qupv3_wrap1_s3_clk_src",
831 .parent_data = gcc_parent_data_0,
832 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
833 .ops = &clk_rcg2_ops,
836 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
840 .parent_map = gcc_parent_map_0,
841 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
842 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
845 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
846 .name = "gcc_qupv3_wrap1_s4_clk_src",
847 .parent_data = gcc_parent_data_0,
848 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
849 .ops = &clk_rcg2_ops,
852 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
856 .parent_map = gcc_parent_map_0,
857 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
858 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
861 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
862 .name = "gcc_qupv3_wrap1_s5_clk_src",
863 .parent_data = gcc_parent_data_0,
864 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
865 .ops = &clk_rcg2_ops,
868 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
872 .parent_map = gcc_parent_map_0,
873 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
874 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
877 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
878 .name = "gcc_qupv3_wrap1_s6_clk_src",
879 .parent_data = gcc_parent_data_0,
880 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
881 .ops = &clk_rcg2_ops,
884 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
888 .parent_map = gcc_parent_map_0,
889 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
890 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
893 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
894 .name = "gcc_qupv3_wrap1_s7_clk_src",
895 .parent_data = gcc_parent_data_0,
896 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
897 .ops = &clk_rcg2_ops,
900 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
904 .parent_map = gcc_parent_map_0,
905 .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
906 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
909 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
910 F(144000, P_BI_TCXO, 16, 3, 25),
911 F(400000, P_BI_TCXO, 12, 1, 4),
912 F(19200000, P_BI_TCXO, 1, 0, 0),
913 F(20000000, P_GCC_GPLL0_OUT_EVEN, 5, 1, 3),
914 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
915 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
916 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
917 F(192000000, P_GCC_GPLL10_OUT_MAIN, 2, 0, 0),
918 F(384000000, P_GCC_GPLL10_OUT_MAIN, 1, 0, 0),
922 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
926 .parent_map = gcc_parent_map_8,
927 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
928 .clkr.hw.init = &(struct clk_init_data){
929 .name = "gcc_sdcc1_apps_clk_src",
930 .parent_data = gcc_parent_data_8,
931 .num_parents = ARRAY_SIZE(gcc_parent_data_8),
932 .ops = &clk_rcg2_floor_ops,
936 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
937 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
938 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
939 F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
943 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
947 .parent_map = gcc_parent_map_1,
948 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
949 .clkr.hw.init = &(struct clk_init_data){
950 .name = "gcc_sdcc1_ice_core_clk_src",
951 .parent_data = gcc_parent_data_1,
952 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
953 .ops = &clk_rcg2_floor_ops,
957 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
958 F(400000, P_BI_TCXO, 12, 1, 4),
959 F(19200000, P_BI_TCXO, 1, 0, 0),
960 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
961 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
962 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
963 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
967 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
971 .parent_map = gcc_parent_map_9,
972 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
973 .clkr.hw.init = &(struct clk_init_data){
974 .name = "gcc_sdcc2_apps_clk_src",
975 .parent_data = gcc_parent_data_9,
976 .num_parents = ARRAY_SIZE(gcc_parent_data_9),
977 .flags = CLK_OPS_PARENT_ENABLE,
978 .ops = &clk_rcg2_floor_ops,
982 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
983 F(400000, P_BI_TCXO, 12, 1, 4),
984 F(19200000, P_BI_TCXO, 1, 0, 0),
985 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
986 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
987 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
991 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
995 .parent_map = gcc_parent_map_1,
996 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
997 .clkr.hw.init = &(struct clk_init_data){
998 .name = "gcc_sdcc4_apps_clk_src",
999 .parent_data = gcc_parent_data_1,
1000 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1001 .ops = &clk_rcg2_floor_ops,
1005 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
1006 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1007 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1008 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
1009 F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
1013 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
1014 .cmd_rcgr = 0x77024,
1017 .parent_map = gcc_parent_map_0,
1018 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
1019 .clkr.hw.init = &(struct clk_init_data){
1020 .name = "gcc_ufs_phy_axi_clk_src",
1021 .parent_data = gcc_parent_data_0,
1022 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1023 .ops = &clk_rcg2_ops,
1027 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
1028 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1029 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
1030 F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
1034 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
1035 .cmd_rcgr = 0x7706c,
1038 .parent_map = gcc_parent_map_0,
1039 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
1040 .clkr.hw.init = &(struct clk_init_data){
1041 .name = "gcc_ufs_phy_ice_core_clk_src",
1042 .parent_data = gcc_parent_data_0,
1043 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1044 .ops = &clk_rcg2_ops,
1048 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
1049 .cmd_rcgr = 0x770a0,
1052 .parent_map = gcc_parent_map_3,
1053 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1054 .clkr.hw.init = &(struct clk_init_data){
1055 .name = "gcc_ufs_phy_phy_aux_clk_src",
1056 .parent_data = gcc_parent_data_3,
1057 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1058 .ops = &clk_rcg2_ops,
1062 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1063 .cmd_rcgr = 0x77084,
1066 .parent_map = gcc_parent_map_0,
1067 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
1068 .clkr.hw.init = &(struct clk_init_data){
1069 .name = "gcc_ufs_phy_unipro_core_clk_src",
1070 .parent_data = gcc_parent_data_0,
1071 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1072 .ops = &clk_rcg2_ops,
1076 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1077 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
1078 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1079 F(200000000, P_GCC_GPLL0_OUT_ODD, 1, 0, 0),
1080 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1084 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1088 .parent_map = gcc_parent_map_1,
1089 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1090 .clkr.hw.init = &(struct clk_init_data){
1091 .name = "gcc_usb30_prim_master_clk_src",
1092 .parent_data = gcc_parent_data_1,
1093 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1094 .ops = &clk_rcg2_ops,
1098 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
1099 F(19200000, P_BI_TCXO, 1, 0, 0),
1103 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1107 .parent_map = gcc_parent_map_3,
1108 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1109 .clkr.hw.init = &(struct clk_init_data){
1110 .name = "gcc_usb30_prim_mock_utmi_clk_src",
1111 .parent_data = gcc_parent_data_3,
1112 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1113 .ops = &clk_rcg2_ops,
1117 static const struct freq_tbl ftbl_gcc_usb30_sec_master_clk_src[] = {
1118 F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0),
1119 F(120000000, P_GCC_GPLL0_OUT_EVEN, 2.5, 0, 0),
1123 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
1124 .cmd_rcgr = 0x9e020,
1127 .parent_map = gcc_parent_map_5,
1128 .freq_tbl = ftbl_gcc_usb30_sec_master_clk_src,
1129 .clkr.hw.init = &(struct clk_init_data){
1130 .name = "gcc_usb30_sec_master_clk_src",
1131 .parent_data = gcc_parent_data_5,
1132 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
1133 .ops = &clk_rcg2_ops,
1137 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
1138 .cmd_rcgr = 0x9e038,
1141 .parent_map = gcc_parent_map_3,
1142 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1143 .clkr.hw.init = &(struct clk_init_data){
1144 .name = "gcc_usb30_sec_mock_utmi_clk_src",
1145 .parent_data = gcc_parent_data_3,
1146 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1147 .ops = &clk_rcg2_ops,
1151 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1155 .parent_map = gcc_parent_map_2,
1156 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1157 .clkr.hw.init = &(struct clk_init_data){
1158 .name = "gcc_usb3_prim_phy_aux_clk_src",
1159 .parent_data = gcc_parent_data_2,
1160 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1161 .ops = &clk_rcg2_ops,
1165 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
1166 .cmd_rcgr = 0x9e064,
1169 .parent_map = gcc_parent_map_2,
1170 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1171 .clkr.hw.init = &(struct clk_init_data){
1172 .name = "gcc_usb3_sec_phy_aux_clk_src",
1173 .parent_data = gcc_parent_data_2,
1174 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1175 .ops = &clk_rcg2_ops,
1179 static const struct freq_tbl ftbl_gcc_sec_ctrl_clk_src[] = {
1180 F(4800000, P_BI_TCXO, 4, 0, 0),
1181 F(19200000, P_BI_TCXO, 1, 0, 0),
1185 static struct clk_rcg2 gcc_sec_ctrl_clk_src = {
1186 .cmd_rcgr = 0x3d02c,
1189 .parent_map = gcc_parent_map_3,
1190 .freq_tbl = ftbl_gcc_sec_ctrl_clk_src,
1191 .clkr.hw.init = &(struct clk_init_data){
1192 .name = "gcc_sec_ctrl_clk_src",
1193 .parent_data = gcc_parent_data_3,
1194 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1195 .ops = &clk_rcg2_ops,
1199 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
1203 .clkr.hw.init = &(struct clk_init_data) {
1204 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
1205 .parent_hws = (const struct clk_hw*[]){
1206 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
1209 .flags = CLK_SET_RATE_PARENT,
1210 .ops = &clk_regmap_div_ro_ops,
1214 static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = {
1218 .clkr.hw.init = &(struct clk_init_data) {
1219 .name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src",
1220 .parent_hws = (const struct clk_hw*[]){
1221 &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
1224 .flags = CLK_SET_RATE_PARENT,
1225 .ops = &clk_regmap_div_ro_ops,
1229 static struct clk_branch gcc_pcie_clkref_en = {
1230 .halt_reg = 0x8c004,
1231 .halt_check = BRANCH_HALT,
1233 .enable_reg = 0x8c004,
1234 .enable_mask = BIT(0),
1235 .hw.init = &(struct clk_init_data){
1236 .name = "gcc_pcie_clkref_en",
1237 .ops = &clk_branch2_ops,
1242 static struct clk_branch gcc_edp_clkref_en = {
1243 .halt_reg = 0x8c008,
1244 .halt_check = BRANCH_HALT,
1246 .enable_reg = 0x8c008,
1247 .enable_mask = BIT(0),
1248 .hw.init = &(struct clk_init_data){
1249 .name = "gcc_edp_clkref_en",
1250 .ops = &clk_branch2_ops,
1255 static struct clk_branch gcc_aggre_noc_pcie_0_axi_clk = {
1256 .halt_reg = 0x6b080,
1257 .halt_check = BRANCH_HALT_SKIP,
1258 .hwcg_reg = 0x6b080,
1261 .enable_reg = 0x52000,
1262 .enable_mask = BIT(12),
1263 .hw.init = &(struct clk_init_data){
1264 .name = "gcc_aggre_noc_pcie_0_axi_clk",
1265 .ops = &clk_branch2_ops,
1270 static struct clk_branch gcc_aggre_noc_pcie_1_axi_clk = {
1271 .halt_reg = 0x8d084,
1272 .halt_check = BRANCH_HALT_SKIP,
1273 .hwcg_reg = 0x8d084,
1276 .enable_reg = 0x52000,
1277 .enable_mask = BIT(11),
1278 .hw.init = &(struct clk_init_data){
1279 .name = "gcc_aggre_noc_pcie_1_axi_clk",
1280 .ops = &clk_branch2_ops,
1285 static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
1286 .halt_reg = 0x90010,
1287 .halt_check = BRANCH_HALT_VOTED,
1288 .hwcg_reg = 0x90010,
1291 .enable_reg = 0x52000,
1292 .enable_mask = BIT(18),
1293 .hw.init = &(struct clk_init_data){
1294 .name = "gcc_aggre_noc_pcie_tbu_clk",
1295 .ops = &clk_branch2_ops,
1300 static struct clk_branch gcc_aggre_noc_pcie_center_sf_axi_clk = {
1301 .halt_reg = 0x8d088,
1302 .halt_check = BRANCH_HALT_VOTED,
1303 .hwcg_reg = 0x8d088,
1306 .enable_reg = 0x52008,
1307 .enable_mask = BIT(28),
1308 .hw.init = &(struct clk_init_data){
1309 .name = "gcc_aggre_noc_pcie_center_sf_axi_clk",
1310 .ops = &clk_branch2_ops,
1315 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1316 .halt_reg = 0x770cc,
1317 .halt_check = BRANCH_HALT_VOTED,
1318 .hwcg_reg = 0x770cc,
1321 .enable_reg = 0x770cc,
1322 .enable_mask = BIT(0),
1323 .hw.init = &(struct clk_init_data){
1324 .name = "gcc_aggre_ufs_phy_axi_clk",
1325 .parent_hws = (const struct clk_hw*[]){
1326 &gcc_ufs_phy_axi_clk_src.clkr.hw,
1329 .flags = CLK_SET_RATE_PARENT,
1330 .ops = &clk_branch2_ops,
1335 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1337 .halt_check = BRANCH_HALT_VOTED,
1341 .enable_reg = 0xf080,
1342 .enable_mask = BIT(0),
1343 .hw.init = &(struct clk_init_data){
1344 .name = "gcc_aggre_usb3_prim_axi_clk",
1345 .parent_hws = (const struct clk_hw*[]){
1346 &gcc_usb30_prim_master_clk_src.clkr.hw,
1349 .flags = CLK_SET_RATE_PARENT,
1350 .ops = &clk_branch2_ops,
1355 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
1356 .halt_reg = 0x9e080,
1357 .halt_check = BRANCH_HALT_VOTED,
1358 .hwcg_reg = 0x9e080,
1361 .enable_reg = 0x9e080,
1362 .enable_mask = BIT(0),
1363 .hw.init = &(struct clk_init_data){
1364 .name = "gcc_aggre_usb3_sec_axi_clk",
1365 .parent_hws = (const struct clk_hw*[]){
1366 &gcc_usb30_sec_master_clk_src.clkr.hw,
1369 .flags = CLK_SET_RATE_PARENT,
1370 .ops = &clk_branch2_ops,
1375 static struct clk_branch gcc_camera_hf_axi_clk = {
1376 .halt_reg = 0x26010,
1377 .halt_check = BRANCH_HALT_SKIP,
1378 .hwcg_reg = 0x26010,
1381 .enable_reg = 0x26010,
1382 .enable_mask = BIT(0),
1383 .hw.init = &(struct clk_init_data){
1384 .name = "gcc_camera_hf_axi_clk",
1385 .ops = &clk_branch2_ops,
1390 static struct clk_branch gcc_camera_sf_axi_clk = {
1391 .halt_reg = 0x2601c,
1392 .halt_check = BRANCH_HALT_SKIP,
1393 .hwcg_reg = 0x2601c,
1396 .enable_reg = 0x2601c,
1397 .enable_mask = BIT(0),
1398 .hw.init = &(struct clk_init_data){
1399 .name = "gcc_camera_sf_axi_clk",
1400 .ops = &clk_branch2_ops,
1405 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1407 .halt_check = BRANCH_HALT_VOTED,
1411 .enable_reg = 0xf07c,
1412 .enable_mask = BIT(0),
1413 .hw.init = &(struct clk_init_data){
1414 .name = "gcc_cfg_noc_usb3_prim_axi_clk",
1415 .parent_hws = (const struct clk_hw*[]){
1416 &gcc_usb30_prim_master_clk_src.clkr.hw,
1419 .flags = CLK_SET_RATE_PARENT,
1420 .ops = &clk_branch2_ops,
1425 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
1426 .halt_reg = 0x9e07c,
1427 .halt_check = BRANCH_HALT_VOTED,
1428 .hwcg_reg = 0x9e07c,
1431 .enable_reg = 0x9e07c,
1432 .enable_mask = BIT(0),
1433 .hw.init = &(struct clk_init_data){
1434 .name = "gcc_cfg_noc_usb3_sec_axi_clk",
1435 .parent_hws = (const struct clk_hw*[]){
1436 &gcc_usb30_sec_master_clk_src.clkr.hw,
1439 .flags = CLK_SET_RATE_PARENT,
1440 .ops = &clk_branch2_ops,
1445 static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1446 .halt_reg = 0x71154,
1447 .halt_check = BRANCH_HALT_SKIP,
1448 .hwcg_reg = 0x71154,
1451 .enable_reg = 0x71154,
1452 .enable_mask = BIT(0),
1453 .hw.init = &(struct clk_init_data){
1454 .name = "gcc_ddrss_gpu_axi_clk",
1455 .ops = &clk_branch2_aon_ops,
1460 static struct clk_branch gcc_ddrss_pcie_sf_clk = {
1461 .halt_reg = 0x8d080,
1462 .halt_check = BRANCH_HALT_SKIP,
1463 .hwcg_reg = 0x8d080,
1466 .enable_reg = 0x52000,
1467 .enable_mask = BIT(19),
1468 .hw.init = &(struct clk_init_data){
1469 .name = "gcc_ddrss_pcie_sf_clk",
1470 .ops = &clk_branch2_ops,
1475 static struct clk_branch gcc_disp_gpll0_clk_src = {
1476 .halt_check = BRANCH_HALT_DELAY,
1478 .enable_reg = 0x52000,
1479 .enable_mask = BIT(7),
1480 .hw.init = &(struct clk_init_data){
1481 .name = "gcc_disp_gpll0_clk_src",
1482 .parent_hws = (const struct clk_hw*[]){
1486 .flags = CLK_SET_RATE_PARENT,
1487 .ops = &clk_branch2_ops,
1492 static struct clk_branch gcc_disp_hf_axi_clk = {
1493 .halt_reg = 0x2700c,
1494 .halt_check = BRANCH_HALT_SKIP,
1495 .hwcg_reg = 0x2700c,
1498 .enable_reg = 0x2700c,
1499 .enable_mask = BIT(0),
1500 .hw.init = &(struct clk_init_data){
1501 .name = "gcc_disp_hf_axi_clk",
1502 .ops = &clk_branch2_ops,
1507 static struct clk_branch gcc_disp_sf_axi_clk = {
1508 .halt_reg = 0x27014,
1509 .halt_check = BRANCH_HALT_SKIP,
1510 .hwcg_reg = 0x27014,
1513 .enable_reg = 0x27014,
1514 .enable_mask = BIT(0),
1515 .hw.init = &(struct clk_init_data){
1516 .name = "gcc_disp_sf_axi_clk",
1517 .ops = &clk_branch2_ops,
1522 static struct clk_branch gcc_gp1_clk = {
1523 .halt_reg = 0x64000,
1524 .halt_check = BRANCH_HALT,
1526 .enable_reg = 0x64000,
1527 .enable_mask = BIT(0),
1528 .hw.init = &(struct clk_init_data){
1529 .name = "gcc_gp1_clk",
1530 .parent_hws = (const struct clk_hw*[]){
1531 &gcc_gp1_clk_src.clkr.hw,
1534 .flags = CLK_SET_RATE_PARENT,
1535 .ops = &clk_branch2_ops,
1540 static struct clk_branch gcc_gp2_clk = {
1541 .halt_reg = 0x65000,
1542 .halt_check = BRANCH_HALT,
1544 .enable_reg = 0x65000,
1545 .enable_mask = BIT(0),
1546 .hw.init = &(struct clk_init_data){
1547 .name = "gcc_gp2_clk",
1548 .parent_hws = (const struct clk_hw*[]){
1549 &gcc_gp2_clk_src.clkr.hw,
1552 .flags = CLK_SET_RATE_PARENT,
1553 .ops = &clk_branch2_ops,
1558 static struct clk_branch gcc_gp3_clk = {
1559 .halt_reg = 0x66000,
1560 .halt_check = BRANCH_HALT,
1562 .enable_reg = 0x66000,
1563 .enable_mask = BIT(0),
1564 .hw.init = &(struct clk_init_data){
1565 .name = "gcc_gp3_clk",
1566 .parent_hws = (const struct clk_hw*[]){
1567 &gcc_gp3_clk_src.clkr.hw,
1570 .flags = CLK_SET_RATE_PARENT,
1571 .ops = &clk_branch2_ops,
1576 static struct clk_branch gcc_gpu_gpll0_clk_src = {
1577 .halt_check = BRANCH_HALT_DELAY,
1579 .enable_reg = 0x52000,
1580 .enable_mask = BIT(15),
1581 .hw.init = &(struct clk_init_data){
1582 .name = "gcc_gpu_gpll0_clk_src",
1583 .parent_hws = (const struct clk_hw*[]){
1587 .flags = CLK_SET_RATE_PARENT,
1588 .ops = &clk_branch2_ops,
1593 static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1594 .halt_check = BRANCH_HALT_DELAY,
1596 .enable_reg = 0x52000,
1597 .enable_mask = BIT(16),
1598 .hw.init = &(struct clk_init_data){
1599 .name = "gcc_gpu_gpll0_div_clk_src",
1600 .parent_hws = (const struct clk_hw*[]){
1601 &gcc_gpll0_out_even.clkr.hw,
1604 .flags = CLK_SET_RATE_PARENT,
1605 .ops = &clk_branch2_ops,
1610 static struct clk_branch gcc_gpu_iref_en = {
1611 .halt_reg = 0x8c014,
1612 .halt_check = BRANCH_HALT,
1614 .enable_reg = 0x8c014,
1615 .enable_mask = BIT(0),
1616 .hw.init = &(struct clk_init_data){
1617 .name = "gcc_gpu_iref_en",
1618 .ops = &clk_branch2_ops,
1623 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1624 .halt_reg = 0x7100c,
1625 .halt_check = BRANCH_HALT_VOTED,
1626 .hwcg_reg = 0x7100c,
1629 .enable_reg = 0x7100c,
1630 .enable_mask = BIT(0),
1631 .hw.init = &(struct clk_init_data){
1632 .name = "gcc_gpu_memnoc_gfx_clk",
1633 .ops = &clk_branch2_aon_ops,
1638 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1639 .halt_reg = 0x71018,
1640 .halt_check = BRANCH_HALT,
1642 .enable_reg = 0x71018,
1643 .enable_mask = BIT(0),
1644 .hw.init = &(struct clk_init_data){
1645 .name = "gcc_gpu_snoc_dvm_gfx_clk",
1646 .ops = &clk_branch2_aon_ops,
1651 static struct clk_branch gcc_pcie0_phy_rchng_clk = {
1652 .halt_reg = 0x6b038,
1653 .halt_check = BRANCH_HALT_VOTED,
1655 .enable_reg = 0x52000,
1656 .enable_mask = BIT(22),
1657 .hw.init = &(struct clk_init_data){
1658 .name = "gcc_pcie0_phy_rchng_clk",
1659 .parent_hws = (const struct clk_hw*[]){
1660 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
1663 .flags = CLK_SET_RATE_PARENT,
1664 .ops = &clk_branch2_ops,
1669 static struct clk_branch gcc_pcie1_phy_rchng_clk = {
1670 .halt_reg = 0x8d038,
1671 .halt_check = BRANCH_HALT_VOTED,
1673 .enable_reg = 0x52000,
1674 .enable_mask = BIT(23),
1675 .hw.init = &(struct clk_init_data){
1676 .name = "gcc_pcie1_phy_rchng_clk",
1677 .parent_hws = (const struct clk_hw*[]){
1678 &gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
1681 .flags = CLK_SET_RATE_PARENT,
1682 .ops = &clk_branch2_ops,
1687 static struct clk_branch gcc_pcie_0_aux_clk = {
1688 .halt_reg = 0x6b028,
1689 .halt_check = BRANCH_HALT_VOTED,
1691 .enable_reg = 0x52008,
1692 .enable_mask = BIT(3),
1693 .hw.init = &(struct clk_init_data){
1694 .name = "gcc_pcie_0_aux_clk",
1695 .parent_hws = (const struct clk_hw*[]){
1696 &gcc_pcie_0_aux_clk_src.clkr.hw,
1699 .flags = CLK_SET_RATE_PARENT,
1700 .ops = &clk_branch2_ops,
1705 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1706 .halt_reg = 0x6b024,
1707 .halt_check = BRANCH_HALT_VOTED,
1708 .hwcg_reg = 0x6b024,
1711 .enable_reg = 0x52008,
1712 .enable_mask = BIT(2),
1713 .hw.init = &(struct clk_init_data){
1714 .name = "gcc_pcie_0_cfg_ahb_clk",
1715 .ops = &clk_branch2_ops,
1720 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1721 .halt_reg = 0x6b01c,
1722 .halt_check = BRANCH_HALT_SKIP,
1724 .enable_reg = 0x52008,
1725 .enable_mask = BIT(1),
1726 .hw.init = &(struct clk_init_data){
1727 .name = "gcc_pcie_0_mstr_axi_clk",
1728 .ops = &clk_branch2_ops,
1733 static struct clk_branch gcc_pcie_0_pipe_clk = {
1734 .halt_reg = 0x6b030,
1735 .halt_check = BRANCH_HALT_SKIP,
1737 .enable_reg = 0x52008,
1738 .enable_mask = BIT(4),
1739 .hw.init = &(struct clk_init_data){
1740 .name = "gcc_pcie_0_pipe_clk",
1741 .parent_hws = (const struct clk_hw*[]){
1742 &gcc_pcie_0_pipe_clk_src.clkr.hw,
1745 .flags = CLK_SET_RATE_PARENT,
1746 .ops = &clk_branch2_ops,
1751 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1752 .halt_reg = 0x6b014,
1753 .halt_check = BRANCH_HALT_VOTED,
1755 .enable_reg = 0x52008,
1756 .enable_mask = BIT(0),
1757 .hw.init = &(struct clk_init_data){
1758 .name = "gcc_pcie_0_slv_axi_clk",
1759 .ops = &clk_branch2_ops,
1764 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1765 .halt_reg = 0x6b010,
1766 .halt_check = BRANCH_HALT_VOTED,
1768 .enable_reg = 0x52008,
1769 .enable_mask = BIT(5),
1770 .hw.init = &(struct clk_init_data){
1771 .name = "gcc_pcie_0_slv_q2a_axi_clk",
1772 .ops = &clk_branch2_ops,
1777 static struct clk_branch gcc_pcie_1_aux_clk = {
1778 .halt_reg = 0x8d028,
1779 .halt_check = BRANCH_HALT_VOTED,
1781 .enable_reg = 0x52000,
1782 .enable_mask = BIT(29),
1783 .hw.init = &(struct clk_init_data){
1784 .name = "gcc_pcie_1_aux_clk",
1785 .parent_hws = (const struct clk_hw*[]){
1786 &gcc_pcie_1_aux_clk_src.clkr.hw,
1789 .flags = CLK_SET_RATE_PARENT,
1790 .ops = &clk_branch2_ops,
1795 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1796 .halt_reg = 0x8d024,
1797 .halt_check = BRANCH_HALT_VOTED,
1798 .hwcg_reg = 0x8d024,
1801 .enable_reg = 0x52000,
1802 .enable_mask = BIT(28),
1803 .hw.init = &(struct clk_init_data){
1804 .name = "gcc_pcie_1_cfg_ahb_clk",
1805 .ops = &clk_branch2_ops,
1810 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1811 .halt_reg = 0x8d01c,
1812 .halt_check = BRANCH_HALT_SKIP,
1814 .enable_reg = 0x52000,
1815 .enable_mask = BIT(27),
1816 .hw.init = &(struct clk_init_data){
1817 .name = "gcc_pcie_1_mstr_axi_clk",
1818 .ops = &clk_branch2_ops,
1823 static struct clk_branch gcc_pcie_1_pipe_clk = {
1824 .halt_reg = 0x8d030,
1825 .halt_check = BRANCH_HALT_SKIP,
1827 .enable_reg = 0x52000,
1828 .enable_mask = BIT(30),
1829 .hw.init = &(struct clk_init_data){
1830 .name = "gcc_pcie_1_pipe_clk",
1831 .parent_hws = (const struct clk_hw*[]){
1832 &gcc_pcie_1_pipe_clk_src.clkr.hw,
1835 .flags = CLK_SET_RATE_PARENT,
1836 .ops = &clk_branch2_ops,
1841 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1842 .halt_reg = 0x8d014,
1843 .halt_check = BRANCH_HALT_VOTED,
1845 .enable_reg = 0x52000,
1846 .enable_mask = BIT(26),
1847 .hw.init = &(struct clk_init_data){
1848 .name = "gcc_pcie_1_slv_axi_clk",
1849 .ops = &clk_branch2_ops,
1854 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
1855 .halt_reg = 0x8d010,
1856 .halt_check = BRANCH_HALT_VOTED,
1858 .enable_reg = 0x52000,
1859 .enable_mask = BIT(25),
1860 .hw.init = &(struct clk_init_data){
1861 .name = "gcc_pcie_1_slv_q2a_axi_clk",
1862 .ops = &clk_branch2_ops,
1867 static struct clk_branch gcc_pcie_throttle_core_clk = {
1868 .halt_reg = 0x90018,
1869 .halt_check = BRANCH_HALT_SKIP,
1870 .hwcg_reg = 0x90018,
1873 .enable_reg = 0x52000,
1874 .enable_mask = BIT(20),
1875 .hw.init = &(struct clk_init_data){
1876 .name = "gcc_pcie_throttle_core_clk",
1877 .ops = &clk_branch2_ops,
1882 static struct clk_branch gcc_pdm2_clk = {
1883 .halt_reg = 0x3300c,
1884 .halt_check = BRANCH_HALT,
1886 .enable_reg = 0x3300c,
1887 .enable_mask = BIT(0),
1888 .hw.init = &(struct clk_init_data){
1889 .name = "gcc_pdm2_clk",
1890 .parent_hws = (const struct clk_hw*[]){
1891 &gcc_pdm2_clk_src.clkr.hw,
1894 .flags = CLK_SET_RATE_PARENT,
1895 .ops = &clk_branch2_ops,
1900 static struct clk_branch gcc_pdm_ahb_clk = {
1901 .halt_reg = 0x33004,
1902 .halt_check = BRANCH_HALT_VOTED,
1903 .hwcg_reg = 0x33004,
1906 .enable_reg = 0x33004,
1907 .enable_mask = BIT(0),
1908 .hw.init = &(struct clk_init_data){
1909 .name = "gcc_pdm_ahb_clk",
1910 .ops = &clk_branch2_ops,
1915 static struct clk_branch gcc_pdm_xo4_clk = {
1916 .halt_reg = 0x33008,
1917 .halt_check = BRANCH_HALT,
1919 .enable_reg = 0x33008,
1920 .enable_mask = BIT(0),
1921 .hw.init = &(struct clk_init_data){
1922 .name = "gcc_pdm_xo4_clk",
1923 .ops = &clk_branch2_ops,
1928 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
1929 .halt_reg = 0x26008,
1930 .halt_check = BRANCH_HALT_VOTED,
1931 .hwcg_reg = 0x26008,
1934 .enable_reg = 0x26008,
1935 .enable_mask = BIT(0),
1936 .hw.init = &(struct clk_init_data){
1937 .name = "gcc_qmip_camera_nrt_ahb_clk",
1938 .ops = &clk_branch2_ops,
1943 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
1944 .halt_reg = 0x2600c,
1945 .halt_check = BRANCH_HALT_VOTED,
1946 .hwcg_reg = 0x2600c,
1949 .enable_reg = 0x2600c,
1950 .enable_mask = BIT(0),
1951 .hw.init = &(struct clk_init_data){
1952 .name = "gcc_qmip_camera_rt_ahb_clk",
1953 .ops = &clk_branch2_ops,
1958 static struct clk_branch gcc_qmip_disp_ahb_clk = {
1959 .halt_reg = 0x27008,
1960 .halt_check = BRANCH_HALT_VOTED,
1962 .enable_reg = 0x27008,
1963 .enable_mask = BIT(0),
1964 .hw.init = &(struct clk_init_data){
1965 .name = "gcc_qmip_disp_ahb_clk",
1966 .ops = &clk_branch2_ops,
1971 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
1972 .halt_reg = 0x28008,
1973 .halt_check = BRANCH_HALT_VOTED,
1974 .hwcg_reg = 0x28008,
1977 .enable_reg = 0x28008,
1978 .enable_mask = BIT(0),
1979 .hw.init = &(struct clk_init_data){
1980 .name = "gcc_qmip_video_vcodec_ahb_clk",
1981 .ops = &clk_branch2_ops,
1986 static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
1987 .halt_reg = 0x4b004,
1988 .halt_check = BRANCH_HALT,
1989 .hwcg_reg = 0x4b004,
1992 .enable_reg = 0x4b004,
1993 .enable_mask = BIT(0),
1994 .hw.init = &(struct clk_init_data){
1995 .name = "gcc_qspi_cnoc_periph_ahb_clk",
1996 .ops = &clk_branch2_ops,
2001 static struct clk_branch gcc_qspi_core_clk = {
2002 .halt_reg = 0x4b008,
2003 .halt_check = BRANCH_HALT,
2005 .enable_reg = 0x4b008,
2006 .enable_mask = BIT(0),
2007 .hw.init = &(struct clk_init_data){
2008 .name = "gcc_qspi_core_clk",
2009 .parent_hws = (const struct clk_hw*[]){
2010 &gcc_qspi_core_clk_src.clkr.hw,
2013 .flags = CLK_SET_RATE_PARENT,
2014 .ops = &clk_branch2_ops,
2019 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
2020 .halt_reg = 0x23008,
2021 .halt_check = BRANCH_HALT_VOTED,
2023 .enable_reg = 0x52008,
2024 .enable_mask = BIT(9),
2025 .hw.init = &(struct clk_init_data){
2026 .name = "gcc_qupv3_wrap0_core_2x_clk",
2027 .ops = &clk_branch2_ops,
2032 static struct clk_branch gcc_qupv3_wrap0_core_clk = {
2033 .halt_reg = 0x23000,
2034 .halt_check = BRANCH_HALT_VOTED,
2036 .enable_reg = 0x52008,
2037 .enable_mask = BIT(8),
2038 .hw.init = &(struct clk_init_data){
2039 .name = "gcc_qupv3_wrap0_core_clk",
2040 .ops = &clk_branch2_ops,
2045 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2046 .halt_reg = 0x1700c,
2047 .halt_check = BRANCH_HALT_VOTED,
2049 .enable_reg = 0x52008,
2050 .enable_mask = BIT(10),
2051 .hw.init = &(struct clk_init_data){
2052 .name = "gcc_qupv3_wrap0_s0_clk",
2053 .parent_hws = (const struct clk_hw*[]){
2054 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
2057 .flags = CLK_SET_RATE_PARENT,
2058 .ops = &clk_branch2_ops,
2063 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2064 .halt_reg = 0x1713c,
2065 .halt_check = BRANCH_HALT_VOTED,
2067 .enable_reg = 0x52008,
2068 .enable_mask = BIT(11),
2069 .hw.init = &(struct clk_init_data){
2070 .name = "gcc_qupv3_wrap0_s1_clk",
2071 .parent_hws = (const struct clk_hw*[]){
2072 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
2075 .flags = CLK_SET_RATE_PARENT,
2076 .ops = &clk_branch2_ops,
2081 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2082 .halt_reg = 0x1726c,
2083 .halt_check = BRANCH_HALT_VOTED,
2085 .enable_reg = 0x52008,
2086 .enable_mask = BIT(12),
2087 .hw.init = &(struct clk_init_data){
2088 .name = "gcc_qupv3_wrap0_s2_clk",
2089 .parent_hws = (const struct clk_hw*[]){
2090 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
2093 .flags = CLK_SET_RATE_PARENT,
2094 .ops = &clk_branch2_ops,
2099 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2100 .halt_reg = 0x1739c,
2101 .halt_check = BRANCH_HALT_VOTED,
2103 .enable_reg = 0x52008,
2104 .enable_mask = BIT(13),
2105 .hw.init = &(struct clk_init_data){
2106 .name = "gcc_qupv3_wrap0_s3_clk",
2107 .parent_hws = (const struct clk_hw*[]){
2108 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
2111 .flags = CLK_SET_RATE_PARENT,
2112 .ops = &clk_branch2_ops,
2117 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2118 .halt_reg = 0x174cc,
2119 .halt_check = BRANCH_HALT_VOTED,
2121 .enable_reg = 0x52008,
2122 .enable_mask = BIT(14),
2123 .hw.init = &(struct clk_init_data){
2124 .name = "gcc_qupv3_wrap0_s4_clk",
2125 .parent_hws = (const struct clk_hw*[]){
2126 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
2129 .flags = CLK_SET_RATE_PARENT,
2130 .ops = &clk_branch2_ops,
2135 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2136 .halt_reg = 0x175fc,
2137 .halt_check = BRANCH_HALT_VOTED,
2139 .enable_reg = 0x52008,
2140 .enable_mask = BIT(15),
2141 .hw.init = &(struct clk_init_data){
2142 .name = "gcc_qupv3_wrap0_s5_clk",
2143 .parent_hws = (const struct clk_hw*[]){
2144 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
2147 .flags = CLK_SET_RATE_PARENT,
2148 .ops = &clk_branch2_ops,
2153 static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2154 .halt_reg = 0x1772c,
2155 .halt_check = BRANCH_HALT_VOTED,
2157 .enable_reg = 0x52008,
2158 .enable_mask = BIT(16),
2159 .hw.init = &(struct clk_init_data){
2160 .name = "gcc_qupv3_wrap0_s6_clk",
2161 .parent_hws = (const struct clk_hw*[]){
2162 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
2165 .flags = CLK_SET_RATE_PARENT,
2166 .ops = &clk_branch2_ops,
2171 static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2172 .halt_reg = 0x1785c,
2173 .halt_check = BRANCH_HALT_VOTED,
2175 .enable_reg = 0x52008,
2176 .enable_mask = BIT(17),
2177 .hw.init = &(struct clk_init_data){
2178 .name = "gcc_qupv3_wrap0_s7_clk",
2179 .parent_hws = (const struct clk_hw*[]){
2180 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
2183 .flags = CLK_SET_RATE_PARENT,
2184 .ops = &clk_branch2_ops,
2189 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
2190 .halt_reg = 0x23140,
2191 .halt_check = BRANCH_HALT_VOTED,
2193 .enable_reg = 0x52008,
2194 .enable_mask = BIT(18),
2195 .hw.init = &(struct clk_init_data){
2196 .name = "gcc_qupv3_wrap1_core_2x_clk",
2197 .ops = &clk_branch2_ops,
2202 static struct clk_branch gcc_qupv3_wrap1_core_clk = {
2203 .halt_reg = 0x23138,
2204 .halt_check = BRANCH_HALT_VOTED,
2206 .enable_reg = 0x52008,
2207 .enable_mask = BIT(19),
2208 .hw.init = &(struct clk_init_data){
2209 .name = "gcc_qupv3_wrap1_core_clk",
2210 .ops = &clk_branch2_ops,
2215 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2216 .halt_reg = 0x1800c,
2217 .halt_check = BRANCH_HALT_VOTED,
2219 .enable_reg = 0x52008,
2220 .enable_mask = BIT(22),
2221 .hw.init = &(struct clk_init_data){
2222 .name = "gcc_qupv3_wrap1_s0_clk",
2223 .parent_hws = (const struct clk_hw*[]){
2224 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
2227 .flags = CLK_SET_RATE_PARENT,
2228 .ops = &clk_branch2_ops,
2233 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2234 .halt_reg = 0x1813c,
2235 .halt_check = BRANCH_HALT_VOTED,
2237 .enable_reg = 0x52008,
2238 .enable_mask = BIT(23),
2239 .hw.init = &(struct clk_init_data){
2240 .name = "gcc_qupv3_wrap1_s1_clk",
2241 .parent_hws = (const struct clk_hw*[]){
2242 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
2245 .flags = CLK_SET_RATE_PARENT,
2246 .ops = &clk_branch2_ops,
2251 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2252 .halt_reg = 0x1826c,
2253 .halt_check = BRANCH_HALT_VOTED,
2255 .enable_reg = 0x52008,
2256 .enable_mask = BIT(24),
2257 .hw.init = &(struct clk_init_data){
2258 .name = "gcc_qupv3_wrap1_s2_clk",
2259 .parent_hws = (const struct clk_hw*[]){
2260 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
2263 .flags = CLK_SET_RATE_PARENT,
2264 .ops = &clk_branch2_ops,
2269 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2270 .halt_reg = 0x1839c,
2271 .halt_check = BRANCH_HALT_VOTED,
2273 .enable_reg = 0x52008,
2274 .enable_mask = BIT(25),
2275 .hw.init = &(struct clk_init_data){
2276 .name = "gcc_qupv3_wrap1_s3_clk",
2277 .parent_hws = (const struct clk_hw*[]){
2278 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
2281 .flags = CLK_SET_RATE_PARENT,
2282 .ops = &clk_branch2_ops,
2287 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2288 .halt_reg = 0x184cc,
2289 .halt_check = BRANCH_HALT_VOTED,
2291 .enable_reg = 0x52008,
2292 .enable_mask = BIT(26),
2293 .hw.init = &(struct clk_init_data){
2294 .name = "gcc_qupv3_wrap1_s4_clk",
2295 .parent_hws = (const struct clk_hw*[]){
2296 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
2299 .flags = CLK_SET_RATE_PARENT,
2300 .ops = &clk_branch2_ops,
2305 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2306 .halt_reg = 0x185fc,
2307 .halt_check = BRANCH_HALT_VOTED,
2309 .enable_reg = 0x52008,
2310 .enable_mask = BIT(27),
2311 .hw.init = &(struct clk_init_data){
2312 .name = "gcc_qupv3_wrap1_s5_clk",
2313 .parent_hws = (const struct clk_hw*[]){
2314 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
2317 .flags = CLK_SET_RATE_PARENT,
2318 .ops = &clk_branch2_ops,
2323 static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
2324 .halt_reg = 0x1872c,
2325 .halt_check = BRANCH_HALT_VOTED,
2327 .enable_reg = 0x52000,
2328 .enable_mask = BIT(13),
2329 .hw.init = &(struct clk_init_data){
2330 .name = "gcc_qupv3_wrap1_s6_clk",
2331 .parent_hws = (const struct clk_hw*[]){
2332 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
2335 .flags = CLK_SET_RATE_PARENT,
2336 .ops = &clk_branch2_ops,
2341 static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
2342 .halt_reg = 0x1885c,
2343 .halt_check = BRANCH_HALT_VOTED,
2345 .enable_reg = 0x52000,
2346 .enable_mask = BIT(14),
2347 .hw.init = &(struct clk_init_data){
2348 .name = "gcc_qupv3_wrap1_s7_clk",
2349 .parent_hws = (const struct clk_hw*[]){
2350 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
2353 .flags = CLK_SET_RATE_PARENT,
2354 .ops = &clk_branch2_ops,
2359 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2360 .halt_reg = 0x17004,
2361 .halt_check = BRANCH_HALT_VOTED,
2362 .hwcg_reg = 0x17004,
2365 .enable_reg = 0x52008,
2366 .enable_mask = BIT(6),
2367 .hw.init = &(struct clk_init_data){
2368 .name = "gcc_qupv3_wrap_0_m_ahb_clk",
2369 .ops = &clk_branch2_ops,
2374 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2375 .halt_reg = 0x17008,
2376 .halt_check = BRANCH_HALT_VOTED,
2377 .hwcg_reg = 0x17008,
2380 .enable_reg = 0x52008,
2381 .enable_mask = BIT(7),
2382 .hw.init = &(struct clk_init_data){
2383 .name = "gcc_qupv3_wrap_0_s_ahb_clk",
2384 .ops = &clk_branch2_ops,
2389 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2390 .halt_reg = 0x18004,
2391 .halt_check = BRANCH_HALT_VOTED,
2392 .hwcg_reg = 0x18004,
2395 .enable_reg = 0x52008,
2396 .enable_mask = BIT(20),
2397 .hw.init = &(struct clk_init_data){
2398 .name = "gcc_qupv3_wrap_1_m_ahb_clk",
2399 .ops = &clk_branch2_ops,
2404 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2405 .halt_reg = 0x18008,
2406 .halt_check = BRANCH_HALT_VOTED,
2407 .hwcg_reg = 0x18008,
2410 .enable_reg = 0x52008,
2411 .enable_mask = BIT(21),
2412 .hw.init = &(struct clk_init_data){
2413 .name = "gcc_qupv3_wrap_1_s_ahb_clk",
2414 .ops = &clk_branch2_ops,
2419 static struct clk_branch gcc_sdcc1_ahb_clk = {
2420 .halt_reg = 0x75004,
2421 .halt_check = BRANCH_HALT,
2423 .enable_reg = 0x75004,
2424 .enable_mask = BIT(0),
2425 .hw.init = &(struct clk_init_data){
2426 .name = "gcc_sdcc1_ahb_clk",
2427 .ops = &clk_branch2_ops,
2432 static struct clk_branch gcc_sdcc1_apps_clk = {
2433 .halt_reg = 0x75008,
2434 .halt_check = BRANCH_HALT,
2436 .enable_reg = 0x75008,
2437 .enable_mask = BIT(0),
2438 .hw.init = &(struct clk_init_data){
2439 .name = "gcc_sdcc1_apps_clk",
2440 .parent_hws = (const struct clk_hw*[]){
2441 &gcc_sdcc1_apps_clk_src.clkr.hw,
2444 .flags = CLK_SET_RATE_PARENT,
2445 .ops = &clk_branch2_ops,
2450 static struct clk_branch gcc_sdcc1_ice_core_clk = {
2451 .halt_reg = 0x75024,
2452 .halt_check = BRANCH_HALT_VOTED,
2453 .hwcg_reg = 0x75024,
2456 .enable_reg = 0x75024,
2457 .enable_mask = BIT(0),
2458 .hw.init = &(struct clk_init_data){
2459 .name = "gcc_sdcc1_ice_core_clk",
2460 .parent_hws = (const struct clk_hw*[]){
2461 &gcc_sdcc1_ice_core_clk_src.clkr.hw,
2464 .flags = CLK_SET_RATE_PARENT,
2465 .ops = &clk_branch2_ops,
2470 static struct clk_branch gcc_sdcc2_ahb_clk = {
2471 .halt_reg = 0x14008,
2472 .halt_check = BRANCH_HALT,
2474 .enable_reg = 0x14008,
2475 .enable_mask = BIT(0),
2476 .hw.init = &(struct clk_init_data){
2477 .name = "gcc_sdcc2_ahb_clk",
2478 .ops = &clk_branch2_ops,
2483 static struct clk_branch gcc_sdcc2_apps_clk = {
2484 .halt_reg = 0x14004,
2485 .halt_check = BRANCH_HALT,
2487 .enable_reg = 0x14004,
2488 .enable_mask = BIT(0),
2489 .hw.init = &(struct clk_init_data){
2490 .name = "gcc_sdcc2_apps_clk",
2491 .parent_hws = (const struct clk_hw*[]){
2492 &gcc_sdcc2_apps_clk_src.clkr.hw,
2495 .flags = CLK_SET_RATE_PARENT,
2496 .ops = &clk_branch2_ops,
2501 static struct clk_branch gcc_sdcc4_ahb_clk = {
2502 .halt_reg = 0x16008,
2503 .halt_check = BRANCH_HALT,
2505 .enable_reg = 0x16008,
2506 .enable_mask = BIT(0),
2507 .hw.init = &(struct clk_init_data){
2508 .name = "gcc_sdcc4_ahb_clk",
2509 .ops = &clk_branch2_ops,
2514 static struct clk_branch gcc_sdcc4_apps_clk = {
2515 .halt_reg = 0x16004,
2516 .halt_check = BRANCH_HALT,
2518 .enable_reg = 0x16004,
2519 .enable_mask = BIT(0),
2520 .hw.init = &(struct clk_init_data){
2521 .name = "gcc_sdcc4_apps_clk",
2522 .parent_hws = (const struct clk_hw*[]){
2523 &gcc_sdcc4_apps_clk_src.clkr.hw,
2526 .flags = CLK_SET_RATE_PARENT,
2527 .ops = &clk_branch2_ops,
2532 static struct clk_branch gcc_throttle_pcie_ahb_clk = {
2533 .halt_reg = 0x9001c,
2534 .halt_check = BRANCH_HALT,
2536 .enable_reg = 0x9001c,
2537 .enable_mask = BIT(0),
2538 .hw.init = &(struct clk_init_data){
2539 .name = "gcc_throttle_pcie_ahb_clk",
2540 .ops = &clk_branch2_ops,
2545 static struct clk_branch gcc_titan_nrt_throttle_core_clk = {
2546 .halt_reg = 0x26024,
2547 .halt_check = BRANCH_HALT_SKIP,
2548 .hwcg_reg = 0x26024,
2551 .enable_reg = 0x26024,
2552 .enable_mask = BIT(0),
2553 .hw.init = &(struct clk_init_data){
2554 .name = "gcc_titan_nrt_throttle_core_clk",
2555 .ops = &clk_branch2_ops,
2560 static struct clk_branch gcc_titan_rt_throttle_core_clk = {
2561 .halt_reg = 0x26018,
2562 .halt_check = BRANCH_HALT_SKIP,
2563 .hwcg_reg = 0x26018,
2566 .enable_reg = 0x26018,
2567 .enable_mask = BIT(0),
2568 .hw.init = &(struct clk_init_data){
2569 .name = "gcc_titan_rt_throttle_core_clk",
2570 .ops = &clk_branch2_ops,
2575 static struct clk_branch gcc_ufs_1_clkref_en = {
2576 .halt_reg = 0x8c000,
2577 .halt_check = BRANCH_HALT,
2579 .enable_reg = 0x8c000,
2580 .enable_mask = BIT(0),
2581 .hw.init = &(struct clk_init_data){
2582 .name = "gcc_ufs_1_clkref_en",
2583 .ops = &clk_branch2_ops,
2588 static struct clk_branch gcc_ufs_phy_ahb_clk = {
2589 .halt_reg = 0x77018,
2590 .halt_check = BRANCH_HALT_VOTED,
2591 .hwcg_reg = 0x77018,
2594 .enable_reg = 0x77018,
2595 .enable_mask = BIT(0),
2596 .hw.init = &(struct clk_init_data){
2597 .name = "gcc_ufs_phy_ahb_clk",
2598 .ops = &clk_branch2_ops,
2603 static struct clk_branch gcc_ufs_phy_axi_clk = {
2604 .halt_reg = 0x77010,
2605 .halt_check = BRANCH_HALT_VOTED,
2606 .hwcg_reg = 0x77010,
2609 .enable_reg = 0x77010,
2610 .enable_mask = BIT(0),
2611 .hw.init = &(struct clk_init_data){
2612 .name = "gcc_ufs_phy_axi_clk",
2613 .parent_hws = (const struct clk_hw*[]){
2614 &gcc_ufs_phy_axi_clk_src.clkr.hw,
2617 .flags = CLK_SET_RATE_PARENT,
2618 .ops = &clk_branch2_ops,
2623 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2624 .halt_reg = 0x77064,
2625 .halt_check = BRANCH_HALT_VOTED,
2626 .hwcg_reg = 0x77064,
2629 .enable_reg = 0x77064,
2630 .enable_mask = BIT(0),
2631 .hw.init = &(struct clk_init_data){
2632 .name = "gcc_ufs_phy_ice_core_clk",
2633 .parent_hws = (const struct clk_hw*[]){
2634 &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2637 .flags = CLK_SET_RATE_PARENT,
2638 .ops = &clk_branch2_ops,
2643 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2644 .halt_reg = 0x7709c,
2645 .halt_check = BRANCH_HALT_VOTED,
2646 .hwcg_reg = 0x7709c,
2649 .enable_reg = 0x7709c,
2650 .enable_mask = BIT(0),
2651 .hw.init = &(struct clk_init_data){
2652 .name = "gcc_ufs_phy_phy_aux_clk",
2653 .parent_hws = (const struct clk_hw*[]){
2654 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2657 .flags = CLK_SET_RATE_PARENT,
2658 .ops = &clk_branch2_ops,
2663 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
2664 .halt_reg = 0x77020,
2665 .halt_check = BRANCH_HALT_DELAY,
2667 .enable_reg = 0x77020,
2668 .enable_mask = BIT(0),
2669 .hw.init = &(struct clk_init_data){
2670 .name = "gcc_ufs_phy_rx_symbol_0_clk",
2671 .parent_hws = (const struct clk_hw*[]){
2672 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
2675 .flags = CLK_SET_RATE_PARENT,
2676 .ops = &clk_branch2_ops,
2681 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
2682 .halt_reg = 0x770b8,
2683 .halt_check = BRANCH_HALT_DELAY,
2685 .enable_reg = 0x770b8,
2686 .enable_mask = BIT(0),
2687 .hw.init = &(struct clk_init_data){
2688 .name = "gcc_ufs_phy_rx_symbol_1_clk",
2689 .parent_hws = (const struct clk_hw*[]){
2690 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
2693 .flags = CLK_SET_RATE_PARENT,
2694 .ops = &clk_branch2_ops,
2699 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
2700 .halt_reg = 0x7701c,
2701 .halt_check = BRANCH_HALT_DELAY,
2703 .enable_reg = 0x7701c,
2704 .enable_mask = BIT(0),
2705 .hw.init = &(struct clk_init_data){
2706 .name = "gcc_ufs_phy_tx_symbol_0_clk",
2707 .parent_hws = (const struct clk_hw*[]){
2708 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
2711 .flags = CLK_SET_RATE_PARENT,
2712 .ops = &clk_branch2_ops,
2717 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2718 .halt_reg = 0x7705c,
2719 .halt_check = BRANCH_HALT_VOTED,
2720 .hwcg_reg = 0x7705c,
2723 .enable_reg = 0x7705c,
2724 .enable_mask = BIT(0),
2725 .hw.init = &(struct clk_init_data){
2726 .name = "gcc_ufs_phy_unipro_core_clk",
2727 .parent_hws = (const struct clk_hw*[]){
2728 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2731 .flags = CLK_SET_RATE_PARENT,
2732 .ops = &clk_branch2_ops,
2737 static struct clk_branch gcc_usb30_prim_master_clk = {
2739 .halt_check = BRANCH_HALT,
2741 .enable_reg = 0xf010,
2742 .enable_mask = BIT(0),
2743 .hw.init = &(struct clk_init_data){
2744 .name = "gcc_usb30_prim_master_clk",
2745 .parent_hws = (const struct clk_hw*[]){
2746 &gcc_usb30_prim_master_clk_src.clkr.hw,
2749 .flags = CLK_SET_RATE_PARENT,
2750 .ops = &clk_branch2_ops,
2755 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
2757 .halt_check = BRANCH_HALT,
2759 .enable_reg = 0xf01c,
2760 .enable_mask = BIT(0),
2761 .hw.init = &(struct clk_init_data){
2762 .name = "gcc_usb30_prim_mock_utmi_clk",
2763 .parent_data = &(const struct clk_parent_data){
2765 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
2768 .flags = CLK_SET_RATE_PARENT,
2769 .ops = &clk_branch2_ops,
2774 static struct clk_branch gcc_usb30_prim_sleep_clk = {
2776 .halt_check = BRANCH_HALT,
2778 .enable_reg = 0xf018,
2779 .enable_mask = BIT(0),
2780 .hw.init = &(struct clk_init_data){
2781 .name = "gcc_usb30_prim_sleep_clk",
2782 .ops = &clk_branch2_ops,
2787 static struct clk_branch gcc_usb30_sec_master_clk = {
2788 .halt_reg = 0x9e010,
2789 .halt_check = BRANCH_HALT,
2791 .enable_reg = 0x9e010,
2792 .enable_mask = BIT(0),
2793 .hw.init = &(struct clk_init_data){
2794 .name = "gcc_usb30_sec_master_clk",
2795 .parent_hws = (const struct clk_hw*[]){
2796 &gcc_usb30_sec_master_clk_src.clkr.hw,
2799 .flags = CLK_SET_RATE_PARENT,
2800 .ops = &clk_branch2_ops,
2805 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
2806 .halt_reg = 0x9e01c,
2807 .halt_check = BRANCH_HALT,
2809 .enable_reg = 0x9e01c,
2810 .enable_mask = BIT(0),
2811 .hw.init = &(struct clk_init_data){
2812 .name = "gcc_usb30_sec_mock_utmi_clk",
2813 .parent_data = &(const struct clk_parent_data){
2815 &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw,
2818 .flags = CLK_SET_RATE_PARENT,
2819 .ops = &clk_branch2_ops,
2824 static struct clk_branch gcc_usb30_sec_sleep_clk = {
2825 .halt_reg = 0x9e018,
2826 .halt_check = BRANCH_HALT,
2828 .enable_reg = 0x9e018,
2829 .enable_mask = BIT(0),
2830 .hw.init = &(struct clk_init_data){
2831 .name = "gcc_usb30_sec_sleep_clk",
2832 .ops = &clk_branch2_ops,
2837 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
2839 .halt_check = BRANCH_HALT,
2841 .enable_reg = 0xf054,
2842 .enable_mask = BIT(0),
2843 .hw.init = &(struct clk_init_data){
2844 .name = "gcc_usb3_prim_phy_aux_clk",
2845 .parent_hws = (const struct clk_hw*[]){
2846 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2849 .flags = CLK_SET_RATE_PARENT,
2850 .ops = &clk_branch2_ops,
2855 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
2857 .halt_check = BRANCH_HALT,
2859 .enable_reg = 0xf058,
2860 .enable_mask = BIT(0),
2861 .hw.init = &(struct clk_init_data){
2862 .name = "gcc_usb3_prim_phy_com_aux_clk",
2863 .parent_hws = (const struct clk_hw*[]){
2864 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2867 .flags = CLK_SET_RATE_PARENT,
2868 .ops = &clk_branch2_ops,
2873 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
2875 .halt_check = BRANCH_HALT_DELAY,
2879 .enable_reg = 0xf05c,
2880 .enable_mask = BIT(0),
2881 .hw.init = &(struct clk_init_data){
2882 .name = "gcc_usb3_prim_phy_pipe_clk",
2883 .parent_hws = (const struct clk_hw*[]){
2884 &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
2887 .flags = CLK_SET_RATE_PARENT,
2888 .ops = &clk_branch2_ops,
2893 static struct clk_branch gcc_cfg_noc_lpass_clk = {
2894 .halt_reg = 0x47020,
2895 .halt_check = BRANCH_HALT,
2897 .enable_reg = 0x47020,
2898 .enable_mask = BIT(0),
2899 .hw.init = &(struct clk_init_data){
2900 .name = "gcc_cfg_noc_lpass_clk",
2901 .ops = &clk_branch2_aon_ops,
2905 static struct clk_branch gcc_mss_cfg_ahb_clk = {
2906 .halt_reg = 0x8a000,
2907 .halt_check = BRANCH_HALT,
2909 .enable_reg = 0x8a000,
2910 .enable_mask = BIT(0),
2911 .hw.init = &(struct clk_init_data){
2912 .name = "gcc_mss_cfg_ahb_clk",
2913 .ops = &clk_branch2_ops,
2918 static struct clk_branch gcc_mss_offline_axi_clk = {
2919 .halt_reg = 0x8a004,
2920 .halt_check = BRANCH_HALT_DELAY,
2922 .enable_reg = 0x8a004,
2923 .enable_mask = BIT(0),
2924 .hw.init = &(struct clk_init_data){
2925 .name = "gcc_mss_offline_axi_clk",
2926 .ops = &clk_branch2_ops,
2931 static struct clk_branch gcc_mss_snoc_axi_clk = {
2932 .halt_reg = 0x8a154,
2933 .halt_check = BRANCH_HALT_DELAY,
2935 .enable_reg = 0x8a154,
2936 .enable_mask = BIT(0),
2937 .hw.init = &(struct clk_init_data){
2938 .name = "gcc_mss_snoc_axi_clk",
2939 .ops = &clk_branch2_ops,
2944 static struct clk_branch gcc_mss_q6_memnoc_axi_clk = {
2945 .halt_reg = 0x8a158,
2946 .halt_check = BRANCH_HALT,
2948 .enable_reg = 0x8a158,
2949 .enable_mask = BIT(0),
2950 .hw.init = &(struct clk_init_data){
2951 .name = "gcc_mss_q6_memnoc_axi_clk",
2952 .ops = &clk_branch2_ops,
2957 static struct clk_regmap_mux gcc_mss_q6ss_boot_clk_src = {
2961 .parent_map = gcc_parent_map_15,
2963 .hw.init = &(struct clk_init_data){
2964 .name = "gcc_mss_q6ss_boot_clk_src",
2965 .parent_data = gcc_parent_data_15,
2966 .num_parents = ARRAY_SIZE(gcc_parent_data_15),
2967 .ops = &clk_regmap_mux_closest_ops,
2972 static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
2973 .halt_reg = 0x9e054,
2974 .halt_check = BRANCH_HALT,
2976 .enable_reg = 0x9e054,
2977 .enable_mask = BIT(0),
2978 .hw.init = &(struct clk_init_data){
2979 .name = "gcc_usb3_sec_phy_aux_clk",
2980 .parent_hws = (const struct clk_hw*[]){
2981 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
2984 .flags = CLK_SET_RATE_PARENT,
2985 .ops = &clk_branch2_ops,
2990 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
2991 .halt_reg = 0x9e058,
2992 .halt_check = BRANCH_HALT,
2994 .enable_reg = 0x9e058,
2995 .enable_mask = BIT(0),
2996 .hw.init = &(struct clk_init_data){
2997 .name = "gcc_usb3_sec_phy_com_aux_clk",
2998 .parent_hws = (const struct clk_hw*[]){
2999 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
3002 .flags = CLK_SET_RATE_PARENT,
3003 .ops = &clk_branch2_ops,
3008 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
3009 .halt_reg = 0x9e05c,
3010 .halt_check = BRANCH_HALT_SKIP,
3011 .hwcg_reg = 0x9e05c,
3014 .enable_reg = 0x9e05c,
3015 .enable_mask = BIT(0),
3016 .hw.init = &(struct clk_init_data){
3017 .name = "gcc_usb3_sec_phy_pipe_clk",
3018 .parent_hws = (const struct clk_hw*[]){
3019 &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw,
3022 .flags = CLK_SET_RATE_PARENT,
3023 .ops = &clk_branch2_ops,
3028 static struct clk_branch gcc_video_axi0_clk = {
3029 .halt_reg = 0x2800c,
3030 .halt_check = BRANCH_HALT_SKIP,
3031 .hwcg_reg = 0x2800c,
3034 .enable_reg = 0x2800c,
3035 .enable_mask = BIT(0),
3036 .hw.init = &(struct clk_init_data){
3037 .name = "gcc_video_axi0_clk",
3038 .ops = &clk_branch2_ops,
3043 static struct clk_branch gcc_video_mvp_throttle_core_clk = {
3044 .halt_reg = 0x28010,
3045 .halt_check = BRANCH_HALT_SKIP,
3046 .hwcg_reg = 0x28010,
3049 .enable_reg = 0x28010,
3050 .enable_mask = BIT(0),
3051 .hw.init = &(struct clk_init_data){
3052 .name = "gcc_video_mvp_throttle_core_clk",
3053 .ops = &clk_branch2_ops,
3058 static struct clk_branch gcc_wpss_ahb_clk = {
3059 .halt_reg = 0x9d154,
3060 .halt_check = BRANCH_HALT,
3062 .enable_reg = 0x9d154,
3063 .enable_mask = BIT(0),
3064 .hw.init = &(struct clk_init_data){
3065 .name = "gcc_wpss_ahb_clk",
3066 .ops = &clk_branch2_ops,
3071 static struct clk_branch gcc_wpss_ahb_bdg_mst_clk = {
3072 .halt_reg = 0x9d158,
3073 .halt_check = BRANCH_HALT,
3075 .enable_reg = 0x9d158,
3076 .enable_mask = BIT(0),
3077 .hw.init = &(struct clk_init_data){
3078 .name = "gcc_wpss_ahb_bdg_mst_clk",
3079 .ops = &clk_branch2_ops,
3084 static struct clk_branch gcc_wpss_rscp_clk = {
3085 .halt_reg = 0x9d16c,
3086 .halt_check = BRANCH_HALT,
3088 .enable_reg = 0x9d16c,
3089 .enable_mask = BIT(0),
3090 .hw.init = &(struct clk_init_data){
3091 .name = "gcc_wpss_rscp_clk",
3092 .ops = &clk_branch2_ops,
3097 static struct gdsc gcc_pcie_0_gdsc = {
3100 .name = "gcc_pcie_0_gdsc",
3102 .pwrsts = PWRSTS_OFF_ON,
3106 static struct gdsc gcc_pcie_1_gdsc = {
3109 .name = "gcc_pcie_1_gdsc",
3111 .pwrsts = PWRSTS_OFF_ON,
3115 static struct gdsc gcc_ufs_phy_gdsc = {
3118 .name = "gcc_ufs_phy_gdsc",
3120 .pwrsts = PWRSTS_OFF_ON,
3124 static struct gdsc gcc_usb30_prim_gdsc = {
3127 .name = "gcc_usb30_prim_gdsc",
3129 .pwrsts = PWRSTS_OFF_ON,
3133 static struct gdsc gcc_usb30_sec_gdsc = {
3136 .name = "gcc_usb30_sec_gdsc",
3138 .pwrsts = PWRSTS_OFF_ON,
3142 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
3145 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
3147 .pwrsts = PWRSTS_OFF_ON,
3151 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
3154 .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
3156 .pwrsts = PWRSTS_OFF_ON,
3160 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc = {
3163 .name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc",
3165 .pwrsts = PWRSTS_OFF_ON,
3169 static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = {
3172 .name = "hlos1_vote_turing_mmu_tbu0_gdsc",
3174 .pwrsts = PWRSTS_OFF_ON,
3178 static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = {
3181 .name = "hlos1_vote_turing_mmu_tbu1_gdsc",
3183 .pwrsts = PWRSTS_OFF_ON,
3187 static struct clk_regmap *gcc_sc7280_clocks[] = {
3188 [GCC_AGGRE_NOC_PCIE_0_AXI_CLK] = &gcc_aggre_noc_pcie_0_axi_clk.clkr,
3189 [GCC_AGGRE_NOC_PCIE_1_AXI_CLK] = &gcc_aggre_noc_pcie_1_axi_clk.clkr,
3190 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3191 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3192 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
3193 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
3194 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
3195 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3196 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
3197 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3198 [GCC_DDRSS_PCIE_SF_CLK] = &gcc_ddrss_pcie_sf_clk.clkr,
3199 [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
3200 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
3201 [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
3202 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3203 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3204 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3205 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3206 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3207 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3208 [GCC_GPLL0] = &gcc_gpll0.clkr,
3209 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
3210 [GCC_GPLL0_OUT_ODD] = &gcc_gpll0_out_odd.clkr,
3211 [GCC_GPLL1] = &gcc_gpll1.clkr,
3212 [GCC_GPLL10] = &gcc_gpll10.clkr,
3213 [GCC_GPLL4] = &gcc_gpll4.clkr,
3214 [GCC_GPLL9] = &gcc_gpll9.clkr,
3215 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3216 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3217 [GCC_GPU_IREF_EN] = &gcc_gpu_iref_en.clkr,
3218 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3219 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3220 [GCC_PCIE0_PHY_RCHNG_CLK] = &gcc_pcie0_phy_rchng_clk.clkr,
3221 [GCC_PCIE1_PHY_RCHNG_CLK] = &gcc_pcie1_phy_rchng_clk.clkr,
3222 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3223 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
3224 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3225 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3226 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
3227 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3228 [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
3229 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3230 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3231 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3232 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
3233 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3234 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3235 [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
3236 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3237 [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,
3238 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3239 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
3240 [GCC_PCIE_THROTTLE_CORE_CLK] = &gcc_pcie_throttle_core_clk.clkr,
3241 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3242 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3243 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3244 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3245 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
3246 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
3247 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3248 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
3249 [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
3250 [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
3251 [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
3252 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
3253 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
3254 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3255 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3256 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3257 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3258 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3259 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3260 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3261 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3262 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3263 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3264 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3265 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3266 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3267 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3268 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3269 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3270 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
3271 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
3272 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3273 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3274 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3275 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3276 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3277 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3278 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3279 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3280 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3281 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3282 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3283 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3284 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
3285 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
3286 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
3287 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
3288 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3289 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3290 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3291 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3292 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3293 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3294 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
3295 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3296 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
3297 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3298 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3299 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3300 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3301 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3302 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3303 [GCC_THROTTLE_PCIE_AHB_CLK] = &gcc_throttle_pcie_ahb_clk.clkr,
3304 [GCC_TITAN_NRT_THROTTLE_CORE_CLK] =
3305 &gcc_titan_nrt_throttle_core_clk.clkr,
3306 [GCC_TITAN_RT_THROTTLE_CORE_CLK] = &gcc_titan_rt_throttle_core_clk.clkr,
3307 [GCC_UFS_1_CLKREF_EN] = &gcc_ufs_1_clkref_en.clkr,
3308 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3309 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3310 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3311 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3312 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3313 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3314 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3315 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3316 [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] =
3317 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
3318 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
3319 [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] =
3320 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
3321 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3322 [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] =
3323 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
3324 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3325 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
3326 &gcc_ufs_phy_unipro_core_clk_src.clkr,
3327 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3328 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3329 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3330 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
3331 &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3332 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] =
3333 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
3334 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3335 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
3336 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
3337 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
3338 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =
3339 &gcc_usb30_sec_mock_utmi_clk_src.clkr,
3340 [GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] =
3341 &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr,
3342 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
3343 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3344 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3345 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3346 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3347 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
3348 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
3349 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
3350 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
3351 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
3352 [GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr,
3353 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
3354 [GCC_VIDEO_MVP_THROTTLE_CORE_CLK] =
3355 &gcc_video_mvp_throttle_core_clk.clkr,
3356 [GCC_CFG_NOC_LPASS_CLK] = &gcc_cfg_noc_lpass_clk.clkr,
3357 [GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC] = &gcc_mss_gpll0_main_div_clk_src.clkr,
3358 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3359 [GCC_MSS_OFFLINE_AXI_CLK] = &gcc_mss_offline_axi_clk.clkr,
3360 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
3361 [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
3362 [GCC_MSS_Q6SS_BOOT_CLK_SRC] = &gcc_mss_q6ss_boot_clk_src.clkr,
3363 [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
3364 [GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK] =
3365 &gcc_aggre_noc_pcie_center_sf_axi_clk.clkr,
3366 [GCC_PCIE_CLKREF_EN] = &gcc_pcie_clkref_en.clkr,
3367 [GCC_EDP_CLKREF_EN] = &gcc_edp_clkref_en.clkr,
3368 [GCC_SEC_CTRL_CLK_SRC] = &gcc_sec_ctrl_clk_src.clkr,
3369 [GCC_WPSS_AHB_CLK] = &gcc_wpss_ahb_clk.clkr,
3370 [GCC_WPSS_AHB_BDG_MST_CLK] = &gcc_wpss_ahb_bdg_mst_clk.clkr,
3371 [GCC_WPSS_RSCP_CLK] = &gcc_wpss_rscp_clk.clkr,
3374 static struct gdsc *gcc_sc7280_gdscs[] = {
3375 [GCC_PCIE_0_GDSC] = &gcc_pcie_0_gdsc,
3376 [GCC_PCIE_1_GDSC] = &gcc_pcie_1_gdsc,
3377 [GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc,
3378 [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc,
3379 [GCC_USB30_SEC_GDSC] = &gcc_usb30_sec_gdsc,
3380 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
3381 [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
3382 [HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc,
3383 [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc,
3384 [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc,
3387 static const struct qcom_reset_map gcc_sc7280_resets[] = {
3388 [GCC_PCIE_0_BCR] = { 0x6b000 },
3389 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3390 [GCC_PCIE_1_BCR] = { 0x8d000 },
3391 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3392 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3393 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3394 [GCC_SDCC1_BCR] = { 0x75000 },
3395 [GCC_SDCC2_BCR] = { 0x14000 },
3396 [GCC_SDCC4_BCR] = { 0x16000 },
3397 [GCC_UFS_PHY_BCR] = { 0x77000 },
3398 [GCC_USB30_PRIM_BCR] = { 0xf000 },
3399 [GCC_USB30_SEC_BCR] = { 0x9e000 },
3400 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3401 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3402 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3403 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3406 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
3407 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
3408 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
3409 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
3410 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
3411 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
3412 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
3413 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
3414 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
3415 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
3416 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
3417 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
3418 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
3419 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
3420 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
3421 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
3422 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
3425 static const struct regmap_config gcc_sc7280_regmap_config = {
3429 .max_register = 0x9f128,
3433 static const struct qcom_cc_desc gcc_sc7280_desc = {
3434 .config = &gcc_sc7280_regmap_config,
3435 .clks = gcc_sc7280_clocks,
3436 .num_clks = ARRAY_SIZE(gcc_sc7280_clocks),
3437 .resets = gcc_sc7280_resets,
3438 .num_resets = ARRAY_SIZE(gcc_sc7280_resets),
3439 .gdscs = gcc_sc7280_gdscs,
3440 .num_gdscs = ARRAY_SIZE(gcc_sc7280_gdscs),
3443 static const struct of_device_id gcc_sc7280_match_table[] = {
3444 { .compatible = "qcom,gcc-sc7280" },
3447 MODULE_DEVICE_TABLE(of, gcc_sc7280_match_table);
3449 static int gcc_sc7280_probe(struct platform_device *pdev)
3451 struct regmap *regmap;
3454 regmap = qcom_cc_map(pdev, &gcc_sc7280_desc);
3456 return PTR_ERR(regmap);
3459 * Keep the clocks always-ON
3460 * GCC_CAMERA_AHB_CLK/XO_CLK, GCC_DISP_AHB_CLK/XO_CLK
3461 * GCC_VIDEO_AHB_CLK/XO_CLK, GCC_GPU_CFG_AHB_CLK
3463 regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0));
3464 regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0));
3465 regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0));
3466 regmap_update_bits(regmap, 0x2701C, BIT(0), BIT(0));
3467 regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0));
3468 regmap_update_bits(regmap, 0x28014, BIT(0), BIT(0));
3469 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
3471 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
3472 ARRAY_SIZE(gcc_dfs_clocks));
3476 return qcom_cc_really_probe(pdev, &gcc_sc7280_desc, regmap);
3479 static struct platform_driver gcc_sc7280_driver = {
3480 .probe = gcc_sc7280_probe,
3482 .name = "gcc-sc7280",
3483 .of_match_table = gcc_sc7280_match_table,
3487 static int __init gcc_sc7280_init(void)
3489 return platform_driver_register(&gcc_sc7280_driver);
3491 subsys_initcall(gcc_sc7280_init);
3493 static void __exit gcc_sc7280_exit(void)
3495 platform_driver_unregister(&gcc_sc7280_driver);
3497 module_exit(gcc_sc7280_exit);
3499 MODULE_DESCRIPTION("QTI GCC SC7280 Driver");
3500 MODULE_LICENSE("GPL v2");