1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
6 #include <linux/clk-provider.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/platform_device.h>
11 #include <linux/regmap.h>
13 #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
15 #include "clk-alpha-pll.h"
16 #include "clk-branch.h"
18 #include "clk-regmap-divider.h"
45 static const struct pll_vco brammo_vco[] = {
46 { 500000000, 1250000000, 0 },
49 static const struct pll_vco default_vco[] = {
50 { 500000000, 1000000000, 2 },
53 static const struct pll_vco spark_vco[] = {
54 { 750000000, 1500000000, 1 },
57 static struct clk_alpha_pll gpll0 = {
59 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
61 .enable_reg = 0x79000,
62 .enable_mask = BIT(0),
63 .hw.init = &(struct clk_init_data){
65 .parent_data = &(const struct clk_parent_data){
69 .ops = &clk_alpha_pll_ops,
74 static const struct clk_div_table post_div_table_gpll0_out_aux2[] = {
79 static struct clk_alpha_pll_postdiv gpll0_out_aux2 = {
82 .post_div_table = post_div_table_gpll0_out_aux2,
83 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_aux2),
85 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
86 .clkr.hw.init = &(struct clk_init_data){
87 .name = "gpll0_out_aux2",
88 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
90 .ops = &clk_alpha_pll_postdiv_ro_ops,
94 static struct clk_alpha_pll gpll1 = {
96 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
98 .enable_reg = 0x79000,
99 .enable_mask = BIT(1),
100 .hw.init = &(struct clk_init_data){
102 .parent_data = &(const struct clk_parent_data){
103 .fw_name = "bi_tcxo",
106 .ops = &clk_alpha_pll_ops,
111 /* 1152MHz configuration */
112 static const struct alpha_pll_config gpll10_config = {
115 .vco_val = 0x1 << 20,
116 .vco_mask = GENMASK(21, 20),
117 .main_output_mask = BIT(0),
118 .config_ctl_val = 0x4001055B,
119 .test_ctl_hi1_val = 0x1,
122 static struct clk_alpha_pll gpll10 = {
124 .vco_table = spark_vco,
125 .num_vco = ARRAY_SIZE(spark_vco),
126 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
128 .enable_reg = 0x79000,
129 .enable_mask = BIT(10),
130 .hw.init = &(struct clk_init_data){
132 .parent_data = &(const struct clk_parent_data){
133 .fw_name = "bi_tcxo",
136 .ops = &clk_alpha_pll_ops,
141 /* 532MHz configuration */
142 static const struct alpha_pll_config gpll11_config = {
146 .alpha_en_mask = BIT(24),
147 .vco_val = 0x2 << 20,
148 .vco_mask = GENMASK(21, 20),
149 .main_output_mask = BIT(0),
150 .config_ctl_val = 0x4001055B,
151 .test_ctl_hi1_val = 0x1,
154 static struct clk_alpha_pll gpll11 = {
156 .vco_table = default_vco,
157 .num_vco = ARRAY_SIZE(default_vco),
158 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
159 .flags = SUPPORTS_DYNAMIC_UPDATE,
161 .enable_reg = 0x79000,
162 .enable_mask = BIT(11),
163 .hw.init = &(struct clk_init_data){
165 .parent_data = &(const struct clk_parent_data){
166 .fw_name = "bi_tcxo",
169 .ops = &clk_alpha_pll_ops,
174 static struct clk_alpha_pll gpll3 = {
176 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
178 .enable_reg = 0x79000,
179 .enable_mask = BIT(3),
180 .hw.init = &(struct clk_init_data){
182 .parent_data = &(const struct clk_parent_data){
183 .fw_name = "bi_tcxo",
186 .ops = &clk_alpha_pll_ops,
191 static const struct clk_div_table post_div_table_gpll3_out_main[] = {
196 static struct clk_alpha_pll_postdiv gpll3_out_main = {
199 .post_div_table = post_div_table_gpll3_out_main,
200 .num_post_div = ARRAY_SIZE(post_div_table_gpll3_out_main),
202 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
203 .clkr.hw.init = &(struct clk_init_data){
204 .name = "gpll3_out_main",
205 .parent_hws = (const struct clk_hw *[]){ &gpll3.clkr.hw },
207 .ops = &clk_alpha_pll_postdiv_ro_ops,
211 static struct clk_alpha_pll gpll4 = {
213 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
215 .enable_reg = 0x79000,
216 .enable_mask = BIT(4),
217 .hw.init = &(struct clk_init_data){
219 .parent_data = &(const struct clk_parent_data){
220 .fw_name = "bi_tcxo",
223 .ops = &clk_alpha_pll_ops,
228 static struct clk_alpha_pll gpll5 = {
230 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
232 .enable_reg = 0x79000,
233 .enable_mask = BIT(5),
234 .hw.init = &(struct clk_init_data){
236 .parent_data = &(const struct clk_parent_data){
237 .fw_name = "bi_tcxo",
240 .ops = &clk_alpha_pll_ops,
245 static struct clk_alpha_pll gpll6 = {
247 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
249 .enable_reg = 0x79000,
250 .enable_mask = BIT(6),
251 .hw.init = &(struct clk_init_data){
253 .parent_data = &(const struct clk_parent_data){
254 .fw_name = "bi_tcxo",
257 .ops = &clk_alpha_pll_ops,
262 static const struct clk_div_table post_div_table_gpll6_out_main[] = {
267 static struct clk_alpha_pll_postdiv gpll6_out_main = {
270 .post_div_table = post_div_table_gpll6_out_main,
271 .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main),
273 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
274 .clkr.hw.init = &(struct clk_init_data){
275 .name = "gpll6_out_main",
276 .parent_hws = (const struct clk_hw *[]){ &gpll6.clkr.hw },
278 .ops = &clk_alpha_pll_postdiv_ro_ops,
282 static struct clk_alpha_pll gpll7 = {
284 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
286 .enable_reg = 0x79000,
287 .enable_mask = BIT(7),
288 .hw.init = &(struct clk_init_data){
290 .parent_data = &(const struct clk_parent_data){
291 .fw_name = "bi_tcxo",
294 .ops = &clk_alpha_pll_ops,
299 /* 533.2MHz configuration */
300 static const struct alpha_pll_config gpll8_config = {
304 .alpha_en_mask = BIT(24),
305 .vco_val = 0x2 << 20,
306 .vco_mask = GENMASK(21, 20),
307 .main_output_mask = BIT(0),
308 .early_output_mask = BIT(3),
309 .post_div_val = 0x1 << 8,
310 .post_div_mask = GENMASK(11, 8),
311 .config_ctl_val = 0x4001055B,
312 .test_ctl_hi1_val = 0x1,
315 static struct clk_alpha_pll gpll8 = {
317 .vco_table = default_vco,
318 .num_vco = ARRAY_SIZE(default_vco),
319 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
320 .flags = SUPPORTS_DYNAMIC_UPDATE,
322 .enable_reg = 0x79000,
323 .enable_mask = BIT(8),
324 .hw.init = &(struct clk_init_data){
326 .parent_data = &(const struct clk_parent_data){
327 .fw_name = "bi_tcxo",
330 .ops = &clk_alpha_pll_ops,
335 static const struct clk_div_table post_div_table_gpll8_out_main[] = {
340 static struct clk_alpha_pll_postdiv gpll8_out_main = {
343 .post_div_table = post_div_table_gpll8_out_main,
344 .num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main),
346 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
347 .clkr.hw.init = &(struct clk_init_data){
348 .name = "gpll8_out_main",
349 .parent_hws = (const struct clk_hw *[]){ &gpll8.clkr.hw },
351 .flags = CLK_SET_RATE_PARENT,
352 .ops = &clk_alpha_pll_postdiv_ro_ops,
356 /* 1152MHz configuration */
357 static const struct alpha_pll_config gpll9_config = {
360 .post_div_val = 0x1 << 8,
361 .post_div_mask = GENMASK(9, 8),
362 .main_output_mask = BIT(0),
363 .early_output_mask = BIT(3),
364 .config_ctl_val = 0x00004289,
365 .test_ctl_val = 0x08000000,
368 static struct clk_alpha_pll gpll9 = {
370 .vco_table = brammo_vco,
371 .num_vco = ARRAY_SIZE(brammo_vco),
372 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO],
374 .enable_reg = 0x79000,
375 .enable_mask = BIT(9),
376 .hw.init = &(struct clk_init_data){
378 .parent_data = &(const struct clk_parent_data){
379 .fw_name = "bi_tcxo",
382 .ops = &clk_alpha_pll_ops,
387 static const struct clk_div_table post_div_table_gpll9_out_main[] = {
392 static struct clk_alpha_pll_postdiv gpll9_out_main = {
395 .post_div_table = post_div_table_gpll9_out_main,
396 .num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main),
398 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO],
399 .clkr.hw.init = &(struct clk_init_data){
400 .name = "gpll9_out_main",
401 .parent_hws = (const struct clk_hw *[]){ &gpll9.clkr.hw },
403 .flags = CLK_SET_RATE_PARENT,
404 .ops = &clk_alpha_pll_postdiv_ro_ops,
408 static const struct parent_map gcc_parent_map_0[] = {
410 { P_GPLL0_OUT_EARLY, 1 },
411 { P_GPLL0_OUT_AUX2, 2 },
414 static const struct clk_parent_data gcc_parents_0[] = {
415 { .fw_name = "bi_tcxo" },
416 { .hw = &gpll0.clkr.hw },
417 { .hw = &gpll0_out_aux2.clkr.hw },
420 static const struct parent_map gcc_parent_map_1[] = {
422 { P_GPLL0_OUT_EARLY, 1 },
423 { P_GPLL0_OUT_AUX2, 2 },
424 { P_GPLL6_OUT_MAIN, 4 },
427 static const struct clk_parent_data gcc_parents_1[] = {
428 { .fw_name = "bi_tcxo" },
429 { .hw = &gpll0.clkr.hw },
430 { .hw = &gpll0_out_aux2.clkr.hw },
431 { .hw = &gpll6_out_main.clkr.hw },
434 static const struct parent_map gcc_parent_map_2[] = {
436 { P_GPLL0_OUT_EARLY, 1 },
437 { P_GPLL0_OUT_AUX2, 2 },
441 static const struct clk_parent_data gcc_parents_2[] = {
442 { .fw_name = "bi_tcxo" },
443 { .hw = &gpll0.clkr.hw },
444 { .hw = &gpll0_out_aux2.clkr.hw },
445 { .fw_name = "sleep_clk" },
448 static const struct parent_map gcc_parent_map_3[] = {
450 { P_GPLL0_OUT_EARLY, 1 },
451 { P_GPLL9_OUT_EARLY, 2 },
452 { P_GPLL10_OUT_MAIN, 3 },
453 { P_GPLL9_OUT_MAIN, 5 },
454 { P_GPLL3_OUT_MAIN, 6 },
457 static const struct clk_parent_data gcc_parents_3[] = {
458 { .fw_name = "bi_tcxo" },
459 { .hw = &gpll0.clkr.hw },
460 { .hw = &gpll9.clkr.hw },
461 { .hw = &gpll10.clkr.hw },
462 { .hw = &gpll9_out_main.clkr.hw },
463 { .hw = &gpll3_out_main.clkr.hw },
466 static const struct parent_map gcc_parent_map_4[] = {
468 { P_GPLL0_OUT_EARLY, 1 },
469 { P_GPLL0_OUT_AUX2, 2 },
470 { P_GPLL10_OUT_MAIN, 3 },
471 { P_GPLL4_OUT_MAIN, 5 },
472 { P_GPLL3_OUT_EARLY, 6 },
475 static const struct clk_parent_data gcc_parents_4[] = {
476 { .fw_name = "bi_tcxo" },
477 { .hw = &gpll0.clkr.hw },
478 { .hw = &gpll0_out_aux2.clkr.hw },
479 { .hw = &gpll10.clkr.hw },
480 { .hw = &gpll4.clkr.hw },
481 { .hw = &gpll3.clkr.hw },
484 static const struct parent_map gcc_parent_map_5[] = {
486 { P_GPLL0_OUT_EARLY, 1 },
487 { P_GPLL0_OUT_AUX2, 2 },
488 { P_GPLL4_OUT_MAIN, 5 },
489 { P_GPLL3_OUT_MAIN, 6 },
492 static const struct clk_parent_data gcc_parents_5[] = {
493 { .fw_name = "bi_tcxo" },
494 { .hw = &gpll0.clkr.hw },
495 { .hw = &gpll0_out_aux2.clkr.hw },
496 { .hw = &gpll4.clkr.hw },
497 { .hw = &gpll3_out_main.clkr.hw },
500 static const struct parent_map gcc_parent_map_6[] = {
502 { P_GPLL0_OUT_EARLY, 1 },
503 { P_GPLL8_OUT_EARLY, 2 },
504 { P_GPLL10_OUT_MAIN, 3 },
505 { P_GPLL8_OUT_MAIN, 4 },
506 { P_GPLL9_OUT_MAIN, 5 },
507 { P_GPLL3_OUT_EARLY, 6 },
510 static const struct clk_parent_data gcc_parents_6[] = {
511 { .fw_name = "bi_tcxo" },
512 { .hw = &gpll0.clkr.hw },
513 { .hw = &gpll8.clkr.hw },
514 { .hw = &gpll10.clkr.hw },
515 { .hw = &gpll8_out_main.clkr.hw },
516 { .hw = &gpll9_out_main.clkr.hw },
517 { .hw = &gpll3.clkr.hw },
520 static const struct parent_map gcc_parent_map_7[] = {
522 { P_GPLL0_OUT_EARLY, 1 },
523 { P_GPLL8_OUT_EARLY, 2 },
524 { P_GPLL10_OUT_MAIN, 3 },
525 { P_GPLL8_OUT_MAIN, 4 },
526 { P_GPLL9_OUT_MAIN, 5 },
527 { P_GPLL3_OUT_MAIN, 6 },
530 static const struct clk_parent_data gcc_parents_7[] = {
531 { .fw_name = "bi_tcxo" },
532 { .hw = &gpll0.clkr.hw },
533 { .hw = &gpll8.clkr.hw },
534 { .hw = &gpll10.clkr.hw },
535 { .hw = &gpll8_out_main.clkr.hw },
536 { .hw = &gpll9_out_main.clkr.hw },
537 { .hw = &gpll3_out_main.clkr.hw },
540 static const struct parent_map gcc_parent_map_8[] = {
542 { P_GPLL0_OUT_EARLY, 1 },
543 { P_GPLL8_OUT_EARLY, 2 },
544 { P_GPLL10_OUT_MAIN, 3 },
545 { P_GPLL6_OUT_MAIN, 4 },
546 { P_GPLL9_OUT_MAIN, 5 },
547 { P_GPLL3_OUT_EARLY, 6 },
550 static const struct clk_parent_data gcc_parents_8[] = {
551 { .fw_name = "bi_tcxo" },
552 { .hw = &gpll0.clkr.hw },
553 { .hw = &gpll8.clkr.hw },
554 { .hw = &gpll10.clkr.hw },
555 { .hw = &gpll6_out_main.clkr.hw },
556 { .hw = &gpll9_out_main.clkr.hw },
557 { .hw = &gpll3.clkr.hw },
560 static const struct parent_map gcc_parent_map_9[] = {
562 { P_GPLL0_OUT_EARLY, 1 },
563 { P_GPLL0_OUT_AUX2, 2 },
564 { P_GPLL10_OUT_MAIN, 3 },
565 { P_GPLL8_OUT_MAIN, 4 },
566 { P_GPLL9_OUT_MAIN, 5 },
567 { P_GPLL3_OUT_EARLY, 6 },
570 static const struct clk_parent_data gcc_parents_9[] = {
571 { .fw_name = "bi_tcxo" },
572 { .hw = &gpll0.clkr.hw },
573 { .hw = &gpll0_out_aux2.clkr.hw },
574 { .hw = &gpll10.clkr.hw },
575 { .hw = &gpll8_out_main.clkr.hw },
576 { .hw = &gpll9_out_main.clkr.hw },
577 { .hw = &gpll3.clkr.hw },
580 static const struct parent_map gcc_parent_map_10[] = {
582 { P_GPLL0_OUT_EARLY, 1 },
583 { P_GPLL8_OUT_EARLY, 2 },
584 { P_GPLL10_OUT_MAIN, 3 },
585 { P_GPLL6_OUT_EARLY, 5 },
586 { P_GPLL3_OUT_MAIN, 6 },
589 static const struct clk_parent_data gcc_parents_10[] = {
590 { .fw_name = "bi_tcxo" },
591 { .hw = &gpll0.clkr.hw },
592 { .hw = &gpll8.clkr.hw },
593 { .hw = &gpll10.clkr.hw },
594 { .hw = &gpll6.clkr.hw },
595 { .hw = &gpll3_out_main.clkr.hw },
598 static const struct parent_map gcc_parent_map_12[] = {
600 { P_GPLL0_OUT_EARLY, 1 },
601 { P_GPLL0_OUT_AUX2, 2 },
602 { P_GPLL7_OUT_MAIN, 3 },
603 { P_GPLL4_OUT_MAIN, 5 },
606 static const struct clk_parent_data gcc_parents_12[] = {
607 { .fw_name = "bi_tcxo" },
608 { .hw = &gpll0.clkr.hw },
609 { .hw = &gpll0_out_aux2.clkr.hw },
610 { .hw = &gpll7.clkr.hw },
611 { .hw = &gpll4.clkr.hw },
614 static const struct parent_map gcc_parent_map_13[] = {
619 static const struct clk_parent_data gcc_parents_13[] = {
620 { .fw_name = "bi_tcxo" },
621 { .fw_name = "sleep_clk" },
624 static const struct parent_map gcc_parent_map_14[] = {
626 { P_GPLL11_OUT_MAIN, 1 },
627 { P_GPLL11_OUT_AUX, 2 },
628 { P_GPLL11_OUT_AUX2, 3 },
631 static const struct clk_parent_data gcc_parents_14[] = {
632 { .fw_name = "bi_tcxo" },
633 { .hw = &gpll11.clkr.hw },
634 { .hw = &gpll11.clkr.hw },
635 { .hw = &gpll11.clkr.hw },
638 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
639 F(19200000, P_BI_TCXO, 1, 0, 0),
643 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
647 .parent_map = gcc_parent_map_0,
648 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
649 .clkr.hw.init = &(struct clk_init_data){
650 .name = "gcc_usb30_prim_mock_utmi_clk_src",
651 .parent_data = gcc_parents_0,
652 .num_parents = ARRAY_SIZE(gcc_parents_0),
653 .ops = &clk_rcg2_ops,
657 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv = {
661 .clkr.hw.init = &(struct clk_init_data) {
662 .name = "gcc_usb30_prim_mock_utmi_postdiv",
663 .parent_hws = (const struct clk_hw *[])
664 { &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw },
666 .flags = CLK_SET_RATE_PARENT,
667 .ops = &clk_regmap_div_ro_ops,
671 static const struct freq_tbl ftbl_gcc_camss_axi_clk_src[] = {
672 F(19200000, P_BI_TCXO, 1, 0, 0),
673 F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),
674 F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0),
675 F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0),
679 static struct clk_rcg2 gcc_camss_axi_clk_src = {
683 .parent_map = gcc_parent_map_4,
684 .freq_tbl = ftbl_gcc_camss_axi_clk_src,
685 .clkr.hw.init = &(struct clk_init_data){
686 .name = "gcc_camss_axi_clk_src",
687 .parent_data = gcc_parents_4,
688 .num_parents = ARRAY_SIZE(gcc_parents_4),
689 .ops = &clk_rcg2_ops,
693 static const struct freq_tbl ftbl_gcc_camss_cci_clk_src[] = {
694 F(19200000, P_BI_TCXO, 1, 0, 0),
695 F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),
699 static struct clk_rcg2 gcc_camss_cci_clk_src = {
703 .parent_map = gcc_parent_map_9,
704 .freq_tbl = ftbl_gcc_camss_cci_clk_src,
705 .clkr.hw.init = &(struct clk_init_data){
706 .name = "gcc_camss_cci_clk_src",
707 .parent_data = gcc_parents_9,
708 .num_parents = ARRAY_SIZE(gcc_parents_9),
709 .ops = &clk_rcg2_ops,
713 static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = {
714 F(19200000, P_BI_TCXO, 1, 0, 0),
715 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
716 F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0),
717 F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0),
721 static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = {
725 .parent_map = gcc_parent_map_5,
726 .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
727 .clkr.hw.init = &(struct clk_init_data){
728 .name = "gcc_camss_csi0phytimer_clk_src",
729 .parent_data = gcc_parents_5,
730 .num_parents = ARRAY_SIZE(gcc_parents_5),
731 .ops = &clk_rcg2_ops,
735 static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = {
739 .parent_map = gcc_parent_map_5,
740 .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
741 .clkr.hw.init = &(struct clk_init_data){
742 .name = "gcc_camss_csi1phytimer_clk_src",
743 .parent_data = gcc_parents_5,
744 .num_parents = ARRAY_SIZE(gcc_parents_5),
745 .ops = &clk_rcg2_ops,
749 static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = {
750 F(19200000, P_BI_TCXO, 1, 0, 0),
751 F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 24),
752 F(64000000, P_GPLL9_OUT_EARLY, 9, 1, 2),
756 static struct clk_rcg2 gcc_camss_mclk0_clk_src = {
760 .parent_map = gcc_parent_map_3,
761 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
762 .clkr.hw.init = &(struct clk_init_data){
763 .name = "gcc_camss_mclk0_clk_src",
764 .parent_data = gcc_parents_3,
765 .num_parents = ARRAY_SIZE(gcc_parents_3),
766 .flags = CLK_OPS_PARENT_ENABLE,
767 .ops = &clk_rcg2_ops,
771 static struct clk_rcg2 gcc_camss_mclk1_clk_src = {
775 .parent_map = gcc_parent_map_3,
776 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
777 .clkr.hw.init = &(struct clk_init_data){
778 .name = "gcc_camss_mclk1_clk_src",
779 .parent_data = gcc_parents_3,
780 .num_parents = ARRAY_SIZE(gcc_parents_3),
781 .flags = CLK_OPS_PARENT_ENABLE,
782 .ops = &clk_rcg2_ops,
786 static struct clk_rcg2 gcc_camss_mclk2_clk_src = {
790 .parent_map = gcc_parent_map_3,
791 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
792 .clkr.hw.init = &(struct clk_init_data){
793 .name = "gcc_camss_mclk2_clk_src",
794 .parent_data = gcc_parents_3,
795 .num_parents = ARRAY_SIZE(gcc_parents_3),
796 .flags = CLK_OPS_PARENT_ENABLE,
797 .ops = &clk_rcg2_ops,
801 static struct clk_rcg2 gcc_camss_mclk3_clk_src = {
805 .parent_map = gcc_parent_map_3,
806 .freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
807 .clkr.hw.init = &(struct clk_init_data){
808 .name = "gcc_camss_mclk3_clk_src",
809 .parent_data = gcc_parents_3,
810 .num_parents = ARRAY_SIZE(gcc_parents_3),
811 .flags = CLK_OPS_PARENT_ENABLE,
812 .ops = &clk_rcg2_ops,
816 static const struct freq_tbl ftbl_gcc_camss_ope_ahb_clk_src[] = {
817 F(19200000, P_BI_TCXO, 1, 0, 0),
818 F(171428571, P_GPLL0_OUT_EARLY, 3.5, 0, 0),
819 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
823 static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = {
827 .parent_map = gcc_parent_map_6,
828 .freq_tbl = ftbl_gcc_camss_ope_ahb_clk_src,
829 .clkr.hw.init = &(struct clk_init_data){
830 .name = "gcc_camss_ope_ahb_clk_src",
831 .parent_data = gcc_parents_6,
832 .num_parents = ARRAY_SIZE(gcc_parents_6),
833 .ops = &clk_rcg2_ops,
837 static const struct freq_tbl ftbl_gcc_camss_ope_clk_src[] = {
838 F(19200000, P_BI_TCXO, 1, 0, 0),
839 F(200000000, P_GPLL8_OUT_MAIN, 2, 0, 0),
840 F(266600000, P_GPLL8_OUT_MAIN, 1, 0, 0),
841 F(465000000, P_GPLL8_OUT_MAIN, 1, 0, 0),
842 F(580000000, P_GPLL8_OUT_EARLY, 1, 0, 0),
846 static struct clk_rcg2 gcc_camss_ope_clk_src = {
850 .parent_map = gcc_parent_map_6,
851 .freq_tbl = ftbl_gcc_camss_ope_clk_src,
852 .clkr.hw.init = &(struct clk_init_data){
853 .name = "gcc_camss_ope_clk_src",
854 .parent_data = gcc_parents_6,
855 .num_parents = ARRAY_SIZE(gcc_parents_6),
856 .flags = CLK_SET_RATE_PARENT,
857 .ops = &clk_rcg2_ops,
861 static const struct freq_tbl ftbl_gcc_camss_tfe_0_clk_src[] = {
862 F(19200000, P_BI_TCXO, 1, 0, 0),
863 F(128000000, P_GPLL10_OUT_MAIN, 9, 0, 0),
864 F(135529412, P_GPLL10_OUT_MAIN, 8.5, 0, 0),
865 F(144000000, P_GPLL10_OUT_MAIN, 8, 0, 0),
866 F(153600000, P_GPLL10_OUT_MAIN, 7.5, 0, 0),
867 F(164571429, P_GPLL10_OUT_MAIN, 7, 0, 0),
868 F(177230769, P_GPLL10_OUT_MAIN, 6.5, 0, 0),
869 F(192000000, P_GPLL10_OUT_MAIN, 6, 0, 0),
870 F(209454545, P_GPLL10_OUT_MAIN, 5.5, 0, 0),
871 F(230400000, P_GPLL10_OUT_MAIN, 5, 0, 0),
872 F(256000000, P_GPLL10_OUT_MAIN, 4.5, 0, 0),
873 F(288000000, P_GPLL10_OUT_MAIN, 4, 0, 0),
874 F(329142857, P_GPLL10_OUT_MAIN, 3.5, 0, 0),
875 F(384000000, P_GPLL10_OUT_MAIN, 3, 0, 0),
876 F(460800000, P_GPLL10_OUT_MAIN, 2.5, 0, 0),
877 F(576000000, P_GPLL10_OUT_MAIN, 2, 0, 0),
881 static struct clk_rcg2 gcc_camss_tfe_0_clk_src = {
885 .parent_map = gcc_parent_map_7,
886 .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src,
887 .clkr.hw.init = &(struct clk_init_data){
888 .name = "gcc_camss_tfe_0_clk_src",
889 .parent_data = gcc_parents_7,
890 .num_parents = ARRAY_SIZE(gcc_parents_7),
891 .ops = &clk_rcg2_ops,
895 static const struct freq_tbl ftbl_gcc_camss_tfe_0_csid_clk_src[] = {
896 F(19200000, P_BI_TCXO, 1, 0, 0),
897 F(120000000, P_GPLL0_OUT_EARLY, 5, 0, 0),
898 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
899 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
900 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
901 F(426400000, P_GPLL3_OUT_EARLY, 2.5, 0, 0),
905 static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = {
909 .parent_map = gcc_parent_map_8,
910 .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src,
911 .clkr.hw.init = &(struct clk_init_data){
912 .name = "gcc_camss_tfe_0_csid_clk_src",
913 .parent_data = gcc_parents_8,
914 .num_parents = ARRAY_SIZE(gcc_parents_8),
915 .ops = &clk_rcg2_ops,
919 static struct clk_rcg2 gcc_camss_tfe_1_clk_src = {
923 .parent_map = gcc_parent_map_7,
924 .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src,
925 .clkr.hw.init = &(struct clk_init_data){
926 .name = "gcc_camss_tfe_1_clk_src",
927 .parent_data = gcc_parents_7,
928 .num_parents = ARRAY_SIZE(gcc_parents_7),
929 .ops = &clk_rcg2_ops,
933 static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = {
937 .parent_map = gcc_parent_map_8,
938 .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src,
939 .clkr.hw.init = &(struct clk_init_data){
940 .name = "gcc_camss_tfe_1_csid_clk_src",
941 .parent_data = gcc_parents_8,
942 .num_parents = ARRAY_SIZE(gcc_parents_8),
943 .ops = &clk_rcg2_ops,
947 static const struct freq_tbl ftbl_gcc_camss_tfe_cphy_rx_clk_src[] = {
948 F(19200000, P_BI_TCXO, 1, 0, 0),
949 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
950 F(341333333, P_GPLL6_OUT_EARLY, 1, 4, 9),
951 F(384000000, P_GPLL6_OUT_EARLY, 2, 0, 0),
955 static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = {
959 .parent_map = gcc_parent_map_10,
960 .freq_tbl = ftbl_gcc_camss_tfe_cphy_rx_clk_src,
961 .clkr.hw.init = &(struct clk_init_data){
962 .name = "gcc_camss_tfe_cphy_rx_clk_src",
963 .parent_data = gcc_parents_10,
964 .num_parents = ARRAY_SIZE(gcc_parents_10),
965 .flags = CLK_OPS_PARENT_ENABLE,
966 .ops = &clk_rcg2_ops,
970 static const struct freq_tbl ftbl_gcc_camss_top_ahb_clk_src[] = {
971 F(19200000, P_BI_TCXO, 1, 0, 0),
972 F(40000000, P_GPLL0_OUT_AUX2, 7.5, 0, 0),
973 F(80000000, P_GPLL0_OUT_EARLY, 7.5, 0, 0),
977 static struct clk_rcg2 gcc_camss_top_ahb_clk_src = {
981 .parent_map = gcc_parent_map_4,
982 .freq_tbl = ftbl_gcc_camss_top_ahb_clk_src,
983 .clkr.hw.init = &(struct clk_init_data){
984 .name = "gcc_camss_top_ahb_clk_src",
985 .parent_data = gcc_parents_4,
986 .num_parents = ARRAY_SIZE(gcc_parents_4),
987 .ops = &clk_rcg2_ops,
991 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
992 F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
993 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
994 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
995 F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0),
999 static struct clk_rcg2 gcc_gp1_clk_src = {
1000 .cmd_rcgr = 0x4d004,
1003 .parent_map = gcc_parent_map_2,
1004 .freq_tbl = ftbl_gcc_gp1_clk_src,
1005 .clkr.hw.init = &(struct clk_init_data){
1006 .name = "gcc_gp1_clk_src",
1007 .parent_data = gcc_parents_2,
1008 .num_parents = ARRAY_SIZE(gcc_parents_2),
1009 .ops = &clk_rcg2_ops,
1013 static struct clk_rcg2 gcc_gp2_clk_src = {
1014 .cmd_rcgr = 0x4e004,
1017 .parent_map = gcc_parent_map_2,
1018 .freq_tbl = ftbl_gcc_gp1_clk_src,
1019 .clkr.hw.init = &(struct clk_init_data){
1020 .name = "gcc_gp2_clk_src",
1021 .parent_data = gcc_parents_2,
1022 .num_parents = ARRAY_SIZE(gcc_parents_2),
1023 .ops = &clk_rcg2_ops,
1027 static struct clk_rcg2 gcc_gp3_clk_src = {
1028 .cmd_rcgr = 0x4f004,
1031 .parent_map = gcc_parent_map_2,
1032 .freq_tbl = ftbl_gcc_gp1_clk_src,
1033 .clkr.hw.init = &(struct clk_init_data){
1034 .name = "gcc_gp3_clk_src",
1035 .parent_data = gcc_parents_2,
1036 .num_parents = ARRAY_SIZE(gcc_parents_2),
1037 .ops = &clk_rcg2_ops,
1041 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
1042 F(19200000, P_BI_TCXO, 1, 0, 0),
1043 F(60000000, P_GPLL0_OUT_AUX2, 5, 0, 0),
1047 static struct clk_rcg2 gcc_pdm2_clk_src = {
1048 .cmd_rcgr = 0x20010,
1051 .parent_map = gcc_parent_map_0,
1052 .freq_tbl = ftbl_gcc_pdm2_clk_src,
1053 .clkr.hw.init = &(struct clk_init_data){
1054 .name = "gcc_pdm2_clk_src",
1055 .parent_data = gcc_parents_0,
1056 .num_parents = ARRAY_SIZE(gcc_parents_0),
1057 .ops = &clk_rcg2_ops,
1061 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
1062 F(7372800, P_GPLL0_OUT_AUX2, 1, 384, 15625),
1063 F(14745600, P_GPLL0_OUT_AUX2, 1, 768, 15625),
1064 F(19200000, P_BI_TCXO, 1, 0, 0),
1065 F(29491200, P_GPLL0_OUT_AUX2, 1, 1536, 15625),
1066 F(32000000, P_GPLL0_OUT_AUX2, 1, 8, 75),
1067 F(48000000, P_GPLL0_OUT_AUX2, 1, 4, 25),
1068 F(64000000, P_GPLL0_OUT_AUX2, 1, 16, 75),
1069 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1070 F(80000000, P_GPLL0_OUT_AUX2, 1, 4, 15),
1071 F(96000000, P_GPLL0_OUT_AUX2, 1, 8, 25),
1072 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1073 F(102400000, P_GPLL0_OUT_AUX2, 1, 128, 375),
1074 F(112000000, P_GPLL0_OUT_AUX2, 1, 28, 75),
1075 F(117964800, P_GPLL0_OUT_AUX2, 1, 6144, 15625),
1076 F(120000000, P_GPLL0_OUT_AUX2, 2.5, 0, 0),
1077 F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
1081 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
1082 .name = "gcc_qupv3_wrap0_s0_clk_src",
1083 .parent_data = gcc_parents_1,
1084 .num_parents = ARRAY_SIZE(gcc_parents_1),
1085 .ops = &clk_rcg2_ops,
1088 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
1089 .cmd_rcgr = 0x1f148,
1092 .parent_map = gcc_parent_map_1,
1093 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1094 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
1097 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
1098 .name = "gcc_qupv3_wrap0_s1_clk_src",
1099 .parent_data = gcc_parents_1,
1100 .num_parents = ARRAY_SIZE(gcc_parents_1),
1101 .ops = &clk_rcg2_ops,
1104 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
1105 .cmd_rcgr = 0x1f278,
1108 .parent_map = gcc_parent_map_1,
1109 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1110 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
1113 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
1114 .name = "gcc_qupv3_wrap0_s2_clk_src",
1115 .parent_data = gcc_parents_1,
1116 .num_parents = ARRAY_SIZE(gcc_parents_1),
1117 .ops = &clk_rcg2_ops,
1120 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
1121 .cmd_rcgr = 0x1f3a8,
1124 .parent_map = gcc_parent_map_1,
1125 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1126 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
1129 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
1130 .name = "gcc_qupv3_wrap0_s3_clk_src",
1131 .parent_data = gcc_parents_1,
1132 .num_parents = ARRAY_SIZE(gcc_parents_1),
1133 .ops = &clk_rcg2_ops,
1136 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
1137 .cmd_rcgr = 0x1f4d8,
1140 .parent_map = gcc_parent_map_1,
1141 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1142 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
1145 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
1146 .name = "gcc_qupv3_wrap0_s4_clk_src",
1147 .parent_data = gcc_parents_1,
1148 .num_parents = ARRAY_SIZE(gcc_parents_1),
1149 .ops = &clk_rcg2_ops,
1152 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
1153 .cmd_rcgr = 0x1f608,
1156 .parent_map = gcc_parent_map_1,
1157 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1158 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
1161 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
1162 .name = "gcc_qupv3_wrap0_s5_clk_src",
1163 .parent_data = gcc_parents_1,
1164 .num_parents = ARRAY_SIZE(gcc_parents_1),
1165 .ops = &clk_rcg2_ops,
1168 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
1169 .cmd_rcgr = 0x1f738,
1172 .parent_map = gcc_parent_map_1,
1173 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1174 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
1177 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
1178 F(144000, P_BI_TCXO, 16, 3, 25),
1179 F(400000, P_BI_TCXO, 12, 1, 4),
1180 F(20000000, P_GPLL0_OUT_AUX2, 5, 1, 3),
1181 F(25000000, P_GPLL0_OUT_AUX2, 6, 1, 2),
1182 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1183 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1184 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
1185 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
1189 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
1190 .cmd_rcgr = 0x38028,
1193 .parent_map = gcc_parent_map_1,
1194 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
1195 .clkr.hw.init = &(struct clk_init_data){
1196 .name = "gcc_sdcc1_apps_clk_src",
1197 .parent_data = gcc_parents_1,
1198 .num_parents = ARRAY_SIZE(gcc_parents_1),
1199 .ops = &clk_rcg2_floor_ops,
1203 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
1204 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1205 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1206 F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),
1207 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1208 F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0),
1212 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
1213 .cmd_rcgr = 0x38010,
1216 .parent_map = gcc_parent_map_0,
1217 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
1218 .clkr.hw.init = &(struct clk_init_data){
1219 .name = "gcc_sdcc1_ice_core_clk_src",
1220 .parent_data = gcc_parents_0,
1221 .num_parents = ARRAY_SIZE(gcc_parents_0),
1222 .ops = &clk_rcg2_ops,
1226 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
1227 F(400000, P_BI_TCXO, 12, 1, 4),
1228 F(19200000, P_BI_TCXO, 1, 0, 0),
1229 F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
1230 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1231 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1232 F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
1236 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
1237 .cmd_rcgr = 0x1e00c,
1240 .parent_map = gcc_parent_map_12,
1241 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
1242 .clkr.hw.init = &(struct clk_init_data){
1243 .name = "gcc_sdcc2_apps_clk_src",
1244 .parent_data = gcc_parents_12,
1245 .num_parents = ARRAY_SIZE(gcc_parents_12),
1246 .ops = &clk_rcg2_ops,
1250 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1251 F(66666667, P_GPLL0_OUT_AUX2, 4.5, 0, 0),
1252 F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0),
1253 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1254 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
1258 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1259 .cmd_rcgr = 0x1a01c,
1262 .parent_map = gcc_parent_map_0,
1263 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1264 .clkr.hw.init = &(struct clk_init_data){
1265 .name = "gcc_usb30_prim_master_clk_src",
1266 .parent_data = gcc_parents_0,
1267 .num_parents = ARRAY_SIZE(gcc_parents_0),
1268 .ops = &clk_rcg2_ops,
1272 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1273 .cmd_rcgr = 0x1a060,
1276 .parent_map = gcc_parent_map_13,
1277 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1278 .clkr.hw.init = &(struct clk_init_data){
1279 .name = "gcc_usb3_prim_phy_aux_clk_src",
1280 .parent_data = gcc_parents_13,
1281 .num_parents = ARRAY_SIZE(gcc_parents_13),
1282 .ops = &clk_rcg2_ops,
1286 static const struct freq_tbl ftbl_gcc_video_venus_clk_src[] = {
1287 F(133333333, P_GPLL11_OUT_MAIN, 4.5, 0, 0),
1288 F(240000000, P_GPLL11_OUT_MAIN, 2.5, 0, 0),
1289 F(300000000, P_GPLL11_OUT_MAIN, 2, 0, 0),
1290 F(384000000, P_GPLL11_OUT_MAIN, 2, 0, 0),
1294 static struct clk_rcg2 gcc_video_venus_clk_src = {
1295 .cmd_rcgr = 0x58060,
1298 .parent_map = gcc_parent_map_14,
1299 .freq_tbl = ftbl_gcc_video_venus_clk_src,
1300 .clkr.hw.init = &(struct clk_init_data){
1301 .name = "gcc_video_venus_clk_src",
1302 .parent_data = gcc_parents_14,
1303 .num_parents = ARRAY_SIZE(gcc_parents_14),
1304 .flags = CLK_SET_RATE_PARENT,
1305 .ops = &clk_rcg2_ops,
1309 static struct clk_branch gcc_ahb2phy_csi_clk = {
1310 .halt_reg = 0x1d004,
1311 .halt_check = BRANCH_HALT_DELAY,
1312 .hwcg_reg = 0x1d004,
1315 .enable_reg = 0x1d004,
1316 .enable_mask = BIT(0),
1317 .hw.init = &(struct clk_init_data){
1318 .name = "gcc_ahb2phy_csi_clk",
1319 .ops = &clk_branch2_ops,
1324 static struct clk_branch gcc_ahb2phy_usb_clk = {
1325 .halt_reg = 0x1d008,
1326 .halt_check = BRANCH_HALT,
1327 .hwcg_reg = 0x1d008,
1330 .enable_reg = 0x1d008,
1331 .enable_mask = BIT(0),
1332 .hw.init = &(struct clk_init_data){
1333 .name = "gcc_ahb2phy_usb_clk",
1334 .ops = &clk_branch2_ops,
1339 static struct clk_branch gcc_bimc_gpu_axi_clk = {
1340 .halt_reg = 0x71154,
1341 .halt_check = BRANCH_HALT_DELAY,
1342 .hwcg_reg = 0x71154,
1345 .enable_reg = 0x71154,
1346 .enable_mask = BIT(0),
1347 .hw.init = &(struct clk_init_data){
1348 .name = "gcc_bimc_gpu_axi_clk",
1349 .ops = &clk_branch2_ops,
1354 static struct clk_branch gcc_boot_rom_ahb_clk = {
1355 .halt_reg = 0x23004,
1356 .halt_check = BRANCH_HALT_VOTED,
1357 .hwcg_reg = 0x23004,
1360 .enable_reg = 0x79004,
1361 .enable_mask = BIT(10),
1362 .hw.init = &(struct clk_init_data){
1363 .name = "gcc_boot_rom_ahb_clk",
1364 .ops = &clk_branch2_ops,
1369 static struct clk_branch gcc_cam_throttle_nrt_clk = {
1370 .halt_reg = 0x17070,
1371 .halt_check = BRANCH_HALT_VOTED,
1372 .hwcg_reg = 0x17070,
1375 .enable_reg = 0x79004,
1376 .enable_mask = BIT(27),
1377 .hw.init = &(struct clk_init_data){
1378 .name = "gcc_cam_throttle_nrt_clk",
1379 .ops = &clk_branch2_ops,
1384 static struct clk_branch gcc_cam_throttle_rt_clk = {
1385 .halt_reg = 0x1706c,
1386 .halt_check = BRANCH_HALT_VOTED,
1387 .hwcg_reg = 0x1706c,
1390 .enable_reg = 0x79004,
1391 .enable_mask = BIT(26),
1392 .hw.init = &(struct clk_init_data){
1393 .name = "gcc_cam_throttle_rt_clk",
1394 .ops = &clk_branch2_ops,
1399 static struct clk_branch gcc_camera_ahb_clk = {
1400 .halt_reg = 0x17008,
1401 .halt_check = BRANCH_HALT_DELAY,
1402 .hwcg_reg = 0x17008,
1405 .enable_reg = 0x17008,
1406 .enable_mask = BIT(0),
1407 .hw.init = &(struct clk_init_data){
1408 .name = "gcc_camera_ahb_clk",
1409 .flags = CLK_IS_CRITICAL,
1410 .ops = &clk_branch2_ops,
1415 static struct clk_branch gcc_camera_xo_clk = {
1416 .halt_reg = 0x17028,
1417 .halt_check = BRANCH_HALT,
1419 .enable_reg = 0x17028,
1420 .enable_mask = BIT(0),
1421 .hw.init = &(struct clk_init_data){
1422 .name = "gcc_camera_xo_clk",
1423 .flags = CLK_IS_CRITICAL,
1424 .ops = &clk_branch2_ops,
1429 static struct clk_branch gcc_camss_axi_clk = {
1430 .halt_reg = 0x58044,
1431 .halt_check = BRANCH_HALT,
1433 .enable_reg = 0x58044,
1434 .enable_mask = BIT(0),
1435 .hw.init = &(struct clk_init_data){
1436 .name = "gcc_camss_axi_clk",
1437 .parent_hws = (const struct clk_hw *[])
1438 { &gcc_camss_axi_clk_src.clkr.hw },
1440 .flags = CLK_SET_RATE_PARENT,
1441 .ops = &clk_branch2_ops,
1446 static struct clk_branch gcc_camss_camnoc_atb_clk = {
1447 .halt_reg = 0x5804c,
1448 .halt_check = BRANCH_HALT_DELAY,
1449 .hwcg_reg = 0x5804c,
1452 .enable_reg = 0x5804c,
1453 .enable_mask = BIT(0),
1454 .hw.init = &(struct clk_init_data){
1455 .name = "gcc_camss_camnoc_atb_clk",
1456 .ops = &clk_branch2_ops,
1461 static struct clk_branch gcc_camss_camnoc_nts_xo_clk = {
1462 .halt_reg = 0x58050,
1463 .halt_check = BRANCH_HALT_DELAY,
1464 .hwcg_reg = 0x58050,
1467 .enable_reg = 0x58050,
1468 .enable_mask = BIT(0),
1469 .hw.init = &(struct clk_init_data){
1470 .name = "gcc_camss_camnoc_nts_xo_clk",
1471 .ops = &clk_branch2_ops,
1476 static struct clk_branch gcc_camss_cci_0_clk = {
1477 .halt_reg = 0x56018,
1478 .halt_check = BRANCH_HALT,
1480 .enable_reg = 0x56018,
1481 .enable_mask = BIT(0),
1482 .hw.init = &(struct clk_init_data){
1483 .name = "gcc_camss_cci_0_clk",
1484 .parent_hws = (const struct clk_hw *[])
1485 { &gcc_camss_cci_clk_src.clkr.hw },
1487 .flags = CLK_SET_RATE_PARENT,
1488 .ops = &clk_branch2_ops,
1493 static struct clk_branch gcc_camss_cphy_0_clk = {
1494 .halt_reg = 0x52088,
1495 .halt_check = BRANCH_HALT,
1497 .enable_reg = 0x52088,
1498 .enable_mask = BIT(0),
1499 .hw.init = &(struct clk_init_data){
1500 .name = "gcc_camss_cphy_0_clk",
1501 .parent_hws = (const struct clk_hw *[])
1502 { &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw },
1504 .flags = CLK_SET_RATE_PARENT,
1505 .ops = &clk_branch2_ops,
1510 static struct clk_branch gcc_camss_cphy_1_clk = {
1511 .halt_reg = 0x5208c,
1512 .halt_check = BRANCH_HALT,
1514 .enable_reg = 0x5208c,
1515 .enable_mask = BIT(0),
1516 .hw.init = &(struct clk_init_data){
1517 .name = "gcc_camss_cphy_1_clk",
1518 .parent_hws = (const struct clk_hw *[])
1519 { &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw },
1521 .flags = CLK_SET_RATE_PARENT,
1522 .ops = &clk_branch2_ops,
1527 static struct clk_branch gcc_camss_csi0phytimer_clk = {
1528 .halt_reg = 0x45018,
1529 .halt_check = BRANCH_HALT,
1531 .enable_reg = 0x45018,
1532 .enable_mask = BIT(0),
1533 .hw.init = &(struct clk_init_data){
1534 .name = "gcc_camss_csi0phytimer_clk",
1535 .parent_hws = (const struct clk_hw *[])
1536 { &gcc_camss_csi0phytimer_clk_src.clkr.hw },
1538 .flags = CLK_SET_RATE_PARENT,
1539 .ops = &clk_branch2_ops,
1544 static struct clk_branch gcc_camss_csi1phytimer_clk = {
1545 .halt_reg = 0x45034,
1546 .halt_check = BRANCH_HALT,
1548 .enable_reg = 0x45034,
1549 .enable_mask = BIT(0),
1550 .hw.init = &(struct clk_init_data){
1551 .name = "gcc_camss_csi1phytimer_clk",
1552 .parent_hws = (const struct clk_hw *[])
1553 { &gcc_camss_csi1phytimer_clk_src.clkr.hw },
1555 .flags = CLK_SET_RATE_PARENT,
1556 .ops = &clk_branch2_ops,
1561 static struct clk_branch gcc_camss_mclk0_clk = {
1562 .halt_reg = 0x51018,
1563 .halt_check = BRANCH_HALT,
1565 .enable_reg = 0x51018,
1566 .enable_mask = BIT(0),
1567 .hw.init = &(struct clk_init_data){
1568 .name = "gcc_camss_mclk0_clk",
1569 .parent_hws = (const struct clk_hw *[])
1570 { &gcc_camss_mclk0_clk_src.clkr.hw },
1572 .flags = CLK_SET_RATE_PARENT,
1573 .ops = &clk_branch2_ops,
1578 static struct clk_branch gcc_camss_mclk1_clk = {
1579 .halt_reg = 0x51034,
1580 .halt_check = BRANCH_HALT,
1582 .enable_reg = 0x51034,
1583 .enable_mask = BIT(0),
1584 .hw.init = &(struct clk_init_data){
1585 .name = "gcc_camss_mclk1_clk",
1586 .parent_hws = (const struct clk_hw *[])
1587 { &gcc_camss_mclk1_clk_src.clkr.hw },
1589 .flags = CLK_SET_RATE_PARENT,
1590 .ops = &clk_branch2_ops,
1595 static struct clk_branch gcc_camss_mclk2_clk = {
1596 .halt_reg = 0x51050,
1597 .halt_check = BRANCH_HALT,
1599 .enable_reg = 0x51050,
1600 .enable_mask = BIT(0),
1601 .hw.init = &(struct clk_init_data){
1602 .name = "gcc_camss_mclk2_clk",
1603 .parent_hws = (const struct clk_hw *[])
1604 { &gcc_camss_mclk2_clk_src.clkr.hw },
1606 .flags = CLK_SET_RATE_PARENT,
1607 .ops = &clk_branch2_ops,
1612 static struct clk_branch gcc_camss_mclk3_clk = {
1613 .halt_reg = 0x5106c,
1614 .halt_check = BRANCH_HALT,
1616 .enable_reg = 0x5106c,
1617 .enable_mask = BIT(0),
1618 .hw.init = &(struct clk_init_data){
1619 .name = "gcc_camss_mclk3_clk",
1620 .parent_hws = (const struct clk_hw *[])
1621 { &gcc_camss_mclk3_clk_src.clkr.hw },
1623 .flags = CLK_SET_RATE_PARENT,
1624 .ops = &clk_branch2_ops,
1629 static struct clk_branch gcc_camss_nrt_axi_clk = {
1630 .halt_reg = 0x58054,
1631 .halt_check = BRANCH_HALT,
1633 .enable_reg = 0x58054,
1634 .enable_mask = BIT(0),
1635 .hw.init = &(struct clk_init_data){
1636 .name = "gcc_camss_nrt_axi_clk",
1637 .ops = &clk_branch2_ops,
1642 static struct clk_branch gcc_camss_ope_ahb_clk = {
1643 .halt_reg = 0x5503c,
1644 .halt_check = BRANCH_HALT,
1646 .enable_reg = 0x5503c,
1647 .enable_mask = BIT(0),
1648 .hw.init = &(struct clk_init_data){
1649 .name = "gcc_camss_ope_ahb_clk",
1650 .parent_hws = (const struct clk_hw *[])
1651 { &gcc_camss_ope_ahb_clk_src.clkr.hw },
1653 .flags = CLK_SET_RATE_PARENT,
1654 .ops = &clk_branch2_ops,
1659 static struct clk_branch gcc_camss_ope_clk = {
1660 .halt_reg = 0x5501c,
1661 .halt_check = BRANCH_HALT,
1663 .enable_reg = 0x5501c,
1664 .enable_mask = BIT(0),
1665 .hw.init = &(struct clk_init_data){
1666 .name = "gcc_camss_ope_clk",
1667 .parent_hws = (const struct clk_hw *[])
1668 { &gcc_camss_ope_clk_src.clkr.hw },
1670 .flags = CLK_SET_RATE_PARENT,
1671 .ops = &clk_branch2_ops,
1676 static struct clk_branch gcc_camss_rt_axi_clk = {
1677 .halt_reg = 0x5805c,
1678 .halt_check = BRANCH_HALT,
1680 .enable_reg = 0x5805c,
1681 .enable_mask = BIT(0),
1682 .hw.init = &(struct clk_init_data){
1683 .name = "gcc_camss_rt_axi_clk",
1684 .ops = &clk_branch2_ops,
1689 static struct clk_branch gcc_camss_tfe_0_clk = {
1690 .halt_reg = 0x5201c,
1691 .halt_check = BRANCH_HALT,
1693 .enable_reg = 0x5201c,
1694 .enable_mask = BIT(0),
1695 .hw.init = &(struct clk_init_data){
1696 .name = "gcc_camss_tfe_0_clk",
1697 .parent_hws = (const struct clk_hw *[])
1698 { &gcc_camss_tfe_0_clk_src.clkr.hw },
1700 .flags = CLK_SET_RATE_PARENT,
1701 .ops = &clk_branch2_ops,
1706 static struct clk_branch gcc_camss_tfe_0_cphy_rx_clk = {
1707 .halt_reg = 0x5207c,
1708 .halt_check = BRANCH_HALT,
1710 .enable_reg = 0x5207c,
1711 .enable_mask = BIT(0),
1712 .hw.init = &(struct clk_init_data){
1713 .name = "gcc_camss_tfe_0_cphy_rx_clk",
1714 .parent_hws = (const struct clk_hw *[])
1715 { &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw },
1717 .flags = CLK_SET_RATE_PARENT,
1718 .ops = &clk_branch2_ops,
1723 static struct clk_branch gcc_camss_tfe_0_csid_clk = {
1724 .halt_reg = 0x520ac,
1725 .halt_check = BRANCH_HALT,
1727 .enable_reg = 0x520ac,
1728 .enable_mask = BIT(0),
1729 .hw.init = &(struct clk_init_data){
1730 .name = "gcc_camss_tfe_0_csid_clk",
1731 .parent_hws = (const struct clk_hw *[])
1732 { &gcc_camss_tfe_0_csid_clk_src.clkr.hw },
1734 .flags = CLK_SET_RATE_PARENT,
1735 .ops = &clk_branch2_ops,
1740 static struct clk_branch gcc_camss_tfe_1_clk = {
1741 .halt_reg = 0x5203c,
1742 .halt_check = BRANCH_HALT,
1744 .enable_reg = 0x5203c,
1745 .enable_mask = BIT(0),
1746 .hw.init = &(struct clk_init_data){
1747 .name = "gcc_camss_tfe_1_clk",
1748 .parent_hws = (const struct clk_hw *[])
1749 { &gcc_camss_tfe_1_clk_src.clkr.hw },
1751 .flags = CLK_SET_RATE_PARENT,
1752 .ops = &clk_branch2_ops,
1757 static struct clk_branch gcc_camss_tfe_1_cphy_rx_clk = {
1758 .halt_reg = 0x52080,
1759 .halt_check = BRANCH_HALT,
1761 .enable_reg = 0x52080,
1762 .enable_mask = BIT(0),
1763 .hw.init = &(struct clk_init_data){
1764 .name = "gcc_camss_tfe_1_cphy_rx_clk",
1765 .parent_hws = (const struct clk_hw *[])
1766 { &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw },
1768 .flags = CLK_SET_RATE_PARENT,
1769 .ops = &clk_branch2_ops,
1774 static struct clk_branch gcc_camss_tfe_1_csid_clk = {
1775 .halt_reg = 0x520cc,
1776 .halt_check = BRANCH_HALT,
1778 .enable_reg = 0x520cc,
1779 .enable_mask = BIT(0),
1780 .hw.init = &(struct clk_init_data){
1781 .name = "gcc_camss_tfe_1_csid_clk",
1782 .parent_hws = (const struct clk_hw *[])
1783 { &gcc_camss_tfe_1_csid_clk_src.clkr.hw },
1785 .flags = CLK_SET_RATE_PARENT,
1786 .ops = &clk_branch2_ops,
1791 static struct clk_branch gcc_camss_top_ahb_clk = {
1792 .halt_reg = 0x58028,
1793 .halt_check = BRANCH_HALT,
1795 .enable_reg = 0x58028,
1796 .enable_mask = BIT(0),
1797 .hw.init = &(struct clk_init_data){
1798 .name = "gcc_camss_top_ahb_clk",
1799 .parent_hws = (const struct clk_hw *[])
1800 { &gcc_camss_top_ahb_clk_src.clkr.hw },
1802 .flags = CLK_SET_RATE_PARENT,
1803 .ops = &clk_branch2_ops,
1808 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1809 .halt_reg = 0x1a084,
1810 .halt_check = BRANCH_HALT,
1811 .hwcg_reg = 0x1a084,
1814 .enable_reg = 0x1a084,
1815 .enable_mask = BIT(0),
1816 .hw.init = &(struct clk_init_data){
1817 .name = "gcc_cfg_noc_usb3_prim_axi_clk",
1818 .parent_hws = (const struct clk_hw *[])
1819 { &gcc_usb30_prim_master_clk_src.clkr.hw },
1821 .flags = CLK_SET_RATE_PARENT,
1822 .ops = &clk_branch2_ops,
1827 static struct clk_branch gcc_disp_ahb_clk = {
1828 .halt_reg = 0x1700c,
1829 .halt_check = BRANCH_HALT,
1830 .hwcg_reg = 0x1700c,
1833 .enable_reg = 0x1700c,
1834 .enable_mask = BIT(0),
1835 .hw.init = &(struct clk_init_data){
1836 .name = "gcc_disp_ahb_clk",
1837 .flags = CLK_IS_CRITICAL,
1838 .ops = &clk_branch2_ops,
1843 static struct clk_regmap_div gcc_disp_gpll0_clk_src = {
1847 .clkr.hw.init = &(struct clk_init_data) {
1848 .name = "gcc_disp_gpll0_clk_src",
1849 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
1851 .ops = &clk_regmap_div_ops,
1855 static struct clk_branch gcc_disp_gpll0_div_clk_src = {
1856 .halt_check = BRANCH_HALT_DELAY,
1858 .enable_reg = 0x79004,
1859 .enable_mask = BIT(20),
1860 .hw.init = &(struct clk_init_data){
1861 .name = "gcc_disp_gpll0_div_clk_src",
1862 .parent_hws = (const struct clk_hw *[])
1863 { &gcc_disp_gpll0_clk_src.clkr.hw },
1865 .flags = CLK_SET_RATE_PARENT,
1866 .ops = &clk_branch2_ops,
1871 static struct clk_branch gcc_disp_hf_axi_clk = {
1872 .halt_reg = 0x17020,
1873 .halt_check = BRANCH_HALT,
1874 .hwcg_reg = 0x17020,
1877 .enable_reg = 0x17020,
1878 .enable_mask = BIT(0),
1879 .hw.init = &(struct clk_init_data){
1880 .name = "gcc_disp_hf_axi_clk",
1881 .ops = &clk_branch2_ops,
1886 static struct clk_branch gcc_disp_throttle_core_clk = {
1887 .halt_reg = 0x17064,
1888 .halt_check = BRANCH_HALT_VOTED,
1889 .hwcg_reg = 0x17064,
1892 .enable_reg = 0x7900c,
1893 .enable_mask = BIT(5),
1894 .hw.init = &(struct clk_init_data){
1895 .name = "gcc_disp_throttle_core_clk",
1896 .ops = &clk_branch2_ops,
1901 static struct clk_branch gcc_disp_xo_clk = {
1902 .halt_reg = 0x1702c,
1903 .halt_check = BRANCH_HALT,
1905 .enable_reg = 0x1702c,
1906 .enable_mask = BIT(0),
1907 .hw.init = &(struct clk_init_data){
1908 .name = "gcc_disp_xo_clk",
1909 .flags = CLK_IS_CRITICAL,
1910 .ops = &clk_branch2_ops,
1915 static struct clk_branch gcc_gp1_clk = {
1916 .halt_reg = 0x4d000,
1917 .halt_check = BRANCH_HALT,
1919 .enable_reg = 0x4d000,
1920 .enable_mask = BIT(0),
1921 .hw.init = &(struct clk_init_data){
1922 .name = "gcc_gp1_clk",
1923 .parent_hws = (const struct clk_hw *[])
1924 { &gcc_gp1_clk_src.clkr.hw },
1926 .flags = CLK_SET_RATE_PARENT,
1927 .ops = &clk_branch2_ops,
1932 static struct clk_branch gcc_gp2_clk = {
1933 .halt_reg = 0x4e000,
1934 .halt_check = BRANCH_HALT,
1936 .enable_reg = 0x4e000,
1937 .enable_mask = BIT(0),
1938 .hw.init = &(struct clk_init_data){
1939 .name = "gcc_gp2_clk",
1940 .parent_hws = (const struct clk_hw *[])
1941 { &gcc_gp2_clk_src.clkr.hw },
1943 .flags = CLK_SET_RATE_PARENT,
1944 .ops = &clk_branch2_ops,
1949 static struct clk_branch gcc_gp3_clk = {
1950 .halt_reg = 0x4f000,
1951 .halt_check = BRANCH_HALT,
1953 .enable_reg = 0x4f000,
1954 .enable_mask = BIT(0),
1955 .hw.init = &(struct clk_init_data){
1956 .name = "gcc_gp3_clk",
1957 .parent_hws = (const struct clk_hw *[])
1958 { &gcc_gp3_clk_src.clkr.hw },
1960 .flags = CLK_SET_RATE_PARENT,
1961 .ops = &clk_branch2_ops,
1966 static struct clk_branch gcc_gpu_cfg_ahb_clk = {
1967 .halt_reg = 0x36004,
1968 .halt_check = BRANCH_HALT,
1969 .hwcg_reg = 0x36004,
1972 .enable_reg = 0x36004,
1973 .enable_mask = BIT(0),
1974 .hw.init = &(struct clk_init_data){
1975 .name = "gcc_gpu_cfg_ahb_clk",
1976 .flags = CLK_IS_CRITICAL,
1977 .ops = &clk_branch2_ops,
1982 static struct clk_branch gcc_gpu_gpll0_clk_src = {
1983 .halt_check = BRANCH_HALT_DELAY,
1985 .enable_reg = 0x79004,
1986 .enable_mask = BIT(15),
1987 .hw.init = &(struct clk_init_data){
1988 .name = "gcc_gpu_gpll0_clk_src",
1989 .parent_hws = (const struct clk_hw *[])
1992 .flags = CLK_SET_RATE_PARENT,
1993 .ops = &clk_branch2_ops,
1998 static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1999 .halt_check = BRANCH_HALT_DELAY,
2001 .enable_reg = 0x79004,
2002 .enable_mask = BIT(16),
2003 .hw.init = &(struct clk_init_data){
2004 .name = "gcc_gpu_gpll0_div_clk_src",
2005 .parent_hws = (const struct clk_hw *[])
2006 { &gpll0_out_aux2.clkr.hw },
2008 .flags = CLK_SET_RATE_PARENT,
2009 .ops = &clk_branch2_ops,
2014 static struct clk_branch gcc_gpu_iref_clk = {
2015 .halt_reg = 0x36100,
2016 .halt_check = BRANCH_HALT_DELAY,
2018 .enable_reg = 0x36100,
2019 .enable_mask = BIT(0),
2020 .hw.init = &(struct clk_init_data){
2021 .name = "gcc_gpu_iref_clk",
2022 .ops = &clk_branch2_ops,
2027 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
2028 .halt_reg = 0x3600c,
2029 .halt_check = BRANCH_VOTED,
2030 .hwcg_reg = 0x3600c,
2033 .enable_reg = 0x3600c,
2034 .enable_mask = BIT(0),
2035 .hw.init = &(struct clk_init_data){
2036 .name = "gcc_gpu_memnoc_gfx_clk",
2037 .ops = &clk_branch2_ops,
2042 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
2043 .halt_reg = 0x36018,
2044 .halt_check = BRANCH_HALT,
2046 .enable_reg = 0x36018,
2047 .enable_mask = BIT(0),
2048 .hw.init = &(struct clk_init_data){
2049 .name = "gcc_gpu_snoc_dvm_gfx_clk",
2050 .ops = &clk_branch2_ops,
2055 static struct clk_branch gcc_gpu_throttle_core_clk = {
2056 .halt_reg = 0x36048,
2057 .halt_check = BRANCH_HALT_VOTED,
2058 .hwcg_reg = 0x36048,
2061 .enable_reg = 0x79004,
2062 .enable_mask = BIT(31),
2063 .hw.init = &(struct clk_init_data){
2064 .name = "gcc_gpu_throttle_core_clk",
2065 .flags = CLK_SET_RATE_PARENT,
2066 .ops = &clk_branch2_ops,
2071 static struct clk_branch gcc_pdm2_clk = {
2072 .halt_reg = 0x2000c,
2073 .halt_check = BRANCH_HALT,
2075 .enable_reg = 0x2000c,
2076 .enable_mask = BIT(0),
2077 .hw.init = &(struct clk_init_data){
2078 .name = "gcc_pdm2_clk",
2079 .parent_hws = (const struct clk_hw *[])
2080 { &gcc_pdm2_clk_src.clkr.hw },
2082 .flags = CLK_SET_RATE_PARENT,
2083 .ops = &clk_branch2_ops,
2088 static struct clk_branch gcc_pdm_ahb_clk = {
2089 .halt_reg = 0x20004,
2090 .halt_check = BRANCH_HALT,
2091 .hwcg_reg = 0x20004,
2094 .enable_reg = 0x20004,
2095 .enable_mask = BIT(0),
2096 .hw.init = &(struct clk_init_data){
2097 .name = "gcc_pdm_ahb_clk",
2098 .ops = &clk_branch2_ops,
2103 static struct clk_branch gcc_pdm_xo4_clk = {
2104 .halt_reg = 0x20008,
2105 .halt_check = BRANCH_HALT,
2107 .enable_reg = 0x20008,
2108 .enable_mask = BIT(0),
2109 .hw.init = &(struct clk_init_data){
2110 .name = "gcc_pdm_xo4_clk",
2111 .ops = &clk_branch2_ops,
2116 static struct clk_branch gcc_pwm0_xo512_clk = {
2117 .halt_reg = 0x2002c,
2118 .halt_check = BRANCH_HALT,
2120 .enable_reg = 0x2002c,
2121 .enable_mask = BIT(0),
2122 .hw.init = &(struct clk_init_data){
2123 .name = "gcc_pwm0_xo512_clk",
2124 .ops = &clk_branch2_ops,
2129 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
2130 .halt_reg = 0x17014,
2131 .halt_check = BRANCH_HALT_VOTED,
2132 .hwcg_reg = 0x17014,
2135 .enable_reg = 0x7900c,
2136 .enable_mask = BIT(0),
2137 .hw.init = &(struct clk_init_data){
2138 .name = "gcc_qmip_camera_nrt_ahb_clk",
2139 .ops = &clk_branch2_ops,
2144 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
2145 .halt_reg = 0x17060,
2146 .halt_check = BRANCH_HALT_VOTED,
2147 .hwcg_reg = 0x17060,
2150 .enable_reg = 0x7900c,
2151 .enable_mask = BIT(2),
2152 .hw.init = &(struct clk_init_data){
2153 .name = "gcc_qmip_camera_rt_ahb_clk",
2154 .ops = &clk_branch2_ops,
2159 static struct clk_branch gcc_qmip_disp_ahb_clk = {
2160 .halt_reg = 0x17018,
2161 .halt_check = BRANCH_HALT_VOTED,
2162 .hwcg_reg = 0x17018,
2165 .enable_reg = 0x7900c,
2166 .enable_mask = BIT(1),
2167 .hw.init = &(struct clk_init_data){
2168 .name = "gcc_qmip_disp_ahb_clk",
2169 .ops = &clk_branch2_ops,
2174 static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = {
2175 .halt_reg = 0x36040,
2176 .halt_check = BRANCH_HALT_VOTED,
2177 .hwcg_reg = 0x36040,
2180 .enable_reg = 0x7900c,
2181 .enable_mask = BIT(4),
2182 .hw.init = &(struct clk_init_data){
2183 .name = "gcc_qmip_gpu_cfg_ahb_clk",
2184 .ops = &clk_branch2_ops,
2189 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
2190 .halt_reg = 0x17010,
2191 .halt_check = BRANCH_HALT_VOTED,
2192 .hwcg_reg = 0x17010,
2195 .enable_reg = 0x79004,
2196 .enable_mask = BIT(25),
2197 .hw.init = &(struct clk_init_data){
2198 .name = "gcc_qmip_video_vcodec_ahb_clk",
2199 .ops = &clk_branch2_ops,
2204 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
2205 .halt_reg = 0x1f014,
2206 .halt_check = BRANCH_HALT_VOTED,
2208 .enable_reg = 0x7900c,
2209 .enable_mask = BIT(9),
2210 .hw.init = &(struct clk_init_data){
2211 .name = "gcc_qupv3_wrap0_core_2x_clk",
2212 .ops = &clk_branch2_ops,
2217 static struct clk_branch gcc_qupv3_wrap0_core_clk = {
2218 .halt_reg = 0x1f00c,
2219 .halt_check = BRANCH_HALT_VOTED,
2221 .enable_reg = 0x7900c,
2222 .enable_mask = BIT(8),
2223 .hw.init = &(struct clk_init_data){
2224 .name = "gcc_qupv3_wrap0_core_clk",
2225 .ops = &clk_branch2_ops,
2230 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2231 .halt_reg = 0x1f144,
2232 .halt_check = BRANCH_HALT_VOTED,
2234 .enable_reg = 0x7900c,
2235 .enable_mask = BIT(10),
2236 .hw.init = &(struct clk_init_data){
2237 .name = "gcc_qupv3_wrap0_s0_clk",
2238 .parent_hws = (const struct clk_hw *[])
2239 { &gcc_qupv3_wrap0_s0_clk_src.clkr.hw },
2241 .flags = CLK_SET_RATE_PARENT,
2242 .ops = &clk_branch2_ops,
2247 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2248 .halt_reg = 0x1f274,
2249 .halt_check = BRANCH_HALT_VOTED,
2251 .enable_reg = 0x7900c,
2252 .enable_mask = BIT(11),
2253 .hw.init = &(struct clk_init_data){
2254 .name = "gcc_qupv3_wrap0_s1_clk",
2255 .parent_hws = (const struct clk_hw *[])
2256 { &gcc_qupv3_wrap0_s1_clk_src.clkr.hw },
2258 .flags = CLK_SET_RATE_PARENT,
2259 .ops = &clk_branch2_ops,
2264 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2265 .halt_reg = 0x1f3a4,
2266 .halt_check = BRANCH_HALT_VOTED,
2268 .enable_reg = 0x7900c,
2269 .enable_mask = BIT(12),
2270 .hw.init = &(struct clk_init_data){
2271 .name = "gcc_qupv3_wrap0_s2_clk",
2272 .parent_hws = (const struct clk_hw *[])
2273 { &gcc_qupv3_wrap0_s2_clk_src.clkr.hw },
2275 .flags = CLK_SET_RATE_PARENT,
2276 .ops = &clk_branch2_ops,
2281 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2282 .halt_reg = 0x1f4d4,
2283 .halt_check = BRANCH_HALT_VOTED,
2285 .enable_reg = 0x7900c,
2286 .enable_mask = BIT(13),
2287 .hw.init = &(struct clk_init_data){
2288 .name = "gcc_qupv3_wrap0_s3_clk",
2289 .parent_hws = (const struct clk_hw *[])
2290 { &gcc_qupv3_wrap0_s3_clk_src.clkr.hw },
2292 .flags = CLK_SET_RATE_PARENT,
2293 .ops = &clk_branch2_ops,
2298 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2299 .halt_reg = 0x1f604,
2300 .halt_check = BRANCH_HALT_VOTED,
2302 .enable_reg = 0x7900c,
2303 .enable_mask = BIT(14),
2304 .hw.init = &(struct clk_init_data){
2305 .name = "gcc_qupv3_wrap0_s4_clk",
2306 .parent_hws = (const struct clk_hw *[])
2307 { &gcc_qupv3_wrap0_s4_clk_src.clkr.hw },
2309 .flags = CLK_SET_RATE_PARENT,
2310 .ops = &clk_branch2_ops,
2315 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2316 .halt_reg = 0x1f734,
2317 .halt_check = BRANCH_HALT_VOTED,
2319 .enable_reg = 0x7900c,
2320 .enable_mask = BIT(15),
2321 .hw.init = &(struct clk_init_data){
2322 .name = "gcc_qupv3_wrap0_s5_clk",
2323 .parent_hws = (const struct clk_hw *[])
2324 { &gcc_qupv3_wrap0_s5_clk_src.clkr.hw },
2326 .flags = CLK_SET_RATE_PARENT,
2327 .ops = &clk_branch2_ops,
2332 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2333 .halt_reg = 0x1f004,
2334 .halt_check = BRANCH_HALT_VOTED,
2335 .hwcg_reg = 0x1f004,
2338 .enable_reg = 0x7900c,
2339 .enable_mask = BIT(6),
2340 .hw.init = &(struct clk_init_data){
2341 .name = "gcc_qupv3_wrap_0_m_ahb_clk",
2342 .ops = &clk_branch2_ops,
2347 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2348 .halt_reg = 0x1f008,
2349 .halt_check = BRANCH_HALT_VOTED,
2350 .hwcg_reg = 0x1f008,
2353 .enable_reg = 0x7900c,
2354 .enable_mask = BIT(7),
2355 .hw.init = &(struct clk_init_data){
2356 .name = "gcc_qupv3_wrap_0_s_ahb_clk",
2357 .ops = &clk_branch2_ops,
2362 static struct clk_branch gcc_sdcc1_ahb_clk = {
2363 .halt_reg = 0x38008,
2364 .halt_check = BRANCH_HALT,
2366 .enable_reg = 0x38008,
2367 .enable_mask = BIT(0),
2368 .hw.init = &(struct clk_init_data){
2369 .name = "gcc_sdcc1_ahb_clk",
2370 .ops = &clk_branch2_ops,
2375 static struct clk_branch gcc_sdcc1_apps_clk = {
2376 .halt_reg = 0x38004,
2377 .halt_check = BRANCH_HALT,
2379 .enable_reg = 0x38004,
2380 .enable_mask = BIT(0),
2381 .hw.init = &(struct clk_init_data){
2382 .name = "gcc_sdcc1_apps_clk",
2383 .parent_hws = (const struct clk_hw *[])
2384 { &gcc_sdcc1_apps_clk_src.clkr.hw },
2386 .flags = CLK_SET_RATE_PARENT,
2387 .ops = &clk_branch2_ops,
2392 static struct clk_branch gcc_sdcc1_ice_core_clk = {
2393 .halt_reg = 0x3800c,
2394 .halt_check = BRANCH_HALT,
2395 .hwcg_reg = 0x3800c,
2398 .enable_reg = 0x3800c,
2399 .enable_mask = BIT(0),
2400 .hw.init = &(struct clk_init_data){
2401 .name = "gcc_sdcc1_ice_core_clk",
2402 .parent_hws = (const struct clk_hw *[])
2403 { &gcc_sdcc1_ice_core_clk_src.clkr.hw },
2405 .flags = CLK_SET_RATE_PARENT,
2406 .ops = &clk_branch2_ops,
2411 static struct clk_branch gcc_sdcc2_ahb_clk = {
2412 .halt_reg = 0x1e008,
2413 .halt_check = BRANCH_HALT,
2415 .enable_reg = 0x1e008,
2416 .enable_mask = BIT(0),
2417 .hw.init = &(struct clk_init_data){
2418 .name = "gcc_sdcc2_ahb_clk",
2419 .ops = &clk_branch2_ops,
2424 static struct clk_branch gcc_sdcc2_apps_clk = {
2425 .halt_reg = 0x1e004,
2426 .halt_check = BRANCH_HALT,
2428 .enable_reg = 0x1e004,
2429 .enable_mask = BIT(0),
2430 .hw.init = &(struct clk_init_data){
2431 .name = "gcc_sdcc2_apps_clk",
2432 .parent_hws = (const struct clk_hw *[])
2433 { &gcc_sdcc2_apps_clk_src.clkr.hw },
2435 .flags = CLK_SET_RATE_PARENT,
2436 .ops = &clk_branch2_ops,
2441 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
2442 .halt_reg = 0x2b06c,
2443 .halt_check = BRANCH_HALT_VOTED,
2444 .hwcg_reg = 0x2b06c,
2447 .enable_reg = 0x79004,
2448 .enable_mask = BIT(0),
2449 .hw.init = &(struct clk_init_data){
2450 .name = "gcc_sys_noc_cpuss_ahb_clk",
2451 .flags = CLK_IS_CRITICAL,
2452 .ops = &clk_branch2_ops,
2457 static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = {
2458 .halt_reg = 0x1a080,
2459 .halt_check = BRANCH_HALT,
2460 .hwcg_reg = 0x1a080,
2463 .enable_reg = 0x1a080,
2464 .enable_mask = BIT(0),
2465 .hw.init = &(struct clk_init_data){
2466 .name = "gcc_sys_noc_usb3_prim_axi_clk",
2467 .parent_hws = (const struct clk_hw *[])
2468 { &gcc_usb30_prim_master_clk_src.clkr.hw },
2470 .flags = CLK_SET_RATE_PARENT,
2471 .ops = &clk_branch2_ops,
2476 static struct clk_branch gcc_usb30_prim_master_clk = {
2477 .halt_reg = 0x1a010,
2478 .halt_check = BRANCH_HALT,
2480 .enable_reg = 0x1a010,
2481 .enable_mask = BIT(0),
2482 .hw.init = &(struct clk_init_data){
2483 .name = "gcc_usb30_prim_master_clk",
2484 .parent_hws = (const struct clk_hw *[])
2485 { &gcc_usb30_prim_master_clk_src.clkr.hw },
2487 .flags = CLK_SET_RATE_PARENT,
2488 .ops = &clk_branch2_ops,
2493 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
2494 .halt_reg = 0x1a018,
2495 .halt_check = BRANCH_HALT,
2497 .enable_reg = 0x1a018,
2498 .enable_mask = BIT(0),
2499 .hw.init = &(struct clk_init_data){
2500 .name = "gcc_usb30_prim_mock_utmi_clk",
2501 .parent_hws = (const struct clk_hw *[])
2502 { &gcc_usb30_prim_mock_utmi_postdiv.clkr.hw },
2504 .flags = CLK_SET_RATE_PARENT,
2505 .ops = &clk_branch2_ops,
2510 static struct clk_branch gcc_usb30_prim_sleep_clk = {
2511 .halt_reg = 0x1a014,
2512 .halt_check = BRANCH_HALT,
2514 .enable_reg = 0x1a014,
2515 .enable_mask = BIT(0),
2516 .hw.init = &(struct clk_init_data){
2517 .name = "gcc_usb30_prim_sleep_clk",
2518 .ops = &clk_branch2_ops,
2523 static struct clk_branch gcc_usb3_prim_clkref_clk = {
2524 .halt_reg = 0x9f000,
2525 .halt_check = BRANCH_HALT,
2527 .enable_reg = 0x9f000,
2528 .enable_mask = BIT(0),
2529 .hw.init = &(struct clk_init_data){
2530 .name = "gcc_usb3_prim_clkref_clk",
2531 .ops = &clk_branch2_ops,
2536 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
2537 .halt_reg = 0x1a054,
2538 .halt_check = BRANCH_HALT,
2540 .enable_reg = 0x1a054,
2541 .enable_mask = BIT(0),
2542 .hw.init = &(struct clk_init_data){
2543 .name = "gcc_usb3_prim_phy_com_aux_clk",
2544 .parent_hws = (const struct clk_hw *[])
2545 { &gcc_usb3_prim_phy_aux_clk_src.clkr.hw },
2547 .flags = CLK_SET_RATE_PARENT,
2548 .ops = &clk_branch2_ops,
2553 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
2554 .halt_reg = 0x1a058,
2555 .halt_check = BRANCH_HALT_SKIP,
2556 .hwcg_reg = 0x1a058,
2559 .enable_reg = 0x1a058,
2560 .enable_mask = BIT(0),
2561 .hw.init = &(struct clk_init_data){
2562 .name = "gcc_usb3_prim_phy_pipe_clk",
2563 .ops = &clk_branch2_ops,
2568 static struct clk_branch gcc_vcodec0_axi_clk = {
2569 .halt_reg = 0x6e008,
2570 .halt_check = BRANCH_HALT,
2572 .enable_reg = 0x6e008,
2573 .enable_mask = BIT(0),
2574 .hw.init = &(struct clk_init_data){
2575 .name = "gcc_vcodec0_axi_clk",
2576 .ops = &clk_branch2_ops,
2581 static struct clk_branch gcc_venus_ahb_clk = {
2582 .halt_reg = 0x6e010,
2583 .halt_check = BRANCH_HALT,
2585 .enable_reg = 0x6e010,
2586 .enable_mask = BIT(0),
2587 .hw.init = &(struct clk_init_data){
2588 .name = "gcc_venus_ahb_clk",
2589 .ops = &clk_branch2_ops,
2594 static struct clk_branch gcc_venus_ctl_axi_clk = {
2595 .halt_reg = 0x6e004,
2596 .halt_check = BRANCH_HALT,
2598 .enable_reg = 0x6e004,
2599 .enable_mask = BIT(0),
2600 .hw.init = &(struct clk_init_data){
2601 .name = "gcc_venus_ctl_axi_clk",
2602 .ops = &clk_branch2_ops,
2607 static struct clk_branch gcc_video_ahb_clk = {
2608 .halt_reg = 0x17004,
2609 .halt_check = BRANCH_HALT,
2610 .hwcg_reg = 0x17004,
2613 .enable_reg = 0x17004,
2614 .enable_mask = BIT(0),
2615 .hw.init = &(struct clk_init_data){
2616 .name = "gcc_video_ahb_clk",
2617 .ops = &clk_branch2_ops,
2622 static struct clk_branch gcc_video_axi0_clk = {
2623 .halt_reg = 0x1701c,
2624 .halt_check = BRANCH_HALT,
2625 .hwcg_reg = 0x1701c,
2628 .enable_reg = 0x1701c,
2629 .enable_mask = BIT(0),
2630 .hw.init = &(struct clk_init_data){
2631 .name = "gcc_video_axi0_clk",
2632 .ops = &clk_branch2_ops,
2637 static struct clk_branch gcc_video_throttle_core_clk = {
2638 .halt_reg = 0x17068,
2639 .halt_check = BRANCH_HALT_VOTED,
2640 .hwcg_reg = 0x17068,
2643 .enable_reg = 0x79004,
2644 .enable_mask = BIT(28),
2645 .hw.init = &(struct clk_init_data){
2646 .name = "gcc_video_throttle_core_clk",
2647 .ops = &clk_branch2_ops,
2652 static struct clk_branch gcc_video_vcodec0_sys_clk = {
2653 .halt_reg = 0x580a4,
2654 .halt_check = BRANCH_HALT_DELAY,
2655 .hwcg_reg = 0x580a4,
2658 .enable_reg = 0x580a4,
2659 .enable_mask = BIT(0),
2660 .hw.init = &(struct clk_init_data){
2661 .name = "gcc_video_vcodec0_sys_clk",
2662 .parent_hws = (const struct clk_hw *[])
2663 { &gcc_video_venus_clk_src.clkr.hw },
2665 .flags = CLK_SET_RATE_PARENT,
2666 .ops = &clk_branch2_ops,
2671 static struct clk_branch gcc_video_venus_ctl_clk = {
2672 .halt_reg = 0x5808c,
2673 .halt_check = BRANCH_HALT,
2675 .enable_reg = 0x5808c,
2676 .enable_mask = BIT(0),
2677 .hw.init = &(struct clk_init_data){
2678 .name = "gcc_video_venus_ctl_clk",
2679 .parent_hws = (const struct clk_hw *[])
2680 { &gcc_video_venus_clk_src.clkr.hw },
2682 .flags = CLK_SET_RATE_PARENT,
2683 .ops = &clk_branch2_ops,
2688 static struct clk_branch gcc_video_xo_clk = {
2689 .halt_reg = 0x17024,
2690 .halt_check = BRANCH_HALT,
2692 .enable_reg = 0x17024,
2693 .enable_mask = BIT(0),
2694 .hw.init = &(struct clk_init_data){
2695 .name = "gcc_video_xo_clk",
2696 .ops = &clk_branch2_ops,
2701 static struct gdsc gcc_camss_top_gdsc = {
2704 .name = "gcc_camss_top",
2706 .pwrsts = PWRSTS_OFF_ON,
2709 static struct gdsc gcc_usb30_prim_gdsc = {
2712 .name = "gcc_usb30_prim",
2714 .pwrsts = PWRSTS_OFF_ON,
2717 static struct gdsc gcc_vcodec0_gdsc = {
2720 .name = "gcc_vcodec0",
2722 .pwrsts = PWRSTS_OFF_ON,
2725 static struct gdsc gcc_venus_gdsc = {
2728 .name = "gcc_venus",
2730 .pwrsts = PWRSTS_OFF_ON,
2733 static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = {
2736 .name = "hlos1_vote_turing_mmu_tbu1",
2738 .pwrsts = PWRSTS_OFF_ON,
2742 static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = {
2745 .name = "hlos1_vote_turing_mmu_tbu0",
2747 .pwrsts = PWRSTS_OFF_ON,
2751 static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc = {
2754 .name = "hlos1_vote_mm_snoc_mmu_tbu_rt",
2756 .pwrsts = PWRSTS_OFF_ON,
2760 static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc = {
2763 .name = "hlos1_vote_mm_snoc_mmu_tbu_nrt",
2765 .pwrsts = PWRSTS_OFF_ON,
2769 static struct clk_regmap *gcc_qcm2290_clocks[] = {
2770 [GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr,
2771 [GCC_AHB2PHY_USB_CLK] = &gcc_ahb2phy_usb_clk.clkr,
2772 [GCC_BIMC_GPU_AXI_CLK] = &gcc_bimc_gpu_axi_clk.clkr,
2773 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2774 [GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr,
2775 [GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr,
2776 [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
2777 [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
2778 [GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr,
2779 [GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr,
2780 [GCC_CAMSS_CAMNOC_ATB_CLK] = &gcc_camss_camnoc_atb_clk.clkr,
2781 [GCC_CAMSS_CAMNOC_NTS_XO_CLK] = &gcc_camss_camnoc_nts_xo_clk.clkr,
2782 [GCC_CAMSS_CCI_0_CLK] = &gcc_camss_cci_0_clk.clkr,
2783 [GCC_CAMSS_CCI_CLK_SRC] = &gcc_camss_cci_clk_src.clkr,
2784 [GCC_CAMSS_CPHY_0_CLK] = &gcc_camss_cphy_0_clk.clkr,
2785 [GCC_CAMSS_CPHY_1_CLK] = &gcc_camss_cphy_1_clk.clkr,
2786 [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
2787 [GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr,
2788 [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
2789 [GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr,
2790 [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
2791 [GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr,
2792 [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
2793 [GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr,
2794 [GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr,
2795 [GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr,
2796 [GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr,
2797 [GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr,
2798 [GCC_CAMSS_NRT_AXI_CLK] = &gcc_camss_nrt_axi_clk.clkr,
2799 [GCC_CAMSS_OPE_AHB_CLK] = &gcc_camss_ope_ahb_clk.clkr,
2800 [GCC_CAMSS_OPE_AHB_CLK_SRC] = &gcc_camss_ope_ahb_clk_src.clkr,
2801 [GCC_CAMSS_OPE_CLK] = &gcc_camss_ope_clk.clkr,
2802 [GCC_CAMSS_OPE_CLK_SRC] = &gcc_camss_ope_clk_src.clkr,
2803 [GCC_CAMSS_RT_AXI_CLK] = &gcc_camss_rt_axi_clk.clkr,
2804 [GCC_CAMSS_TFE_0_CLK] = &gcc_camss_tfe_0_clk.clkr,
2805 [GCC_CAMSS_TFE_0_CLK_SRC] = &gcc_camss_tfe_0_clk_src.clkr,
2806 [GCC_CAMSS_TFE_0_CPHY_RX_CLK] = &gcc_camss_tfe_0_cphy_rx_clk.clkr,
2807 [GCC_CAMSS_TFE_0_CSID_CLK] = &gcc_camss_tfe_0_csid_clk.clkr,
2808 [GCC_CAMSS_TFE_0_CSID_CLK_SRC] = &gcc_camss_tfe_0_csid_clk_src.clkr,
2809 [GCC_CAMSS_TFE_1_CLK] = &gcc_camss_tfe_1_clk.clkr,
2810 [GCC_CAMSS_TFE_1_CLK_SRC] = &gcc_camss_tfe_1_clk_src.clkr,
2811 [GCC_CAMSS_TFE_1_CPHY_RX_CLK] = &gcc_camss_tfe_1_cphy_rx_clk.clkr,
2812 [GCC_CAMSS_TFE_1_CSID_CLK] = &gcc_camss_tfe_1_csid_clk.clkr,
2813 [GCC_CAMSS_TFE_1_CSID_CLK_SRC] = &gcc_camss_tfe_1_csid_clk_src.clkr,
2814 [GCC_CAMSS_TFE_CPHY_RX_CLK_SRC] = &gcc_camss_tfe_cphy_rx_clk_src.clkr,
2815 [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
2816 [GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr,
2817 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
2818 [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
2819 [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
2820 [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
2821 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
2822 [GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr,
2823 [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
2824 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2825 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
2826 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2827 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
2828 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2829 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
2830 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
2831 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
2832 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
2833 [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
2834 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
2835 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
2836 [GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr,
2837 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2838 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
2839 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2840 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
2841 [GCC_PWM0_XO512_CLK] = &gcc_pwm0_xo512_clk.clkr,
2842 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
2843 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
2844 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
2845 [GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr,
2846 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
2847 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
2848 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
2849 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
2850 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
2851 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
2852 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
2853 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
2854 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
2855 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
2856 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
2857 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
2858 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
2859 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
2860 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
2861 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
2862 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
2863 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2864 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2865 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
2866 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
2867 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
2868 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2869 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2870 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
2871 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
2872 [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr,
2873 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
2874 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
2875 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
2876 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
2877 &gcc_usb30_prim_mock_utmi_clk_src.clkr,
2878 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV] =
2879 &gcc_usb30_prim_mock_utmi_postdiv.clkr,
2880 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
2881 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
2882 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
2883 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
2884 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
2885 [GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr,
2886 [GCC_VENUS_AHB_CLK] = &gcc_venus_ahb_clk.clkr,
2887 [GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr,
2888 [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
2889 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
2890 [GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr,
2891 [GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr,
2892 [GCC_VIDEO_VENUS_CLK_SRC] = &gcc_video_venus_clk_src.clkr,
2893 [GCC_VIDEO_VENUS_CTL_CLK] = &gcc_video_venus_ctl_clk.clkr,
2894 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
2895 [GPLL0] = &gpll0.clkr,
2896 [GPLL0_OUT_AUX2] = &gpll0_out_aux2.clkr,
2897 [GPLL1] = &gpll1.clkr,
2898 [GPLL10] = &gpll10.clkr,
2899 [GPLL11] = &gpll11.clkr,
2900 [GPLL3] = &gpll3.clkr,
2901 [GPLL3_OUT_MAIN] = &gpll3_out_main.clkr,
2902 [GPLL4] = &gpll4.clkr,
2903 [GPLL5] = &gpll5.clkr,
2904 [GPLL6] = &gpll6.clkr,
2905 [GPLL6_OUT_MAIN] = &gpll6_out_main.clkr,
2906 [GPLL7] = &gpll7.clkr,
2907 [GPLL8] = &gpll8.clkr,
2908 [GPLL8_OUT_MAIN] = &gpll8_out_main.clkr,
2909 [GPLL9] = &gpll9.clkr,
2910 [GPLL9_OUT_MAIN] = &gpll9_out_main.clkr,
2913 static const struct qcom_reset_map gcc_qcm2290_resets[] = {
2914 [GCC_CAMSS_OPE_BCR] = { 0x55000 },
2915 [GCC_CAMSS_TFE_BCR] = { 0x52000 },
2916 [GCC_CAMSS_TOP_BCR] = { 0x58000 },
2917 [GCC_GPU_BCR] = { 0x36000 },
2918 [GCC_MMSS_BCR] = { 0x17000 },
2919 [GCC_PDM_BCR] = { 0x20000 },
2920 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x1f000 },
2921 [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 },
2922 [GCC_SDCC1_BCR] = { 0x38000 },
2923 [GCC_SDCC2_BCR] = { 0x1e000 },
2924 [GCC_USB30_PRIM_BCR] = { 0x1a000 },
2925 [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 },
2926 [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 },
2927 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 },
2928 [GCC_VCODEC0_BCR] = { 0x58094 },
2929 [GCC_VENUS_BCR] = { 0x58078 },
2930 [GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 },
2933 static struct gdsc *gcc_qcm2290_gdscs[] = {
2934 [GCC_CAMSS_TOP_GDSC] = &gcc_camss_top_gdsc,
2935 [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc,
2936 [GCC_VCODEC0_GDSC] = &gcc_vcodec0_gdsc,
2937 [GCC_VENUS_GDSC] = &gcc_venus_gdsc,
2938 [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc,
2939 [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc,
2940 [HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc,
2941 [HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc,
2944 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
2945 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
2946 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
2947 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
2948 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
2949 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
2950 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
2953 static const struct regmap_config gcc_qcm2290_regmap_config = {
2957 .max_register = 0xc7000,
2961 static const struct qcom_cc_desc gcc_qcm2290_desc = {
2962 .config = &gcc_qcm2290_regmap_config,
2963 .clks = gcc_qcm2290_clocks,
2964 .num_clks = ARRAY_SIZE(gcc_qcm2290_clocks),
2965 .resets = gcc_qcm2290_resets,
2966 .num_resets = ARRAY_SIZE(gcc_qcm2290_resets),
2967 .gdscs = gcc_qcm2290_gdscs,
2968 .num_gdscs = ARRAY_SIZE(gcc_qcm2290_gdscs),
2971 static const struct of_device_id gcc_qcm2290_match_table[] = {
2972 { .compatible = "qcom,gcc-qcm2290" },
2975 MODULE_DEVICE_TABLE(of, gcc_qcm2290_match_table);
2977 static int gcc_qcm2290_probe(struct platform_device *pdev)
2979 struct regmap *regmap;
2982 regmap = qcom_cc_map(pdev, &gcc_qcm2290_desc);
2984 return PTR_ERR(regmap);
2986 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
2987 ARRAY_SIZE(gcc_dfs_clocks));
2991 clk_alpha_pll_configure(&gpll10, regmap, &gpll10_config);
2992 clk_alpha_pll_configure(&gpll11, regmap, &gpll11_config);
2993 clk_alpha_pll_configure(&gpll8, regmap, &gpll8_config);
2994 clk_alpha_pll_configure(&gpll9, regmap, &gpll9_config);
2996 return qcom_cc_really_probe(pdev, &gcc_qcm2290_desc, regmap);
2999 static struct platform_driver gcc_qcm2290_driver = {
3000 .probe = gcc_qcm2290_probe,
3002 .name = "gcc-qcm2290",
3003 .of_match_table = gcc_qcm2290_match_table,
3007 static int __init gcc_qcm2290_init(void)
3009 return platform_driver_register(&gcc_qcm2290_driver);
3011 subsys_initcall(gcc_qcm2290_init);
3013 static void __exit gcc_qcm2290_exit(void)
3015 platform_driver_unregister(&gcc_qcm2290_driver);
3017 module_exit(gcc_qcm2290_exit);
3019 MODULE_DESCRIPTION("QTI GCC QCM2290 Driver");
3020 MODULE_LICENSE("GPL v2");