drivers/clk/qcom/gcc-msm8994.c

   1 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/err.h>
  16 #include <linux/ctype.h>
  17 #include <linux/io.h>
  18 #include <linux/of.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/module.h>
  21 #include <linux/regmap.h>
  22
  23 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
  24
  25 #include "common.h"
  26 #include "clk-regmap.h"
  27 #include "clk-alpha-pll.h"
  28 #include "clk-rcg.h"
  29 #include "clk-branch.h"
  30 #include "reset.h"
  31
  32 enum {
  33         P_XO,
  34         P_GPLL0,
  35         P_GPLL4,
  36 };
  37
  38 static const struct parent_map gcc_xo_gpll0_map[] = {
  39         { P_XO, 0 },
  40         { P_GPLL0, 1 },
  41 };
  42
  43 static const char * const gcc_xo_gpll0[] = {
  44         "xo",
  45         "gpll0",
  46 };
  47
  48 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
  49         { P_XO, 0 },
  50         { P_GPLL0, 1 },
  51         { P_GPLL4, 5 },
  52 };
  53
  54 static const char * const gcc_xo_gpll0_gpll4[] = {
  55         "xo",
  56         "gpll0",
  57         "gpll4",
  58 };
  59
  60 static struct clk_fixed_factor xo = {
  61         .mult = 1,
  62         .div = 1,
  63         .hw.init = &(struct clk_init_data)
  64         {
  65                 .name = "xo",
  66                 .parent_names = (const char *[]) { "xo_board" },
  67                 .num_parents = 1,
  68                 .ops = &clk_fixed_factor_ops,
  69         },
  70 };
  71
  72 static struct clk_alpha_pll gpll0_early = {
  73         .offset = 0x00000,
  74         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  75         .clkr = {
  76                 .enable_reg = 0x1480,
  77                 .enable_mask = BIT(0),
  78                 .hw.init = &(struct clk_init_data)
  79                 {
  80                         .name = "gpll0_early",
  81                         .parent_names = (const char *[]) { "xo" },
  82                         .num_parents = 1,
  83                         .ops = &clk_alpha_pll_ops,
  84                 },
  85         },
  86 };
  87
  88 static struct clk_alpha_pll_postdiv gpll0 = {
  89         .offset = 0x00000,
  90         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  91         .clkr.hw.init = &(struct clk_init_data)
  92         {
  93                 .name = "gpll0",
  94                 .parent_names = (const char *[]) { "gpll0_early" },
  95                 .num_parents = 1,
  96                 .ops = &clk_alpha_pll_postdiv_ops,
  97         },
  98 };
  99
 100 static struct clk_alpha_pll gpll4_early = {
 101         .offset = 0x1dc0,
 102         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 103         .clkr = {
 104                 .enable_reg = 0x1480,
 105                 .enable_mask = BIT(4),
 106                 .hw.init = &(struct clk_init_data)
 107                 {
 108                         .name = "gpll4_early",
 109                         .parent_names = (const char *[]) { "xo" },
 110                         .num_parents = 1,
 111                         .ops = &clk_alpha_pll_ops,
 112                 },
 113         },
 114 };
 115
 116 static struct clk_alpha_pll_postdiv gpll4 = {
 117         .offset = 0x1dc0,
 118         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 119         .clkr.hw.init = &(struct clk_init_data)
 120         {
 121                 .name = "gpll4",
 122                 .parent_names = (const char *[]) { "gpll4_early" },
 123                 .num_parents = 1,
 124                 .ops = &clk_alpha_pll_postdiv_ops,
 125         },
 126 };
 127
 128 static struct freq_tbl ftbl_ufs_axi_clk_src[] = {
 129         F(50000000, P_GPLL0, 12, 0, 0),
 130         F(100000000, P_GPLL0, 6, 0, 0),
 131         F(150000000, P_GPLL0, 4, 0, 0),
 132         F(171430000, P_GPLL0, 3.5, 0, 0),
 133         F(200000000, P_GPLL0, 3, 0, 0),
 134         F(240000000, P_GPLL0, 2.5, 0, 0),
 135         { }
 136 };
 137
 138 static struct clk_rcg2 ufs_axi_clk_src = {
 139         .cmd_rcgr = 0x1d68,
 140         .mnd_width = 8,
 141         .hid_width = 5,
 142         .parent_map = gcc_xo_gpll0_map,
 143         .freq_tbl = ftbl_ufs_axi_clk_src,
 144         .clkr.hw.init = &(struct clk_init_data)
 145         {
 146                 .name = "ufs_axi_clk_src",
 147                 .parent_names = gcc_xo_gpll0,
 148                 .num_parents = 2,
 149                 .ops = &clk_rcg2_ops,
 150         },
 151 };
 152
 153 static struct freq_tbl ftbl_usb30_master_clk_src[] = {
 154         F(19200000, P_XO, 1, 0, 0),
 155         F(125000000, P_GPLL0, 1, 5, 24),
 156         { }
 157 };
 158
 159 static struct clk_rcg2 usb30_master_clk_src = {
 160         .cmd_rcgr = 0x03d4,
 161         .mnd_width = 8,
 162         .hid_width = 5,
 163         .parent_map = gcc_xo_gpll0_map,
 164         .freq_tbl = ftbl_usb30_master_clk_src,
 165         .clkr.hw.init = &(struct clk_init_data)
 166         {
 167                 .name = "usb30_master_clk_src",
 168                 .parent_names = gcc_xo_gpll0,
 169                 .num_parents = 2,
 170                 .ops = &clk_rcg2_ops,
 171         },
 172 };
 173
 174 static struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
 175         F(19200000, P_XO, 1, 0, 0),
 176         F(50000000, P_GPLL0, 12, 0, 0),
 177         { }
 178 };
 179
 180 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 181         .cmd_rcgr = 0x0660,
 182         .hid_width = 5,
 183         .parent_map = gcc_xo_gpll0_map,
 184         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 185         .clkr.hw.init = &(struct clk_init_data)
 186         {
 187                 .name = "blsp1_qup1_i2c_apps_clk_src",
 188                 .parent_names = gcc_xo_gpll0,
 189                 .num_parents = 2,
 190                 .ops = &clk_rcg2_ops,
 191         },
 192 };
 193
 194 static struct freq_tbl ftbl_blspqup_spi_apps_clk_src[] = {
 195         F(960000, P_XO, 10, 1, 2),
 196         F(4800000, P_XO, 4, 0, 0),
 197         F(9600000, P_XO, 2, 0, 0),
 198         F(15000000, P_GPLL0, 10, 1, 4),
 199         F(19200000, P_XO, 1, 0, 0),
 200         F(24000000, P_GPLL0, 12.5, 1, 2),
 201         F(25000000, P_GPLL0, 12, 1, 2),
 202         F(48000000, P_GPLL0, 12.5, 0, 0),
 203         F(50000000, P_GPLL0, 12, 0, 0),
 204         { }
 205 };
 206
 207 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 208         .cmd_rcgr = 0x064c,
 209         .mnd_width = 8,
 210         .hid_width = 5,
 211         .parent_map = gcc_xo_gpll0_map,
 212         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 213         .clkr.hw.init = &(struct clk_init_data)
 214         {
 215                 .name = "blsp1_qup1_spi_apps_clk_src",
 216                 .parent_names = gcc_xo_gpll0,
 217                 .num_parents = 2,
 218                 .ops = &clk_rcg2_ops,
 219         },
 220 };
 221
 222 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 223         .cmd_rcgr = 0x06e0,
 224         .hid_width = 5,
 225         .parent_map = gcc_xo_gpll0_map,
 226         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 227         .clkr.hw.init = &(struct clk_init_data)
 228         {
 229                 .name = "blsp1_qup2_i2c_apps_clk_src",
 230                 .parent_names = gcc_xo_gpll0,
 231                 .num_parents = 2,
 232                 .ops = &clk_rcg2_ops,
 233         },
 234 };
 235
 236 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 237         .cmd_rcgr = 0x06cc,
 238         .mnd_width = 8,
 239         .hid_width = 5,
 240         .parent_map = gcc_xo_gpll0_map,
 241         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 242         .clkr.hw.init = &(struct clk_init_data)
 243         {
 244                 .name = "blsp1_qup2_spi_apps_clk_src",
 245                 .parent_names = gcc_xo_gpll0,
 246                 .num_parents = 2,
 247                 .ops = &clk_rcg2_ops,
 248         },
 249 };
 250
 251 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 252         .cmd_rcgr = 0x0760,
 253         .hid_width = 5,
 254         .parent_map = gcc_xo_gpll0_map,
 255         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 256         .clkr.hw.init = &(struct clk_init_data)
 257         {
 258                 .name = "blsp1_qup3_i2c_apps_clk_src",
 259                 .parent_names = gcc_xo_gpll0,
 260                 .num_parents = 2,
 261                 .ops = &clk_rcg2_ops,
 262         },
 263 };
 264
 265 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 266         .cmd_rcgr = 0x074c,
 267         .mnd_width = 8,
 268         .hid_width = 5,
 269         .parent_map = gcc_xo_gpll0_map,
 270         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 271         .clkr.hw.init = &(struct clk_init_data)
 272         {
 273                 .name = "blsp1_qup3_spi_apps_clk_src",
 274                 .parent_names = gcc_xo_gpll0,
 275                 .num_parents = 2,
 276                 .ops = &clk_rcg2_ops,
 277         },
 278 };
 279
 280 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 281         .cmd_rcgr = 0x07e0,
 282         .hid_width = 5,
 283         .parent_map = gcc_xo_gpll0_map,
 284         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 285         .clkr.hw.init = &(struct clk_init_data)
 286         {
 287                 .name = "blsp1_qup4_i2c_apps_clk_src",
 288                 .parent_names = gcc_xo_gpll0,
 289                 .num_parents = 2,
 290                 .ops = &clk_rcg2_ops,
 291         },
 292 };
 293
 294 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 295         .cmd_rcgr = 0x07cc,
 296         .mnd_width = 8,
 297         .hid_width = 5,
 298         .parent_map = gcc_xo_gpll0_map,
 299         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 300         .clkr.hw.init = &(struct clk_init_data)
 301         {
 302                 .name = "blsp1_qup4_spi_apps_clk_src",
 303                 .parent_names = gcc_xo_gpll0,
 304                 .num_parents = 2,
 305                 .ops = &clk_rcg2_ops,
 306         },
 307 };
 308
 309 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 310         .cmd_rcgr = 0x0860,
 311         .hid_width = 5,
 312         .parent_map = gcc_xo_gpll0_map,
 313         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 314         .clkr.hw.init = &(struct clk_init_data)
 315         {
 316                 .name = "blsp1_qup5_i2c_apps_clk_src",
 317                 .parent_names = gcc_xo_gpll0,
 318                 .num_parents = 2,
 319                 .ops = &clk_rcg2_ops,
 320         },
 321 };
 322
 323 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 324         .cmd_rcgr = 0x084c,
 325         .mnd_width = 8,
 326         .hid_width = 5,
 327         .parent_map = gcc_xo_gpll0_map,
 328         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 329         .clkr.hw.init = &(struct clk_init_data)
 330         {
 331                 .name = "blsp1_qup5_spi_apps_clk_src",
 332                 .parent_names = gcc_xo_gpll0,
 333                 .num_parents = 2,
 334                 .ops = &clk_rcg2_ops,
 335         },
 336 };
 337
 338 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 339         .cmd_rcgr = 0x08e0,
 340         .hid_width = 5,
 341         .parent_map = gcc_xo_gpll0_map,
 342         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 343         .clkr.hw.init = &(struct clk_init_data)
 344         {
 345                 .name = "blsp1_qup6_i2c_apps_clk_src",
 346                 .parent_names = gcc_xo_gpll0,
 347                 .num_parents = 2,
 348                 .ops = &clk_rcg2_ops,
 349         },
 350 };
 351
 352 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 353         .cmd_rcgr = 0x08cc,
 354         .mnd_width = 8,
 355         .hid_width = 5,
 356         .parent_map = gcc_xo_gpll0_map,
 357         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 358         .clkr.hw.init = &(struct clk_init_data)
 359         {
 360                 .name = "blsp1_qup6_spi_apps_clk_src",
 361                 .parent_names = gcc_xo_gpll0,
 362                 .num_parents = 2,
 363                 .ops = &clk_rcg2_ops,
 364         },
 365 };
 366
 367 static struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
 368         F(3686400, P_GPLL0, 1, 96, 15625),
 369         F(7372800, P_GPLL0, 1, 192, 15625),
 370         F(14745600, P_GPLL0, 1, 384, 15625),
 371         F(16000000, P_GPLL0, 5, 2, 15),
 372         F(19200000, P_XO, 1, 0, 0),
 373         F(24000000, P_GPLL0, 5, 1, 5),
 374         F(32000000, P_GPLL0, 1, 4, 75),
 375         F(40000000, P_GPLL0, 15, 0, 0),
 376         F(46400000, P_GPLL0, 1, 29, 375),
 377         F(48000000, P_GPLL0, 12.5, 0, 0),
 378         F(51200000, P_GPLL0, 1, 32, 375),
 379         F(56000000, P_GPLL0, 1, 7, 75),
 380         F(58982400, P_GPLL0, 1, 1536, 15625),
 381         F(60000000, P_GPLL0, 10, 0, 0),
 382         F(63160000, P_GPLL0, 9.5, 0, 0),
 383         { }
 384 };
 385
 386 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 387         .cmd_rcgr = 0x068c,
 388         .mnd_width = 16,
 389         .hid_width = 5,
 390         .parent_map = gcc_xo_gpll0_map,
 391         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 392         .clkr.hw.init = &(struct clk_init_data)
 393         {
 394                 .name = "blsp1_uart1_apps_clk_src",
 395                 .parent_names = gcc_xo_gpll0,
 396                 .num_parents = 2,
 397                 .ops = &clk_rcg2_ops,
 398         },
 399 };
 400
 401 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 402         .cmd_rcgr = 0x070c,
 403         .mnd_width = 16,
 404         .hid_width = 5,
 405         .parent_map = gcc_xo_gpll0_map,
 406         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 407         .clkr.hw.init = &(struct clk_init_data)
 408         {
 409                 .name = "blsp1_uart2_apps_clk_src",
 410                 .parent_names = gcc_xo_gpll0,
 411                 .num_parents = 2,
 412                 .ops = &clk_rcg2_ops,
 413         },
 414 };
 415
 416 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 417         .cmd_rcgr = 0x078c,
 418         .mnd_width = 16,
 419         .hid_width = 5,
 420         .parent_map = gcc_xo_gpll0_map,
 421         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 422         .clkr.hw.init = &(struct clk_init_data)
 423         {
 424                 .name = "blsp1_uart3_apps_clk_src",
 425                 .parent_names = gcc_xo_gpll0,
 426                 .num_parents = 2,
 427                 .ops = &clk_rcg2_ops,
 428         },
 429 };
 430
 431 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 432         .cmd_rcgr = 0x080c,
 433         .mnd_width = 16,
 434         .hid_width = 5,
 435         .parent_map = gcc_xo_gpll0_map,
 436         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 437         .clkr.hw.init = &(struct clk_init_data)
 438         {
 439                 .name = "blsp1_uart4_apps_clk_src",
 440                 .parent_names = gcc_xo_gpll0,
 441                 .num_parents = 2,
 442                 .ops = &clk_rcg2_ops,
 443         },
 444 };
 445
 446 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 447         .cmd_rcgr = 0x088c,
 448         .mnd_width = 16,
 449         .hid_width = 5,
 450         .parent_map = gcc_xo_gpll0_map,
 451         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 452         .clkr.hw.init = &(struct clk_init_data)
 453         {
 454                 .name = "blsp1_uart5_apps_clk_src",
 455                 .parent_names = gcc_xo_gpll0,
 456                 .num_parents = 2,
 457                 .ops = &clk_rcg2_ops,
 458         },
 459 };
 460
 461 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 462         .cmd_rcgr = 0x090c,
 463         .mnd_width = 16,
 464         .hid_width = 5,
 465         .parent_map = gcc_xo_gpll0_map,
 466         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 467         .clkr.hw.init = &(struct clk_init_data)
 468         {
 469                 .name = "blsp1_uart6_apps_clk_src",
 470                 .parent_names = gcc_xo_gpll0,
 471                 .num_parents = 2,
 472                 .ops = &clk_rcg2_ops,
 473         },
 474 };
 475
 476 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
 477         .cmd_rcgr = 0x09a0,
 478         .hid_width = 5,
 479         .parent_map = gcc_xo_gpll0_map,
 480         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 481         .clkr.hw.init = &(struct clk_init_data)
 482         {
 483                 .name = "blsp2_qup1_i2c_apps_clk_src",
 484                 .parent_names = gcc_xo_gpll0,
 485                 .num_parents = 2,
 486                 .ops = &clk_rcg2_ops,
 487         },
 488 };
 489
 490 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
 491         .cmd_rcgr = 0x098c,
 492         .mnd_width = 8,
 493         .hid_width = 5,
 494         .parent_map = gcc_xo_gpll0_map,
 495         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 496         .clkr.hw.init = &(struct clk_init_data)
 497         {
 498                 .name = "blsp2_qup1_spi_apps_clk_src",
 499                 .parent_names = gcc_xo_gpll0,
 500                 .num_parents = 2,
 501                 .ops = &clk_rcg2_ops,
 502         },
 503 };
 504
 505 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
 506         .cmd_rcgr = 0x0a20,
 507         .hid_width = 5,
 508         .parent_map = gcc_xo_gpll0_map,
 509         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 510         .clkr.hw.init = &(struct clk_init_data)
 511         {
 512                 .name = "blsp2_qup2_i2c_apps_clk_src",
 513                 .parent_names = gcc_xo_gpll0,
 514                 .num_parents = 2,
 515                 .ops = &clk_rcg2_ops,
 516         },
 517 };
 518
 519 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
 520         .cmd_rcgr = 0x0a0c,
 521         .mnd_width = 8,
 522         .hid_width = 5,
 523         .parent_map = gcc_xo_gpll0_map,
 524         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 525         .clkr.hw.init = &(struct clk_init_data)
 526         {
 527                 .name = "blsp2_qup2_spi_apps_clk_src",
 528                 .parent_names = gcc_xo_gpll0,
 529                 .num_parents = 2,
 530                 .ops = &clk_rcg2_ops,
 531         },
 532 };
 533
 534 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
 535         .cmd_rcgr = 0x0aa0,
 536         .hid_width = 5,
 537         .parent_map = gcc_xo_gpll0_map,
 538         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 539         .clkr.hw.init = &(struct clk_init_data)
 540         {
 541                 .name = "blsp2_qup3_i2c_apps_clk_src",
 542                 .parent_names = gcc_xo_gpll0,
 543                 .num_parents = 2,
 544                 .ops = &clk_rcg2_ops,
 545         },
 546 };
 547
 548 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
 549         .cmd_rcgr = 0x0a8c,
 550         .mnd_width = 8,
 551         .hid_width = 5,
 552         .parent_map = gcc_xo_gpll0_map,
 553         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 554         .clkr.hw.init = &(struct clk_init_data)
 555         {
 556                 .name = "blsp2_qup3_spi_apps_clk_src",
 557                 .parent_names = gcc_xo_gpll0,
 558                 .num_parents = 2,
 559                 .ops = &clk_rcg2_ops,
 560         },
 561 };
 562
 563 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
 564         .cmd_rcgr = 0x0b20,
 565         .hid_width = 5,
 566         .parent_map = gcc_xo_gpll0_map,
 567         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 568         .clkr.hw.init = &(struct clk_init_data)
 569         {
 570                 .name = "blsp2_qup4_i2c_apps_clk_src",
 571                 .parent_names = gcc_xo_gpll0,
 572                 .num_parents = 2,
 573                 .ops = &clk_rcg2_ops,
 574         },
 575 };
 576
 577 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
 578         .cmd_rcgr = 0x0b0c,
 579         .mnd_width = 8,
 580         .hid_width = 5,
 581         .parent_map = gcc_xo_gpll0_map,
 582         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 583         .clkr.hw.init = &(struct clk_init_data)
 584         {
 585                 .name = "blsp2_qup4_spi_apps_clk_src",
 586                 .parent_names = gcc_xo_gpll0,
 587                 .num_parents = 2,
 588                 .ops = &clk_rcg2_ops,
 589         },
 590 };
 591
 592 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
 593         .cmd_rcgr = 0x0ba0,
 594         .hid_width = 5,
 595         .parent_map = gcc_xo_gpll0_map,
 596         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 597         .clkr.hw.init = &(struct clk_init_data)
 598         {
 599                 .name = "blsp2_qup5_i2c_apps_clk_src",
 600                 .parent_names = gcc_xo_gpll0,
 601                 .num_parents = 2,
 602                 .ops = &clk_rcg2_ops,
 603         },
 604 };
 605
 606 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
 607         .cmd_rcgr = 0x0b8c,
 608         .mnd_width = 8,
 609         .hid_width = 5,
 610         .parent_map = gcc_xo_gpll0_map,
 611         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 612         .clkr.hw.init = &(struct clk_init_data)
 613         {
 614                 .name = "blsp2_qup5_spi_apps_clk_src",
 615                 .parent_names = gcc_xo_gpll0,
 616                 .num_parents = 2,
 617                 .ops = &clk_rcg2_ops,
 618         },
 619 };
 620
 621 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
 622         .cmd_rcgr = 0x0c20,
 623         .hid_width = 5,
 624         .parent_map = gcc_xo_gpll0_map,
 625         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 626         .clkr.hw.init = &(struct clk_init_data)
 627         {
 628                 .name = "blsp2_qup6_i2c_apps_clk_src",
 629                 .parent_names = gcc_xo_gpll0,
 630                 .num_parents = 2,
 631                 .ops = &clk_rcg2_ops,
 632         },
 633 };
 634
 635 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
 636         .cmd_rcgr = 0x0c0c,
 637         .mnd_width = 8,
 638         .hid_width = 5,
 639         .parent_map = gcc_xo_gpll0_map,
 640         .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
 641         .clkr.hw.init = &(struct clk_init_data)
 642         {
 643                 .name = "blsp2_qup6_spi_apps_clk_src",
 644                 .parent_names = gcc_xo_gpll0,
 645                 .num_parents = 2,
 646                 .ops = &clk_rcg2_ops,
 647         },
 648 };
 649
 650 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
 651         .cmd_rcgr = 0x09cc,
 652         .mnd_width = 16,
 653         .hid_width = 5,
 654         .parent_map = gcc_xo_gpll0_map,
 655         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 656         .clkr.hw.init = &(struct clk_init_data)
 657         {
 658                 .name = "blsp2_uart1_apps_clk_src",
 659                 .parent_names = gcc_xo_gpll0,
 660                 .num_parents = 2,
 661                 .ops = &clk_rcg2_ops,
 662         },
 663 };
 664
 665 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
 666         .cmd_rcgr = 0x0a4c,
 667         .mnd_width = 16,
 668         .hid_width = 5,
 669         .parent_map = gcc_xo_gpll0_map,
 670         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 671         .clkr.hw.init = &(struct clk_init_data)
 672         {
 673                 .name = "blsp2_uart2_apps_clk_src",
 674                 .parent_names = gcc_xo_gpll0,
 675                 .num_parents = 2,
 676                 .ops = &clk_rcg2_ops,
 677         },
 678 };
 679
 680 static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
 681         .cmd_rcgr = 0x0acc,
 682         .mnd_width = 16,
 683         .hid_width = 5,
 684         .parent_map = gcc_xo_gpll0_map,
 685         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 686         .clkr.hw.init = &(struct clk_init_data)
 687         {
 688                 .name = "blsp2_uart3_apps_clk_src",
 689                 .parent_names = gcc_xo_gpll0,
 690                 .num_parents = 2,
 691                 .ops = &clk_rcg2_ops,
 692         },
 693 };
 694
 695 static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
 696         .cmd_rcgr = 0x0b4c,
 697         .mnd_width = 16,
 698         .hid_width = 5,
 699         .parent_map = gcc_xo_gpll0_map,
 700         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 701         .clkr.hw.init = &(struct clk_init_data)
 702         {
 703                 .name = "blsp2_uart4_apps_clk_src",
 704                 .parent_names = gcc_xo_gpll0,
 705                 .num_parents = 2,
 706                 .ops = &clk_rcg2_ops,
 707         },
 708 };
 709
 710 static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
 711         .cmd_rcgr = 0x0bcc,
 712         .mnd_width = 16,
 713         .hid_width = 5,
 714         .parent_map = gcc_xo_gpll0_map,
 715         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 716         .clkr.hw.init = &(struct clk_init_data)
 717         {
 718                 .name = "blsp2_uart5_apps_clk_src",
 719                 .parent_names = gcc_xo_gpll0,
 720                 .num_parents = 2,
 721                 .ops = &clk_rcg2_ops,
 722         },
 723 };
 724
 725 static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
 726         .cmd_rcgr = 0x0c4c,
 727         .mnd_width = 16,
 728         .hid_width = 5,
 729         .parent_map = gcc_xo_gpll0_map,
 730         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 731         .clkr.hw.init = &(struct clk_init_data)
 732         {
 733                 .name = "blsp2_uart6_apps_clk_src",
 734                 .parent_names = gcc_xo_gpll0,
 735                 .num_parents = 2,
 736                 .ops = &clk_rcg2_ops,
 737         },
 738 };
 739
 740 static struct freq_tbl ftbl_gp1_clk_src[] = {
 741         F(19200000, P_XO, 1, 0, 0),
 742         F(100000000, P_GPLL0, 6, 0, 0),
 743         F(200000000, P_GPLL0, 3, 0, 0),
 744         { }
 745 };
 746
 747 static struct clk_rcg2 gp1_clk_src = {
 748         .cmd_rcgr = 0x1904,
 749         .mnd_width = 8,
 750         .hid_width = 5,
 751         .parent_map = gcc_xo_gpll0_map,
 752         .freq_tbl = ftbl_gp1_clk_src,
 753         .clkr.hw.init = &(struct clk_init_data)
 754         {
 755                 .name = "gp1_clk_src",
 756                 .parent_names = gcc_xo_gpll0,
 757                 .num_parents = 2,
 758                 .ops = &clk_rcg2_ops,
 759         },
 760 };
 761
 762 static struct freq_tbl ftbl_gp2_clk_src[] = {
 763         F(19200000, P_XO, 1, 0, 0),
 764         F(100000000, P_GPLL0, 6, 0, 0),
 765         F(200000000, P_GPLL0, 3, 0, 0),
 766         { }
 767 };
 768
 769 static struct clk_rcg2 gp2_clk_src = {
 770         .cmd_rcgr = 0x1944,
 771         .mnd_width = 8,
 772         .hid_width = 5,
 773         .parent_map = gcc_xo_gpll0_map,
 774         .freq_tbl = ftbl_gp2_clk_src,
 775         .clkr.hw.init = &(struct clk_init_data)
 776         {
 777                 .name = "gp2_clk_src",
 778                 .parent_names = gcc_xo_gpll0,
 779                 .num_parents = 2,
 780                 .ops = &clk_rcg2_ops,
 781         },
 782 };
 783
 784 static struct freq_tbl ftbl_gp3_clk_src[] = {
 785         F(19200000, P_XO, 1, 0, 0),
 786         F(100000000, P_GPLL0, 6, 0, 0),
 787         F(200000000, P_GPLL0, 3, 0, 0),
 788         { }
 789 };
 790
 791 static struct clk_rcg2 gp3_clk_src = {
 792         .cmd_rcgr = 0x1984,
 793         .mnd_width = 8,
 794         .hid_width = 5,
 795         .parent_map = gcc_xo_gpll0_map,
 796         .freq_tbl = ftbl_gp3_clk_src,
 797         .clkr.hw.init = &(struct clk_init_data)
 798         {
 799                 .name = "gp3_clk_src",
 800                 .parent_names = gcc_xo_gpll0,
 801                 .num_parents = 2,
 802                 .ops = &clk_rcg2_ops,
 803         },
 804 };
 805
 806 static struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
 807         F(1011000, P_XO, 1, 1, 19),
 808         { }
 809 };
 810
 811 static struct clk_rcg2 pcie_0_aux_clk_src = {
 812         .cmd_rcgr = 0x1b00,
 813         .mnd_width = 8,
 814         .hid_width = 5,
 815         .freq_tbl = ftbl_pcie_0_aux_clk_src,
 816         .clkr.hw.init = &(struct clk_init_data)
 817         {
 818                 .name = "pcie_0_aux_clk_src",
 819                 .parent_names = (const char *[]) { "xo" },
 820                 .num_parents = 1,
 821                 .ops = &clk_rcg2_ops,
 822         },
 823 };
 824
 825 static struct freq_tbl ftbl_pcie_pipe_clk_src[] = {
 826         F(125000000, P_XO, 1, 0, 0),
 827         { }
 828 };
 829
 830 static struct clk_rcg2 pcie_0_pipe_clk_src = {
 831         .cmd_rcgr = 0x1adc,
 832         .hid_width = 5,
 833         .freq_tbl = ftbl_pcie_pipe_clk_src,
 834         .clkr.hw.init = &(struct clk_init_data)
 835         {
 836                 .name = "pcie_0_pipe_clk_src",
 837                 .parent_names = (const char *[]) { "xo" },
 838                 .num_parents = 1,
 839                 .ops = &clk_rcg2_ops,
 840         },
 841 };
 842
 843 static struct freq_tbl ftbl_pcie_1_aux_clk_src[] = {
 844         F(1011000, P_XO, 1, 1, 19),
 845         { }
 846 };
 847
 848 static struct clk_rcg2 pcie_1_aux_clk_src = {
 849         .cmd_rcgr = 0x1b80,
 850         .mnd_width = 8,
 851         .hid_width = 5,
 852         .freq_tbl = ftbl_pcie_1_aux_clk_src,
 853         .clkr.hw.init = &(struct clk_init_data)
 854         {
 855                 .name = "pcie_1_aux_clk_src",
 856                 .parent_names = (const char *[]) { "xo" },
 857                 .num_parents = 1,
 858                 .ops = &clk_rcg2_ops,
 859         },
 860 };
 861
 862 static struct clk_rcg2 pcie_1_pipe_clk_src = {
 863         .cmd_rcgr = 0x1b5c,
 864         .hid_width = 5,
 865         .freq_tbl = ftbl_pcie_pipe_clk_src,
 866         .clkr.hw.init = &(struct clk_init_data)
 867         {
 868                 .name = "pcie_1_pipe_clk_src",
 869                 .parent_names = (const char *[]) { "xo" },
 870                 .num_parents = 1,
 871                 .ops = &clk_rcg2_ops,
 872         },
 873 };
 874
 875 static struct freq_tbl ftbl_pdm2_clk_src[] = {
 876         F(60000000, P_GPLL0, 10, 0, 0),
 877         { }
 878 };
 879
 880 static struct clk_rcg2 pdm2_clk_src = {
 881         .cmd_rcgr = 0x0cd0,
 882         .hid_width = 5,
 883         .parent_map = gcc_xo_gpll0_map,
 884         .freq_tbl = ftbl_pdm2_clk_src,
 885         .clkr.hw.init = &(struct clk_init_data)
 886         {
 887                 .name = "pdm2_clk_src",
 888                 .parent_names = gcc_xo_gpll0,
 889                 .num_parents = 2,
 890                 .ops = &clk_rcg2_ops,
 891         },
 892 };
 893
 894 static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
 895         F(144000, P_XO, 16, 3, 25),
 896         F(400000, P_XO, 12, 1, 4),
 897         F(20000000, P_GPLL0, 15, 1, 2),
 898         F(25000000, P_GPLL0, 12, 1, 2),
 899         F(50000000, P_GPLL0, 12, 0, 0),
 900         F(100000000, P_GPLL0, 6, 0, 0),
 901         F(192000000, P_GPLL4, 2, 0, 0),
 902         F(384000000, P_GPLL4, 1, 0, 0),
 903         { }
 904 };
 905
 906 static struct clk_rcg2 sdcc1_apps_clk_src = {
 907         .cmd_rcgr = 0x04d0,
 908         .mnd_width = 8,
 909         .hid_width = 5,
 910         .parent_map = gcc_xo_gpll0_gpll4_map,
 911         .freq_tbl = ftbl_sdcc1_apps_clk_src,
 912         .clkr.hw.init = &(struct clk_init_data)
 913         {
 914                 .name = "sdcc1_apps_clk_src",
 915                 .parent_names = gcc_xo_gpll0_gpll4,
 916                 .num_parents = 3,
 917                 .ops = &clk_rcg2_floor_ops,
 918         },
 919 };
 920
 921 static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = {
 922         F(144000, P_XO, 16, 3, 25),
 923         F(400000, P_XO, 12, 1, 4),
 924         F(20000000, P_GPLL0, 15, 1, 2),
 925         F(25000000, P_GPLL0, 12, 1, 2),
 926         F(50000000, P_GPLL0, 12, 0, 0),
 927         F(100000000, P_GPLL0, 6, 0, 0),
 928         F(200000000, P_GPLL0, 3, 0, 0),
 929         { }
 930 };
 931
 932 static struct clk_rcg2 sdcc2_apps_clk_src = {
 933         .cmd_rcgr = 0x0510,
 934         .mnd_width = 8,
 935         .hid_width = 5,
 936         .parent_map = gcc_xo_gpll0_map,
 937         .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
 938         .clkr.hw.init = &(struct clk_init_data)
 939         {
 940                 .name = "sdcc2_apps_clk_src",
 941                 .parent_names = gcc_xo_gpll0,
 942                 .num_parents = 2,
 943                 .ops = &clk_rcg2_floor_ops,
 944         },
 945 };
 946
 947 static struct clk_rcg2 sdcc3_apps_clk_src = {
 948         .cmd_rcgr = 0x0550,
 949         .mnd_width = 8,
 950         .hid_width = 5,
 951         .parent_map = gcc_xo_gpll0_map,
 952         .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
 953         .clkr.hw.init = &(struct clk_init_data)
 954         {
 955                 .name = "sdcc3_apps_clk_src",
 956                 .parent_names = gcc_xo_gpll0,
 957                 .num_parents = 2,
 958                 .ops = &clk_rcg2_floor_ops,
 959         },
 960 };
 961
 962 static struct clk_rcg2 sdcc4_apps_clk_src = {
 963         .cmd_rcgr = 0x0590,
 964         .mnd_width = 8,
 965         .hid_width = 5,
 966         .parent_map = gcc_xo_gpll0_map,
 967         .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
 968         .clkr.hw.init = &(struct clk_init_data)
 969         {
 970                 .name = "sdcc4_apps_clk_src",
 971                 .parent_names = gcc_xo_gpll0,
 972                 .num_parents = 2,
 973                 .ops = &clk_rcg2_floor_ops,
 974         },
 975 };
 976
 977 static struct freq_tbl ftbl_tsif_ref_clk_src[] = {
 978         F(105500, P_XO, 1, 1, 182),
 979         { }
 980 };
 981
 982 static struct clk_rcg2 tsif_ref_clk_src = {
 983         .cmd_rcgr = 0x0d90,
 984         .mnd_width = 8,
 985         .hid_width = 5,
 986         .freq_tbl = ftbl_tsif_ref_clk_src,
 987         .clkr.hw.init = &(struct clk_init_data)
 988         {
 989                 .name = "tsif_ref_clk_src",
 990                 .parent_names = (const char *[]) { "xo" },
 991                 .num_parents = 1,
 992                 .ops = &clk_rcg2_ops,
 993         },
 994 };
 995
 996 static struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
 997         F(19200000, P_XO, 1, 0, 0),
 998         F(60000000, P_GPLL0, 10, 0, 0),
 999         { }
1000 };
1001
1002 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1003         .cmd_rcgr = 0x03e8,
1004         .hid_width = 5,
1005         .parent_map = gcc_xo_gpll0_map,
1006         .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
1007         .clkr.hw.init = &(struct clk_init_data)
1008         {
1009                 .name = "usb30_mock_utmi_clk_src",
1010                 .parent_names = gcc_xo_gpll0,
1011                 .num_parents = 2,
1012                 .ops = &clk_rcg2_ops,
1013         },
1014 };
1015
1016 static struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
1017         F(1200000, P_XO, 16, 0, 0),
1018         { }
1019 };
1020
1021 static struct clk_rcg2 usb3_phy_aux_clk_src = {
1022         .cmd_rcgr = 0x1414,
1023         .hid_width = 5,
1024         .freq_tbl = ftbl_usb3_phy_aux_clk_src,
1025         .clkr.hw.init = &(struct clk_init_data)
1026         {
1027                 .name = "usb3_phy_aux_clk_src",
1028                 .parent_names = (const char *[]) { "xo" },
1029                 .num_parents = 1,
1030                 .ops = &clk_rcg2_ops,
1031         },
1032 };
1033
1034 static struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
1035         F(75000000, P_GPLL0, 8, 0, 0),
1036         { }
1037 };
1038
1039 static struct clk_rcg2 usb_hs_system_clk_src = {
1040         .cmd_rcgr = 0x0490,
1041         .hid_width = 5,
1042         .parent_map = gcc_xo_gpll0_map,
1043         .freq_tbl = ftbl_usb_hs_system_clk_src,
1044         .clkr.hw.init = &(struct clk_init_data)
1045         {
1046                 .name = "usb_hs_system_clk_src",
1047                 .parent_names = gcc_xo_gpll0,
1048                 .num_parents = 2,
1049                 .ops = &clk_rcg2_ops,
1050         },
1051 };
1052
1053 static struct clk_branch gcc_blsp1_ahb_clk = {
1054         .halt_reg = 0x05c4,
1055         .halt_check = BRANCH_HALT_VOTED,
1056         .clkr = {
1057                 .enable_reg = 0x1484,
1058                 .enable_mask = BIT(17),
1059                 .hw.init = &(struct clk_init_data)
1060                 {
1061                         .name = "gcc_blsp1_ahb_clk",
1062                         .ops = &clk_branch2_ops,
1063                 },
1064         },
1065 };
1066
1067 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1068         .halt_reg = 0x0648,
1069         .clkr = {
1070                 .enable_reg = 0x0648,
1071                 .enable_mask = BIT(0),
1072                 .hw.init = &(struct clk_init_data)
1073                 {
1074                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
1075                         .parent_names = (const char *[]) {
1076                                 "blsp1_qup1_i2c_apps_clk_src",
1077                         },
1078                         .num_parents = 1,
1079                         .flags = CLK_SET_RATE_PARENT,
1080                         .ops = &clk_branch2_ops,
1081                 },
1082         },
1083 };
1084
1085 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1086         .halt_reg = 0x0644,
1087         .clkr = {
1088                 .enable_reg = 0x0644,
1089                 .enable_mask = BIT(0),
1090                 .hw.init = &(struct clk_init_data)
1091                 {
1092                         .name = "gcc_blsp1_qup1_spi_apps_clk",
1093                         .parent_names = (const char *[]) {
1094                                 "blsp1_qup1_spi_apps_clk_src",
1095                         },
1096                         .num_parents = 1,
1097                         .flags = CLK_SET_RATE_PARENT,
1098                         .ops = &clk_branch2_ops,
1099                 },
1100         },
1101 };
1102
1103 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1104         .halt_reg = 0x06c8,
1105         .clkr = {
1106                 .enable_reg = 0x06c8,
1107                 .enable_mask = BIT(0),
1108                 .hw.init = &(struct clk_init_data)
1109                 {
1110                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
1111                         .parent_names = (const char *[]) {
1112                                 "blsp1_qup2_i2c_apps_clk_src",
1113                         },
1114                         .num_parents = 1,
1115                         .flags = CLK_SET_RATE_PARENT,
1116                         .ops = &clk_branch2_ops,
1117                 },
1118         },
1119 };
1120
1121 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1122         .halt_reg = 0x06c4,
1123         .clkr = {
1124                 .enable_reg = 0x06c4,
1125                 .enable_mask = BIT(0),
1126                 .hw.init = &(struct clk_init_data)
1127                 {
1128                         .name = "gcc_blsp1_qup2_spi_apps_clk",
1129                         .parent_names = (const char *[]) {
1130                                 "blsp1_qup2_spi_apps_clk_src",
1131                         },
1132                         .num_parents = 1,
1133                         .flags = CLK_SET_RATE_PARENT,
1134                         .ops = &clk_branch2_ops,
1135                 },
1136         },
1137 };
1138
1139 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1140         .halt_reg = 0x0748,
1141         .clkr = {
1142                 .enable_reg = 0x0748,
1143                 .enable_mask = BIT(0),
1144                 .hw.init = &(struct clk_init_data)
1145                 {
1146                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
1147                         .parent_names = (const char *[]) {
1148                                 "blsp1_qup3_i2c_apps_clk_src",
1149                         },
1150                         .num_parents = 1,
1151                         .flags = CLK_SET_RATE_PARENT,
1152                         .ops = &clk_branch2_ops,
1153                 },
1154         },
1155 };
1156
1157 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1158         .halt_reg = 0x0744,
1159         .clkr = {
1160                 .enable_reg = 0x0744,
1161                 .enable_mask = BIT(0),
1162                 .hw.init = &(struct clk_init_data)
1163                 {
1164                         .name = "gcc_blsp1_qup3_spi_apps_clk",
1165                         .parent_names = (const char *[]) {
1166                                 "blsp1_qup3_spi_apps_clk_src",
1167                         },
1168                         .num_parents = 1,
1169                         .flags = CLK_SET_RATE_PARENT,
1170                         .ops = &clk_branch2_ops,
1171                 },
1172         },
1173 };
1174
1175 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1176         .halt_reg = 0x07c8,
1177         .clkr = {
1178                 .enable_reg = 0x07c8,
1179                 .enable_mask = BIT(0),
1180                 .hw.init = &(struct clk_init_data)
1181                 {
1182                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
1183                         .parent_names = (const char *[]) {
1184                                 "blsp1_qup4_i2c_apps_clk_src",
1185                         },
1186                         .num_parents = 1,
1187                         .flags = CLK_SET_RATE_PARENT,
1188                         .ops = &clk_branch2_ops,
1189                 },
1190         },
1191 };
1192
1193 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1194         .halt_reg = 0x07c4,
1195         .clkr = {
1196                 .enable_reg = 0x07c4,
1197                 .enable_mask = BIT(0),
1198                 .hw.init = &(struct clk_init_data)
1199                 {
1200                         .name = "gcc_blsp1_qup4_spi_apps_clk",
1201                         .parent_names = (const char *[]) {
1202                                 "blsp1_qup4_spi_apps_clk_src",
1203                         },
1204                         .num_parents = 1,
1205                         .flags = CLK_SET_RATE_PARENT,
1206                         .ops = &clk_branch2_ops,
1207                 },
1208         },
1209 };
1210
1211 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1212         .halt_reg = 0x0848,
1213         .clkr = {
1214                 .enable_reg = 0x0848,
1215                 .enable_mask = BIT(0),
1216                 .hw.init = &(struct clk_init_data)
1217                 {
1218                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
1219                         .parent_names = (const char *[]) {
1220                                 "blsp1_qup5_i2c_apps_clk_src",
1221                         },
1222                         .num_parents = 1,
1223                         .flags = CLK_SET_RATE_PARENT,
1224                         .ops = &clk_branch2_ops,
1225                 },
1226         },
1227 };
1228
1229 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1230         .halt_reg = 0x0844,
1231         .clkr = {
1232                 .enable_reg = 0x0844,
1233                 .enable_mask = BIT(0),
1234                 .hw.init = &(struct clk_init_data)
1235                 {
1236                         .name = "gcc_blsp1_qup5_spi_apps_clk",
1237                         .parent_names = (const char *[]) {
1238                                 "blsp1_qup5_spi_apps_clk_src",
1239                         },
1240                         .num_parents = 1,
1241                         .flags = CLK_SET_RATE_PARENT,
1242                         .ops = &clk_branch2_ops,
1243                 },
1244         },
1245 };
1246
1247 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1248         .halt_reg = 0x08c8,
1249         .clkr = {
1250                 .enable_reg = 0x08c8,
1251                 .enable_mask = BIT(0),
1252                 .hw.init = &(struct clk_init_data)
1253                 {
1254                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
1255                         .parent_names = (const char *[]) {
1256                                 "blsp1_qup6_i2c_apps_clk_src",
1257                         },
1258                         .num_parents = 1,
1259                         .flags = CLK_SET_RATE_PARENT,
1260                         .ops = &clk_branch2_ops,
1261                 },
1262         },
1263 };
1264
1265 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1266         .halt_reg = 0x08c4,
1267         .clkr = {
1268                 .enable_reg = 0x08c4,
1269                 .enable_mask = BIT(0),
1270                 .hw.init = &(struct clk_init_data)
1271                 {
1272                         .name = "gcc_blsp1_qup6_spi_apps_clk",
1273                         .parent_names = (const char *[]) {
1274                                 "blsp1_qup6_spi_apps_clk_src",
1275                         },
1276                         .num_parents = 1,
1277                         .flags = CLK_SET_RATE_PARENT,
1278                         .ops = &clk_branch2_ops,
1279                 },
1280         },
1281 };
1282
1283 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1284         .halt_reg = 0x0684,
1285         .clkr = {
1286                 .enable_reg = 0x0684,
1287                 .enable_mask = BIT(0),
1288                 .hw.init = &(struct clk_init_data)
1289                 {
1290                         .name = "gcc_blsp1_uart1_apps_clk",
1291                         .parent_names = (const char *[]) {
1292                                 "blsp1_uart1_apps_clk_src",
1293                         },
1294                         .num_parents = 1,
1295                         .flags = CLK_SET_RATE_PARENT,
1296                         .ops = &clk_branch2_ops,
1297                 },
1298         },
1299 };
1300
1301 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1302         .halt_reg = 0x0704,
1303         .clkr = {
1304                 .enable_reg = 0x0704,
1305                 .enable_mask = BIT(0),
1306                 .hw.init = &(struct clk_init_data)
1307                 {
1308                         .name = "gcc_blsp1_uart2_apps_clk",
1309                         .parent_names = (const char *[]) {
1310                                 "blsp1_uart2_apps_clk_src",
1311                         },
1312                         .num_parents = 1,
1313                         .flags = CLK_SET_RATE_PARENT,
1314                         .ops = &clk_branch2_ops,
1315                 },
1316         },
1317 };
1318
1319 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1320         .halt_reg = 0x0784,
1321         .clkr = {
1322                 .enable_reg = 0x0784,
1323                 .enable_mask = BIT(0),
1324                 .hw.init = &(struct clk_init_data)
1325                 {
1326                         .name = "gcc_blsp1_uart3_apps_clk",
1327                         .parent_names = (const char *[]) {
1328                                 "blsp1_uart3_apps_clk_src",
1329                         },
1330                         .num_parents = 1,
1331                         .flags = CLK_SET_RATE_PARENT,
1332                         .ops = &clk_branch2_ops,
1333                 },
1334         },
1335 };
1336
1337 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1338         .halt_reg = 0x0804,
1339         .clkr = {
1340                 .enable_reg = 0x0804,
1341                 .enable_mask = BIT(0),
1342                 .hw.init = &(struct clk_init_data)
1343                 {
1344                         .name = "gcc_blsp1_uart4_apps_clk",
1345                         .parent_names = (const char *[]) {
1346                                 "blsp1_uart4_apps_clk_src",
1347                         },
1348                         .num_parents = 1,
1349                         .flags = CLK_SET_RATE_PARENT,
1350                         .ops = &clk_branch2_ops,
1351                 },
1352         },
1353 };
1354
1355 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1356         .halt_reg = 0x0884,
1357         .clkr = {
1358                 .enable_reg = 0x0884,
1359                 .enable_mask = BIT(0),
1360                 .hw.init = &(struct clk_init_data)
1361                 {
1362                         .name = "gcc_blsp1_uart5_apps_clk",
1363                         .parent_names = (const char *[]) {
1364                                 "blsp1_uart5_apps_clk_src",
1365                         },
1366                         .num_parents = 1,
1367                         .flags = CLK_SET_RATE_PARENT,
1368                         .ops = &clk_branch2_ops,
1369                 },
1370         },
1371 };
1372
1373 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1374         .halt_reg = 0x0904,
1375         .clkr = {
1376                 .enable_reg = 0x0904,
1377                 .enable_mask = BIT(0),
1378                 .hw.init = &(struct clk_init_data)
1379                 {
1380                         .name = "gcc_blsp1_uart6_apps_clk",
1381                         .parent_names = (const char *[]) {
1382                                 "blsp1_uart6_apps_clk_src",
1383                         },
1384                         .num_parents = 1,
1385                         .flags = CLK_SET_RATE_PARENT,
1386                         .ops = &clk_branch2_ops,
1387                 },
1388         },
1389 };
1390
1391 static struct clk_branch gcc_blsp2_ahb_clk = {
1392         .halt_reg = 0x0944,
1393         .halt_check = BRANCH_HALT_VOTED,
1394         .clkr = {
1395                 .enable_reg = 0x1484,
1396                 .enable_mask = BIT(15),
1397                 .hw.init = &(struct clk_init_data)
1398                 {
1399                         .name = "gcc_blsp2_ahb_clk",
1400                         .ops = &clk_branch2_ops,
1401                 },
1402         },
1403 };
1404
1405 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1406         .halt_reg = 0x0988,
1407         .clkr = {
1408                 .enable_reg = 0x0988,
1409                 .enable_mask = BIT(0),
1410                 .hw.init = &(struct clk_init_data)
1411                 {
1412                         .name = "gcc_blsp2_qup1_i2c_apps_clk",
1413                         .parent_names = (const char *[]) {
1414                                 "blsp2_qup1_i2c_apps_clk_src",
1415                         },
1416                         .num_parents = 1,
1417                         .flags = CLK_SET_RATE_PARENT,
1418                         .ops = &clk_branch2_ops,
1419                 },
1420         },
1421 };
1422
1423 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1424         .halt_reg = 0x0984,
1425         .clkr = {
1426                 .enable_reg = 0x0984,
1427                 .enable_mask = BIT(0),
1428                 .hw.init = &(struct clk_init_data)
1429                 {
1430                         .name = "gcc_blsp2_qup1_spi_apps_clk",
1431                         .parent_names = (const char *[]) {
1432                                 "blsp2_qup1_spi_apps_clk_src",
1433                         },
1434                         .num_parents = 1,
1435                         .flags = CLK_SET_RATE_PARENT,
1436                         .ops = &clk_branch2_ops,
1437                 },
1438         },
1439 };
1440
1441 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1442         .halt_reg = 0x0a08,
1443         .clkr = {
1444                 .enable_reg = 0x0a08,
1445                 .enable_mask = BIT(0),
1446                 .hw.init = &(struct clk_init_data)
1447                 {
1448                         .name = "gcc_blsp2_qup2_i2c_apps_clk",
1449                         .parent_names = (const char *[]) {
1450                                 "blsp2_qup2_i2c_apps_clk_src",
1451                         },
1452                         .num_parents = 1,
1453                         .flags = CLK_SET_RATE_PARENT,
1454                         .ops = &clk_branch2_ops,
1455                 },
1456         },
1457 };
1458
1459 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1460         .halt_reg = 0x0a04,
1461         .clkr = {
1462                 .enable_reg = 0x0a04,
1463                 .enable_mask = BIT(0),
1464                 .hw.init = &(struct clk_init_data)
1465                 {
1466                         .name = "gcc_blsp2_qup2_spi_apps_clk",
1467                         .parent_names = (const char *[]) {
1468                                 "blsp2_qup2_spi_apps_clk_src",
1469                         },
1470                         .num_parents = 1,
1471                         .flags = CLK_SET_RATE_PARENT,
1472                         .ops = &clk_branch2_ops,
1473                 },
1474         },
1475 };
1476
1477 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1478         .halt_reg = 0x0a88,
1479         .clkr = {
1480                 .enable_reg = 0x0a88,
1481                 .enable_mask = BIT(0),
1482                 .hw.init = &(struct clk_init_data)
1483                 {
1484                         .name = "gcc_blsp2_qup3_i2c_apps_clk",
1485                         .parent_names = (const char *[]) {
1486                                 "blsp2_qup3_i2c_apps_clk_src",
1487                         },
1488                         .num_parents = 1,
1489                         .flags = CLK_SET_RATE_PARENT,
1490                         .ops = &clk_branch2_ops,
1491                 },
1492         },
1493 };
1494
1495 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1496         .halt_reg = 0x0a84,
1497         .clkr = {
1498                 .enable_reg = 0x0a84,
1499                 .enable_mask = BIT(0),
1500                 .hw.init = &(struct clk_init_data)
1501                 {
1502                         .name = "gcc_blsp2_qup3_spi_apps_clk",
1503                         .parent_names = (const char *[]) {
1504                                 "blsp2_qup3_spi_apps_clk_src",
1505                         },
1506                         .num_parents = 1,
1507                         .flags = CLK_SET_RATE_PARENT,
1508                         .ops = &clk_branch2_ops,
1509                 },
1510         },
1511 };
1512
1513 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1514         .halt_reg = 0x0b08,
1515         .clkr = {
1516                 .enable_reg = 0x0b08,
1517                 .enable_mask = BIT(0),
1518                 .hw.init = &(struct clk_init_data)
1519                 {
1520                         .name = "gcc_blsp2_qup4_i2c_apps_clk",
1521                         .parent_names = (const char *[]) {
1522                                 "blsp2_qup4_i2c_apps_clk_src",
1523                         },
1524                         .num_parents = 1,
1525                         .flags = CLK_SET_RATE_PARENT,
1526                         .ops = &clk_branch2_ops,
1527                 },
1528         },
1529 };
1530
1531 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1532         .halt_reg = 0x0b04,
1533         .clkr = {
1534                 .enable_reg = 0x0b04,
1535                 .enable_mask = BIT(0),
1536                 .hw.init = &(struct clk_init_data)
1537                 {
1538                         .name = "gcc_blsp2_qup4_spi_apps_clk",
1539                         .parent_names = (const char *[]) {
1540                                 "blsp2_qup4_spi_apps_clk_src",
1541                         },
1542                         .num_parents = 1,
1543                         .flags = CLK_SET_RATE_PARENT,
1544                         .ops = &clk_branch2_ops,
1545                 },
1546         },
1547 };
1548
1549 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1550         .halt_reg = 0x0b88,
1551         .clkr = {
1552                 .enable_reg = 0x0b88,
1553                 .enable_mask = BIT(0),
1554                 .hw.init = &(struct clk_init_data)
1555                 {
1556                         .name = "gcc_blsp2_qup5_i2c_apps_clk",
1557                         .parent_names = (const char *[]) {
1558                                 "blsp2_qup5_i2c_apps_clk_src",
1559                         },
1560                         .num_parents = 1,
1561                         .flags = CLK_SET_RATE_PARENT,
1562                         .ops = &clk_branch2_ops,
1563                 },
1564         },
1565 };
1566
1567 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1568         .halt_reg = 0x0b84,
1569         .clkr = {
1570                 .enable_reg = 0x0b84,
1571                 .enable_mask = BIT(0),
1572                 .hw.init = &(struct clk_init_data)
1573                 {
1574                         .name = "gcc_blsp2_qup5_spi_apps_clk",
1575                         .parent_names = (const char *[]) {
1576                                 "blsp2_qup5_spi_apps_clk_src",
1577                         },
1578                         .num_parents = 1,
1579                         .flags = CLK_SET_RATE_PARENT,
1580                         .ops = &clk_branch2_ops,
1581                 },
1582         },
1583 };
1584
1585 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1586         .halt_reg = 0x0c08,
1587         .clkr = {
1588                 .enable_reg = 0x0c08,
1589                 .enable_mask = BIT(0),
1590                 .hw.init = &(struct clk_init_data)
1591                 {
1592                         .name = "gcc_blsp2_qup6_i2c_apps_clk",
1593                         .parent_names = (const char *[]) {
1594                                 "blsp2_qup6_i2c_apps_clk_src",
1595                         },
1596                         .num_parents = 1,
1597                         .flags = CLK_SET_RATE_PARENT,
1598                         .ops = &clk_branch2_ops,
1599                 },
1600         },
1601 };
1602
1603 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1604         .halt_reg = 0x0c04,
1605         .clkr = {
1606                 .enable_reg = 0x0c04,
1607                 .enable_mask = BIT(0),
1608                 .hw.init = &(struct clk_init_data)
1609                 {
1610                         .name = "gcc_blsp2_qup6_spi_apps_clk",
1611                         .parent_names = (const char *[]) {
1612                                 "blsp2_qup6_spi_apps_clk_src",
1613                         },
1614                         .num_parents = 1,
1615                         .flags = CLK_SET_RATE_PARENT,
1616                         .ops = &clk_branch2_ops,
1617                 },
1618         },
1619 };
1620
1621 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1622         .halt_reg = 0x09c4,
1623         .clkr = {
1624                 .enable_reg = 0x09c4,
1625                 .enable_mask = BIT(0),
1626                 .hw.init = &(struct clk_init_data)
1627                 {
1628                         .name = "gcc_blsp2_uart1_apps_clk",
1629                         .parent_names = (const char *[]) {
1630                                 "blsp2_uart1_apps_clk_src",
1631                         },
1632                         .num_parents = 1,
1633                         .flags = CLK_SET_RATE_PARENT,
1634                         .ops = &clk_branch2_ops,
1635                 },
1636         },
1637 };
1638
1639 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1640         .halt_reg = 0x0a44,
1641         .clkr = {
1642                 .enable_reg = 0x0a44,
1643                 .enable_mask = BIT(0),
1644                 .hw.init = &(struct clk_init_data)
1645                 {
1646                         .name = "gcc_blsp2_uart2_apps_clk",
1647                         .parent_names = (const char *[]) {
1648                                 "blsp2_uart2_apps_clk_src",
1649                         },
1650                         .num_parents = 1,
1651                         .flags = CLK_SET_RATE_PARENT,
1652                         .ops = &clk_branch2_ops,
1653                 },
1654         },
1655 };
1656
1657 static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1658         .halt_reg = 0x0ac4,
1659         .clkr = {
1660                 .enable_reg = 0x0ac4,
1661                 .enable_mask = BIT(0),
1662                 .hw.init = &(struct clk_init_data)
1663                 {
1664                         .name = "gcc_blsp2_uart3_apps_clk",
1665                         .parent_names = (const char *[]) {
1666                                 "blsp2_uart3_apps_clk_src",
1667                         },
1668                         .num_parents = 1,
1669                         .flags = CLK_SET_RATE_PARENT,
1670                         .ops = &clk_branch2_ops,
1671                 },
1672         },
1673 };
1674
1675 static struct clk_branch gcc_blsp2_uart4_apps_clk = {
1676         .halt_reg = 0x0b44,
1677         .clkr = {
1678                 .enable_reg = 0x0b44,
1679                 .enable_mask = BIT(0),
1680                 .hw.init = &(struct clk_init_data)
1681                 {
1682                         .name = "gcc_blsp2_uart4_apps_clk",
1683                         .parent_names = (const char *[]) {
1684                                 "blsp2_uart4_apps_clk_src",
1685                         },
1686                         .num_parents = 1,
1687                         .flags = CLK_SET_RATE_PARENT,
1688                         .ops = &clk_branch2_ops,
1689                 },
1690         },
1691 };
1692
1693 static struct clk_branch gcc_blsp2_uart5_apps_clk = {
1694         .halt_reg = 0x0bc4,
1695         .clkr = {
1696                 .enable_reg = 0x0bc4,
1697                 .enable_mask = BIT(0),
1698                 .hw.init = &(struct clk_init_data)
1699                 {
1700                         .name = "gcc_blsp2_uart5_apps_clk",
1701                         .parent_names = (const char *[]) {
1702                                 "blsp2_uart5_apps_clk_src",
1703                         },
1704                         .num_parents = 1,
1705                         .flags = CLK_SET_RATE_PARENT,
1706                         .ops = &clk_branch2_ops,
1707                 },
1708         },
1709 };
1710
1711 static struct clk_branch gcc_blsp2_uart6_apps_clk = {
1712         .halt_reg = 0x0c44,
1713         .clkr = {
1714                 .enable_reg = 0x0c44,
1715                 .enable_mask = BIT(0),
1716                 .hw.init = &(struct clk_init_data)
1717                 {
1718                         .name = "gcc_blsp2_uart6_apps_clk",
1719                         .parent_names = (const char *[]) {
1720                                 "blsp2_uart6_apps_clk_src",
1721                         },
1722                         .num_parents = 1,
1723                         .flags = CLK_SET_RATE_PARENT,
1724                         .ops = &clk_branch2_ops,
1725                 },
1726         },
1727 };
1728
1729 static struct clk_branch gcc_gp1_clk = {
1730         .halt_reg = 0x1900,
1731         .clkr = {
1732                 .enable_reg = 0x1900,
1733                 .enable_mask = BIT(0),
1734                 .hw.init = &(struct clk_init_data)
1735                 {
1736                         .name = "gcc_gp1_clk",
1737                         .parent_names = (const char *[]) {
1738                                 "gp1_clk_src",
1739                         },
1740                         .num_parents = 1,
1741                         .flags = CLK_SET_RATE_PARENT,
1742                         .ops = &clk_branch2_ops,
1743                 },
1744         },
1745 };
1746
1747 static struct clk_branch gcc_gp2_clk = {
1748         .halt_reg = 0x1940,
1749         .clkr = {
1750                 .enable_reg = 0x1940,
1751                 .enable_mask = BIT(0),
1752                 .hw.init = &(struct clk_init_data)
1753                 {
1754                         .name = "gcc_gp2_clk",
1755                         .parent_names = (const char *[]) {
1756                                 "gp2_clk_src",
1757                         },
1758                         .num_parents = 1,
1759                         .flags = CLK_SET_RATE_PARENT,
1760                         .ops = &clk_branch2_ops,
1761                 },
1762         },
1763 };
1764
1765 static struct clk_branch gcc_gp3_clk = {
1766         .halt_reg = 0x1980,
1767         .clkr = {
1768                 .enable_reg = 0x1980,
1769                 .enable_mask = BIT(0),
1770                 .hw.init = &(struct clk_init_data)
1771                 {
1772                         .name = "gcc_gp3_clk",
1773                         .parent_names = (const char *[]) {
1774                                 "gp3_clk_src",
1775                         },
1776                         .num_parents = 1,
1777                         .flags = CLK_SET_RATE_PARENT,
1778                         .ops = &clk_branch2_ops,
1779                 },
1780         },
1781 };
1782
1783 static struct clk_branch gcc_pcie_0_aux_clk = {
1784         .halt_reg = 0x1ad4,
1785         .clkr = {
1786                 .enable_reg = 0x1ad4,
1787                 .enable_mask = BIT(0),
1788                 .hw.init = &(struct clk_init_data)
1789                 {
1790                         .name = "gcc_pcie_0_aux_clk",
1791                         .parent_names = (const char *[]) {
1792                                 "pcie_0_aux_clk_src",
1793                         },
1794                         .num_parents = 1,
1795                         .flags = CLK_SET_RATE_PARENT,
1796                         .ops = &clk_branch2_ops,
1797                 },
1798         },
1799 };
1800
1801 static struct clk_branch gcc_pcie_0_pipe_clk = {
1802         .halt_reg = 0x1ad8,
1803         .halt_check = BRANCH_HALT_DELAY,
1804         .clkr = {
1805                 .enable_reg = 0x1ad8,
1806                 .enable_mask = BIT(0),
1807                 .hw.init = &(struct clk_init_data)
1808                 {
1809                         .name = "gcc_pcie_0_pipe_clk",
1810                         .parent_names = (const char *[]) {
1811                                 "pcie_0_pipe_clk_src",
1812                         },
1813                         .num_parents = 1,
1814                         .flags = CLK_SET_RATE_PARENT,
1815                         .ops = &clk_branch2_ops,
1816                 },
1817         },
1818 };
1819
1820 static struct clk_branch gcc_pcie_1_aux_clk = {
1821         .halt_reg = 0x1b54,
1822         .clkr = {
1823                 .enable_reg = 0x1b54,
1824                 .enable_mask = BIT(0),
1825                 .hw.init = &(struct clk_init_data)
1826                 {
1827                         .name = "gcc_pcie_1_aux_clk",
1828                         .parent_names = (const char *[]) {
1829                                 "pcie_1_aux_clk_src",
1830                         },
1831                         .num_parents = 1,
1832                         .flags = CLK_SET_RATE_PARENT,
1833                         .ops = &clk_branch2_ops,
1834                 },
1835         },
1836 };
1837
1838 static struct clk_branch gcc_pcie_1_pipe_clk = {
1839         .halt_reg = 0x1b58,
1840         .halt_check = BRANCH_HALT_DELAY,
1841         .clkr = {
1842                 .enable_reg = 0x1b58,
1843                 .enable_mask = BIT(0),
1844                 .hw.init = &(struct clk_init_data)
1845                 {
1846                         .name = "gcc_pcie_1_pipe_clk",
1847                         .parent_names = (const char *[]) {
1848                                 "pcie_1_pipe_clk_src",
1849                         },
1850                         .num_parents = 1,
1851                         .flags = CLK_SET_RATE_PARENT,
1852                         .ops = &clk_branch2_ops,
1853                 },
1854         },
1855 };
1856
1857 static struct clk_branch gcc_pdm2_clk = {
1858         .halt_reg = 0x0ccc,
1859         .clkr = {
1860                 .enable_reg = 0x0ccc,
1861                 .enable_mask = BIT(0),
1862                 .hw.init = &(struct clk_init_data)
1863                 {
1864                         .name = "gcc_pdm2_clk",
1865                         .parent_names = (const char *[]) {
1866                                 "pdm2_clk_src",
1867                         },
1868                         .num_parents = 1,
1869                         .flags = CLK_SET_RATE_PARENT,
1870                         .ops = &clk_branch2_ops,
1871                 },
1872         },
1873 };
1874
1875 static struct clk_branch gcc_sdcc1_apps_clk = {
1876         .halt_reg = 0x04c4,
1877         .clkr = {
1878                 .enable_reg = 0x04c4,
1879                 .enable_mask = BIT(0),
1880                 .hw.init = &(struct clk_init_data)
1881                 {
1882                         .name = "gcc_sdcc1_apps_clk",
1883                         .parent_names = (const char *[]) {
1884                                 "sdcc1_apps_clk_src",
1885                         },
1886                         .num_parents = 1,
1887                         .flags = CLK_SET_RATE_PARENT,
1888                         .ops = &clk_branch2_ops,
1889                 },
1890         },
1891 };
1892
1893 static struct clk_branch gcc_sdcc1_ahb_clk = {
1894         .halt_reg = 0x04c8,
1895         .clkr = {
1896                 .enable_reg = 0x04c8,
1897                 .enable_mask = BIT(0),
1898                 .hw.init = &(struct clk_init_data)
1899                 {
1900                         .name = "gcc_sdcc1_ahb_clk",
1901                         .parent_names = (const char *[]){
1902                                 "periph_noc_clk_src",
1903                         },
1904                         .num_parents = 1,
1905                         .ops = &clk_branch2_ops,
1906                 },
1907         },
1908 };
1909
1910 static struct clk_branch gcc_sdcc2_apps_clk = {
1911         .halt_reg = 0x0504,
1912         .clkr = {
1913                 .enable_reg = 0x0504,
1914                 .enable_mask = BIT(0),
1915                 .hw.init = &(struct clk_init_data)
1916                 {
1917                         .name = "gcc_sdcc2_apps_clk",
1918                         .parent_names = (const char *[]) {
1919                                 "sdcc2_apps_clk_src",
1920                         },
1921                         .num_parents = 1,
1922                         .flags = CLK_SET_RATE_PARENT,
1923                         .ops = &clk_branch2_ops,
1924                 },
1925         },
1926 };
1927
1928 static struct clk_branch gcc_sdcc3_apps_clk = {
1929         .halt_reg = 0x0544,
1930         .clkr = {
1931                 .enable_reg = 0x0544,
1932                 .enable_mask = BIT(0),
1933                 .hw.init = &(struct clk_init_data)
1934                 {
1935                         .name = "gcc_sdcc3_apps_clk",
1936                         .parent_names = (const char *[]) {
1937                                 "sdcc3_apps_clk_src",
1938                         },
1939                         .num_parents = 1,
1940                         .flags = CLK_SET_RATE_PARENT,
1941                         .ops = &clk_branch2_ops,
1942                 },
1943         },
1944 };
1945
1946 static struct clk_branch gcc_sdcc4_apps_clk = {
1947         .halt_reg = 0x0584,
1948         .clkr = {
1949                 .enable_reg = 0x0584,
1950                 .enable_mask = BIT(0),
1951                 .hw.init = &(struct clk_init_data)
1952                 {
1953                         .name = "gcc_sdcc4_apps_clk",
1954                         .parent_names = (const char *[]) {
1955                                 "sdcc4_apps_clk_src",
1956                         },
1957                         .num_parents = 1,
1958                         .flags = CLK_SET_RATE_PARENT,
1959                         .ops = &clk_branch2_ops,
1960                 },
1961         },
1962 };
1963
1964 static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
1965         .halt_reg = 0x1d7c,
1966         .clkr = {
1967                 .enable_reg = 0x1d7c,
1968                 .enable_mask = BIT(0),
1969                 .hw.init = &(struct clk_init_data)
1970                 {
1971                         .name = "gcc_sys_noc_ufs_axi_clk",
1972                         .parent_names = (const char *[]) {
1973                                 "ufs_axi_clk_src",
1974                         },
1975                         .num_parents = 1,
1976                         .flags = CLK_SET_RATE_PARENT,
1977                         .ops = &clk_branch2_ops,
1978                 },
1979         },
1980 };
1981
1982 static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
1983         .halt_reg = 0x03fc,
1984         .clkr = {
1985                 .enable_reg = 0x03fc,
1986                 .enable_mask = BIT(0),
1987                 .hw.init = &(struct clk_init_data)
1988                 {
1989                         .name = "gcc_sys_noc_usb3_axi_clk",
1990                         .parent_names = (const char *[]) {
1991                                 "usb30_master_clk_src",
1992                         },
1993                         .num_parents = 1,
1994                         .flags = CLK_SET_RATE_PARENT,
1995                         .ops = &clk_branch2_ops,
1996                 },
1997         },
1998 };
1999
2000 static struct clk_branch gcc_tsif_ref_clk = {
2001         .halt_reg = 0x0d88,
2002         .clkr = {
2003                 .enable_reg = 0x0d88,
2004                 .enable_mask = BIT(0),
2005                 .hw.init = &(struct clk_init_data)
2006                 {
2007                         .name = "gcc_tsif_ref_clk",
2008                         .parent_names = (const char *[]) {
2009                                 "tsif_ref_clk_src",
2010                         },
2011                         .num_parents = 1,
2012                         .flags = CLK_SET_RATE_PARENT,
2013                         .ops = &clk_branch2_ops,
2014                 },
2015         },
2016 };
2017
2018 static struct clk_branch gcc_ufs_axi_clk = {
2019         .halt_reg = 0x1d48,
2020         .clkr = {
2021                 .enable_reg = 0x1d48,
2022                 .enable_mask = BIT(0),
2023                 .hw.init = &(struct clk_init_data)
2024                 {
2025                         .name = "gcc_ufs_axi_clk",
2026                         .parent_names = (const char *[]) {
2027                                 "ufs_axi_clk_src",
2028                         },
2029                         .num_parents = 1,
2030                         .flags = CLK_SET_RATE_PARENT,
2031                         .ops = &clk_branch2_ops,
2032                 },
2033         },
2034 };
2035
2036 static struct clk_branch gcc_ufs_rx_cfg_clk = {
2037         .halt_reg = 0x1d54,
2038         .clkr = {
2039                 .enable_reg = 0x1d54,
2040                 .enable_mask = BIT(0),
2041                 .hw.init = &(struct clk_init_data)
2042                 {
2043                         .name = "gcc_ufs_rx_cfg_clk",
2044                         .parent_names = (const char *[]) {
2045                                 "ufs_axi_clk_src",
2046                         },
2047                         .num_parents = 1,
2048                         .flags = CLK_SET_RATE_PARENT,
2049                         .ops = &clk_branch2_ops,
2050                 },
2051         },
2052 };
2053
2054 static struct clk_branch gcc_ufs_tx_cfg_clk = {
2055         .halt_reg = 0x1d50,
2056         .clkr = {
2057                 .enable_reg = 0x1d50,
2058                 .enable_mask = BIT(0),
2059                 .hw.init = &(struct clk_init_data)
2060                 {
2061                         .name = "gcc_ufs_tx_cfg_clk",
2062                         .parent_names = (const char *[]) {
2063                                 "ufs_axi_clk_src",
2064                         },
2065                         .num_parents = 1,
2066                         .flags = CLK_SET_RATE_PARENT,
2067                         .ops = &clk_branch2_ops,
2068                 },
2069         },
2070 };
2071
2072 static struct clk_branch gcc_usb30_master_clk = {
2073         .halt_reg = 0x03c8,
2074         .clkr = {
2075                 .enable_reg = 0x03c8,
2076                 .enable_mask = BIT(0),
2077                 .hw.init = &(struct clk_init_data)
2078                 {
2079                         .name = "gcc_usb30_master_clk",
2080                         .parent_names = (const char *[]) {
2081                                 "usb30_master_clk_src",
2082                         },
2083                         .num_parents = 1,
2084                         .flags = CLK_SET_RATE_PARENT,
2085                         .ops = &clk_branch2_ops,
2086                 },
2087         },
2088 };
2089
2090 static struct clk_branch gcc_usb30_mock_utmi_clk = {
2091         .halt_reg = 0x03d0,
2092         .clkr = {
2093                 .enable_reg = 0x03d0,
2094                 .enable_mask = BIT(0),
2095                 .hw.init = &(struct clk_init_data)
2096                 {
2097                         .name = "gcc_usb30_mock_utmi_clk",
2098                         .parent_names = (const char *[]) {
2099                                 "usb30_mock_utmi_clk_src",
2100                         },
2101                         .num_parents = 1,
2102                         .flags = CLK_SET_RATE_PARENT,
2103                         .ops = &clk_branch2_ops,
2104                 },
2105         },
2106 };
2107
2108 static struct clk_branch gcc_usb3_phy_aux_clk = {
2109         .halt_reg = 0x1408,
2110         .clkr = {
2111                 .enable_reg = 0x1408,
2112                 .enable_mask = BIT(0),
2113                 .hw.init = &(struct clk_init_data)
2114                 {
2115                         .name = "gcc_usb3_phy_aux_clk",
2116                         .parent_names = (const char *[]) {
2117                                 "usb3_phy_aux_clk_src",
2118                         },
2119                         .num_parents = 1,
2120                         .flags = CLK_SET_RATE_PARENT,
2121                         .ops = &clk_branch2_ops,
2122                 },
2123         },
2124 };
2125
2126 static struct clk_branch gcc_usb_hs_system_clk = {
2127         .halt_reg = 0x0484,
2128         .clkr = {
2129                 .enable_reg = 0x0484,
2130                 .enable_mask = BIT(0),
2131                 .hw.init = &(struct clk_init_data)
2132                 {
2133                         .name = "gcc_usb_hs_system_clk",
2134                         .parent_names = (const char *[]) {
2135                                 "usb_hs_system_clk_src",
2136                         },
2137                         .num_parents = 1,
2138                         .flags = CLK_SET_RATE_PARENT,
2139                         .ops = &clk_branch2_ops,
2140                 },
2141         },
2142 };
2143
2144 static struct clk_regmap *gcc_msm8994_clocks[] = {
2145         [GPLL0_EARLY] = &gpll0_early.clkr,
2146         [GPLL0] = &gpll0.clkr,
2147         [GPLL4_EARLY] = &gpll4_early.clkr,
2148         [GPLL4] = &gpll4.clkr,
2149         [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
2150         [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2151         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2152         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2153         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2154         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2155         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2156         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2157         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2158         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2159         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2160         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2161         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2162         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2163         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2164         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2165         [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2166         [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
2167         [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
2168         [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
2169         [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2170         [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2171         [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2172         [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2173         [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2174         [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2175         [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2176         [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2177         [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
2178         [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
2179         [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
2180         [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
2181         [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2182         [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2183         [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
2184         [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
2185         [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
2186         [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
2187         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2188         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2189         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2190         [PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
2191         [PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
2192         [PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr,
2193         [PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr,
2194         [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2195         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2196         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2197         [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
2198         [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
2199         [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
2200         [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2201         [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2202         [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2203         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2204         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2205         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2206         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2207         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2208         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2209         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2210         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2211         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2212         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2213         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2214         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2215         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2216         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2217         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2218         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2219         [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
2220         [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
2221         [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
2222         [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2223         [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2224         [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2225         [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2226         [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2227         [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2228         [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2229         [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2230         [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2231         [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
2232         [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
2233         [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
2234         [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
2235         [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2236         [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2237         [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
2238         [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
2239         [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
2240         [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
2241         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2242         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2243         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2244         [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2245         [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2246         [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
2247         [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
2248         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2249         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2250         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2251         [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
2252         [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
2253         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2254         [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
2255         [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
2256         [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
2257         [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
2258         [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
2259         [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
2260         [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2261         [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2262         [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2263         [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2264 };
2265
2266 static const struct regmap_config gcc_msm8994_regmap_config = {
2267         .reg_bits       = 32,
2268         .reg_stride     = 4,
2269         .val_bits       = 32,
2270         .max_register   = 0x2000,
2271         .fast_io        = true,
2272 };
2273
2274 static const struct qcom_cc_desc gcc_msm8994_desc = {
2275         .config = &gcc_msm8994_regmap_config,
2276         .clks = gcc_msm8994_clocks,
2277         .num_clks = ARRAY_SIZE(gcc_msm8994_clocks),
2278 };
2279
2280 static const struct of_device_id gcc_msm8994_match_table[] = {
2281         { .compatible = "qcom,gcc-msm8994" },
2282         {}
2283 };
2284 MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table);
2285
2286 static int gcc_msm8994_probe(struct platform_device *pdev)
2287 {
2288         struct device *dev = &pdev->dev;
2289         struct clk *clk;
2290
2291         clk = devm_clk_register(dev, &xo.hw);
2292         if (IS_ERR(clk))
2293                 return PTR_ERR(clk);
2294
2295         return qcom_cc_probe(pdev, &gcc_msm8994_desc);
2296 }
2297
2298 static struct platform_driver gcc_msm8994_driver = {
2299         .probe          = gcc_msm8994_probe,
2300         .driver         = {
2301                 .name   = "gcc-msm8994",
2302                 .of_match_table = gcc_msm8994_match_table,
2303         },
2304 };
2305
2306 static int __init gcc_msm8994_init(void)
2307 {
2308         return platform_driver_register(&gcc_msm8994_driver);
2309 }
2310 core_initcall(gcc_msm8994_init);
2311
2312 static void __exit gcc_msm8994_exit(void)
2313 {
2314         platform_driver_unregister(&gcc_msm8994_driver);
2315 }
2316 module_exit(gcc_msm8994_exit);
2317
2318 MODULE_DESCRIPTION("Qualcomm GCC MSM8994 Driver");
2319 MODULE_LICENSE("GPL v2");
2320 MODULE_ALIAS("platform:gcc-msm8994");