1 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/err.h>
16 #include <linux/ctype.h>
19 #include <linux/platform_device.h>
20 #include <linux/module.h>
21 #include <linux/regmap.h>
23 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
26 #include "clk-regmap.h"
27 #include "clk-alpha-pll.h"
29 #include "clk-branch.h"
38 static const struct parent_map gcc_xo_gpll0_map[] = {
43 static const char * const gcc_xo_gpll0[] = {
48 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
54 static const char * const gcc_xo_gpll0_gpll4[] = {
60 static struct clk_fixed_factor xo = {
63 .hw.init = &(struct clk_init_data)
66 .parent_names = (const char *[]) { "xo_board" },
68 .ops = &clk_fixed_factor_ops,
72 static struct clk_alpha_pll gpll0_early = {
74 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
77 .enable_mask = BIT(0),
78 .hw.init = &(struct clk_init_data)
80 .name = "gpll0_early",
81 .parent_names = (const char *[]) { "xo" },
83 .ops = &clk_alpha_pll_ops,
88 static struct clk_alpha_pll_postdiv gpll0 = {
90 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
91 .clkr.hw.init = &(struct clk_init_data)
94 .parent_names = (const char *[]) { "gpll0_early" },
96 .ops = &clk_alpha_pll_postdiv_ops,
100 static struct clk_alpha_pll gpll4_early = {
102 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
104 .enable_reg = 0x1480,
105 .enable_mask = BIT(4),
106 .hw.init = &(struct clk_init_data)
108 .name = "gpll4_early",
109 .parent_names = (const char *[]) { "xo" },
111 .ops = &clk_alpha_pll_ops,
116 static struct clk_alpha_pll_postdiv gpll4 = {
118 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
119 .clkr.hw.init = &(struct clk_init_data)
122 .parent_names = (const char *[]) { "gpll4_early" },
124 .ops = &clk_alpha_pll_postdiv_ops,
128 static struct freq_tbl ftbl_ufs_axi_clk_src[] = {
129 F(50000000, P_GPLL0, 12, 0, 0),
130 F(100000000, P_GPLL0, 6, 0, 0),
131 F(150000000, P_GPLL0, 4, 0, 0),
132 F(171430000, P_GPLL0, 3.5, 0, 0),
133 F(200000000, P_GPLL0, 3, 0, 0),
134 F(240000000, P_GPLL0, 2.5, 0, 0),
138 static struct clk_rcg2 ufs_axi_clk_src = {
142 .parent_map = gcc_xo_gpll0_map,
143 .freq_tbl = ftbl_ufs_axi_clk_src,
144 .clkr.hw.init = &(struct clk_init_data)
146 .name = "ufs_axi_clk_src",
147 .parent_names = gcc_xo_gpll0,
149 .ops = &clk_rcg2_ops,
153 static struct freq_tbl ftbl_usb30_master_clk_src[] = {
154 F(19200000, P_XO, 1, 0, 0),
155 F(125000000, P_GPLL0, 1, 5, 24),
159 static struct clk_rcg2 usb30_master_clk_src = {
163 .parent_map = gcc_xo_gpll0_map,
164 .freq_tbl = ftbl_usb30_master_clk_src,
165 .clkr.hw.init = &(struct clk_init_data)
167 .name = "usb30_master_clk_src",
168 .parent_names = gcc_xo_gpll0,
170 .ops = &clk_rcg2_ops,
174 static struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
175 F(19200000, P_XO, 1, 0, 0),
176 F(50000000, P_GPLL0, 12, 0, 0),
180 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
183 .parent_map = gcc_xo_gpll0_map,
184 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
185 .clkr.hw.init = &(struct clk_init_data)
187 .name = "blsp1_qup1_i2c_apps_clk_src",
188 .parent_names = gcc_xo_gpll0,
190 .ops = &clk_rcg2_ops,
194 static struct freq_tbl ftbl_blspqup_spi_apps_clk_src[] = {
195 F(960000, P_XO, 10, 1, 2),
196 F(4800000, P_XO, 4, 0, 0),
197 F(9600000, P_XO, 2, 0, 0),
198 F(15000000, P_GPLL0, 10, 1, 4),
199 F(19200000, P_XO, 1, 0, 0),
200 F(24000000, P_GPLL0, 12.5, 1, 2),
201 F(25000000, P_GPLL0, 12, 1, 2),
202 F(48000000, P_GPLL0, 12.5, 0, 0),
203 F(50000000, P_GPLL0, 12, 0, 0),
207 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
211 .parent_map = gcc_xo_gpll0_map,
212 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
213 .clkr.hw.init = &(struct clk_init_data)
215 .name = "blsp1_qup1_spi_apps_clk_src",
216 .parent_names = gcc_xo_gpll0,
218 .ops = &clk_rcg2_ops,
222 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
225 .parent_map = gcc_xo_gpll0_map,
226 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
227 .clkr.hw.init = &(struct clk_init_data)
229 .name = "blsp1_qup2_i2c_apps_clk_src",
230 .parent_names = gcc_xo_gpll0,
232 .ops = &clk_rcg2_ops,
236 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
240 .parent_map = gcc_xo_gpll0_map,
241 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
242 .clkr.hw.init = &(struct clk_init_data)
244 .name = "blsp1_qup2_spi_apps_clk_src",
245 .parent_names = gcc_xo_gpll0,
247 .ops = &clk_rcg2_ops,
251 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
254 .parent_map = gcc_xo_gpll0_map,
255 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
256 .clkr.hw.init = &(struct clk_init_data)
258 .name = "blsp1_qup3_i2c_apps_clk_src",
259 .parent_names = gcc_xo_gpll0,
261 .ops = &clk_rcg2_ops,
265 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
269 .parent_map = gcc_xo_gpll0_map,
270 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
271 .clkr.hw.init = &(struct clk_init_data)
273 .name = "blsp1_qup3_spi_apps_clk_src",
274 .parent_names = gcc_xo_gpll0,
276 .ops = &clk_rcg2_ops,
280 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
283 .parent_map = gcc_xo_gpll0_map,
284 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
285 .clkr.hw.init = &(struct clk_init_data)
287 .name = "blsp1_qup4_i2c_apps_clk_src",
288 .parent_names = gcc_xo_gpll0,
290 .ops = &clk_rcg2_ops,
294 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
298 .parent_map = gcc_xo_gpll0_map,
299 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
300 .clkr.hw.init = &(struct clk_init_data)
302 .name = "blsp1_qup4_spi_apps_clk_src",
303 .parent_names = gcc_xo_gpll0,
305 .ops = &clk_rcg2_ops,
309 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
312 .parent_map = gcc_xo_gpll0_map,
313 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
314 .clkr.hw.init = &(struct clk_init_data)
316 .name = "blsp1_qup5_i2c_apps_clk_src",
317 .parent_names = gcc_xo_gpll0,
319 .ops = &clk_rcg2_ops,
323 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
327 .parent_map = gcc_xo_gpll0_map,
328 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
329 .clkr.hw.init = &(struct clk_init_data)
331 .name = "blsp1_qup5_spi_apps_clk_src",
332 .parent_names = gcc_xo_gpll0,
334 .ops = &clk_rcg2_ops,
338 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
341 .parent_map = gcc_xo_gpll0_map,
342 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
343 .clkr.hw.init = &(struct clk_init_data)
345 .name = "blsp1_qup6_i2c_apps_clk_src",
346 .parent_names = gcc_xo_gpll0,
348 .ops = &clk_rcg2_ops,
352 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
356 .parent_map = gcc_xo_gpll0_map,
357 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
358 .clkr.hw.init = &(struct clk_init_data)
360 .name = "blsp1_qup6_spi_apps_clk_src",
361 .parent_names = gcc_xo_gpll0,
363 .ops = &clk_rcg2_ops,
367 static struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
368 F(3686400, P_GPLL0, 1, 96, 15625),
369 F(7372800, P_GPLL0, 1, 192, 15625),
370 F(14745600, P_GPLL0, 1, 384, 15625),
371 F(16000000, P_GPLL0, 5, 2, 15),
372 F(19200000, P_XO, 1, 0, 0),
373 F(24000000, P_GPLL0, 5, 1, 5),
374 F(32000000, P_GPLL0, 1, 4, 75),
375 F(40000000, P_GPLL0, 15, 0, 0),
376 F(46400000, P_GPLL0, 1, 29, 375),
377 F(48000000, P_GPLL0, 12.5, 0, 0),
378 F(51200000, P_GPLL0, 1, 32, 375),
379 F(56000000, P_GPLL0, 1, 7, 75),
380 F(58982400, P_GPLL0, 1, 1536, 15625),
381 F(60000000, P_GPLL0, 10, 0, 0),
382 F(63160000, P_GPLL0, 9.5, 0, 0),
386 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
390 .parent_map = gcc_xo_gpll0_map,
391 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
392 .clkr.hw.init = &(struct clk_init_data)
394 .name = "blsp1_uart1_apps_clk_src",
395 .parent_names = gcc_xo_gpll0,
397 .ops = &clk_rcg2_ops,
401 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
405 .parent_map = gcc_xo_gpll0_map,
406 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
407 .clkr.hw.init = &(struct clk_init_data)
409 .name = "blsp1_uart2_apps_clk_src",
410 .parent_names = gcc_xo_gpll0,
412 .ops = &clk_rcg2_ops,
416 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
420 .parent_map = gcc_xo_gpll0_map,
421 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
422 .clkr.hw.init = &(struct clk_init_data)
424 .name = "blsp1_uart3_apps_clk_src",
425 .parent_names = gcc_xo_gpll0,
427 .ops = &clk_rcg2_ops,
431 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
435 .parent_map = gcc_xo_gpll0_map,
436 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
437 .clkr.hw.init = &(struct clk_init_data)
439 .name = "blsp1_uart4_apps_clk_src",
440 .parent_names = gcc_xo_gpll0,
442 .ops = &clk_rcg2_ops,
446 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
450 .parent_map = gcc_xo_gpll0_map,
451 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
452 .clkr.hw.init = &(struct clk_init_data)
454 .name = "blsp1_uart5_apps_clk_src",
455 .parent_names = gcc_xo_gpll0,
457 .ops = &clk_rcg2_ops,
461 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
465 .parent_map = gcc_xo_gpll0_map,
466 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
467 .clkr.hw.init = &(struct clk_init_data)
469 .name = "blsp1_uart6_apps_clk_src",
470 .parent_names = gcc_xo_gpll0,
472 .ops = &clk_rcg2_ops,
476 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
479 .parent_map = gcc_xo_gpll0_map,
480 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
481 .clkr.hw.init = &(struct clk_init_data)
483 .name = "blsp2_qup1_i2c_apps_clk_src",
484 .parent_names = gcc_xo_gpll0,
486 .ops = &clk_rcg2_ops,
490 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
494 .parent_map = gcc_xo_gpll0_map,
495 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
496 .clkr.hw.init = &(struct clk_init_data)
498 .name = "blsp2_qup1_spi_apps_clk_src",
499 .parent_names = gcc_xo_gpll0,
501 .ops = &clk_rcg2_ops,
505 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
508 .parent_map = gcc_xo_gpll0_map,
509 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
510 .clkr.hw.init = &(struct clk_init_data)
512 .name = "blsp2_qup2_i2c_apps_clk_src",
513 .parent_names = gcc_xo_gpll0,
515 .ops = &clk_rcg2_ops,
519 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
523 .parent_map = gcc_xo_gpll0_map,
524 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
525 .clkr.hw.init = &(struct clk_init_data)
527 .name = "blsp2_qup2_spi_apps_clk_src",
528 .parent_names = gcc_xo_gpll0,
530 .ops = &clk_rcg2_ops,
534 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
537 .parent_map = gcc_xo_gpll0_map,
538 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
539 .clkr.hw.init = &(struct clk_init_data)
541 .name = "blsp2_qup3_i2c_apps_clk_src",
542 .parent_names = gcc_xo_gpll0,
544 .ops = &clk_rcg2_ops,
548 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
552 .parent_map = gcc_xo_gpll0_map,
553 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
554 .clkr.hw.init = &(struct clk_init_data)
556 .name = "blsp2_qup3_spi_apps_clk_src",
557 .parent_names = gcc_xo_gpll0,
559 .ops = &clk_rcg2_ops,
563 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
566 .parent_map = gcc_xo_gpll0_map,
567 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
568 .clkr.hw.init = &(struct clk_init_data)
570 .name = "blsp2_qup4_i2c_apps_clk_src",
571 .parent_names = gcc_xo_gpll0,
573 .ops = &clk_rcg2_ops,
577 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
581 .parent_map = gcc_xo_gpll0_map,
582 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
583 .clkr.hw.init = &(struct clk_init_data)
585 .name = "blsp2_qup4_spi_apps_clk_src",
586 .parent_names = gcc_xo_gpll0,
588 .ops = &clk_rcg2_ops,
592 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
595 .parent_map = gcc_xo_gpll0_map,
596 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
597 .clkr.hw.init = &(struct clk_init_data)
599 .name = "blsp2_qup5_i2c_apps_clk_src",
600 .parent_names = gcc_xo_gpll0,
602 .ops = &clk_rcg2_ops,
606 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
610 .parent_map = gcc_xo_gpll0_map,
611 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
612 .clkr.hw.init = &(struct clk_init_data)
614 .name = "blsp2_qup5_spi_apps_clk_src",
615 .parent_names = gcc_xo_gpll0,
617 .ops = &clk_rcg2_ops,
621 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
624 .parent_map = gcc_xo_gpll0_map,
625 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
626 .clkr.hw.init = &(struct clk_init_data)
628 .name = "blsp2_qup6_i2c_apps_clk_src",
629 .parent_names = gcc_xo_gpll0,
631 .ops = &clk_rcg2_ops,
635 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
639 .parent_map = gcc_xo_gpll0_map,
640 .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
641 .clkr.hw.init = &(struct clk_init_data)
643 .name = "blsp2_qup6_spi_apps_clk_src",
644 .parent_names = gcc_xo_gpll0,
646 .ops = &clk_rcg2_ops,
650 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
654 .parent_map = gcc_xo_gpll0_map,
655 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
656 .clkr.hw.init = &(struct clk_init_data)
658 .name = "blsp2_uart1_apps_clk_src",
659 .parent_names = gcc_xo_gpll0,
661 .ops = &clk_rcg2_ops,
665 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
669 .parent_map = gcc_xo_gpll0_map,
670 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
671 .clkr.hw.init = &(struct clk_init_data)
673 .name = "blsp2_uart2_apps_clk_src",
674 .parent_names = gcc_xo_gpll0,
676 .ops = &clk_rcg2_ops,
680 static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
684 .parent_map = gcc_xo_gpll0_map,
685 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
686 .clkr.hw.init = &(struct clk_init_data)
688 .name = "blsp2_uart3_apps_clk_src",
689 .parent_names = gcc_xo_gpll0,
691 .ops = &clk_rcg2_ops,
695 static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
699 .parent_map = gcc_xo_gpll0_map,
700 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
701 .clkr.hw.init = &(struct clk_init_data)
703 .name = "blsp2_uart4_apps_clk_src",
704 .parent_names = gcc_xo_gpll0,
706 .ops = &clk_rcg2_ops,
710 static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
714 .parent_map = gcc_xo_gpll0_map,
715 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
716 .clkr.hw.init = &(struct clk_init_data)
718 .name = "blsp2_uart5_apps_clk_src",
719 .parent_names = gcc_xo_gpll0,
721 .ops = &clk_rcg2_ops,
725 static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
729 .parent_map = gcc_xo_gpll0_map,
730 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
731 .clkr.hw.init = &(struct clk_init_data)
733 .name = "blsp2_uart6_apps_clk_src",
734 .parent_names = gcc_xo_gpll0,
736 .ops = &clk_rcg2_ops,
740 static struct freq_tbl ftbl_gp1_clk_src[] = {
741 F(19200000, P_XO, 1, 0, 0),
742 F(100000000, P_GPLL0, 6, 0, 0),
743 F(200000000, P_GPLL0, 3, 0, 0),
747 static struct clk_rcg2 gp1_clk_src = {
751 .parent_map = gcc_xo_gpll0_map,
752 .freq_tbl = ftbl_gp1_clk_src,
753 .clkr.hw.init = &(struct clk_init_data)
755 .name = "gp1_clk_src",
756 .parent_names = gcc_xo_gpll0,
758 .ops = &clk_rcg2_ops,
762 static struct freq_tbl ftbl_gp2_clk_src[] = {
763 F(19200000, P_XO, 1, 0, 0),
764 F(100000000, P_GPLL0, 6, 0, 0),
765 F(200000000, P_GPLL0, 3, 0, 0),
769 static struct clk_rcg2 gp2_clk_src = {
773 .parent_map = gcc_xo_gpll0_map,
774 .freq_tbl = ftbl_gp2_clk_src,
775 .clkr.hw.init = &(struct clk_init_data)
777 .name = "gp2_clk_src",
778 .parent_names = gcc_xo_gpll0,
780 .ops = &clk_rcg2_ops,
784 static struct freq_tbl ftbl_gp3_clk_src[] = {
785 F(19200000, P_XO, 1, 0, 0),
786 F(100000000, P_GPLL0, 6, 0, 0),
787 F(200000000, P_GPLL0, 3, 0, 0),
791 static struct clk_rcg2 gp3_clk_src = {
795 .parent_map = gcc_xo_gpll0_map,
796 .freq_tbl = ftbl_gp3_clk_src,
797 .clkr.hw.init = &(struct clk_init_data)
799 .name = "gp3_clk_src",
800 .parent_names = gcc_xo_gpll0,
802 .ops = &clk_rcg2_ops,
806 static struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
807 F(1011000, P_XO, 1, 1, 19),
811 static struct clk_rcg2 pcie_0_aux_clk_src = {
815 .freq_tbl = ftbl_pcie_0_aux_clk_src,
816 .clkr.hw.init = &(struct clk_init_data)
818 .name = "pcie_0_aux_clk_src",
819 .parent_names = (const char *[]) { "xo" },
821 .ops = &clk_rcg2_ops,
825 static struct freq_tbl ftbl_pcie_pipe_clk_src[] = {
826 F(125000000, P_XO, 1, 0, 0),
830 static struct clk_rcg2 pcie_0_pipe_clk_src = {
833 .freq_tbl = ftbl_pcie_pipe_clk_src,
834 .clkr.hw.init = &(struct clk_init_data)
836 .name = "pcie_0_pipe_clk_src",
837 .parent_names = (const char *[]) { "xo" },
839 .ops = &clk_rcg2_ops,
843 static struct freq_tbl ftbl_pcie_1_aux_clk_src[] = {
844 F(1011000, P_XO, 1, 1, 19),
848 static struct clk_rcg2 pcie_1_aux_clk_src = {
852 .freq_tbl = ftbl_pcie_1_aux_clk_src,
853 .clkr.hw.init = &(struct clk_init_data)
855 .name = "pcie_1_aux_clk_src",
856 .parent_names = (const char *[]) { "xo" },
858 .ops = &clk_rcg2_ops,
862 static struct clk_rcg2 pcie_1_pipe_clk_src = {
865 .freq_tbl = ftbl_pcie_pipe_clk_src,
866 .clkr.hw.init = &(struct clk_init_data)
868 .name = "pcie_1_pipe_clk_src",
869 .parent_names = (const char *[]) { "xo" },
871 .ops = &clk_rcg2_ops,
875 static struct freq_tbl ftbl_pdm2_clk_src[] = {
876 F(60000000, P_GPLL0, 10, 0, 0),
880 static struct clk_rcg2 pdm2_clk_src = {
883 .parent_map = gcc_xo_gpll0_map,
884 .freq_tbl = ftbl_pdm2_clk_src,
885 .clkr.hw.init = &(struct clk_init_data)
887 .name = "pdm2_clk_src",
888 .parent_names = gcc_xo_gpll0,
890 .ops = &clk_rcg2_ops,
894 static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
895 F(144000, P_XO, 16, 3, 25),
896 F(400000, P_XO, 12, 1, 4),
897 F(20000000, P_GPLL0, 15, 1, 2),
898 F(25000000, P_GPLL0, 12, 1, 2),
899 F(50000000, P_GPLL0, 12, 0, 0),
900 F(100000000, P_GPLL0, 6, 0, 0),
901 F(192000000, P_GPLL4, 2, 0, 0),
902 F(384000000, P_GPLL4, 1, 0, 0),
906 static struct clk_rcg2 sdcc1_apps_clk_src = {
910 .parent_map = gcc_xo_gpll0_gpll4_map,
911 .freq_tbl = ftbl_sdcc1_apps_clk_src,
912 .clkr.hw.init = &(struct clk_init_data)
914 .name = "sdcc1_apps_clk_src",
915 .parent_names = gcc_xo_gpll0_gpll4,
917 .ops = &clk_rcg2_floor_ops,
921 static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = {
922 F(144000, P_XO, 16, 3, 25),
923 F(400000, P_XO, 12, 1, 4),
924 F(20000000, P_GPLL0, 15, 1, 2),
925 F(25000000, P_GPLL0, 12, 1, 2),
926 F(50000000, P_GPLL0, 12, 0, 0),
927 F(100000000, P_GPLL0, 6, 0, 0),
928 F(200000000, P_GPLL0, 3, 0, 0),
932 static struct clk_rcg2 sdcc2_apps_clk_src = {
936 .parent_map = gcc_xo_gpll0_map,
937 .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
938 .clkr.hw.init = &(struct clk_init_data)
940 .name = "sdcc2_apps_clk_src",
941 .parent_names = gcc_xo_gpll0,
943 .ops = &clk_rcg2_floor_ops,
947 static struct clk_rcg2 sdcc3_apps_clk_src = {
951 .parent_map = gcc_xo_gpll0_map,
952 .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
953 .clkr.hw.init = &(struct clk_init_data)
955 .name = "sdcc3_apps_clk_src",
956 .parent_names = gcc_xo_gpll0,
958 .ops = &clk_rcg2_floor_ops,
962 static struct clk_rcg2 sdcc4_apps_clk_src = {
966 .parent_map = gcc_xo_gpll0_map,
967 .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
968 .clkr.hw.init = &(struct clk_init_data)
970 .name = "sdcc4_apps_clk_src",
971 .parent_names = gcc_xo_gpll0,
973 .ops = &clk_rcg2_floor_ops,
977 static struct freq_tbl ftbl_tsif_ref_clk_src[] = {
978 F(105500, P_XO, 1, 1, 182),
982 static struct clk_rcg2 tsif_ref_clk_src = {
986 .freq_tbl = ftbl_tsif_ref_clk_src,
987 .clkr.hw.init = &(struct clk_init_data)
989 .name = "tsif_ref_clk_src",
990 .parent_names = (const char *[]) { "xo" },
992 .ops = &clk_rcg2_ops,
996 static struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
997 F(19200000, P_XO, 1, 0, 0),
998 F(60000000, P_GPLL0, 10, 0, 0),
1002 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1005 .parent_map = gcc_xo_gpll0_map,
1006 .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
1007 .clkr.hw.init = &(struct clk_init_data)
1009 .name = "usb30_mock_utmi_clk_src",
1010 .parent_names = gcc_xo_gpll0,
1012 .ops = &clk_rcg2_ops,
1016 static struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
1017 F(1200000, P_XO, 16, 0, 0),
1021 static struct clk_rcg2 usb3_phy_aux_clk_src = {
1024 .freq_tbl = ftbl_usb3_phy_aux_clk_src,
1025 .clkr.hw.init = &(struct clk_init_data)
1027 .name = "usb3_phy_aux_clk_src",
1028 .parent_names = (const char *[]) { "xo" },
1030 .ops = &clk_rcg2_ops,
1034 static struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
1035 F(75000000, P_GPLL0, 8, 0, 0),
1039 static struct clk_rcg2 usb_hs_system_clk_src = {
1042 .parent_map = gcc_xo_gpll0_map,
1043 .freq_tbl = ftbl_usb_hs_system_clk_src,
1044 .clkr.hw.init = &(struct clk_init_data)
1046 .name = "usb_hs_system_clk_src",
1047 .parent_names = gcc_xo_gpll0,
1049 .ops = &clk_rcg2_ops,
1053 static struct clk_branch gcc_blsp1_ahb_clk = {
1055 .halt_check = BRANCH_HALT_VOTED,
1057 .enable_reg = 0x1484,
1058 .enable_mask = BIT(17),
1059 .hw.init = &(struct clk_init_data)
1061 .name = "gcc_blsp1_ahb_clk",
1062 .ops = &clk_branch2_ops,
1067 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1070 .enable_reg = 0x0648,
1071 .enable_mask = BIT(0),
1072 .hw.init = &(struct clk_init_data)
1074 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1075 .parent_names = (const char *[]) {
1076 "blsp1_qup1_i2c_apps_clk_src",
1079 .flags = CLK_SET_RATE_PARENT,
1080 .ops = &clk_branch2_ops,
1085 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1088 .enable_reg = 0x0644,
1089 .enable_mask = BIT(0),
1090 .hw.init = &(struct clk_init_data)
1092 .name = "gcc_blsp1_qup1_spi_apps_clk",
1093 .parent_names = (const char *[]) {
1094 "blsp1_qup1_spi_apps_clk_src",
1097 .flags = CLK_SET_RATE_PARENT,
1098 .ops = &clk_branch2_ops,
1103 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1106 .enable_reg = 0x06c8,
1107 .enable_mask = BIT(0),
1108 .hw.init = &(struct clk_init_data)
1110 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1111 .parent_names = (const char *[]) {
1112 "blsp1_qup2_i2c_apps_clk_src",
1115 .flags = CLK_SET_RATE_PARENT,
1116 .ops = &clk_branch2_ops,
1121 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1124 .enable_reg = 0x06c4,
1125 .enable_mask = BIT(0),
1126 .hw.init = &(struct clk_init_data)
1128 .name = "gcc_blsp1_qup2_spi_apps_clk",
1129 .parent_names = (const char *[]) {
1130 "blsp1_qup2_spi_apps_clk_src",
1133 .flags = CLK_SET_RATE_PARENT,
1134 .ops = &clk_branch2_ops,
1139 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1142 .enable_reg = 0x0748,
1143 .enable_mask = BIT(0),
1144 .hw.init = &(struct clk_init_data)
1146 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1147 .parent_names = (const char *[]) {
1148 "blsp1_qup3_i2c_apps_clk_src",
1151 .flags = CLK_SET_RATE_PARENT,
1152 .ops = &clk_branch2_ops,
1157 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1160 .enable_reg = 0x0744,
1161 .enable_mask = BIT(0),
1162 .hw.init = &(struct clk_init_data)
1164 .name = "gcc_blsp1_qup3_spi_apps_clk",
1165 .parent_names = (const char *[]) {
1166 "blsp1_qup3_spi_apps_clk_src",
1169 .flags = CLK_SET_RATE_PARENT,
1170 .ops = &clk_branch2_ops,
1175 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1178 .enable_reg = 0x07c8,
1179 .enable_mask = BIT(0),
1180 .hw.init = &(struct clk_init_data)
1182 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1183 .parent_names = (const char *[]) {
1184 "blsp1_qup4_i2c_apps_clk_src",
1187 .flags = CLK_SET_RATE_PARENT,
1188 .ops = &clk_branch2_ops,
1193 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1196 .enable_reg = 0x07c4,
1197 .enable_mask = BIT(0),
1198 .hw.init = &(struct clk_init_data)
1200 .name = "gcc_blsp1_qup4_spi_apps_clk",
1201 .parent_names = (const char *[]) {
1202 "blsp1_qup4_spi_apps_clk_src",
1205 .flags = CLK_SET_RATE_PARENT,
1206 .ops = &clk_branch2_ops,
1211 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1214 .enable_reg = 0x0848,
1215 .enable_mask = BIT(0),
1216 .hw.init = &(struct clk_init_data)
1218 .name = "gcc_blsp1_qup5_i2c_apps_clk",
1219 .parent_names = (const char *[]) {
1220 "blsp1_qup5_i2c_apps_clk_src",
1223 .flags = CLK_SET_RATE_PARENT,
1224 .ops = &clk_branch2_ops,
1229 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1232 .enable_reg = 0x0844,
1233 .enable_mask = BIT(0),
1234 .hw.init = &(struct clk_init_data)
1236 .name = "gcc_blsp1_qup5_spi_apps_clk",
1237 .parent_names = (const char *[]) {
1238 "blsp1_qup5_spi_apps_clk_src",
1241 .flags = CLK_SET_RATE_PARENT,
1242 .ops = &clk_branch2_ops,
1247 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1250 .enable_reg = 0x08c8,
1251 .enable_mask = BIT(0),
1252 .hw.init = &(struct clk_init_data)
1254 .name = "gcc_blsp1_qup6_i2c_apps_clk",
1255 .parent_names = (const char *[]) {
1256 "blsp1_qup6_i2c_apps_clk_src",
1259 .flags = CLK_SET_RATE_PARENT,
1260 .ops = &clk_branch2_ops,
1265 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1268 .enable_reg = 0x08c4,
1269 .enable_mask = BIT(0),
1270 .hw.init = &(struct clk_init_data)
1272 .name = "gcc_blsp1_qup6_spi_apps_clk",
1273 .parent_names = (const char *[]) {
1274 "blsp1_qup6_spi_apps_clk_src",
1277 .flags = CLK_SET_RATE_PARENT,
1278 .ops = &clk_branch2_ops,
1283 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1286 .enable_reg = 0x0684,
1287 .enable_mask = BIT(0),
1288 .hw.init = &(struct clk_init_data)
1290 .name = "gcc_blsp1_uart1_apps_clk",
1291 .parent_names = (const char *[]) {
1292 "blsp1_uart1_apps_clk_src",
1295 .flags = CLK_SET_RATE_PARENT,
1296 .ops = &clk_branch2_ops,
1301 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1304 .enable_reg = 0x0704,
1305 .enable_mask = BIT(0),
1306 .hw.init = &(struct clk_init_data)
1308 .name = "gcc_blsp1_uart2_apps_clk",
1309 .parent_names = (const char *[]) {
1310 "blsp1_uart2_apps_clk_src",
1313 .flags = CLK_SET_RATE_PARENT,
1314 .ops = &clk_branch2_ops,
1319 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1322 .enable_reg = 0x0784,
1323 .enable_mask = BIT(0),
1324 .hw.init = &(struct clk_init_data)
1326 .name = "gcc_blsp1_uart3_apps_clk",
1327 .parent_names = (const char *[]) {
1328 "blsp1_uart3_apps_clk_src",
1331 .flags = CLK_SET_RATE_PARENT,
1332 .ops = &clk_branch2_ops,
1337 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1340 .enable_reg = 0x0804,
1341 .enable_mask = BIT(0),
1342 .hw.init = &(struct clk_init_data)
1344 .name = "gcc_blsp1_uart4_apps_clk",
1345 .parent_names = (const char *[]) {
1346 "blsp1_uart4_apps_clk_src",
1349 .flags = CLK_SET_RATE_PARENT,
1350 .ops = &clk_branch2_ops,
1355 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1358 .enable_reg = 0x0884,
1359 .enable_mask = BIT(0),
1360 .hw.init = &(struct clk_init_data)
1362 .name = "gcc_blsp1_uart5_apps_clk",
1363 .parent_names = (const char *[]) {
1364 "blsp1_uart5_apps_clk_src",
1367 .flags = CLK_SET_RATE_PARENT,
1368 .ops = &clk_branch2_ops,
1373 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1376 .enable_reg = 0x0904,
1377 .enable_mask = BIT(0),
1378 .hw.init = &(struct clk_init_data)
1380 .name = "gcc_blsp1_uart6_apps_clk",
1381 .parent_names = (const char *[]) {
1382 "blsp1_uart6_apps_clk_src",
1385 .flags = CLK_SET_RATE_PARENT,
1386 .ops = &clk_branch2_ops,
1391 static struct clk_branch gcc_blsp2_ahb_clk = {
1393 .halt_check = BRANCH_HALT_VOTED,
1395 .enable_reg = 0x1484,
1396 .enable_mask = BIT(15),
1397 .hw.init = &(struct clk_init_data)
1399 .name = "gcc_blsp2_ahb_clk",
1400 .ops = &clk_branch2_ops,
1405 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1408 .enable_reg = 0x0988,
1409 .enable_mask = BIT(0),
1410 .hw.init = &(struct clk_init_data)
1412 .name = "gcc_blsp2_qup1_i2c_apps_clk",
1413 .parent_names = (const char *[]) {
1414 "blsp2_qup1_i2c_apps_clk_src",
1417 .flags = CLK_SET_RATE_PARENT,
1418 .ops = &clk_branch2_ops,
1423 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1426 .enable_reg = 0x0984,
1427 .enable_mask = BIT(0),
1428 .hw.init = &(struct clk_init_data)
1430 .name = "gcc_blsp2_qup1_spi_apps_clk",
1431 .parent_names = (const char *[]) {
1432 "blsp2_qup1_spi_apps_clk_src",
1435 .flags = CLK_SET_RATE_PARENT,
1436 .ops = &clk_branch2_ops,
1441 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1444 .enable_reg = 0x0a08,
1445 .enable_mask = BIT(0),
1446 .hw.init = &(struct clk_init_data)
1448 .name = "gcc_blsp2_qup2_i2c_apps_clk",
1449 .parent_names = (const char *[]) {
1450 "blsp2_qup2_i2c_apps_clk_src",
1453 .flags = CLK_SET_RATE_PARENT,
1454 .ops = &clk_branch2_ops,
1459 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1462 .enable_reg = 0x0a04,
1463 .enable_mask = BIT(0),
1464 .hw.init = &(struct clk_init_data)
1466 .name = "gcc_blsp2_qup2_spi_apps_clk",
1467 .parent_names = (const char *[]) {
1468 "blsp2_qup2_spi_apps_clk_src",
1471 .flags = CLK_SET_RATE_PARENT,
1472 .ops = &clk_branch2_ops,
1477 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1480 .enable_reg = 0x0a88,
1481 .enable_mask = BIT(0),
1482 .hw.init = &(struct clk_init_data)
1484 .name = "gcc_blsp2_qup3_i2c_apps_clk",
1485 .parent_names = (const char *[]) {
1486 "blsp2_qup3_i2c_apps_clk_src",
1489 .flags = CLK_SET_RATE_PARENT,
1490 .ops = &clk_branch2_ops,
1495 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1498 .enable_reg = 0x0a84,
1499 .enable_mask = BIT(0),
1500 .hw.init = &(struct clk_init_data)
1502 .name = "gcc_blsp2_qup3_spi_apps_clk",
1503 .parent_names = (const char *[]) {
1504 "blsp2_qup3_spi_apps_clk_src",
1507 .flags = CLK_SET_RATE_PARENT,
1508 .ops = &clk_branch2_ops,
1513 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1516 .enable_reg = 0x0b08,
1517 .enable_mask = BIT(0),
1518 .hw.init = &(struct clk_init_data)
1520 .name = "gcc_blsp2_qup4_i2c_apps_clk",
1521 .parent_names = (const char *[]) {
1522 "blsp2_qup4_i2c_apps_clk_src",
1525 .flags = CLK_SET_RATE_PARENT,
1526 .ops = &clk_branch2_ops,
1531 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1534 .enable_reg = 0x0b04,
1535 .enable_mask = BIT(0),
1536 .hw.init = &(struct clk_init_data)
1538 .name = "gcc_blsp2_qup4_spi_apps_clk",
1539 .parent_names = (const char *[]) {
1540 "blsp2_qup4_spi_apps_clk_src",
1543 .flags = CLK_SET_RATE_PARENT,
1544 .ops = &clk_branch2_ops,
1549 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1552 .enable_reg = 0x0b88,
1553 .enable_mask = BIT(0),
1554 .hw.init = &(struct clk_init_data)
1556 .name = "gcc_blsp2_qup5_i2c_apps_clk",
1557 .parent_names = (const char *[]) {
1558 "blsp2_qup5_i2c_apps_clk_src",
1561 .flags = CLK_SET_RATE_PARENT,
1562 .ops = &clk_branch2_ops,
1567 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1570 .enable_reg = 0x0b84,
1571 .enable_mask = BIT(0),
1572 .hw.init = &(struct clk_init_data)
1574 .name = "gcc_blsp2_qup5_spi_apps_clk",
1575 .parent_names = (const char *[]) {
1576 "blsp2_qup5_spi_apps_clk_src",
1579 .flags = CLK_SET_RATE_PARENT,
1580 .ops = &clk_branch2_ops,
1585 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1588 .enable_reg = 0x0c08,
1589 .enable_mask = BIT(0),
1590 .hw.init = &(struct clk_init_data)
1592 .name = "gcc_blsp2_qup6_i2c_apps_clk",
1593 .parent_names = (const char *[]) {
1594 "blsp2_qup6_i2c_apps_clk_src",
1597 .flags = CLK_SET_RATE_PARENT,
1598 .ops = &clk_branch2_ops,
1603 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1606 .enable_reg = 0x0c04,
1607 .enable_mask = BIT(0),
1608 .hw.init = &(struct clk_init_data)
1610 .name = "gcc_blsp2_qup6_spi_apps_clk",
1611 .parent_names = (const char *[]) {
1612 "blsp2_qup6_spi_apps_clk_src",
1615 .flags = CLK_SET_RATE_PARENT,
1616 .ops = &clk_branch2_ops,
1621 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1624 .enable_reg = 0x09c4,
1625 .enable_mask = BIT(0),
1626 .hw.init = &(struct clk_init_data)
1628 .name = "gcc_blsp2_uart1_apps_clk",
1629 .parent_names = (const char *[]) {
1630 "blsp2_uart1_apps_clk_src",
1633 .flags = CLK_SET_RATE_PARENT,
1634 .ops = &clk_branch2_ops,
1639 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1642 .enable_reg = 0x0a44,
1643 .enable_mask = BIT(0),
1644 .hw.init = &(struct clk_init_data)
1646 .name = "gcc_blsp2_uart2_apps_clk",
1647 .parent_names = (const char *[]) {
1648 "blsp2_uart2_apps_clk_src",
1651 .flags = CLK_SET_RATE_PARENT,
1652 .ops = &clk_branch2_ops,
1657 static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1660 .enable_reg = 0x0ac4,
1661 .enable_mask = BIT(0),
1662 .hw.init = &(struct clk_init_data)
1664 .name = "gcc_blsp2_uart3_apps_clk",
1665 .parent_names = (const char *[]) {
1666 "blsp2_uart3_apps_clk_src",
1669 .flags = CLK_SET_RATE_PARENT,
1670 .ops = &clk_branch2_ops,
1675 static struct clk_branch gcc_blsp2_uart4_apps_clk = {
1678 .enable_reg = 0x0b44,
1679 .enable_mask = BIT(0),
1680 .hw.init = &(struct clk_init_data)
1682 .name = "gcc_blsp2_uart4_apps_clk",
1683 .parent_names = (const char *[]) {
1684 "blsp2_uart4_apps_clk_src",
1687 .flags = CLK_SET_RATE_PARENT,
1688 .ops = &clk_branch2_ops,
1693 static struct clk_branch gcc_blsp2_uart5_apps_clk = {
1696 .enable_reg = 0x0bc4,
1697 .enable_mask = BIT(0),
1698 .hw.init = &(struct clk_init_data)
1700 .name = "gcc_blsp2_uart5_apps_clk",
1701 .parent_names = (const char *[]) {
1702 "blsp2_uart5_apps_clk_src",
1705 .flags = CLK_SET_RATE_PARENT,
1706 .ops = &clk_branch2_ops,
1711 static struct clk_branch gcc_blsp2_uart6_apps_clk = {
1714 .enable_reg = 0x0c44,
1715 .enable_mask = BIT(0),
1716 .hw.init = &(struct clk_init_data)
1718 .name = "gcc_blsp2_uart6_apps_clk",
1719 .parent_names = (const char *[]) {
1720 "blsp2_uart6_apps_clk_src",
1723 .flags = CLK_SET_RATE_PARENT,
1724 .ops = &clk_branch2_ops,
1729 static struct clk_branch gcc_gp1_clk = {
1732 .enable_reg = 0x1900,
1733 .enable_mask = BIT(0),
1734 .hw.init = &(struct clk_init_data)
1736 .name = "gcc_gp1_clk",
1737 .parent_names = (const char *[]) {
1741 .flags = CLK_SET_RATE_PARENT,
1742 .ops = &clk_branch2_ops,
1747 static struct clk_branch gcc_gp2_clk = {
1750 .enable_reg = 0x1940,
1751 .enable_mask = BIT(0),
1752 .hw.init = &(struct clk_init_data)
1754 .name = "gcc_gp2_clk",
1755 .parent_names = (const char *[]) {
1759 .flags = CLK_SET_RATE_PARENT,
1760 .ops = &clk_branch2_ops,
1765 static struct clk_branch gcc_gp3_clk = {
1768 .enable_reg = 0x1980,
1769 .enable_mask = BIT(0),
1770 .hw.init = &(struct clk_init_data)
1772 .name = "gcc_gp3_clk",
1773 .parent_names = (const char *[]) {
1777 .flags = CLK_SET_RATE_PARENT,
1778 .ops = &clk_branch2_ops,
1783 static struct clk_branch gcc_pcie_0_aux_clk = {
1786 .enable_reg = 0x1ad4,
1787 .enable_mask = BIT(0),
1788 .hw.init = &(struct clk_init_data)
1790 .name = "gcc_pcie_0_aux_clk",
1791 .parent_names = (const char *[]) {
1792 "pcie_0_aux_clk_src",
1795 .flags = CLK_SET_RATE_PARENT,
1796 .ops = &clk_branch2_ops,
1801 static struct clk_branch gcc_pcie_0_pipe_clk = {
1803 .halt_check = BRANCH_HALT_DELAY,
1805 .enable_reg = 0x1ad8,
1806 .enable_mask = BIT(0),
1807 .hw.init = &(struct clk_init_data)
1809 .name = "gcc_pcie_0_pipe_clk",
1810 .parent_names = (const char *[]) {
1811 "pcie_0_pipe_clk_src",
1814 .flags = CLK_SET_RATE_PARENT,
1815 .ops = &clk_branch2_ops,
1820 static struct clk_branch gcc_pcie_1_aux_clk = {
1823 .enable_reg = 0x1b54,
1824 .enable_mask = BIT(0),
1825 .hw.init = &(struct clk_init_data)
1827 .name = "gcc_pcie_1_aux_clk",
1828 .parent_names = (const char *[]) {
1829 "pcie_1_aux_clk_src",
1832 .flags = CLK_SET_RATE_PARENT,
1833 .ops = &clk_branch2_ops,
1838 static struct clk_branch gcc_pcie_1_pipe_clk = {
1840 .halt_check = BRANCH_HALT_DELAY,
1842 .enable_reg = 0x1b58,
1843 .enable_mask = BIT(0),
1844 .hw.init = &(struct clk_init_data)
1846 .name = "gcc_pcie_1_pipe_clk",
1847 .parent_names = (const char *[]) {
1848 "pcie_1_pipe_clk_src",
1851 .flags = CLK_SET_RATE_PARENT,
1852 .ops = &clk_branch2_ops,
1857 static struct clk_branch gcc_pdm2_clk = {
1860 .enable_reg = 0x0ccc,
1861 .enable_mask = BIT(0),
1862 .hw.init = &(struct clk_init_data)
1864 .name = "gcc_pdm2_clk",
1865 .parent_names = (const char *[]) {
1869 .flags = CLK_SET_RATE_PARENT,
1870 .ops = &clk_branch2_ops,
1875 static struct clk_branch gcc_sdcc1_apps_clk = {
1878 .enable_reg = 0x04c4,
1879 .enable_mask = BIT(0),
1880 .hw.init = &(struct clk_init_data)
1882 .name = "gcc_sdcc1_apps_clk",
1883 .parent_names = (const char *[]) {
1884 "sdcc1_apps_clk_src",
1887 .flags = CLK_SET_RATE_PARENT,
1888 .ops = &clk_branch2_ops,
1893 static struct clk_branch gcc_sdcc1_ahb_clk = {
1896 .enable_reg = 0x04c8,
1897 .enable_mask = BIT(0),
1898 .hw.init = &(struct clk_init_data)
1900 .name = "gcc_sdcc1_ahb_clk",
1901 .parent_names = (const char *[]){
1902 "periph_noc_clk_src",
1905 .ops = &clk_branch2_ops,
1910 static struct clk_branch gcc_sdcc2_apps_clk = {
1913 .enable_reg = 0x0504,
1914 .enable_mask = BIT(0),
1915 .hw.init = &(struct clk_init_data)
1917 .name = "gcc_sdcc2_apps_clk",
1918 .parent_names = (const char *[]) {
1919 "sdcc2_apps_clk_src",
1922 .flags = CLK_SET_RATE_PARENT,
1923 .ops = &clk_branch2_ops,
1928 static struct clk_branch gcc_sdcc3_apps_clk = {
1931 .enable_reg = 0x0544,
1932 .enable_mask = BIT(0),
1933 .hw.init = &(struct clk_init_data)
1935 .name = "gcc_sdcc3_apps_clk",
1936 .parent_names = (const char *[]) {
1937 "sdcc3_apps_clk_src",
1940 .flags = CLK_SET_RATE_PARENT,
1941 .ops = &clk_branch2_ops,
1946 static struct clk_branch gcc_sdcc4_apps_clk = {
1949 .enable_reg = 0x0584,
1950 .enable_mask = BIT(0),
1951 .hw.init = &(struct clk_init_data)
1953 .name = "gcc_sdcc4_apps_clk",
1954 .parent_names = (const char *[]) {
1955 "sdcc4_apps_clk_src",
1958 .flags = CLK_SET_RATE_PARENT,
1959 .ops = &clk_branch2_ops,
1964 static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
1967 .enable_reg = 0x1d7c,
1968 .enable_mask = BIT(0),
1969 .hw.init = &(struct clk_init_data)
1971 .name = "gcc_sys_noc_ufs_axi_clk",
1972 .parent_names = (const char *[]) {
1976 .flags = CLK_SET_RATE_PARENT,
1977 .ops = &clk_branch2_ops,
1982 static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
1985 .enable_reg = 0x03fc,
1986 .enable_mask = BIT(0),
1987 .hw.init = &(struct clk_init_data)
1989 .name = "gcc_sys_noc_usb3_axi_clk",
1990 .parent_names = (const char *[]) {
1991 "usb30_master_clk_src",
1994 .flags = CLK_SET_RATE_PARENT,
1995 .ops = &clk_branch2_ops,
2000 static struct clk_branch gcc_tsif_ref_clk = {
2003 .enable_reg = 0x0d88,
2004 .enable_mask = BIT(0),
2005 .hw.init = &(struct clk_init_data)
2007 .name = "gcc_tsif_ref_clk",
2008 .parent_names = (const char *[]) {
2012 .flags = CLK_SET_RATE_PARENT,
2013 .ops = &clk_branch2_ops,
2018 static struct clk_branch gcc_ufs_axi_clk = {
2021 .enable_reg = 0x1d48,
2022 .enable_mask = BIT(0),
2023 .hw.init = &(struct clk_init_data)
2025 .name = "gcc_ufs_axi_clk",
2026 .parent_names = (const char *[]) {
2030 .flags = CLK_SET_RATE_PARENT,
2031 .ops = &clk_branch2_ops,
2036 static struct clk_branch gcc_ufs_rx_cfg_clk = {
2039 .enable_reg = 0x1d54,
2040 .enable_mask = BIT(0),
2041 .hw.init = &(struct clk_init_data)
2043 .name = "gcc_ufs_rx_cfg_clk",
2044 .parent_names = (const char *[]) {
2048 .flags = CLK_SET_RATE_PARENT,
2049 .ops = &clk_branch2_ops,
2054 static struct clk_branch gcc_ufs_tx_cfg_clk = {
2057 .enable_reg = 0x1d50,
2058 .enable_mask = BIT(0),
2059 .hw.init = &(struct clk_init_data)
2061 .name = "gcc_ufs_tx_cfg_clk",
2062 .parent_names = (const char *[]) {
2066 .flags = CLK_SET_RATE_PARENT,
2067 .ops = &clk_branch2_ops,
2072 static struct clk_branch gcc_usb30_master_clk = {
2075 .enable_reg = 0x03c8,
2076 .enable_mask = BIT(0),
2077 .hw.init = &(struct clk_init_data)
2079 .name = "gcc_usb30_master_clk",
2080 .parent_names = (const char *[]) {
2081 "usb30_master_clk_src",
2084 .flags = CLK_SET_RATE_PARENT,
2085 .ops = &clk_branch2_ops,
2090 static struct clk_branch gcc_usb30_mock_utmi_clk = {
2093 .enable_reg = 0x03d0,
2094 .enable_mask = BIT(0),
2095 .hw.init = &(struct clk_init_data)
2097 .name = "gcc_usb30_mock_utmi_clk",
2098 .parent_names = (const char *[]) {
2099 "usb30_mock_utmi_clk_src",
2102 .flags = CLK_SET_RATE_PARENT,
2103 .ops = &clk_branch2_ops,
2108 static struct clk_branch gcc_usb3_phy_aux_clk = {
2111 .enable_reg = 0x1408,
2112 .enable_mask = BIT(0),
2113 .hw.init = &(struct clk_init_data)
2115 .name = "gcc_usb3_phy_aux_clk",
2116 .parent_names = (const char *[]) {
2117 "usb3_phy_aux_clk_src",
2120 .flags = CLK_SET_RATE_PARENT,
2121 .ops = &clk_branch2_ops,
2126 static struct clk_branch gcc_usb_hs_system_clk = {
2129 .enable_reg = 0x0484,
2130 .enable_mask = BIT(0),
2131 .hw.init = &(struct clk_init_data)
2133 .name = "gcc_usb_hs_system_clk",
2134 .parent_names = (const char *[]) {
2135 "usb_hs_system_clk_src",
2138 .flags = CLK_SET_RATE_PARENT,
2139 .ops = &clk_branch2_ops,
2144 static struct clk_regmap *gcc_msm8994_clocks[] = {
2145 [GPLL0_EARLY] = &gpll0_early.clkr,
2146 [GPLL0] = &gpll0.clkr,
2147 [GPLL4_EARLY] = &gpll4_early.clkr,
2148 [GPLL4] = &gpll4.clkr,
2149 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
2150 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2151 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2152 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2153 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2154 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2155 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2156 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2157 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2158 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2159 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2160 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2161 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2162 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2163 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2164 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2165 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2166 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
2167 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
2168 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
2169 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2170 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2171 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2172 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2173 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2174 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2175 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2176 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2177 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
2178 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
2179 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
2180 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
2181 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2182 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2183 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
2184 [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
2185 [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
2186 [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
2187 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2188 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2189 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2190 [PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
2191 [PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
2192 [PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr,
2193 [PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr,
2194 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2195 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2196 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2197 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
2198 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
2199 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
2200 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2201 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2202 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2203 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2204 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2205 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2206 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2207 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2208 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2209 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2210 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2211 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2212 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2213 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2214 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2215 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2216 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2217 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2218 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2219 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
2220 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
2221 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
2222 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2223 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2224 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2225 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2226 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2227 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2228 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2229 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2230 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2231 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
2232 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
2233 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
2234 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
2235 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2236 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2237 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
2238 [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
2239 [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
2240 [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
2241 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2242 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2243 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2244 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2245 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2246 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
2247 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
2248 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2249 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2250 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2251 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
2252 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
2253 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2254 [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
2255 [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
2256 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
2257 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
2258 [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
2259 [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
2260 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2261 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2262 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2263 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2266 static const struct regmap_config gcc_msm8994_regmap_config = {
2270 .max_register = 0x2000,
2274 static const struct qcom_cc_desc gcc_msm8994_desc = {
2275 .config = &gcc_msm8994_regmap_config,
2276 .clks = gcc_msm8994_clocks,
2277 .num_clks = ARRAY_SIZE(gcc_msm8994_clocks),
2280 static const struct of_device_id gcc_msm8994_match_table[] = {
2281 { .compatible = "qcom,gcc-msm8994" },
2284 MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table);
2286 static int gcc_msm8994_probe(struct platform_device *pdev)
2288 struct device *dev = &pdev->dev;
2291 clk = devm_clk_register(dev, &xo.hw);
2293 return PTR_ERR(clk);
2295 return qcom_cc_probe(pdev, &gcc_msm8994_desc);
2298 static struct platform_driver gcc_msm8994_driver = {
2299 .probe = gcc_msm8994_probe,
2301 .name = "gcc-msm8994",
2302 .of_match_table = gcc_msm8994_match_table,
2306 static int __init gcc_msm8994_init(void)
2308 return platform_driver_register(&gcc_msm8994_driver);
2310 core_initcall(gcc_msm8994_init);
2312 static void __exit gcc_msm8994_exit(void)
2314 platform_driver_unregister(&gcc_msm8994_driver);
2316 module_exit(gcc_msm8994_exit);
2318 MODULE_DESCRIPTION("Qualcomm GCC MSM8994 Driver");
2319 MODULE_LICENSE("GPL v2");
2320 MODULE_ALIAS("platform:gcc-msm8994");