drivers/clk/qcom/gcc-msm8994.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
   3  */
   4
   5 #include <linux/clk-provider.h>
   6 #include <linux/kernel.h>
   7 #include <linux/init.h>
   8 #include <linux/err.h>
   9 #include <linux/ctype.h>
  10 #include <linux/io.h>
  11 #include <linux/of.h>
  12 #include <linux/of_device.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/module.h>
  15 #include <linux/regmap.h>
  16
  17 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
  18
  19 #include "common.h"
  20 #include "clk-regmap.h"
  21 #include "clk-alpha-pll.h"
  22 #include "clk-rcg.h"
  23 #include "clk-branch.h"
  24 #include "reset.h"
  25 #include "gdsc.h"
  26
  27 enum {
  28         P_XO,
  29         P_GPLL0,
  30         P_GPLL4,
  31 };
  32
  33 static struct clk_alpha_pll gpll0_early = {
  34         .offset = 0,
  35         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  36         .clkr = {
  37                 .enable_reg = 0x1480,
  38                 .enable_mask = BIT(0),
  39                 .hw.init = &(struct clk_init_data){
  40                         .name = "gpll0_early",
  41                         .parent_data = &(const struct clk_parent_data){
  42                                 .fw_name = "xo",
  43                         },
  44                         .num_parents = 1,
  45                         .ops = &clk_alpha_pll_ops,
  46                 },
  47         },
  48 };
  49
  50 static struct clk_alpha_pll_postdiv gpll0 = {
  51         .offset = 0,
  52         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  53         .clkr.hw.init = &(struct clk_init_data){
  54                 .name = "gpll0",
  55                 .parent_names = (const char *[]) { "gpll0_early" },
  56                 .num_parents = 1,
  57                 .ops = &clk_alpha_pll_postdiv_ops,
  58         },
  59 };
  60
  61 static struct clk_alpha_pll gpll4_early = {
  62         .offset = 0x1dc0,
  63         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  64         .clkr = {
  65                 .enable_reg = 0x1480,
  66                 .enable_mask = BIT(4),
  67                 .hw.init = &(struct clk_init_data){
  68                         .name = "gpll4_early",
  69                         .parent_data = &(const struct clk_parent_data){
  70                                 .fw_name = "xo",
  71                         },
  72                         .num_parents = 1,
  73                         .ops = &clk_alpha_pll_ops,
  74                 },
  75         },
  76 };
  77
  78 static struct clk_alpha_pll_postdiv gpll4 = {
  79         .offset = 0x1dc0,
  80         .width = 4,
  81         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  82         .clkr.hw.init = &(struct clk_init_data){
  83                 .name = "gpll4",
  84                 .parent_names = (const char *[]) { "gpll4_early" },
  85                 .num_parents = 1,
  86                 .ops = &clk_alpha_pll_postdiv_ops,
  87         },
  88 };
  89
  90 static const struct parent_map gcc_xo_gpll0_map[] = {
  91         { P_XO, 0 },
  92         { P_GPLL0, 1 },
  93 };
  94
  95 static const struct clk_parent_data gcc_xo_gpll0[] = {
  96         { .fw_name = "xo" },
  97         { .hw = &gpll0.clkr.hw },
  98 };
  99
 100 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
 101         { P_XO, 0 },
 102         { P_GPLL0, 1 },
 103         { P_GPLL4, 5 },
 104 };
 105
 106 static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
 107         { .fw_name = "xo" },
 108         { .hw = &gpll0.clkr.hw },
 109         { .hw = &gpll4.clkr.hw },
 110 };
 111
 112 static struct freq_tbl ftbl_ufs_axi_clk_src[] = {
 113         F(50000000, P_GPLL0, 12, 0, 0),
 114         F(100000000, P_GPLL0, 6, 0, 0),
 115         F(150000000, P_GPLL0, 4, 0, 0),
 116         F(171430000, P_GPLL0, 3.5, 0, 0),
 117         F(200000000, P_GPLL0, 3, 0, 0),
 118         F(240000000, P_GPLL0, 2.5, 0, 0),
 119         { }
 120 };
 121
 122 static struct clk_rcg2 ufs_axi_clk_src = {
 123         .cmd_rcgr = 0x1d68,
 124         .mnd_width = 8,
 125         .hid_width = 5,
 126         .parent_map = gcc_xo_gpll0_map,
 127         .freq_tbl = ftbl_ufs_axi_clk_src,
 128         .clkr.hw.init = &(struct clk_init_data){
 129                 .name = "ufs_axi_clk_src",
 130                 .parent_data = gcc_xo_gpll0,
 131                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 132                 .ops = &clk_rcg2_ops,
 133         },
 134 };
 135
 136 static struct freq_tbl ftbl_usb30_master_clk_src[] = {
 137         F(19200000, P_XO, 1, 0, 0),
 138         F(125000000, P_GPLL0, 1, 5, 24),
 139         { }
 140 };
 141
 142 static struct clk_rcg2 usb30_master_clk_src = {
 143         .cmd_rcgr = 0x03d4,
 144         .mnd_width = 8,
 145         .hid_width = 5,
 146         .parent_map = gcc_xo_gpll0_map,
 147         .freq_tbl = ftbl_usb30_master_clk_src,
 148         .clkr.hw.init = &(struct clk_init_data){
 149                 .name = "usb30_master_clk_src",
 150                 .parent_data = gcc_xo_gpll0,
 151                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 152                 .ops = &clk_rcg2_ops,
 153         },
 154 };
 155
 156 static struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
 157         F(19200000, P_XO, 1, 0, 0),
 158         F(50000000, P_GPLL0, 12, 0, 0),
 159         { }
 160 };
 161
 162 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 163         .cmd_rcgr = 0x0660,
 164         .hid_width = 5,
 165         .parent_map = gcc_xo_gpll0_map,
 166         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 167         .clkr.hw.init = &(struct clk_init_data){
 168                 .name = "blsp1_qup1_i2c_apps_clk_src",
 169                 .parent_data = gcc_xo_gpll0,
 170                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 171                 .ops = &clk_rcg2_ops,
 172         },
 173 };
 174
 175 static struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
 176         F(960000, P_XO, 10, 1, 2),
 177         F(4800000, P_XO, 4, 0, 0),
 178         F(9600000, P_XO, 2, 0, 0),
 179         F(15000000, P_GPLL0, 10, 1, 4),
 180         F(19200000, P_XO, 1, 0, 0),
 181         F(24000000, P_GPLL0, 12.5, 1, 2),
 182         F(25000000, P_GPLL0, 12, 1, 2),
 183         F(48000000, P_GPLL0, 12.5, 0, 0),
 184         F(50000000, P_GPLL0, 12, 0, 0),
 185         { }
 186 };
 187
 188 static struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src_8992[] = {
 189         F(960000, P_XO, 10, 1, 2),
 190         F(4800000, P_XO, 4, 0, 0),
 191         F(9600000, P_XO, 2, 0, 0),
 192         F(15000000, P_GPLL0, 10, 1, 4),
 193         F(19200000, P_XO, 1, 0, 0),
 194         F(25000000, P_GPLL0, 12, 1, 2),
 195         F(50000000, P_GPLL0, 12, 0, 0),
 196         { }
 197 };
 198
 199 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 200         .cmd_rcgr = 0x064c,
 201         .mnd_width = 8,
 202         .hid_width = 5,
 203         .parent_map = gcc_xo_gpll0_map,
 204         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 205         .clkr.hw.init = &(struct clk_init_data){
 206                 .name = "blsp1_qup1_spi_apps_clk_src",
 207                 .parent_data = gcc_xo_gpll0,
 208                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 209                 .ops = &clk_rcg2_ops,
 210         },
 211 };
 212
 213 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 214         .cmd_rcgr = 0x06e0,
 215         .hid_width = 5,
 216         .parent_map = gcc_xo_gpll0_map,
 217         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 218         .clkr.hw.init = &(struct clk_init_data){
 219                 .name = "blsp1_qup2_i2c_apps_clk_src",
 220                 .parent_data = gcc_xo_gpll0,
 221                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 222                 .ops = &clk_rcg2_ops,
 223         },
 224 };
 225
 226 static struct freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = {
 227         F(960000, P_XO, 10, 1, 2),
 228         F(4800000, P_XO, 4, 0, 0),
 229         F(9600000, P_XO, 2, 0, 0),
 230         F(15000000, P_GPLL0, 10, 1, 4),
 231         F(19200000, P_XO, 1, 0, 0),
 232         F(24000000, P_GPLL0, 12.5, 1, 2),
 233         F(25000000, P_GPLL0, 12, 1, 2),
 234         F(42860000, P_GPLL0, 14, 0, 0),
 235         F(46150000, P_GPLL0, 13, 0, 0),
 236         { }
 237 };
 238
 239 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 240         .cmd_rcgr = 0x06cc,
 241         .mnd_width = 8,
 242         .hid_width = 5,
 243         .parent_map = gcc_xo_gpll0_map,
 244         .freq_tbl = ftbl_blsp1_qup2_spi_apps_clk_src,
 245         .clkr.hw.init = &(struct clk_init_data){
 246                 .name = "blsp1_qup2_spi_apps_clk_src",
 247                 .parent_data = gcc_xo_gpll0,
 248                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 249                 .ops = &clk_rcg2_ops,
 250         },
 251 };
 252
 253 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 254         .cmd_rcgr = 0x0760,
 255         .hid_width = 5,
 256         .parent_map = gcc_xo_gpll0_map,
 257         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 258         .clkr.hw.init = &(struct clk_init_data){
 259                 .name = "blsp1_qup3_i2c_apps_clk_src",
 260                 .parent_data = gcc_xo_gpll0,
 261                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 262                 .ops = &clk_rcg2_ops,
 263         },
 264 };
 265
 266 static struct freq_tbl ftbl_blsp1_qup3_4_spi_apps_clk_src[] = {
 267         F(960000, P_XO, 10, 1, 2),
 268         F(4800000, P_XO, 4, 0, 0),
 269         F(9600000, P_XO, 2, 0, 0),
 270         F(15000000, P_GPLL0, 10, 1, 4),
 271         F(19200000, P_XO, 1, 0, 0),
 272         F(24000000, P_GPLL0, 12.5, 1, 2),
 273         F(25000000, P_GPLL0, 12, 1, 2),
 274         F(42860000, P_GPLL0, 14, 0, 0),
 275         F(44440000, P_GPLL0, 13.5, 0, 0),
 276         { }
 277 };
 278
 279 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 280         .cmd_rcgr = 0x074c,
 281         .mnd_width = 8,
 282         .hid_width = 5,
 283         .parent_map = gcc_xo_gpll0_map,
 284         .freq_tbl = ftbl_blsp1_qup3_4_spi_apps_clk_src,
 285         .clkr.hw.init = &(struct clk_init_data){
 286                 .name = "blsp1_qup3_spi_apps_clk_src",
 287                 .parent_data = gcc_xo_gpll0,
 288                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 289                 .ops = &clk_rcg2_ops,
 290         },
 291 };
 292
 293 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 294         .cmd_rcgr = 0x07e0,
 295         .hid_width = 5,
 296         .parent_map = gcc_xo_gpll0_map,
 297         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 298         .clkr.hw.init = &(struct clk_init_data){
 299                 .name = "blsp1_qup4_i2c_apps_clk_src",
 300                 .parent_data = gcc_xo_gpll0,
 301                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 302                 .ops = &clk_rcg2_ops,
 303         },
 304 };
 305
 306 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 307         .cmd_rcgr = 0x07cc,
 308         .mnd_width = 8,
 309         .hid_width = 5,
 310         .parent_map = gcc_xo_gpll0_map,
 311         .freq_tbl = ftbl_blsp1_qup3_4_spi_apps_clk_src,
 312         .clkr.hw.init = &(struct clk_init_data){
 313                 .name = "blsp1_qup4_spi_apps_clk_src",
 314                 .parent_data = gcc_xo_gpll0,
 315                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 316                 .ops = &clk_rcg2_ops,
 317         },
 318 };
 319
 320 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 321         .cmd_rcgr = 0x0860,
 322         .hid_width = 5,
 323         .parent_map = gcc_xo_gpll0_map,
 324         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 325         .clkr.hw.init = &(struct clk_init_data){
 326                 .name = "blsp1_qup5_i2c_apps_clk_src",
 327                 .parent_data = gcc_xo_gpll0,
 328                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 329                 .ops = &clk_rcg2_ops,
 330         },
 331 };
 332
 333 static struct freq_tbl ftbl_blsp1_qup5_spi_apps_clk_src[] = {
 334         F(960000, P_XO, 10, 1, 2),
 335         F(4800000, P_XO, 4, 0, 0),
 336         F(9600000, P_XO, 2, 0, 0),
 337         F(15000000, P_GPLL0, 10, 1, 4),
 338         F(19200000, P_XO, 1, 0, 0),
 339         F(24000000, P_GPLL0, 12.5, 1, 2),
 340         F(25000000, P_GPLL0, 12, 1, 2),
 341         F(40000000, P_GPLL0, 15, 0, 0),
 342         F(42860000, P_GPLL0, 14, 0, 0),
 343         { }
 344 };
 345
 346 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 347         .cmd_rcgr = 0x084c,
 348         .mnd_width = 8,
 349         .hid_width = 5,
 350         .parent_map = gcc_xo_gpll0_map,
 351         .freq_tbl = ftbl_blsp1_qup5_spi_apps_clk_src,
 352         .clkr.hw.init = &(struct clk_init_data){
 353                 .name = "blsp1_qup5_spi_apps_clk_src",
 354                 .parent_data = gcc_xo_gpll0,
 355                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 356                 .ops = &clk_rcg2_ops,
 357         },
 358 };
 359
 360 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 361         .cmd_rcgr = 0x08e0,
 362         .hid_width = 5,
 363         .parent_map = gcc_xo_gpll0_map,
 364         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 365         .clkr.hw.init = &(struct clk_init_data){
 366                 .name = "blsp1_qup6_i2c_apps_clk_src",
 367                 .parent_data = gcc_xo_gpll0,
 368                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 369                 .ops = &clk_rcg2_ops,
 370         },
 371 };
 372
 373 static struct freq_tbl ftbl_blsp1_qup6_spi_apps_clk_src[] = {
 374         F(960000, P_XO, 10, 1, 2),
 375         F(4800000, P_XO, 4, 0, 0),
 376         F(9600000, P_XO, 2, 0, 0),
 377         F(15000000, P_GPLL0, 10, 1, 4),
 378         F(19200000, P_XO, 1, 0, 0),
 379         F(24000000, P_GPLL0, 12.5, 1, 2),
 380         F(27906976, P_GPLL0, 1, 2, 43),
 381         F(41380000, P_GPLL0, 15, 0, 0),
 382         F(42860000, P_GPLL0, 14, 0, 0),
 383         { }
 384 };
 385
 386 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 387         .cmd_rcgr = 0x08cc,
 388         .mnd_width = 8,
 389         .hid_width = 5,
 390         .parent_map = gcc_xo_gpll0_map,
 391         .freq_tbl = ftbl_blsp1_qup6_spi_apps_clk_src,
 392         .clkr.hw.init = &(struct clk_init_data){
 393                 .name = "blsp1_qup6_spi_apps_clk_src",
 394                 .parent_data = gcc_xo_gpll0,
 395                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 396                 .ops = &clk_rcg2_ops,
 397         },
 398 };
 399
 400 static struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
 401         F(3686400, P_GPLL0, 1, 96, 15625),
 402         F(7372800, P_GPLL0, 1, 192, 15625),
 403         F(14745600, P_GPLL0, 1, 384, 15625),
 404         F(16000000, P_GPLL0, 5, 2, 15),
 405         F(19200000, P_XO, 1, 0, 0),
 406         F(24000000, P_GPLL0, 5, 1, 5),
 407         F(32000000, P_GPLL0, 1, 4, 75),
 408         F(40000000, P_GPLL0, 15, 0, 0),
 409         F(46400000, P_GPLL0, 1, 29, 375),
 410         F(48000000, P_GPLL0, 12.5, 0, 0),
 411         F(51200000, P_GPLL0, 1, 32, 375),
 412         F(56000000, P_GPLL0, 1, 7, 75),
 413         F(58982400, P_GPLL0, 1, 1536, 15625),
 414         F(60000000, P_GPLL0, 10, 0, 0),
 415         F(63160000, P_GPLL0, 9.5, 0, 0),
 416         { }
 417 };
 418
 419 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 420         .cmd_rcgr = 0x068c,
 421         .mnd_width = 16,
 422         .hid_width = 5,
 423         .parent_map = gcc_xo_gpll0_map,
 424         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 425         .clkr.hw.init = &(struct clk_init_data){
 426                 .name = "blsp1_uart1_apps_clk_src",
 427                 .parent_data = gcc_xo_gpll0,
 428                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 429                 .ops = &clk_rcg2_ops,
 430         },
 431 };
 432
 433 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 434         .cmd_rcgr = 0x070c,
 435         .mnd_width = 16,
 436         .hid_width = 5,
 437         .parent_map = gcc_xo_gpll0_map,
 438         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 439         .clkr.hw.init = &(struct clk_init_data){
 440                 .name = "blsp1_uart2_apps_clk_src",
 441                 .parent_data = gcc_xo_gpll0,
 442                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 443                 .ops = &clk_rcg2_ops,
 444         },
 445 };
 446
 447 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 448         .cmd_rcgr = 0x078c,
 449         .mnd_width = 16,
 450         .hid_width = 5,
 451         .parent_map = gcc_xo_gpll0_map,
 452         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 453         .clkr.hw.init = &(struct clk_init_data){
 454                 .name = "blsp1_uart3_apps_clk_src",
 455                 .parent_data = gcc_xo_gpll0,
 456                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 457                 .ops = &clk_rcg2_ops,
 458         },
 459 };
 460
 461 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 462         .cmd_rcgr = 0x080c,
 463         .mnd_width = 16,
 464         .hid_width = 5,
 465         .parent_map = gcc_xo_gpll0_map,
 466         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 467         .clkr.hw.init = &(struct clk_init_data){
 468                 .name = "blsp1_uart4_apps_clk_src",
 469                 .parent_data = gcc_xo_gpll0,
 470                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 471                 .ops = &clk_rcg2_ops,
 472         },
 473 };
 474
 475 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 476         .cmd_rcgr = 0x088c,
 477         .mnd_width = 16,
 478         .hid_width = 5,
 479         .parent_map = gcc_xo_gpll0_map,
 480         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 481         .clkr.hw.init = &(struct clk_init_data){
 482                 .name = "blsp1_uart5_apps_clk_src",
 483                 .parent_data = gcc_xo_gpll0,
 484                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 485                 .ops = &clk_rcg2_ops,
 486         },
 487 };
 488
 489 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 490         .cmd_rcgr = 0x090c,
 491         .mnd_width = 16,
 492         .hid_width = 5,
 493         .parent_map = gcc_xo_gpll0_map,
 494         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 495         .clkr.hw.init = &(struct clk_init_data){
 496                 .name = "blsp1_uart6_apps_clk_src",
 497                 .parent_data = gcc_xo_gpll0,
 498                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 499                 .ops = &clk_rcg2_ops,
 500         },
 501 };
 502
 503 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
 504         .cmd_rcgr = 0x09a0,
 505         .hid_width = 5,
 506         .parent_map = gcc_xo_gpll0_map,
 507         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 508         .clkr.hw.init = &(struct clk_init_data){
 509                 .name = "blsp2_qup1_i2c_apps_clk_src",
 510                 .parent_data = gcc_xo_gpll0,
 511                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 512                 .ops = &clk_rcg2_ops,
 513         },
 514 };
 515
 516 static struct freq_tbl ftbl_blsp2_qup1_2_spi_apps_clk_src[] = {
 517         F(960000, P_XO, 10, 1, 2),
 518         F(4800000, P_XO, 4, 0, 0),
 519         F(9600000, P_XO, 2, 0, 0),
 520         F(15000000, P_GPLL0, 10, 1, 4),
 521         F(19200000, P_XO, 1, 0, 0),
 522         F(24000000, P_GPLL0, 12.5, 1, 2),
 523         F(25000000, P_GPLL0, 12, 1, 2),
 524         F(42860000, P_GPLL0, 14, 0, 0),
 525         F(44440000, P_GPLL0, 13.5, 0, 0),
 526         { }
 527 };
 528
 529 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
 530         .cmd_rcgr = 0x098c,
 531         .mnd_width = 8,
 532         .hid_width = 5,
 533         .parent_map = gcc_xo_gpll0_map,
 534         .freq_tbl = ftbl_blsp2_qup1_2_spi_apps_clk_src,
 535         .clkr.hw.init = &(struct clk_init_data){
 536                 .name = "blsp2_qup1_spi_apps_clk_src",
 537                 .parent_data = gcc_xo_gpll0,
 538                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 539                 .ops = &clk_rcg2_ops,
 540         },
 541 };
 542
 543 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
 544         .cmd_rcgr = 0x0a20,
 545         .hid_width = 5,
 546         .parent_map = gcc_xo_gpll0_map,
 547         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 548         .clkr.hw.init = &(struct clk_init_data){
 549                 .name = "blsp2_qup2_i2c_apps_clk_src",
 550                 .parent_data = gcc_xo_gpll0,
 551                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 552                 .ops = &clk_rcg2_ops,
 553         },
 554 };
 555
 556 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
 557         .cmd_rcgr = 0x0a0c,
 558         .mnd_width = 8,
 559         .hid_width = 5,
 560         .parent_map = gcc_xo_gpll0_map,
 561         .freq_tbl = ftbl_blsp2_qup1_2_spi_apps_clk_src,
 562         .clkr.hw.init = &(struct clk_init_data){
 563                 .name = "blsp2_qup2_spi_apps_clk_src",
 564                 .parent_data = gcc_xo_gpll0,
 565                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 566                 .ops = &clk_rcg2_ops,
 567         },
 568 };
 569
 570 static struct freq_tbl ftbl_blsp2_qup3_4_spi_apps_clk_src[] = {
 571         F(960000, P_XO, 10, 1, 2),
 572         F(4800000, P_XO, 4, 0, 0),
 573         F(9600000, P_XO, 2, 0, 0),
 574         F(15000000, P_GPLL0, 10, 1, 4),
 575         F(19200000, P_XO, 1, 0, 0),
 576         F(24000000, P_GPLL0, 12.5, 1, 2),
 577         F(25000000, P_GPLL0, 12, 1, 2),
 578         F(42860000, P_GPLL0, 14, 0, 0),
 579         F(48000000, P_GPLL0, 12.5, 0, 0),
 580         { }
 581 };
 582
 583 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
 584         .cmd_rcgr = 0x0aa0,
 585         .hid_width = 5,
 586         .parent_map = gcc_xo_gpll0_map,
 587         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 588         .clkr.hw.init = &(struct clk_init_data){
 589                 .name = "blsp2_qup3_i2c_apps_clk_src",
 590                 .parent_data = gcc_xo_gpll0,
 591                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 592                 .ops = &clk_rcg2_ops,
 593         },
 594 };
 595
 596 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
 597         .cmd_rcgr = 0x0a8c,
 598         .mnd_width = 8,
 599         .hid_width = 5,
 600         .parent_map = gcc_xo_gpll0_map,
 601         .freq_tbl = ftbl_blsp2_qup3_4_spi_apps_clk_src,
 602         .clkr.hw.init = &(struct clk_init_data){
 603                 .name = "blsp2_qup3_spi_apps_clk_src",
 604                 .parent_data = gcc_xo_gpll0,
 605                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 606                 .ops = &clk_rcg2_ops,
 607         },
 608 };
 609
 610 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
 611         .cmd_rcgr = 0x0b20,
 612         .hid_width = 5,
 613         .parent_map = gcc_xo_gpll0_map,
 614         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 615         .clkr.hw.init = &(struct clk_init_data){
 616                 .name = "blsp2_qup4_i2c_apps_clk_src",
 617                 .parent_data = gcc_xo_gpll0,
 618                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 619                 .ops = &clk_rcg2_ops,
 620         },
 621 };
 622
 623 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
 624         .cmd_rcgr = 0x0b0c,
 625         .mnd_width = 8,
 626         .hid_width = 5,
 627         .parent_map = gcc_xo_gpll0_map,
 628         .freq_tbl = ftbl_blsp2_qup3_4_spi_apps_clk_src,
 629         .clkr.hw.init = &(struct clk_init_data){
 630                 .name = "blsp2_qup4_spi_apps_clk_src",
 631                 .parent_data = gcc_xo_gpll0,
 632                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 633                 .ops = &clk_rcg2_ops,
 634         },
 635 };
 636
 637 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
 638         .cmd_rcgr = 0x0ba0,
 639         .hid_width = 5,
 640         .parent_map = gcc_xo_gpll0_map,
 641         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 642         .clkr.hw.init = &(struct clk_init_data){
 643                 .name = "blsp2_qup5_i2c_apps_clk_src",
 644                 .parent_data = gcc_xo_gpll0,
 645                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 646                 .ops = &clk_rcg2_ops,
 647         },
 648 };
 649
 650 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
 651         .cmd_rcgr = 0x0b8c,
 652         .mnd_width = 8,
 653         .hid_width = 5,
 654         .parent_map = gcc_xo_gpll0_map,
 655         /* BLSP1 QUP1 and BLSP2 QUP5 use the same freqs */
 656         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 657         .clkr.hw.init = &(struct clk_init_data){
 658                 .name = "blsp2_qup5_spi_apps_clk_src",
 659                 .parent_data = gcc_xo_gpll0,
 660                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 661                 .ops = &clk_rcg2_ops,
 662         },
 663 };
 664
 665 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
 666         .cmd_rcgr = 0x0c20,
 667         .hid_width = 5,
 668         .parent_map = gcc_xo_gpll0_map,
 669         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 670         .clkr.hw.init = &(struct clk_init_data){
 671                 .name = "blsp2_qup6_i2c_apps_clk_src",
 672                 .parent_data = gcc_xo_gpll0,
 673                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 674                 .ops = &clk_rcg2_ops,
 675         },
 676 };
 677
 678 static struct freq_tbl ftbl_blsp2_qup6_spi_apps_clk_src[] = {
 679         F(960000, P_XO, 10, 1, 2),
 680         F(4800000, P_XO, 4, 0, 0),
 681         F(9600000, P_XO, 2, 0, 0),
 682         F(15000000, P_GPLL0, 10, 1, 4),
 683         F(19200000, P_XO, 1, 0, 0),
 684         F(24000000, P_GPLL0, 12.5, 1, 2),
 685         F(25000000, P_GPLL0, 12, 1, 2),
 686         F(44440000, P_GPLL0, 13.5, 0, 0),
 687         F(48000000, P_GPLL0, 12.5, 0, 0),
 688         { }
 689 };
 690
 691 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
 692         .cmd_rcgr = 0x0c0c,
 693         .mnd_width = 8,
 694         .hid_width = 5,
 695         .parent_map = gcc_xo_gpll0_map,
 696         .freq_tbl = ftbl_blsp2_qup6_spi_apps_clk_src,
 697         .clkr.hw.init = &(struct clk_init_data){
 698                 .name = "blsp2_qup6_spi_apps_clk_src",
 699                 .parent_data = gcc_xo_gpll0,
 700                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 701                 .ops = &clk_rcg2_ops,
 702         },
 703 };
 704
 705 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
 706         .cmd_rcgr = 0x09cc,
 707         .mnd_width = 16,
 708         .hid_width = 5,
 709         .parent_map = gcc_xo_gpll0_map,
 710         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 711         .clkr.hw.init = &(struct clk_init_data){
 712                 .name = "blsp2_uart1_apps_clk_src",
 713                 .parent_data = gcc_xo_gpll0,
 714                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 715                 .ops = &clk_rcg2_ops,
 716         },
 717 };
 718
 719 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
 720         .cmd_rcgr = 0x0a4c,
 721         .mnd_width = 16,
 722         .hid_width = 5,
 723         .parent_map = gcc_xo_gpll0_map,
 724         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 725         .clkr.hw.init = &(struct clk_init_data){
 726                 .name = "blsp2_uart2_apps_clk_src",
 727                 .parent_data = gcc_xo_gpll0,
 728                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 729                 .ops = &clk_rcg2_ops,
 730         },
 731 };
 732
 733 static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
 734         .cmd_rcgr = 0x0acc,
 735         .mnd_width = 16,
 736         .hid_width = 5,
 737         .parent_map = gcc_xo_gpll0_map,
 738         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 739         .clkr.hw.init = &(struct clk_init_data){
 740                 .name = "blsp2_uart3_apps_clk_src",
 741                 .parent_data = gcc_xo_gpll0,
 742                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 743                 .ops = &clk_rcg2_ops,
 744         },
 745 };
 746
 747 static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
 748         .cmd_rcgr = 0x0b4c,
 749         .mnd_width = 16,
 750         .hid_width = 5,
 751         .parent_map = gcc_xo_gpll0_map,
 752         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 753         .clkr.hw.init = &(struct clk_init_data){
 754                 .name = "blsp2_uart4_apps_clk_src",
 755                 .parent_data = gcc_xo_gpll0,
 756                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 757                 .ops = &clk_rcg2_ops,
 758         },
 759 };
 760
 761 static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
 762         .cmd_rcgr = 0x0bcc,
 763         .mnd_width = 16,
 764         .hid_width = 5,
 765         .parent_map = gcc_xo_gpll0_map,
 766         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 767         .clkr.hw.init = &(struct clk_init_data){
 768                 .name = "blsp2_uart5_apps_clk_src",
 769                 .parent_data = gcc_xo_gpll0,
 770                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 771                 .ops = &clk_rcg2_ops,
 772         },
 773 };
 774
 775 static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
 776         .cmd_rcgr = 0x0c4c,
 777         .mnd_width = 16,
 778         .hid_width = 5,
 779         .parent_map = gcc_xo_gpll0_map,
 780         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 781         .clkr.hw.init = &(struct clk_init_data){
 782                 .name = "blsp2_uart6_apps_clk_src",
 783                 .parent_data = gcc_xo_gpll0,
 784                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 785                 .ops = &clk_rcg2_ops,
 786         },
 787 };
 788
 789 static struct freq_tbl ftbl_gp1_clk_src[] = {
 790         F(19200000, P_XO, 1, 0, 0),
 791         F(100000000, P_GPLL0, 6, 0, 0),
 792         F(200000000, P_GPLL0, 3, 0, 0),
 793         { }
 794 };
 795
 796 static struct clk_rcg2 gp1_clk_src = {
 797         .cmd_rcgr = 0x1904,
 798         .mnd_width = 8,
 799         .hid_width = 5,
 800         .parent_map = gcc_xo_gpll0_map,
 801         .freq_tbl = ftbl_gp1_clk_src,
 802         .clkr.hw.init = &(struct clk_init_data){
 803                 .name = "gp1_clk_src",
 804                 .parent_data = gcc_xo_gpll0,
 805                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 806                 .ops = &clk_rcg2_ops,
 807         },
 808 };
 809
 810 static struct freq_tbl ftbl_gp2_clk_src[] = {
 811         F(19200000, P_XO, 1, 0, 0),
 812         F(100000000, P_GPLL0, 6, 0, 0),
 813         F(200000000, P_GPLL0, 3, 0, 0),
 814         { }
 815 };
 816
 817 static struct clk_rcg2 gp2_clk_src = {
 818         .cmd_rcgr = 0x1944,
 819         .mnd_width = 8,
 820         .hid_width = 5,
 821         .parent_map = gcc_xo_gpll0_map,
 822         .freq_tbl = ftbl_gp2_clk_src,
 823         .clkr.hw.init = &(struct clk_init_data){
 824                 .name = "gp2_clk_src",
 825                 .parent_data = gcc_xo_gpll0,
 826                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 827                 .ops = &clk_rcg2_ops,
 828         },
 829 };
 830
 831 static struct freq_tbl ftbl_gp3_clk_src[] = {
 832         F(19200000, P_XO, 1, 0, 0),
 833         F(100000000, P_GPLL0, 6, 0, 0),
 834         F(200000000, P_GPLL0, 3, 0, 0),
 835         { }
 836 };
 837
 838 static struct clk_rcg2 gp3_clk_src = {
 839         .cmd_rcgr = 0x1984,
 840         .mnd_width = 8,
 841         .hid_width = 5,
 842         .parent_map = gcc_xo_gpll0_map,
 843         .freq_tbl = ftbl_gp3_clk_src,
 844         .clkr.hw.init = &(struct clk_init_data){
 845                 .name = "gp3_clk_src",
 846                 .parent_data = gcc_xo_gpll0,
 847                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 848                 .ops = &clk_rcg2_ops,
 849         },
 850 };
 851
 852 static struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
 853         F(1011000, P_XO, 1, 1, 19),
 854         { }
 855 };
 856
 857 static struct clk_rcg2 pcie_0_aux_clk_src = {
 858         .cmd_rcgr = 0x1b00,
 859         .mnd_width = 8,
 860         .hid_width = 5,
 861         .freq_tbl = ftbl_pcie_0_aux_clk_src,
 862         .clkr.hw.init = &(struct clk_init_data){
 863                 .name = "pcie_0_aux_clk_src",
 864                 .parent_data = &(const struct clk_parent_data){
 865                                 .fw_name = "xo",
 866                 },
 867                 .num_parents = 1,
 868                 .ops = &clk_rcg2_ops,
 869         },
 870 };
 871
 872 static struct freq_tbl ftbl_pcie_pipe_clk_src[] = {
 873         F(125000000, P_XO, 1, 0, 0),
 874         { }
 875 };
 876
 877 static struct clk_rcg2 pcie_0_pipe_clk_src = {
 878         .cmd_rcgr = 0x1adc,
 879         .hid_width = 5,
 880         .freq_tbl = ftbl_pcie_pipe_clk_src,
 881         .clkr.hw.init = &(struct clk_init_data){
 882                 .name = "pcie_0_pipe_clk_src",
 883                 .parent_data = &(const struct clk_parent_data){
 884                                 .fw_name = "xo",
 885                 },
 886                 .num_parents = 1,
 887                 .ops = &clk_rcg2_ops,
 888         },
 889 };
 890
 891 static struct freq_tbl ftbl_pcie_1_aux_clk_src[] = {
 892         F(1011000, P_XO, 1, 1, 19),
 893         { }
 894 };
 895
 896 static struct clk_rcg2 pcie_1_aux_clk_src = {
 897         .cmd_rcgr = 0x1b80,
 898         .mnd_width = 8,
 899         .hid_width = 5,
 900         .freq_tbl = ftbl_pcie_1_aux_clk_src,
 901         .clkr.hw.init = &(struct clk_init_data){
 902                 .name = "pcie_1_aux_clk_src",
 903                 .parent_data = &(const struct clk_parent_data){
 904                                 .fw_name = "xo",
 905                 },
 906                 .num_parents = 1,
 907                 .ops = &clk_rcg2_ops,
 908         },
 909 };
 910
 911 static struct clk_rcg2 pcie_1_pipe_clk_src = {
 912         .cmd_rcgr = 0x1b5c,
 913         .hid_width = 5,
 914         .freq_tbl = ftbl_pcie_pipe_clk_src,
 915         .clkr.hw.init = &(struct clk_init_data){
 916                 .name = "pcie_1_pipe_clk_src",
 917                 .parent_data = &(const struct clk_parent_data){
 918                                 .fw_name = "xo",
 919                 },
 920                 .num_parents = 1,
 921                 .ops = &clk_rcg2_ops,
 922         },
 923 };
 924
 925 static struct freq_tbl ftbl_pdm2_clk_src[] = {
 926         F(60000000, P_GPLL0, 10, 0, 0),
 927         { }
 928 };
 929
 930 static struct clk_rcg2 pdm2_clk_src = {
 931         .cmd_rcgr = 0x0cd0,
 932         .hid_width = 5,
 933         .parent_map = gcc_xo_gpll0_map,
 934         .freq_tbl = ftbl_pdm2_clk_src,
 935         .clkr.hw.init = &(struct clk_init_data){
 936                 .name = "pdm2_clk_src",
 937                 .parent_data = gcc_xo_gpll0,
 938                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 939                 .ops = &clk_rcg2_ops,
 940         },
 941 };
 942
 943 static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
 944         F(144000, P_XO, 16, 3, 25),
 945         F(400000, P_XO, 12, 1, 4),
 946         F(20000000, P_GPLL0, 15, 1, 2),
 947         F(25000000, P_GPLL0, 12, 1, 2),
 948         F(50000000, P_GPLL0, 12, 0, 0),
 949         F(100000000, P_GPLL0, 6, 0, 0),
 950         F(192000000, P_GPLL4, 2, 0, 0),
 951         F(384000000, P_GPLL4, 1, 0, 0),
 952         { }
 953 };
 954
 955 static struct freq_tbl ftbl_sdcc1_apps_clk_src_8992[] = {
 956         F(144000, P_XO, 16, 3, 25),
 957         F(400000, P_XO, 12, 1, 4),
 958         F(20000000, P_GPLL0, 15, 1, 2),
 959         F(25000000, P_GPLL0, 12, 1, 2),
 960         F(50000000, P_GPLL0, 12, 0, 0),
 961         F(100000000, P_GPLL0, 6, 0, 0),
 962         F(172000000, P_GPLL4, 2, 0, 0),
 963         F(344000000, P_GPLL4, 1, 0, 0),
 964         { }
 965 };
 966
 967 static struct clk_rcg2 sdcc1_apps_clk_src = {
 968         .cmd_rcgr = 0x04d0,
 969         .mnd_width = 8,
 970         .hid_width = 5,
 971         .parent_map = gcc_xo_gpll0_gpll4_map,
 972         .freq_tbl = ftbl_sdcc1_apps_clk_src,
 973         .clkr.hw.init = &(struct clk_init_data){
 974                 .name = "sdcc1_apps_clk_src",
 975                 .parent_data = gcc_xo_gpll0_gpll4,
 976                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
 977                 .ops = &clk_rcg2_floor_ops,
 978         },
 979 };
 980
 981 static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = {
 982         F(144000, P_XO, 16, 3, 25),
 983         F(400000, P_XO, 12, 1, 4),
 984         F(20000000, P_GPLL0, 15, 1, 2),
 985         F(25000000, P_GPLL0, 12, 1, 2),
 986         F(50000000, P_GPLL0, 12, 0, 0),
 987         F(100000000, P_GPLL0, 6, 0, 0),
 988         F(200000000, P_GPLL0, 3, 0, 0),
 989         { }
 990 };
 991
 992 static struct clk_rcg2 sdcc2_apps_clk_src = {
 993         .cmd_rcgr = 0x0510,
 994         .mnd_width = 8,
 995         .hid_width = 5,
 996         .parent_map = gcc_xo_gpll0_map,
 997         .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
 998         .clkr.hw.init = &(struct clk_init_data){
 999                 .name = "sdcc2_apps_clk_src",
1000                 .parent_data = gcc_xo_gpll0,
1001                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1002                 .ops = &clk_rcg2_floor_ops,
1003         },
1004 };
1005
1006 static struct clk_rcg2 sdcc3_apps_clk_src = {
1007         .cmd_rcgr = 0x0550,
1008         .mnd_width = 8,
1009         .hid_width = 5,
1010         .parent_map = gcc_xo_gpll0_map,
1011         .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
1012         .clkr.hw.init = &(struct clk_init_data){
1013                 .name = "sdcc3_apps_clk_src",
1014                 .parent_data = gcc_xo_gpll0,
1015                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1016                 .ops = &clk_rcg2_floor_ops,
1017         },
1018 };
1019
1020 static struct clk_rcg2 sdcc4_apps_clk_src = {
1021         .cmd_rcgr = 0x0590,
1022         .mnd_width = 8,
1023         .hid_width = 5,
1024         .parent_map = gcc_xo_gpll0_map,
1025         .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
1026         .clkr.hw.init = &(struct clk_init_data){
1027                 .name = "sdcc4_apps_clk_src",
1028                 .parent_data = gcc_xo_gpll0,
1029                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1030                 .ops = &clk_rcg2_floor_ops,
1031         },
1032 };
1033
1034 static struct freq_tbl ftbl_tsif_ref_clk_src[] = {
1035         F(105500, P_XO, 1, 1, 182),
1036         { }
1037 };
1038
1039 static struct clk_rcg2 tsif_ref_clk_src = {
1040         .cmd_rcgr = 0x0d90,
1041         .mnd_width = 8,
1042         .hid_width = 5,
1043         .freq_tbl = ftbl_tsif_ref_clk_src,
1044         .clkr.hw.init = &(struct clk_init_data){
1045                 .name = "tsif_ref_clk_src",
1046                 .parent_data = &(const struct clk_parent_data){
1047                                 .fw_name = "xo",
1048                 },
1049                 .num_parents = 1,
1050                 .ops = &clk_rcg2_ops,
1051         },
1052 };
1053
1054 static struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
1055         F(19200000, P_XO, 1, 0, 0),
1056         F(60000000, P_GPLL0, 10, 0, 0),
1057         { }
1058 };
1059
1060 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1061         .cmd_rcgr = 0x03e8,
1062         .hid_width = 5,
1063         .parent_map = gcc_xo_gpll0_map,
1064         .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
1065         .clkr.hw.init = &(struct clk_init_data){
1066                 .name = "usb30_mock_utmi_clk_src",
1067                 .parent_data = gcc_xo_gpll0,
1068                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1069                 .ops = &clk_rcg2_ops,
1070         },
1071 };
1072
1073 static struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
1074         F(1200000, P_XO, 16, 0, 0),
1075         { }
1076 };
1077
1078 static struct clk_rcg2 usb3_phy_aux_clk_src = {
1079         .cmd_rcgr = 0x1414,
1080         .hid_width = 5,
1081         .freq_tbl = ftbl_usb3_phy_aux_clk_src,
1082         .clkr.hw.init = &(struct clk_init_data){
1083                 .name = "usb3_phy_aux_clk_src",
1084                 .parent_data = &(const struct clk_parent_data){
1085                                 .fw_name = "xo",
1086                 },
1087                 .num_parents = 1,
1088                 .ops = &clk_rcg2_ops,
1089         },
1090 };
1091
1092 static struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
1093         F(75000000, P_GPLL0, 8, 0, 0),
1094         { }
1095 };
1096
1097 static struct clk_rcg2 usb_hs_system_clk_src = {
1098         .cmd_rcgr = 0x0490,
1099         .hid_width = 5,
1100         .parent_map = gcc_xo_gpll0_map,
1101         .freq_tbl = ftbl_usb_hs_system_clk_src,
1102         .clkr.hw.init = &(struct clk_init_data){
1103                 .name = "usb_hs_system_clk_src",
1104                 .parent_data = gcc_xo_gpll0,
1105                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1106                 .ops = &clk_rcg2_ops,
1107         },
1108 };
1109
1110 static struct clk_branch gcc_blsp1_ahb_clk = {
1111         .halt_reg = 0x05c4,
1112         .halt_check = BRANCH_HALT_VOTED,
1113         .clkr = {
1114                 .enable_reg = 0x1484,
1115                 .enable_mask = BIT(17),
1116                 .hw.init = &(struct clk_init_data){
1117                         .name = "gcc_blsp1_ahb_clk",
1118                         .ops = &clk_branch2_ops,
1119                 },
1120         },
1121 };
1122
1123 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1124         .halt_reg = 0x0648,
1125         .clkr = {
1126                 .enable_reg = 0x0648,
1127                 .enable_mask = BIT(0),
1128                 .hw.init = &(struct clk_init_data){
1129                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
1130                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_i2c_apps_clk_src.clkr.hw },
1131                         .num_parents = 1,
1132                         .flags = CLK_SET_RATE_PARENT,
1133                         .ops = &clk_branch2_ops,
1134                 },
1135         },
1136 };
1137
1138 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1139         .halt_reg = 0x0644,
1140         .clkr = {
1141                 .enable_reg = 0x0644,
1142                 .enable_mask = BIT(0),
1143                 .hw.init = &(struct clk_init_data){
1144                         .name = "gcc_blsp1_qup1_spi_apps_clk",
1145                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_spi_apps_clk_src.clkr.hw },
1146                         .num_parents = 1,
1147                         .flags = CLK_SET_RATE_PARENT,
1148                         .ops = &clk_branch2_ops,
1149                 },
1150         },
1151 };
1152
1153 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1154         .halt_reg = 0x06c8,
1155         .clkr = {
1156                 .enable_reg = 0x06c8,
1157                 .enable_mask = BIT(0),
1158                 .hw.init = &(struct clk_init_data){
1159                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
1160                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_i2c_apps_clk_src.clkr.hw },
1161                         .num_parents = 1,
1162                         .flags = CLK_SET_RATE_PARENT,
1163                         .ops = &clk_branch2_ops,
1164                 },
1165         },
1166 };
1167
1168 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1169         .halt_reg = 0x06c4,
1170         .clkr = {
1171                 .enable_reg = 0x06c4,
1172                 .enable_mask = BIT(0),
1173                 .hw.init = &(struct clk_init_data){
1174                         .name = "gcc_blsp1_qup2_spi_apps_clk",
1175                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_spi_apps_clk_src.clkr.hw },
1176                         .num_parents = 1,
1177                         .flags = CLK_SET_RATE_PARENT,
1178                         .ops = &clk_branch2_ops,
1179                 },
1180         },
1181 };
1182
1183 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1184         .halt_reg = 0x0748,
1185         .clkr = {
1186                 .enable_reg = 0x0748,
1187                 .enable_mask = BIT(0),
1188                 .hw.init = &(struct clk_init_data){
1189                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
1190                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_i2c_apps_clk_src.clkr.hw },
1191                         .num_parents = 1,
1192                         .flags = CLK_SET_RATE_PARENT,
1193                         .ops = &clk_branch2_ops,
1194                 },
1195         },
1196 };
1197
1198 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1199         .halt_reg = 0x0744,
1200         .clkr = {
1201                 .enable_reg = 0x0744,
1202                 .enable_mask = BIT(0),
1203                 .hw.init = &(struct clk_init_data){
1204                         .name = "gcc_blsp1_qup3_spi_apps_clk",
1205                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_spi_apps_clk_src.clkr.hw },
1206                         .num_parents = 1,
1207                         .flags = CLK_SET_RATE_PARENT,
1208                         .ops = &clk_branch2_ops,
1209                 },
1210         },
1211 };
1212
1213 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1214         .halt_reg = 0x07c8,
1215         .clkr = {
1216                 .enable_reg = 0x07c8,
1217                 .enable_mask = BIT(0),
1218                 .hw.init = &(struct clk_init_data){
1219                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
1220                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_i2c_apps_clk_src.clkr.hw },
1221                         .num_parents = 1,
1222                         .flags = CLK_SET_RATE_PARENT,
1223                         .ops = &clk_branch2_ops,
1224                 },
1225         },
1226 };
1227
1228 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1229         .halt_reg = 0x07c4,
1230         .clkr = {
1231                 .enable_reg = 0x07c4,
1232                 .enable_mask = BIT(0),
1233                 .hw.init = &(struct clk_init_data){
1234                         .name = "gcc_blsp1_qup4_spi_apps_clk",
1235                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_spi_apps_clk_src.clkr.hw },
1236                         .num_parents = 1,
1237                         .flags = CLK_SET_RATE_PARENT,
1238                         .ops = &clk_branch2_ops,
1239                 },
1240         },
1241 };
1242
1243 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1244         .halt_reg = 0x0848,
1245         .clkr = {
1246                 .enable_reg = 0x0848,
1247                 .enable_mask = BIT(0),
1248                 .hw.init = &(struct clk_init_data){
1249                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
1250                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_i2c_apps_clk_src.clkr.hw },
1251                         .num_parents = 1,
1252                         .flags = CLK_SET_RATE_PARENT,
1253                         .ops = &clk_branch2_ops,
1254                 },
1255         },
1256 };
1257
1258 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1259         .halt_reg = 0x0844,
1260         .clkr = {
1261                 .enable_reg = 0x0844,
1262                 .enable_mask = BIT(0),
1263                 .hw.init = &(struct clk_init_data){
1264                         .name = "gcc_blsp1_qup5_spi_apps_clk",
1265                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_spi_apps_clk_src.clkr.hw },
1266                         .num_parents = 1,
1267                         .flags = CLK_SET_RATE_PARENT,
1268                         .ops = &clk_branch2_ops,
1269                 },
1270         },
1271 };
1272
1273 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1274         .halt_reg = 0x08c8,
1275         .clkr = {
1276                 .enable_reg = 0x08c8,
1277                 .enable_mask = BIT(0),
1278                 .hw.init = &(struct clk_init_data){
1279                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
1280                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
1281                         .num_parents = 1,
1282                         .flags = CLK_SET_RATE_PARENT,
1283                         .ops = &clk_branch2_ops,
1284                 },
1285         },
1286 };
1287
1288 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1289         .halt_reg = 0x08c4,
1290         .clkr = {
1291                 .enable_reg = 0x08c4,
1292                 .enable_mask = BIT(0),
1293                 .hw.init = &(struct clk_init_data){
1294                         .name = "gcc_blsp1_qup6_spi_apps_clk",
1295                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_spi_apps_clk_src.clkr.hw },
1296                         .num_parents = 1,
1297                         .flags = CLK_SET_RATE_PARENT,
1298                         .ops = &clk_branch2_ops,
1299                 },
1300         },
1301 };
1302
1303 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1304         .halt_reg = 0x0684,
1305         .clkr = {
1306                 .enable_reg = 0x0684,
1307                 .enable_mask = BIT(0),
1308                 .hw.init = &(struct clk_init_data){
1309                         .name = "gcc_blsp1_uart1_apps_clk",
1310                         .parent_hws = (const struct clk_hw *[]){ &blsp1_uart1_apps_clk_src.clkr.hw },
1311                         .num_parents = 1,
1312                         .flags = CLK_SET_RATE_PARENT,
1313                         .ops = &clk_branch2_ops,
1314                 },
1315         },
1316 };
1317
1318 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1319         .halt_reg = 0x0704,
1320         .clkr = {
1321                 .enable_reg = 0x0704,
1322                 .enable_mask = BIT(0),
1323                 .hw.init = &(struct clk_init_data){
1324                         .name = "gcc_blsp1_uart2_apps_clk",
1325                         .parent_hws = (const struct clk_hw *[]){ &blsp1_uart2_apps_clk_src.clkr.hw },
1326                         .num_parents = 1,
1327                         .flags = CLK_SET_RATE_PARENT,
1328                         .ops = &clk_branch2_ops,
1329                 },
1330         },
1331 };
1332
1333 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1334         .halt_reg = 0x0784,
1335         .clkr = {
1336                 .enable_reg = 0x0784,
1337                 .enable_mask = BIT(0),
1338                 .hw.init = &(struct clk_init_data){
1339                         .name = "gcc_blsp1_uart3_apps_clk",
1340                         .parent_hws = (const struct clk_hw *[]){ &blsp1_uart3_apps_clk_src.clkr.hw },
1341                         .num_parents = 1,
1342                         .flags = CLK_SET_RATE_PARENT,
1343                         .ops = &clk_branch2_ops,
1344                 },
1345         },
1346 };
1347
1348 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1349         .halt_reg = 0x0804,
1350         .clkr = {
1351                 .enable_reg = 0x0804,
1352                 .enable_mask = BIT(0),
1353                 .hw.init = &(struct clk_init_data){
1354                         .name = "gcc_blsp1_uart4_apps_clk",
1355                         .parent_hws = (const struct clk_hw *[]){ &blsp1_uart4_apps_clk_src.clkr.hw },
1356                         .num_parents = 1,
1357                         .flags = CLK_SET_RATE_PARENT,
1358                         .ops = &clk_branch2_ops,
1359                 },
1360         },
1361 };
1362
1363 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1364         .halt_reg = 0x0884,
1365         .clkr = {
1366                 .enable_reg = 0x0884,
1367                 .enable_mask = BIT(0),
1368                 .hw.init = &(struct clk_init_data){
1369                         .name = "gcc_blsp1_uart5_apps_clk",
1370                         .parent_hws = (const struct clk_hw *[]){ &blsp1_uart5_apps_clk_src.clkr.hw },
1371                         .num_parents = 1,
1372                         .flags = CLK_SET_RATE_PARENT,
1373                         .ops = &clk_branch2_ops,
1374                 },
1375         },
1376 };
1377
1378 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1379         .halt_reg = 0x0904,
1380         .clkr = {
1381                 .enable_reg = 0x0904,
1382                 .enable_mask = BIT(0),
1383                 .hw.init = &(struct clk_init_data){
1384                         .name = "gcc_blsp1_uart6_apps_clk",
1385                         .parent_hws = (const struct clk_hw *[]){ &blsp1_uart6_apps_clk_src.clkr.hw },
1386                         .num_parents = 1,
1387                         .flags = CLK_SET_RATE_PARENT,
1388                         .ops = &clk_branch2_ops,
1389                 },
1390         },
1391 };
1392
1393 static struct clk_branch gcc_blsp2_ahb_clk = {
1394         .halt_reg = 0x0944,
1395         .halt_check = BRANCH_HALT_VOTED,
1396         .clkr = {
1397                 .enable_reg = 0x1484,
1398                 .enable_mask = BIT(15),
1399                 .hw.init = &(struct clk_init_data){
1400                         .name = "gcc_blsp2_ahb_clk",
1401                         .ops = &clk_branch2_ops,
1402                 },
1403         },
1404 };
1405
1406 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1407         .halt_reg = 0x0988,
1408         .clkr = {
1409                 .enable_reg = 0x0988,
1410                 .enable_mask = BIT(0),
1411                 .hw.init = &(struct clk_init_data){
1412                         .name = "gcc_blsp2_qup1_i2c_apps_clk",
1413                         .parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_i2c_apps_clk_src.clkr.hw },
1414                         .num_parents = 1,
1415                         .flags = CLK_SET_RATE_PARENT,
1416                         .ops = &clk_branch2_ops,
1417                 },
1418         },
1419 };
1420
1421 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1422         .halt_reg = 0x0984,
1423         .clkr = {
1424                 .enable_reg = 0x0984,
1425                 .enable_mask = BIT(0),
1426                 .hw.init = &(struct clk_init_data){
1427                         .name = "gcc_blsp2_qup1_spi_apps_clk",
1428                         .parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_spi_apps_clk_src.clkr.hw },
1429                         .num_parents = 1,
1430                         .flags = CLK_SET_RATE_PARENT,
1431                         .ops = &clk_branch2_ops,
1432                 },
1433         },
1434 };
1435
1436 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1437         .halt_reg = 0x0a08,
1438         .clkr = {
1439                 .enable_reg = 0x0a08,
1440                 .enable_mask = BIT(0),
1441                 .hw.init = &(struct clk_init_data){
1442                         .name = "gcc_blsp2_qup2_i2c_apps_clk",
1443                         .parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_i2c_apps_clk_src.clkr.hw },
1444                         .num_parents = 1,
1445                         .flags = CLK_SET_RATE_PARENT,
1446                         .ops = &clk_branch2_ops,
1447                 },
1448         },
1449 };
1450
1451 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1452         .halt_reg = 0x0a04,
1453         .clkr = {
1454                 .enable_reg = 0x0a04,
1455                 .enable_mask = BIT(0),
1456                 .hw.init = &(struct clk_init_data){
1457                         .name = "gcc_blsp2_qup2_spi_apps_clk",
1458                         .parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_spi_apps_clk_src.clkr.hw },
1459                         .num_parents = 1,
1460                         .flags = CLK_SET_RATE_PARENT,
1461                         .ops = &clk_branch2_ops,
1462                 },
1463         },
1464 };
1465
1466 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1467         .halt_reg = 0x0a88,
1468         .clkr = {
1469                 .enable_reg = 0x0a88,
1470                 .enable_mask = BIT(0),
1471                 .hw.init = &(struct clk_init_data){
1472                         .name = "gcc_blsp2_qup3_i2c_apps_clk",
1473                         .parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_i2c_apps_clk_src.clkr.hw },
1474                         .num_parents = 1,
1475                         .flags = CLK_SET_RATE_PARENT,
1476                         .ops = &clk_branch2_ops,
1477                 },
1478         },
1479 };
1480
1481 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1482         .halt_reg = 0x0a84,
1483         .clkr = {
1484                 .enable_reg = 0x0a84,
1485                 .enable_mask = BIT(0),
1486                 .hw.init = &(struct clk_init_data){
1487                         .name = "gcc_blsp2_qup3_spi_apps_clk",
1488                         .parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_spi_apps_clk_src.clkr.hw },
1489                         .num_parents = 1,
1490                         .flags = CLK_SET_RATE_PARENT,
1491                         .ops = &clk_branch2_ops,
1492                 },
1493         },
1494 };
1495
1496 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1497         .halt_reg = 0x0b08,
1498         .clkr = {
1499                 .enable_reg = 0x0b08,
1500                 .enable_mask = BIT(0),
1501                 .hw.init = &(struct clk_init_data){
1502                         .name = "gcc_blsp2_qup4_i2c_apps_clk",
1503                         .parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_i2c_apps_clk_src.clkr.hw },
1504                         .num_parents = 1,
1505                         .flags = CLK_SET_RATE_PARENT,
1506                         .ops = &clk_branch2_ops,
1507                 },
1508         },
1509 };
1510
1511 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1512         .halt_reg = 0x0b04,
1513         .clkr = {
1514                 .enable_reg = 0x0b04,
1515                 .enable_mask = BIT(0),
1516                 .hw.init = &(struct clk_init_data){
1517                         .name = "gcc_blsp2_qup4_spi_apps_clk",
1518                         .parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_spi_apps_clk_src.clkr.hw },
1519                         .num_parents = 1,
1520                         .flags = CLK_SET_RATE_PARENT,
1521                         .ops = &clk_branch2_ops,
1522                 },
1523         },
1524 };
1525
1526 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1527         .halt_reg = 0x0b88,
1528         .clkr = {
1529                 .enable_reg = 0x0b88,
1530                 .enable_mask = BIT(0),
1531                 .hw.init = &(struct clk_init_data){
1532                         .name = "gcc_blsp2_qup5_i2c_apps_clk",
1533                         .parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_i2c_apps_clk_src.clkr.hw },
1534                         .num_parents = 1,
1535                         .flags = CLK_SET_RATE_PARENT,
1536                         .ops = &clk_branch2_ops,
1537                 },
1538         },
1539 };
1540
1541 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1542         .halt_reg = 0x0b84,
1543         .clkr = {
1544                 .enable_reg = 0x0b84,
1545                 .enable_mask = BIT(0),
1546                 .hw.init = &(struct clk_init_data){
1547                         .name = "gcc_blsp2_qup5_spi_apps_clk",
1548                         .parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_spi_apps_clk_src.clkr.hw },
1549                         .num_parents = 1,
1550                         .flags = CLK_SET_RATE_PARENT,
1551                         .ops = &clk_branch2_ops,
1552                 },
1553         },
1554 };
1555
1556 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1557         .halt_reg = 0x0c08,
1558         .clkr = {
1559                 .enable_reg = 0x0c08,
1560                 .enable_mask = BIT(0),
1561                 .hw.init = &(struct clk_init_data){
1562                         .name = "gcc_blsp2_qup6_i2c_apps_clk",
1563                         .parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_i2c_apps_clk_src.clkr.hw },
1564                         .num_parents = 1,
1565                         .flags = CLK_SET_RATE_PARENT,
1566                         .ops = &clk_branch2_ops,
1567                 },
1568         },
1569 };
1570
1571 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1572         .halt_reg = 0x0c04,
1573         .clkr = {
1574                 .enable_reg = 0x0c04,
1575                 .enable_mask = BIT(0),
1576                 .hw.init = &(struct clk_init_data){
1577                         .name = "gcc_blsp2_qup6_spi_apps_clk",
1578                         .parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_spi_apps_clk_src.clkr.hw },
1579                         .num_parents = 1,
1580                         .flags = CLK_SET_RATE_PARENT,
1581                         .ops = &clk_branch2_ops,
1582                 },
1583         },
1584 };
1585
1586 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1587         .halt_reg = 0x09c4,
1588         .clkr = {
1589                 .enable_reg = 0x09c4,
1590                 .enable_mask = BIT(0),
1591                 .hw.init = &(struct clk_init_data){
1592                         .name = "gcc_blsp2_uart1_apps_clk",
1593                         .parent_hws = (const struct clk_hw *[]){ &blsp2_uart1_apps_clk_src.clkr.hw },
1594                         .num_parents = 1,
1595                         .flags = CLK_SET_RATE_PARENT,
1596                         .ops = &clk_branch2_ops,
1597                 },
1598         },
1599 };
1600
1601 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1602         .halt_reg = 0x0a44,
1603         .clkr = {
1604                 .enable_reg = 0x0a44,
1605                 .enable_mask = BIT(0),
1606                 .hw.init = &(struct clk_init_data){
1607                         .name = "gcc_blsp2_uart2_apps_clk",
1608                         .parent_hws = (const struct clk_hw *[]){ &blsp2_uart2_apps_clk_src.clkr.hw },
1609                         .num_parents = 1,
1610                         .flags = CLK_SET_RATE_PARENT,
1611                         .ops = &clk_branch2_ops,
1612                 },
1613         },
1614 };
1615
1616 static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1617         .halt_reg = 0x0ac4,
1618         .clkr = {
1619                 .enable_reg = 0x0ac4,
1620                 .enable_mask = BIT(0),
1621                 .hw.init = &(struct clk_init_data){
1622                         .name = "gcc_blsp2_uart3_apps_clk",
1623                         .parent_hws = (const struct clk_hw *[]){ &blsp2_uart3_apps_clk_src.clkr.hw },
1624                         .num_parents = 1,
1625                         .flags = CLK_SET_RATE_PARENT,
1626                         .ops = &clk_branch2_ops,
1627                 },
1628         },
1629 };
1630
1631 static struct clk_branch gcc_blsp2_uart4_apps_clk = {
1632         .halt_reg = 0x0b44,
1633         .clkr = {
1634                 .enable_reg = 0x0b44,
1635                 .enable_mask = BIT(0),
1636                 .hw.init = &(struct clk_init_data){
1637                         .name = "gcc_blsp2_uart4_apps_clk",
1638                         .parent_hws = (const struct clk_hw *[]){ &blsp2_uart4_apps_clk_src.clkr.hw },
1639                         .num_parents = 1,
1640                         .flags = CLK_SET_RATE_PARENT,
1641                         .ops = &clk_branch2_ops,
1642                 },
1643         },
1644 };
1645
1646 static struct clk_branch gcc_blsp2_uart5_apps_clk = {
1647         .halt_reg = 0x0bc4,
1648         .clkr = {
1649                 .enable_reg = 0x0bc4,
1650                 .enable_mask = BIT(0),
1651                 .hw.init = &(struct clk_init_data){
1652                         .name = "gcc_blsp2_uart5_apps_clk",
1653                         .parent_hws = (const struct clk_hw *[]){ &blsp2_uart5_apps_clk_src.clkr.hw },
1654                         .num_parents = 1,
1655                         .flags = CLK_SET_RATE_PARENT,
1656                         .ops = &clk_branch2_ops,
1657                 },
1658         },
1659 };
1660
1661 static struct clk_branch gcc_blsp2_uart6_apps_clk = {
1662         .halt_reg = 0x0c44,
1663         .clkr = {
1664                 .enable_reg = 0x0c44,
1665                 .enable_mask = BIT(0),
1666                 .hw.init = &(struct clk_init_data){
1667                         .name = "gcc_blsp2_uart6_apps_clk",
1668                         .parent_hws = (const struct clk_hw *[]){ &blsp2_uart6_apps_clk_src.clkr.hw },
1669                         .num_parents = 1,
1670                         .flags = CLK_SET_RATE_PARENT,
1671                         .ops = &clk_branch2_ops,
1672                 },
1673         },
1674 };
1675
1676 static struct clk_branch gcc_gp1_clk = {
1677         .halt_reg = 0x1900,
1678         .clkr = {
1679                 .enable_reg = 0x1900,
1680                 .enable_mask = BIT(0),
1681                 .hw.init = &(struct clk_init_data){
1682                         .name = "gcc_gp1_clk",
1683                         .parent_hws = (const struct clk_hw *[]){ &gp1_clk_src.clkr.hw },
1684                         .num_parents = 1,
1685                         .flags = CLK_SET_RATE_PARENT,
1686                         .ops = &clk_branch2_ops,
1687                 },
1688         },
1689 };
1690
1691 static struct clk_branch gcc_gp2_clk = {
1692         .halt_reg = 0x1940,
1693         .clkr = {
1694                 .enable_reg = 0x1940,
1695                 .enable_mask = BIT(0),
1696                 .hw.init = &(struct clk_init_data){
1697                         .name = "gcc_gp2_clk",
1698                         .parent_hws = (const struct clk_hw *[]){ &gp2_clk_src.clkr.hw },
1699                         .num_parents = 1,
1700                         .flags = CLK_SET_RATE_PARENT,
1701                         .ops = &clk_branch2_ops,
1702                 },
1703         },
1704 };
1705
1706 static struct clk_branch gcc_gp3_clk = {
1707         .halt_reg = 0x1980,
1708         .clkr = {
1709                 .enable_reg = 0x1980,
1710                 .enable_mask = BIT(0),
1711                 .hw.init = &(struct clk_init_data){
1712                         .name = "gcc_gp3_clk",
1713                         .parent_hws = (const struct clk_hw *[]){ &gp3_clk_src.clkr.hw },
1714                         .num_parents = 1,
1715                         .flags = CLK_SET_RATE_PARENT,
1716                         .ops = &clk_branch2_ops,
1717                 },
1718         },
1719 };
1720
1721 static struct clk_branch gcc_lpass_q6_axi_clk = {
1722         .halt_reg = 0x0280,
1723         .clkr = {
1724                 .enable_reg = 0x0280,
1725                 .enable_mask = BIT(0),
1726                 .hw.init = &(struct clk_init_data){
1727                         .name = "gcc_lpass_q6_axi_clk",
1728                         .ops = &clk_branch2_ops,
1729                 },
1730         },
1731 };
1732
1733 static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
1734         .halt_reg = 0x0284,
1735         .clkr = {
1736                 .enable_reg = 0x0284,
1737                 .enable_mask = BIT(0),
1738                 .hw.init = &(struct clk_init_data){
1739                         .name = "gcc_mss_q6_bimc_axi_clk",
1740                         .ops = &clk_branch2_ops,
1741                 },
1742         },
1743 };
1744
1745 static struct clk_branch gcc_pcie_0_aux_clk = {
1746         .halt_reg = 0x1ad4,
1747         .clkr = {
1748                 .enable_reg = 0x1ad4,
1749                 .enable_mask = BIT(0),
1750                 .hw.init = &(struct clk_init_data){
1751                         .name = "gcc_pcie_0_aux_clk",
1752                         .parent_hws = (const struct clk_hw *[]){ &pcie_0_aux_clk_src.clkr.hw },
1753                         .num_parents = 1,
1754                         .flags = CLK_SET_RATE_PARENT,
1755                         .ops = &clk_branch2_ops,
1756                 },
1757         },
1758 };
1759
1760 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1761         .halt_reg = 0x1ad0,
1762         .clkr = {
1763                 .enable_reg = 0x1ad0,
1764                 .enable_mask = BIT(0),
1765                 .hw.init = &(struct clk_init_data){
1766                         .name = "gcc_pcie_0_cfg_ahb_clk",
1767                         .ops = &clk_branch2_ops,
1768                 },
1769         },
1770 };
1771
1772 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1773         .halt_reg = 0x1acc,
1774         .clkr = {
1775                 .enable_reg = 0x1acc,
1776                 .enable_mask = BIT(0),
1777                 .hw.init = &(struct clk_init_data){
1778                         .name = "gcc_pcie_0_mstr_axi_clk",
1779                         .ops = &clk_branch2_ops,
1780                 },
1781         },
1782 };
1783
1784 static struct clk_branch gcc_pcie_0_pipe_clk = {
1785         .halt_reg = 0x1ad8,
1786         .halt_check = BRANCH_HALT_DELAY,
1787         .clkr = {
1788                 .enable_reg = 0x1ad8,
1789                 .enable_mask = BIT(0),
1790                 .hw.init = &(struct clk_init_data){
1791                         .name = "gcc_pcie_0_pipe_clk",
1792                         .parent_hws = (const struct clk_hw *[]){ &pcie_0_pipe_clk_src.clkr.hw },
1793                         .num_parents = 1,
1794                         .flags = CLK_SET_RATE_PARENT,
1795                         .ops = &clk_branch2_ops,
1796                 },
1797         },
1798 };
1799
1800 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1801         .halt_reg = 0x1ac8,
1802         .halt_check = BRANCH_HALT_DELAY,
1803         .clkr = {
1804                 .enable_reg = 0x1ac8,
1805                 .enable_mask = BIT(0),
1806                 .hw.init = &(struct clk_init_data){
1807                         .name = "gcc_pcie_0_slv_axi_clk",
1808                         .ops = &clk_branch2_ops,
1809                 },
1810         },
1811 };
1812
1813 static struct clk_branch gcc_pcie_1_aux_clk = {
1814         .halt_reg = 0x1b54,
1815         .clkr = {
1816                 .enable_reg = 0x1b54,
1817                 .enable_mask = BIT(0),
1818                 .hw.init = &(struct clk_init_data){
1819                         .name = "gcc_pcie_1_aux_clk",
1820                         .parent_hws = (const struct clk_hw *[]){ &pcie_1_aux_clk_src.clkr.hw },
1821                         .num_parents = 1,
1822                         .flags = CLK_SET_RATE_PARENT,
1823                         .ops = &clk_branch2_ops,
1824                 },
1825         },
1826 };
1827
1828 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1829         .halt_reg = 0x1b54,
1830         .clkr = {
1831                 .enable_reg = 0x1b54,
1832                 .enable_mask = BIT(0),
1833                 .hw.init = &(struct clk_init_data){
1834                         .name = "gcc_pcie_1_cfg_ahb_clk",
1835                         .ops = &clk_branch2_ops,
1836                 },
1837         },
1838 };
1839
1840 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1841         .halt_reg = 0x1b50,
1842         .clkr = {
1843                 .enable_reg = 0x1b50,
1844                 .enable_mask = BIT(0),
1845                 .hw.init = &(struct clk_init_data){
1846                         .name = "gcc_pcie_1_mstr_axi_clk",
1847                         .ops = &clk_branch2_ops,
1848                 },
1849         },
1850 };
1851
1852 static struct clk_branch gcc_pcie_1_pipe_clk = {
1853         .halt_reg = 0x1b58,
1854         .halt_check = BRANCH_HALT_DELAY,
1855         .clkr = {
1856                 .enable_reg = 0x1b58,
1857                 .enable_mask = BIT(0),
1858                 .hw.init = &(struct clk_init_data){
1859                         .name = "gcc_pcie_1_pipe_clk",
1860                         .parent_hws = (const struct clk_hw *[]){ &pcie_1_pipe_clk_src.clkr.hw },
1861                         .num_parents = 1,
1862                         .flags = CLK_SET_RATE_PARENT,
1863                         .ops = &clk_branch2_ops,
1864                 },
1865         },
1866 };
1867
1868 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1869         .halt_reg = 0x1b48,
1870         .clkr = {
1871                 .enable_reg = 0x1b48,
1872                 .enable_mask = BIT(0),
1873                 .hw.init = &(struct clk_init_data){
1874                         .name = "gcc_pcie_1_slv_axi_clk",
1875                         .ops = &clk_branch2_ops,
1876                 },
1877         },
1878 };
1879
1880 static struct clk_branch gcc_pdm2_clk = {
1881         .halt_reg = 0x0ccc,
1882         .clkr = {
1883                 .enable_reg = 0x0ccc,
1884                 .enable_mask = BIT(0),
1885                 .hw.init = &(struct clk_init_data){
1886                         .name = "gcc_pdm2_clk",
1887                         .parent_hws = (const struct clk_hw *[]){ &pdm2_clk_src.clkr.hw },
1888                         .num_parents = 1,
1889                         .flags = CLK_SET_RATE_PARENT,
1890                         .ops = &clk_branch2_ops,
1891                 },
1892         },
1893 };
1894
1895 static struct clk_branch gcc_pdm_ahb_clk = {
1896         .halt_reg = 0x0cc4,
1897         .clkr = {
1898                 .enable_reg = 0x0cc4,
1899                 .enable_mask = BIT(0),
1900                 .hw.init = &(struct clk_init_data){
1901                         .name = "gcc_pdm_ahb_clk",
1902                         .ops = &clk_branch2_ops,
1903                 },
1904         },
1905 };
1906
1907 static struct clk_branch gcc_sdcc1_apps_clk = {
1908         .halt_reg = 0x04c4,
1909         .clkr = {
1910                 .enable_reg = 0x04c4,
1911                 .enable_mask = BIT(0),
1912                 .hw.init = &(struct clk_init_data){
1913                         .name = "gcc_sdcc1_apps_clk",
1914                         .parent_hws = (const struct clk_hw *[]){ &sdcc1_apps_clk_src.clkr.hw },
1915                         .num_parents = 1,
1916                         .flags = CLK_SET_RATE_PARENT,
1917                         .ops = &clk_branch2_ops,
1918                 },
1919         },
1920 };
1921
1922 static struct clk_branch gcc_sdcc1_ahb_clk = {
1923         .halt_reg = 0x04c8,
1924         .clkr = {
1925                 .enable_reg = 0x04c8,
1926                 .enable_mask = BIT(0),
1927                 .hw.init = &(struct clk_init_data){
1928                         .name = "gcc_sdcc1_ahb_clk",
1929                         .ops = &clk_branch2_ops,
1930                 },
1931         },
1932 };
1933
1934 static struct clk_branch gcc_sdcc2_ahb_clk = {
1935         .halt_reg = 0x0508,
1936         .clkr = {
1937                 .enable_reg = 0x0508,
1938                 .enable_mask = BIT(0),
1939                 .hw.init = &(struct clk_init_data){
1940                         .name = "gcc_sdcc2_ahb_clk",
1941                         .ops = &clk_branch2_ops,
1942                 },
1943         },
1944 };
1945
1946 static struct clk_branch gcc_sdcc2_apps_clk = {
1947         .halt_reg = 0x0504,
1948         .clkr = {
1949                 .enable_reg = 0x0504,
1950                 .enable_mask = BIT(0),
1951                 .hw.init = &(struct clk_init_data){
1952                         .name = "gcc_sdcc2_apps_clk",
1953                         .parent_hws = (const struct clk_hw *[]){ &sdcc2_apps_clk_src.clkr.hw },
1954                         .num_parents = 1,
1955                         .flags = CLK_SET_RATE_PARENT,
1956                         .ops = &clk_branch2_ops,
1957                 },
1958         },
1959 };
1960
1961 static struct clk_branch gcc_sdcc3_ahb_clk = {
1962         .halt_reg = 0x0548,
1963         .clkr = {
1964                 .enable_reg = 0x0548,
1965                 .enable_mask = BIT(0),
1966                 .hw.init = &(struct clk_init_data){
1967                         .name = "gcc_sdcc3_ahb_clk",
1968                         .ops = &clk_branch2_ops,
1969                 },
1970         },
1971 };
1972
1973 static struct clk_branch gcc_sdcc3_apps_clk = {
1974         .halt_reg = 0x0544,
1975         .clkr = {
1976                 .enable_reg = 0x0544,
1977                 .enable_mask = BIT(0),
1978                 .hw.init = &(struct clk_init_data){
1979                         .name = "gcc_sdcc3_apps_clk",
1980                         .parent_hws = (const struct clk_hw *[]){ &sdcc3_apps_clk_src.clkr.hw },
1981                         .num_parents = 1,
1982                         .flags = CLK_SET_RATE_PARENT,
1983                         .ops = &clk_branch2_ops,
1984                 },
1985         },
1986 };
1987
1988 static struct clk_branch gcc_sdcc4_ahb_clk = {
1989         .halt_reg = 0x0588,
1990         .clkr = {
1991                 .enable_reg = 0x0588,
1992                 .enable_mask = BIT(0),
1993                 .hw.init = &(struct clk_init_data){
1994                         .name = "gcc_sdcc4_ahb_clk",
1995                         .ops = &clk_branch2_ops,
1996                 },
1997         },
1998 };
1999
2000 static struct clk_branch gcc_sdcc4_apps_clk = {
2001         .halt_reg = 0x0584,
2002         .clkr = {
2003                 .enable_reg = 0x0584,
2004                 .enable_mask = BIT(0),
2005                 .hw.init = &(struct clk_init_data){
2006                         .name = "gcc_sdcc4_apps_clk",
2007                         .parent_hws = (const struct clk_hw *[]){ &sdcc4_apps_clk_src.clkr.hw },
2008                         .num_parents = 1,
2009                         .flags = CLK_SET_RATE_PARENT,
2010                         .ops = &clk_branch2_ops,
2011                 },
2012         },
2013 };
2014
2015 static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
2016         .halt_reg = 0x1d7c,
2017         .clkr = {
2018                 .enable_reg = 0x1d7c,
2019                 .enable_mask = BIT(0),
2020                 .hw.init = &(struct clk_init_data){
2021                         .name = "gcc_sys_noc_ufs_axi_clk",
2022                         .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
2023                         .num_parents = 1,
2024                         .flags = CLK_SET_RATE_PARENT,
2025                         .ops = &clk_branch2_ops,
2026                 },
2027         },
2028 };
2029
2030 static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
2031         .halt_reg = 0x03fc,
2032         .clkr = {
2033                 .enable_reg = 0x03fc,
2034                 .enable_mask = BIT(0),
2035                 .hw.init = &(struct clk_init_data){
2036                         .name = "gcc_sys_noc_usb3_axi_clk",
2037                         .parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw },
2038                         .num_parents = 1,
2039                         .flags = CLK_SET_RATE_PARENT,
2040                         .ops = &clk_branch2_ops,
2041                 },
2042         },
2043 };
2044
2045 static struct clk_branch gcc_tsif_ahb_clk = {
2046         .halt_reg = 0x0d84,
2047         .clkr = {
2048                 .enable_reg = 0x0d84,
2049                 .enable_mask = BIT(0),
2050                 .hw.init = &(struct clk_init_data){
2051                         .name = "gcc_tsif_ahb_clk",
2052                         .ops = &clk_branch2_ops,
2053                 },
2054         },
2055 };
2056
2057 static struct clk_branch gcc_tsif_ref_clk = {
2058         .halt_reg = 0x0d88,
2059         .clkr = {
2060                 .enable_reg = 0x0d88,
2061                 .enable_mask = BIT(0),
2062                 .hw.init = &(struct clk_init_data){
2063                         .name = "gcc_tsif_ref_clk",
2064                         .parent_hws = (const struct clk_hw *[]){ &tsif_ref_clk_src.clkr.hw },
2065                         .num_parents = 1,
2066                         .flags = CLK_SET_RATE_PARENT,
2067                         .ops = &clk_branch2_ops,
2068                 },
2069         },
2070 };
2071
2072 static struct clk_branch gcc_ufs_ahb_clk = {
2073         .halt_reg = 0x1d4c,
2074         .clkr = {
2075                 .enable_reg = 0x1d4c,
2076                 .enable_mask = BIT(0),
2077                 .hw.init = &(struct clk_init_data){
2078                         .name = "gcc_ufs_ahb_clk",
2079                         .ops = &clk_branch2_ops,
2080                 },
2081         },
2082 };
2083
2084 static struct clk_branch gcc_ufs_axi_clk = {
2085         .halt_reg = 0x1d48,
2086         .clkr = {
2087                 .enable_reg = 0x1d48,
2088                 .enable_mask = BIT(0),
2089                 .hw.init = &(struct clk_init_data){
2090                         .name = "gcc_ufs_axi_clk",
2091                         .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
2092                         .num_parents = 1,
2093                         .flags = CLK_SET_RATE_PARENT,
2094                         .ops = &clk_branch2_ops,
2095                 },
2096         },
2097 };
2098
2099 static struct clk_branch gcc_ufs_rx_cfg_clk = {
2100         .halt_reg = 0x1d54,
2101         .clkr = {
2102                 .enable_reg = 0x1d54,
2103                 .enable_mask = BIT(0),
2104                 .hw.init = &(struct clk_init_data){
2105                         .name = "gcc_ufs_rx_cfg_clk",
2106                         .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
2107                         .num_parents = 1,
2108                         .flags = CLK_SET_RATE_PARENT,
2109                         .ops = &clk_branch2_ops,
2110                 },
2111         },
2112 };
2113
2114 static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2115         .halt_reg = 0x1d60,
2116         .halt_check = BRANCH_HALT_DELAY,
2117         .clkr = {
2118                 .enable_reg = 0x1d60,
2119                 .enable_mask = BIT(0),
2120                 .hw.init = &(struct clk_init_data){
2121                         .name = "gcc_ufs_rx_symbol_0_clk",
2122                         .ops = &clk_branch2_ops,
2123                 },
2124         },
2125 };
2126
2127 static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2128         .halt_reg = 0x1d64,
2129         .halt_check = BRANCH_HALT_DELAY,
2130         .clkr = {
2131                 .enable_reg = 0x1d64,
2132                 .enable_mask = BIT(0),
2133                 .hw.init = &(struct clk_init_data){
2134                         .name = "gcc_ufs_rx_symbol_1_clk",
2135                         .ops = &clk_branch2_ops,
2136                 },
2137         },
2138 };
2139
2140 static struct clk_branch gcc_ufs_tx_cfg_clk = {
2141         .halt_reg = 0x1d50,
2142         .clkr = {
2143                 .enable_reg = 0x1d50,
2144                 .enable_mask = BIT(0),
2145                 .hw.init = &(struct clk_init_data){
2146                         .name = "gcc_ufs_tx_cfg_clk",
2147                         .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
2148                         .num_parents = 1,
2149                         .flags = CLK_SET_RATE_PARENT,
2150                         .ops = &clk_branch2_ops,
2151                 },
2152         },
2153 };
2154
2155 static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2156         .halt_reg = 0x1d58,
2157         .halt_check = BRANCH_HALT_DELAY,
2158         .clkr = {
2159                 .enable_reg = 0x1d58,
2160                 .enable_mask = BIT(0),
2161                 .hw.init = &(struct clk_init_data){
2162                         .name = "gcc_ufs_tx_symbol_0_clk",
2163                         .ops = &clk_branch2_ops,
2164                 },
2165         },
2166 };
2167
2168 static struct clk_branch gcc_ufs_tx_symbol_1_clk = {
2169         .halt_reg = 0x1d5c,
2170         .halt_check = BRANCH_HALT_DELAY,
2171         .clkr = {
2172                 .enable_reg = 0x1d5c,
2173                 .enable_mask = BIT(0),
2174                 .hw.init = &(struct clk_init_data){
2175                         .name = "gcc_ufs_tx_symbol_1_clk",
2176                         .ops = &clk_branch2_ops,
2177                 },
2178         },
2179 };
2180
2181 static struct clk_branch gcc_usb2_hs_phy_sleep_clk = {
2182         .halt_reg = 0x04ac,
2183         .clkr = {
2184                 .enable_reg = 0x04ac,
2185                 .enable_mask = BIT(0),
2186                 .hw.init = &(struct clk_init_data){
2187                         .name = "gcc_usb2_hs_phy_sleep_clk",
2188                         .parent_data = &(const struct clk_parent_data){
2189                                 .fw_name = "sleep",
2190                                 .name = "sleep"
2191                         },
2192                         .num_parents = 1,
2193                         .ops = &clk_branch2_ops,
2194                 },
2195         },
2196 };
2197
2198 static struct clk_branch gcc_usb30_master_clk = {
2199         .halt_reg = 0x03c8,
2200         .clkr = {
2201                 .enable_reg = 0x03c8,
2202                 .enable_mask = BIT(0),
2203                 .hw.init = &(struct clk_init_data){
2204                         .name = "gcc_usb30_master_clk",
2205                         .parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw },
2206                         .num_parents = 1,
2207                         .flags = CLK_SET_RATE_PARENT,
2208                         .ops = &clk_branch2_ops,
2209                 },
2210         },
2211 };
2212
2213 static struct clk_branch gcc_usb30_mock_utmi_clk = {
2214         .halt_reg = 0x03d0,
2215         .clkr = {
2216                 .enable_reg = 0x03d0,
2217                 .enable_mask = BIT(0),
2218                 .hw.init = &(struct clk_init_data){
2219                         .name = "gcc_usb30_mock_utmi_clk",
2220                         .parent_hws = (const struct clk_hw *[]){ &usb30_mock_utmi_clk_src.clkr.hw },
2221                         .num_parents = 1,
2222                         .flags = CLK_SET_RATE_PARENT,
2223                         .ops = &clk_branch2_ops,
2224                 },
2225         },
2226 };
2227
2228 static struct clk_branch gcc_usb30_sleep_clk = {
2229         .halt_reg = 0x03cc,
2230         .clkr = {
2231                 .enable_reg = 0x03cc,
2232                 .enable_mask = BIT(0),
2233                 .hw.init = &(struct clk_init_data){
2234                         .name = "gcc_usb30_sleep_clk",
2235                         .parent_data = &(const struct clk_parent_data){
2236                                 .fw_name = "sleep",
2237                                 .name = "sleep"
2238                         },
2239                         .num_parents = 1,
2240                         .ops = &clk_branch2_ops,
2241                 },
2242         },
2243 };
2244
2245 static struct clk_branch gcc_usb3_phy_aux_clk = {
2246         .halt_reg = 0x1408,
2247         .clkr = {
2248                 .enable_reg = 0x1408,
2249                 .enable_mask = BIT(0),
2250                 .hw.init = &(struct clk_init_data){
2251                         .name = "gcc_usb3_phy_aux_clk",
2252                         .parent_hws = (const struct clk_hw *[]){ &usb3_phy_aux_clk_src.clkr.hw },
2253                         .num_parents = 1,
2254                         .flags = CLK_SET_RATE_PARENT,
2255                         .ops = &clk_branch2_ops,
2256                 },
2257         },
2258 };
2259
2260 static struct clk_branch gcc_usb3_phy_pipe_clk = {
2261         .halt_reg = 0x140c,
2262         .halt_check = BRANCH_HALT_SKIP,
2263         .clkr = {
2264                 .enable_reg = 0x140c,
2265                 .enable_mask = BIT(0),
2266                 .hw.init = &(struct clk_init_data){
2267                         .name = "gcc_usb3_phy_pipe_clk",
2268                         .ops = &clk_branch2_ops,
2269                 },
2270         },
2271 };
2272
2273 static struct clk_branch gcc_usb_hs_ahb_clk = {
2274         .halt_reg = 0x0488,
2275         .clkr = {
2276                 .enable_reg = 0x0488,
2277                 .enable_mask = BIT(0),
2278                 .hw.init = &(struct clk_init_data){
2279                         .name = "gcc_usb_hs_ahb_clk",
2280                         .ops = &clk_branch2_ops,
2281                 },
2282         },
2283 };
2284
2285 static struct clk_branch gcc_usb_hs_system_clk = {
2286         .halt_reg = 0x0484,
2287         .clkr = {
2288                 .enable_reg = 0x0484,
2289                 .enable_mask = BIT(0),
2290                 .hw.init = &(struct clk_init_data){
2291                         .name = "gcc_usb_hs_system_clk",
2292                         .parent_hws = (const struct clk_hw *[]){ &usb_hs_system_clk_src.clkr.hw },
2293                         .num_parents = 1,
2294                         .flags = CLK_SET_RATE_PARENT,
2295                         .ops = &clk_branch2_ops,
2296                 },
2297         },
2298 };
2299
2300 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
2301         .halt_reg = 0x1a84,
2302         .clkr = {
2303                 .enable_reg = 0x1a84,
2304                 .enable_mask = BIT(0),
2305                 .hw.init = &(struct clk_init_data){
2306                         .name = "gcc_usb_phy_cfg_ahb2phy_clk",
2307                         .ops = &clk_branch2_ops,
2308                 },
2309         },
2310 };
2311
2312 static struct clk_branch gpll0_out_mmsscc = {
2313         .halt_check = BRANCH_HALT_DELAY,
2314         .clkr = {
2315                 .enable_reg = 0x1484,
2316                 .enable_mask = BIT(26),
2317                 .hw.init = &(struct clk_init_data){
2318                         .name = "gpll0_out_mmsscc",
2319                         .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
2320                         .num_parents = 1,
2321                         .ops = &clk_branch2_ops,
2322                 },
2323         },
2324 };
2325
2326 static struct clk_branch gpll0_out_msscc = {
2327         .halt_check = BRANCH_HALT_DELAY,
2328         .clkr = {
2329                 .enable_reg = 0x1484,
2330                 .enable_mask = BIT(27),
2331                 .hw.init = &(struct clk_init_data){
2332                         .name = "gpll0_out_msscc",
2333                         .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
2334                         .num_parents = 1,
2335                         .ops = &clk_branch2_ops,
2336                 },
2337         },
2338 };
2339
2340 static struct clk_branch pcie_0_phy_ldo = {
2341         .halt_reg = 0x1e00,
2342         .halt_check = BRANCH_HALT_SKIP,
2343         .clkr = {
2344                 .enable_reg = 0x1E00,
2345                 .enable_mask = BIT(0),
2346                 .hw.init = &(struct clk_init_data){
2347                         .name = "pcie_0_phy_ldo",
2348                         .ops = &clk_branch2_ops,
2349                 },
2350         },
2351 };
2352
2353 static struct clk_branch pcie_1_phy_ldo = {
2354         .halt_reg = 0x1e04,
2355         .halt_check = BRANCH_HALT_SKIP,
2356         .clkr = {
2357                 .enable_reg = 0x1E04,
2358                 .enable_mask = BIT(0),
2359                 .hw.init = &(struct clk_init_data){
2360                         .name = "pcie_1_phy_ldo",
2361                         .ops = &clk_branch2_ops,
2362                 },
2363         },
2364 };
2365
2366 static struct clk_branch ufs_phy_ldo = {
2367         .halt_reg = 0x1e0c,
2368         .halt_check = BRANCH_HALT_SKIP,
2369         .clkr = {
2370                 .enable_reg = 0x1E0C,
2371                 .enable_mask = BIT(0),
2372                 .hw.init = &(struct clk_init_data){
2373                         .name = "ufs_phy_ldo",
2374                         .ops = &clk_branch2_ops,
2375                 },
2376         },
2377 };
2378
2379 static struct clk_branch usb_ss_phy_ldo = {
2380         .halt_reg = 0x1e08,
2381         .halt_check = BRANCH_HALT_SKIP,
2382         .clkr = {
2383                 .enable_reg = 0x1E08,
2384                 .enable_mask = BIT(0),
2385                 .hw.init = &(struct clk_init_data){
2386                         .name = "usb_ss_phy_ldo",
2387                         .ops = &clk_branch2_ops,
2388                 },
2389         },
2390 };
2391
2392 static struct clk_branch gcc_boot_rom_ahb_clk = {
2393         .halt_reg = 0x0e04,
2394         .halt_check = BRANCH_HALT_VOTED,
2395         .hwcg_reg = 0x0e04,
2396         .hwcg_bit = 1,
2397         .clkr = {
2398                 .enable_reg = 0x1484,
2399                 .enable_mask = BIT(10),
2400                 .hw.init = &(struct clk_init_data){
2401                         .name = "gcc_boot_rom_ahb_clk",
2402                         .ops = &clk_branch2_ops,
2403                 },
2404         },
2405 };
2406
2407 static struct clk_branch gcc_prng_ahb_clk = {
2408         .halt_reg = 0x0d04,
2409         .halt_check = BRANCH_HALT_VOTED,
2410         .clkr = {
2411                 .enable_reg = 0x1484,
2412                 .enable_mask = BIT(13),
2413                 .hw.init = &(struct clk_init_data){
2414                         .name = "gcc_prng_ahb_clk",
2415                         .ops = &clk_branch2_ops,
2416                 },
2417         },
2418 };
2419
2420 static struct gdsc pcie_0_gdsc = {
2421                 .gdscr = 0x1ac4,
2422                 .pd = {
2423                         .name = "pcie_0",
2424                 },
2425                 .pwrsts = PWRSTS_OFF_ON,
2426 };
2427
2428 static struct gdsc pcie_1_gdsc = {
2429                 .gdscr = 0x1b44,
2430                 .pd = {
2431                         .name = "pcie_1",
2432                 },
2433                 .pwrsts = PWRSTS_OFF_ON,
2434 };
2435
2436 static struct gdsc usb30_gdsc = {
2437                 .gdscr = 0x3c4,
2438                 .pd = {
2439                         .name = "usb30",
2440                 },
2441                 .pwrsts = PWRSTS_OFF_ON,
2442 };
2443
2444 static struct gdsc ufs_gdsc = {
2445                 .gdscr = 0x1d44,
2446                 .pd = {
2447                         .name = "ufs",
2448                 },
2449                 .pwrsts = PWRSTS_OFF_ON,
2450 };
2451
2452 static struct clk_regmap *gcc_msm8994_clocks[] = {
2453         [GPLL0_EARLY] = &gpll0_early.clkr,
2454         [GPLL0] = &gpll0.clkr,
2455         [GPLL4_EARLY] = &gpll4_early.clkr,
2456         [GPLL4] = &gpll4.clkr,
2457         [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
2458         [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2459         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2460         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2461         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2462         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2463         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2464         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2465         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2466         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2467         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2468         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2469         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2470         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2471         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2472         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2473         [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2474         [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
2475         [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
2476         [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
2477         [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2478         [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2479         [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2480         [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2481         [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2482         [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2483         [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2484         [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2485         [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
2486         [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
2487         [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
2488         [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
2489         [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2490         [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2491         [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
2492         [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
2493         [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
2494         [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
2495         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2496         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2497         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2498         [PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
2499         [PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
2500         [PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr,
2501         [PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr,
2502         [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2503         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2504         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2505         [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
2506         [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
2507         [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
2508         [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2509         [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2510         [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2511         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2512         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2513         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2514         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2515         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2516         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2517         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2518         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2519         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2520         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2521         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2522         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2523         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2524         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2525         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2526         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2527         [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
2528         [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
2529         [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
2530         [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2531         [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2532         [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2533         [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2534         [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2535         [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2536         [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2537         [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2538         [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2539         [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
2540         [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
2541         [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
2542         [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
2543         [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2544         [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2545         [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
2546         [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
2547         [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
2548         [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
2549         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2550         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2551         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2552         [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
2553         [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
2554         [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2555         [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
2556         [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
2557         [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2558         [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
2559         [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
2560         [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
2561         [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
2562         [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
2563         [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
2564         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2565         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2566         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2567         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2568         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2569         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2570         [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
2571         [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
2572         [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
2573         [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
2574         [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
2575         [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
2576         [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
2577         [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
2578         [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
2579         [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
2580         [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
2581         [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
2582         [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
2583         [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
2584         [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
2585         [GCC_UFS_TX_SYMBOL_1_CLK] = &gcc_ufs_tx_symbol_1_clk.clkr,
2586         [GCC_USB2_HS_PHY_SLEEP_CLK] = &gcc_usb2_hs_phy_sleep_clk.clkr,
2587         [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2588         [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2589         [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2590         [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2591         [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
2592         [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
2593         [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2594         [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
2595         [GPLL0_OUT_MMSSCC] = &gpll0_out_mmsscc.clkr,
2596         [GPLL0_OUT_MSSCC] = &gpll0_out_msscc.clkr,
2597         [PCIE_0_PHY_LDO] = &pcie_0_phy_ldo.clkr,
2598         [PCIE_1_PHY_LDO] = &pcie_1_phy_ldo.clkr,
2599         [UFS_PHY_LDO] = &ufs_phy_ldo.clkr,
2600         [USB_SS_PHY_LDO] = &usb_ss_phy_ldo.clkr,
2601         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2602         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2603
2604         /*
2605          * The following clocks should NOT be managed by this driver, but they once were
2606          * mistakengly added. Now they are only here to indicate that they are not defined
2607          * on purpose, even though the names will stay in the header file (for ABI sanity).
2608          */
2609         [CONFIG_NOC_CLK_SRC] = NULL,
2610         [PERIPH_NOC_CLK_SRC] = NULL,
2611         [SYSTEM_NOC_CLK_SRC] = NULL,
2612 };
2613
2614 static struct gdsc *gcc_msm8994_gdscs[] = {
2615         /* This GDSC does not exist, but ABI has to remain intact */
2616         [PCIE_GDSC] = NULL,
2617         [PCIE_0_GDSC] = &pcie_0_gdsc,
2618         [PCIE_1_GDSC] = &pcie_1_gdsc,
2619         [USB30_GDSC] = &usb30_gdsc,
2620         [UFS_GDSC] = &ufs_gdsc,
2621 };
2622
2623 static const struct qcom_reset_map gcc_msm8994_resets[] = {
2624         [USB3_PHY_RESET] = { 0x1400 },
2625         [USB3PHY_PHY_RESET] = { 0x1404 },
2626         [MSS_RESET] = { 0x1680 },
2627         [PCIE_PHY_0_RESET] = { 0x1b18 },
2628         [PCIE_PHY_1_RESET] = { 0x1b98 },
2629         [QUSB2_PHY_RESET] = { 0x04b8 },
2630 };
2631
2632 static const struct regmap_config gcc_msm8994_regmap_config = {
2633         .reg_bits       = 32,
2634         .reg_stride     = 4,
2635         .val_bits       = 32,
2636         .max_register   = 0x2000,
2637         .fast_io        = true,
2638 };
2639
2640 static const struct qcom_cc_desc gcc_msm8994_desc = {
2641         .config = &gcc_msm8994_regmap_config,
2642         .clks = gcc_msm8994_clocks,
2643         .num_clks = ARRAY_SIZE(gcc_msm8994_clocks),
2644         .resets = gcc_msm8994_resets,
2645         .num_resets = ARRAY_SIZE(gcc_msm8994_resets),
2646         .gdscs = gcc_msm8994_gdscs,
2647         .num_gdscs = ARRAY_SIZE(gcc_msm8994_gdscs),
2648 };
2649
2650 static const struct of_device_id gcc_msm8994_match_table[] = {
2651         { .compatible = "qcom,gcc-msm8992" },
2652         { .compatible = "qcom,gcc-msm8994" }, /* V2 and V2.1 */
2653         {}
2654 };
2655 MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table);
2656
2657 static int gcc_msm8994_probe(struct platform_device *pdev)
2658 {
2659         if (of_device_is_compatible(pdev->dev.of_node, "qcom,gcc-msm8992")) {
2660                 /* MSM8992 features less clocks and some have different freq tables */
2661                 gcc_msm8994_desc.clks[UFS_AXI_CLK_SRC] = NULL;
2662                 gcc_msm8994_desc.clks[GCC_LPASS_Q6_AXI_CLK] = NULL;
2663                 gcc_msm8994_desc.clks[UFS_PHY_LDO] = NULL;
2664                 gcc_msm8994_desc.clks[GCC_UFS_AHB_CLK] = NULL;
2665                 gcc_msm8994_desc.clks[GCC_UFS_AXI_CLK] = NULL;
2666                 gcc_msm8994_desc.clks[GCC_UFS_RX_CFG_CLK] = NULL;
2667                 gcc_msm8994_desc.clks[GCC_UFS_RX_SYMBOL_0_CLK] = NULL;
2668                 gcc_msm8994_desc.clks[GCC_UFS_RX_SYMBOL_1_CLK] = NULL;
2669                 gcc_msm8994_desc.clks[GCC_UFS_TX_CFG_CLK] = NULL;
2670                 gcc_msm8994_desc.clks[GCC_UFS_TX_SYMBOL_0_CLK] = NULL;
2671                 gcc_msm8994_desc.clks[GCC_UFS_TX_SYMBOL_1_CLK] = NULL;
2672
2673                 sdcc1_apps_clk_src.freq_tbl = ftbl_sdcc1_apps_clk_src_8992;
2674                 blsp1_qup1_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2675                 blsp1_qup2_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2676                 blsp1_qup3_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2677                 blsp1_qup4_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2678                 blsp1_qup5_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2679                 blsp1_qup6_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2680                 blsp2_qup1_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2681                 blsp2_qup2_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2682                 blsp2_qup3_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2683                 blsp2_qup4_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2684                 blsp2_qup5_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2685                 blsp2_qup6_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2686
2687                 /*
2688                  * Some 8992 boards might *possibly* use
2689                  * PCIe1 clocks and controller, but it's not
2690                  * standard and they should be disabled otherwise.
2691                  */
2692                 gcc_msm8994_desc.clks[PCIE_1_AUX_CLK_SRC] = NULL;
2693                 gcc_msm8994_desc.clks[PCIE_1_PIPE_CLK_SRC] = NULL;
2694                 gcc_msm8994_desc.clks[PCIE_1_PHY_LDO] = NULL;
2695                 gcc_msm8994_desc.clks[GCC_PCIE_1_AUX_CLK] = NULL;
2696                 gcc_msm8994_desc.clks[GCC_PCIE_1_CFG_AHB_CLK] = NULL;
2697                 gcc_msm8994_desc.clks[GCC_PCIE_1_MSTR_AXI_CLK] = NULL;
2698                 gcc_msm8994_desc.clks[GCC_PCIE_1_PIPE_CLK] = NULL;
2699                 gcc_msm8994_desc.clks[GCC_PCIE_1_SLV_AXI_CLK] = NULL;
2700                 gcc_msm8994_desc.clks[GCC_SYS_NOC_UFS_AXI_CLK] = NULL;
2701         }
2702
2703         return qcom_cc_probe(pdev, &gcc_msm8994_desc);
2704 }
2705
2706 static struct platform_driver gcc_msm8994_driver = {
2707         .probe          = gcc_msm8994_probe,
2708         .driver         = {
2709                 .name   = "gcc-msm8994",
2710                 .of_match_table = gcc_msm8994_match_table,
2711         },
2712 };
2713
2714 static int __init gcc_msm8994_init(void)
2715 {
2716         return platform_driver_register(&gcc_msm8994_driver);
2717 }
2718 core_initcall(gcc_msm8994_init);
2719
2720 static void __exit gcc_msm8994_exit(void)
2721 {
2722         platform_driver_unregister(&gcc_msm8994_driver);
2723 }
2724 module_exit(gcc_msm8994_exit);
2725
2726 MODULE_DESCRIPTION("Qualcomm GCC MSM8994 Driver");
2727 MODULE_LICENSE("GPL v2");
2728 MODULE_ALIAS("platform:gcc-msm8994");