drivers/clk/qcom/gcc-msm8939.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright 2020 Linaro Limited
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/bitops.h>
   8 #include <linux/err.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/of_device.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/regmap.h>
  15 #include <linux/reset-controller.h>
  16
  17 #include <dt-bindings/clock/qcom,gcc-msm8939.h>
  18 #include <dt-bindings/reset/qcom,gcc-msm8939.h>
  19
  20 #include "common.h"
  21 #include "clk-regmap.h"
  22 #include "clk-pll.h"
  23 #include "clk-rcg.h"
  24 #include "clk-branch.h"
  25 #include "reset.h"
  26 #include "gdsc.h"
  27
  28 enum {
  29         P_XO,
  30         P_GPLL0,
  31         P_GPLL0_AUX,
  32         P_BIMC,
  33         P_GPLL1,
  34         P_GPLL1_AUX,
  35         P_GPLL2,
  36         P_GPLL2_AUX,
  37         P_GPLL3,
  38         P_GPLL3_AUX,
  39         P_GPLL4,
  40         P_GPLL5,
  41         P_GPLL5_AUX,
  42         P_GPLL5_EARLY,
  43         P_GPLL6,
  44         P_GPLL6_AUX,
  45         P_SLEEP_CLK,
  46         P_DSI0_PHYPLL_BYTE,
  47         P_DSI0_PHYPLL_DSI,
  48         P_EXT_PRI_I2S,
  49         P_EXT_SEC_I2S,
  50         P_EXT_MCLK,
  51 };
  52
  53 static struct clk_pll gpll0 = {
  54         .l_reg = 0x21004,
  55         .m_reg = 0x21008,
  56         .n_reg = 0x2100c,
  57         .config_reg = 0x21010,
  58         .mode_reg = 0x21000,
  59         .status_reg = 0x2101c,
  60         .status_bit = 17,
  61         .clkr.hw.init = &(struct clk_init_data){
  62                 .name = "gpll0",
  63                 .parent_data = &(const struct clk_parent_data) {
  64                         .fw_name = "xo",
  65                 },
  66                 .num_parents = 1,
  67                 .ops = &clk_pll_ops,
  68         },
  69 };
  70
  71 static struct clk_regmap gpll0_vote = {
  72         .enable_reg = 0x45000,
  73         .enable_mask = BIT(0),
  74         .hw.init = &(struct clk_init_data){
  75                 .name = "gpll0_vote",
  76                 .parent_data = &(const struct clk_parent_data) {
  77                         .hw = &gpll0.clkr.hw,
  78                 },
  79                 .num_parents = 1,
  80                 .ops = &clk_pll_vote_ops,
  81         },
  82 };
  83
  84 static struct clk_pll gpll1 = {
  85         .l_reg = 0x20004,
  86         .m_reg = 0x20008,
  87         .n_reg = 0x2000c,
  88         .config_reg = 0x20010,
  89         .mode_reg = 0x20000,
  90         .status_reg = 0x2001c,
  91         .status_bit = 17,
  92         .clkr.hw.init = &(struct clk_init_data){
  93                 .name = "gpll1",
  94                 .parent_data = &(const struct clk_parent_data) {
  95                         .fw_name = "xo",
  96                 },
  97                 .num_parents = 1,
  98                 .ops = &clk_pll_ops,
  99         },
 100 };
 101
 102 static struct clk_regmap gpll1_vote = {
 103         .enable_reg = 0x45000,
 104         .enable_mask = BIT(1),
 105         .hw.init = &(struct clk_init_data){
 106                 .name = "gpll1_vote",
 107                 .parent_data = &(const struct clk_parent_data) {
 108                         .hw = &gpll1.clkr.hw,
 109                 },
 110                 .num_parents = 1,
 111                 .ops = &clk_pll_vote_ops,
 112         },
 113 };
 114
 115 static struct clk_pll gpll2 = {
 116         .l_reg = 0x4a004,
 117         .m_reg = 0x4a008,
 118         .n_reg = 0x4a00c,
 119         .config_reg = 0x4a010,
 120         .mode_reg = 0x4a000,
 121         .status_reg = 0x4a01c,
 122         .status_bit = 17,
 123         .clkr.hw.init = &(struct clk_init_data){
 124                 .name = "gpll2",
 125                 .parent_data = &(const struct clk_parent_data) {
 126                         .fw_name = "xo",
 127                 },
 128                 .num_parents = 1,
 129                 .ops = &clk_pll_ops,
 130         },
 131 };
 132
 133 static struct clk_regmap gpll2_vote = {
 134         .enable_reg = 0x45000,
 135         .enable_mask = BIT(2),
 136         .hw.init = &(struct clk_init_data){
 137                 .name = "gpll2_vote",
 138                 .parent_data = &(const struct clk_parent_data) {
 139                         .hw = &gpll2.clkr.hw,
 140                 },
 141                 .num_parents = 1,
 142                 .ops = &clk_pll_vote_ops,
 143         },
 144 };
 145
 146 static struct clk_pll bimc_pll = {
 147         .l_reg = 0x23004,
 148         .m_reg = 0x23008,
 149         .n_reg = 0x2300c,
 150         .config_reg = 0x23010,
 151         .mode_reg = 0x23000,
 152         .status_reg = 0x2301c,
 153         .status_bit = 17,
 154         .clkr.hw.init = &(struct clk_init_data){
 155                 .name = "bimc_pll",
 156                 .parent_data = &(const struct clk_parent_data) {
 157                         .fw_name = "xo",
 158                 },
 159                 .num_parents = 1,
 160                 .ops = &clk_pll_ops,
 161         },
 162 };
 163
 164 static struct clk_regmap bimc_pll_vote = {
 165         .enable_reg = 0x45000,
 166         .enable_mask = BIT(3),
 167         .hw.init = &(struct clk_init_data){
 168                 .name = "bimc_pll_vote",
 169                 .parent_data = &(const struct clk_parent_data) {
 170                         .hw = &bimc_pll.clkr.hw,
 171                 },
 172                 .num_parents = 1,
 173                 .ops = &clk_pll_vote_ops,
 174         },
 175 };
 176
 177 static struct clk_pll gpll3 = {
 178         .l_reg = 0x22004,
 179         .m_reg = 0x22008,
 180         .n_reg = 0x2200c,
 181         .config_reg = 0x22010,
 182         .mode_reg = 0x22000,
 183         .status_reg = 0x2201c,
 184         .status_bit = 17,
 185         .clkr.hw.init = &(struct clk_init_data){
 186                 .name = "gpll3",
 187                 .parent_data = &(const struct clk_parent_data) {
 188                         .fw_name = "xo",
 189                 },
 190                 .num_parents = 1,
 191                 .ops = &clk_pll_ops,
 192         },
 193 };
 194
 195 static struct clk_regmap gpll3_vote = {
 196         .enable_reg = 0x45000,
 197         .enable_mask = BIT(4),
 198         .hw.init = &(struct clk_init_data){
 199                 .name = "gpll3_vote",
 200                 .parent_data = &(const struct clk_parent_data) {
 201                         .hw = &gpll3.clkr.hw,
 202                 },
 203                 .num_parents = 1,
 204                 .ops = &clk_pll_vote_ops,
 205         },
 206 };
 207
 208 /* GPLL3 at 1100 MHz, main output enabled. */
 209 static const struct pll_config gpll3_config = {
 210         .l = 57,
 211         .m = 7,
 212         .n = 24,
 213         .vco_val = 0x0,
 214         .vco_mask = BIT(20),
 215         .pre_div_val = 0x0,
 216         .pre_div_mask = BIT(12),
 217         .post_div_val = 0x0,
 218         .post_div_mask = BIT(9) | BIT(8),
 219         .mn_ena_mask = BIT(24),
 220         .main_output_mask = BIT(0),
 221         .aux_output_mask = BIT(1),
 222 };
 223
 224 static struct clk_pll gpll4 = {
 225         .l_reg = 0x24004,
 226         .m_reg = 0x24008,
 227         .n_reg = 0x2400c,
 228         .config_reg = 0x24010,
 229         .mode_reg = 0x24000,
 230         .status_reg = 0x2401c,
 231         .status_bit = 17,
 232         .clkr.hw.init = &(struct clk_init_data){
 233                 .name = "gpll4",
 234                 .parent_data = &(const struct clk_parent_data) {
 235                         .fw_name = "xo",
 236                 },
 237                 .num_parents = 1,
 238                 .ops = &clk_pll_ops,
 239         },
 240 };
 241
 242 static struct clk_regmap gpll4_vote = {
 243         .enable_reg = 0x45000,
 244         .enable_mask = BIT(5),
 245         .hw.init = &(struct clk_init_data){
 246                 .name = "gpll4_vote",
 247                 .parent_data = &(const struct clk_parent_data) {
 248                         .hw = &gpll4.clkr.hw,
 249                 },
 250                 .num_parents = 1,
 251                 .ops = &clk_pll_vote_ops,
 252         },
 253 };
 254
 255 /* GPLL4 at 1200 MHz, main output enabled. */
 256 static struct pll_config gpll4_config = {
 257         .l = 62,
 258         .m = 1,
 259         .n = 2,
 260         .vco_val = 0x0,
 261         .vco_mask = BIT(20),
 262         .pre_div_val = 0x0,
 263         .pre_div_mask = BIT(12),
 264         .post_div_val = 0x0,
 265         .post_div_mask = BIT(9) | BIT(8),
 266         .mn_ena_mask = BIT(24),
 267         .main_output_mask = BIT(0),
 268 };
 269
 270 static struct clk_pll gpll5 = {
 271         .l_reg = 0x25004,
 272         .m_reg = 0x25008,
 273         .n_reg = 0x2500c,
 274         .config_reg = 0x25010,
 275         .mode_reg = 0x25000,
 276         .status_reg = 0x2501c,
 277         .status_bit = 17,
 278         .clkr.hw.init = &(struct clk_init_data){
 279                 .name = "gpll5",
 280                 .parent_data = &(const struct clk_parent_data) {
 281                         .fw_name = "xo",
 282                 },
 283                 .num_parents = 1,
 284                 .ops = &clk_pll_ops,
 285         },
 286 };
 287
 288 static struct clk_regmap gpll5_vote = {
 289         .enable_reg = 0x45000,
 290         .enable_mask = BIT(6),
 291         .hw.init = &(struct clk_init_data){
 292                 .name = "gpll5_vote",
 293                 .parent_data = &(const struct clk_parent_data) {
 294                         .hw = &gpll5.clkr.hw,
 295                 },
 296                 .num_parents = 1,
 297                 .ops = &clk_pll_vote_ops,
 298         },
 299 };
 300
 301 static struct clk_pll gpll6 = {
 302         .l_reg = 0x37004,
 303         .m_reg = 0x37008,
 304         .n_reg = 0x3700c,
 305         .config_reg = 0x37010,
 306         .mode_reg = 0x37000,
 307         .status_reg = 0x3701c,
 308         .status_bit = 17,
 309         .clkr.hw.init = &(struct clk_init_data){
 310                 .name = "gpll6",
 311                 .parent_data = &(const struct clk_parent_data) {
 312                         .fw_name = "xo",
 313                 },
 314                 .num_parents = 1,
 315                 .ops = &clk_pll_ops,
 316         },
 317 };
 318
 319 static struct clk_regmap gpll6_vote = {
 320         .enable_reg = 0x45000,
 321         .enable_mask = BIT(7),
 322         .hw.init = &(struct clk_init_data){
 323                 .name = "gpll6_vote",
 324                 .parent_data = &(const struct clk_parent_data) {
 325                         .hw = &gpll6.clkr.hw,
 326                 },
 327                 .num_parents = 1,
 328                 .ops = &clk_pll_vote_ops,
 329         },
 330 };
 331
 332 static const struct parent_map gcc_xo_gpll0_map[] = {
 333         { P_XO, 0 },
 334         { P_GPLL0, 1 },
 335 };
 336
 337 static const struct clk_parent_data gcc_xo_gpll0_parent_data[] = {
 338         { .fw_name = "xo" },
 339         { .hw = &gpll0_vote.hw },
 340 };
 341
 342 static const struct parent_map gcc_xo_gpll0_bimc_map[] = {
 343         { P_XO, 0 },
 344         { P_GPLL0, 1 },
 345         { P_BIMC, 2 },
 346 };
 347
 348 static const struct clk_parent_data gcc_xo_gpll0_bimc_parent_data[] = {
 349         { .fw_name = "xo" },
 350         { .hw = &gpll0_vote.hw },
 351         { .hw = &bimc_pll_vote.hw },
 352 };
 353
 354 static const struct parent_map gcc_xo_gpll0_gpll6a_map[] = {
 355         { P_XO, 0 },
 356         { P_GPLL0, 1 },
 357         { P_GPLL6_AUX, 2 },
 358 };
 359
 360 static const struct clk_parent_data gcc_xo_gpll0_gpll6a_parent_data[] = {
 361         { .fw_name = "xo" },
 362         { .hw = &gpll0_vote.hw },
 363         { .hw = &gpll6_vote.hw },
 364 };
 365
 366 static const struct parent_map gcc_xo_gpll0_gpll2a_gpll3_gpll6a_map[] = {
 367         { P_XO, 0 },
 368         { P_GPLL0, 1 },
 369         { P_GPLL2_AUX, 4 },
 370         { P_GPLL3, 2 },
 371         { P_GPLL6_AUX, 3 },
 372 };
 373
 374 static const struct clk_parent_data gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data[] = {
 375         { .fw_name = "xo" },
 376         { .hw = &gpll0_vote.hw },
 377         { .hw = &gpll2_vote.hw },
 378         { .hw = &gpll3_vote.hw },
 379         { .hw = &gpll6_vote.hw },
 380 };
 381
 382 static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
 383         { P_XO, 0 },
 384         { P_GPLL0, 1 },
 385         { P_GPLL2, 2 },
 386 };
 387
 388 static const struct clk_parent_data gcc_xo_gpll0_gpll2_parent_data[] = {
 389         { .fw_name = "xo" },
 390         { .hw = &gpll0_vote.hw },
 391         { .hw = &gpll2_vote.hw },
 392 };
 393
 394 static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_map[] = {
 395         { P_XO, 0 },
 396         { P_GPLL0, 1 },
 397         { P_GPLL2, 3 },
 398         { P_GPLL4, 2 },
 399 };
 400
 401 static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4_parent_data[] = {
 402         { .fw_name = "xo" },
 403         { .hw = &gpll0_vote.hw },
 404         { .hw = &gpll2_vote.hw },
 405         { .hw = &gpll4_vote.hw },
 406 };
 407
 408 static const struct parent_map gcc_xo_gpll0a_map[] = {
 409         { P_XO, 0 },
 410         { P_GPLL0_AUX, 2 },
 411 };
 412
 413 static const struct clk_parent_data gcc_xo_gpll0a_parent_data[] = {
 414         { .fw_name = "xo" },
 415         { .hw = &gpll0_vote.hw },
 416 };
 417
 418 static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = {
 419         { P_XO, 0 },
 420         { P_GPLL0, 1 },
 421         { P_GPLL1_AUX, 2 },
 422         { P_SLEEP_CLK, 6 },
 423 };
 424
 425 static const struct clk_parent_data gcc_xo_gpll0_gpll1a_sleep_parent_data[] = {
 426         { .fw_name = "xo" },
 427         { .hw = &gpll0_vote.hw },
 428         { .hw = &gpll1_vote.hw },
 429         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 430 };
 431
 432 static const struct parent_map gcc_xo_gpll0_gpll1a_gpll6_sleep_map[] = {
 433         { P_XO, 0 },
 434         { P_GPLL0, 1 },
 435         { P_GPLL1_AUX, 2 },
 436         { P_GPLL6, 2 },
 437         { P_SLEEP_CLK, 6 },
 438 };
 439
 440 static const struct clk_parent_data gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data[] = {
 441         { .fw_name = "xo" },
 442         { .hw = &gpll0_vote.hw },
 443         { .hw = &gpll1_vote.hw },
 444         { .hw = &gpll6_vote.hw },
 445         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 446 };
 447
 448 static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = {
 449         { P_XO, 0 },
 450         { P_GPLL0, 1 },
 451         { P_GPLL1_AUX, 2 },
 452 };
 453
 454 static const struct clk_parent_data gcc_xo_gpll0_gpll1a_parent_data[] = {
 455         { .fw_name = "xo" },
 456         { .hw = &gpll0_vote.hw },
 457         { .hw = &gpll1_vote.hw },
 458 };
 459
 460 static const struct parent_map gcc_xo_dsibyte_map[] = {
 461         { P_XO, 0, },
 462         { P_DSI0_PHYPLL_BYTE, 2 },
 463 };
 464
 465 static const struct clk_parent_data gcc_xo_dsibyte_parent_data[] = {
 466         { .fw_name = "xo" },
 467         { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
 468 };
 469
 470 static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = {
 471         { P_XO, 0 },
 472         { P_GPLL0_AUX, 2 },
 473         { P_DSI0_PHYPLL_BYTE, 1 },
 474 };
 475
 476 static const struct clk_parent_data gcc_xo_gpll0a_dsibyte_parent_data[] = {
 477         { .fw_name = "xo" },
 478         { .hw = &gpll0_vote.hw },
 479         { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
 480 };
 481
 482 static const struct parent_map gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_map[] = {
 483         { P_XO, 0 },
 484         { P_GPLL1, 1 },
 485         { P_DSI0_PHYPLL_DSI, 2 },
 486         { P_GPLL6, 3 },
 487         { P_GPLL3_AUX, 4 },
 488         { P_GPLL0_AUX, 5 },
 489 };
 490
 491 static const struct clk_parent_data gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data[] = {
 492         { .fw_name = "xo" },
 493         { .hw = &gpll1_vote.hw },
 494         { .fw_name = "dsi0pll", .name = "dsi0pll" },
 495         { .hw = &gpll6_vote.hw },
 496         { .hw = &gpll3_vote.hw },
 497         { .hw = &gpll0_vote.hw },
 498 };
 499
 500 static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = {
 501         { P_XO, 0 },
 502         { P_GPLL0_AUX, 2 },
 503         { P_DSI0_PHYPLL_DSI, 1 },
 504 };
 505
 506 static const struct clk_parent_data gcc_xo_gpll0a_dsiphy_parent_data[] = {
 507         { .fw_name = "xo" },
 508         { .hw = &gpll0_vote.hw },
 509         { .fw_name = "dsi0pll", .name = "dsi0pll" },
 510 };
 511
 512 static const struct parent_map gcc_xo_gpll0_gpll5a_gpll6_bimc_map[] = {
 513         { P_XO, 0 },
 514         { P_GPLL0, 1 },
 515         { P_GPLL5_AUX, 3 },
 516         { P_GPLL6, 2 },
 517         { P_BIMC, 4 },
 518 };
 519
 520 static const struct clk_parent_data gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data[] = {
 521         { .fw_name = "xo" },
 522         { .hw = &gpll0_vote.hw },
 523         { .hw = &gpll5_vote.hw },
 524         { .hw = &gpll6_vote.hw },
 525         { .hw = &bimc_pll_vote.hw },
 526 };
 527
 528 static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = {
 529         { P_XO, 0 },
 530         { P_GPLL0, 1 },
 531         { P_GPLL1, 2 },
 532         { P_SLEEP_CLK, 6 }
 533 };
 534
 535 static const struct clk_parent_data gcc_xo_gpll0_gpll1_sleep_parent_data[] = {
 536         { .fw_name = "xo" },
 537         { .hw = &gpll0_vote.hw },
 538         { .hw = &gpll1_vote.hw },
 539         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 540 };
 541
 542 static const struct parent_map gcc_xo_gpll1_epi2s_emclk_sleep_map[] = {
 543         { P_XO, 0 },
 544         { P_GPLL1, 1 },
 545         { P_EXT_PRI_I2S, 2 },
 546         { P_EXT_MCLK, 3 },
 547         { P_SLEEP_CLK, 6 }
 548 };
 549
 550 static const struct clk_parent_data gcc_xo_gpll1_epi2s_emclk_sleep_parent_data[] = {
 551         { .fw_name = "xo" },
 552         { .hw = &gpll0_vote.hw },
 553         { .fw_name = "ext_pri_i2s", .name = "ext_pri_i2s" },
 554         { .fw_name = "ext_mclk", .name = "ext_mclk" },
 555         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 556 };
 557
 558 static const struct parent_map gcc_xo_gpll1_esi2s_emclk_sleep_map[] = {
 559         { P_XO, 0 },
 560         { P_GPLL1, 1 },
 561         { P_EXT_SEC_I2S, 2 },
 562         { P_EXT_MCLK, 3 },
 563         { P_SLEEP_CLK, 6 }
 564 };
 565
 566 static const struct clk_parent_data gcc_xo_gpll1_esi2s_emclk_sleep_parent_data[] = {
 567         { .fw_name = "xo" },
 568         { .hw = &gpll1_vote.hw },
 569         { .fw_name = "ext_sec_i2s", .name = "ext_sec_i2s" },
 570         { .fw_name = "ext_mclk", .name = "ext_mclk" },
 571         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 572 };
 573
 574 static const struct parent_map gcc_xo_sleep_map[] = {
 575         { P_XO, 0 },
 576         { P_SLEEP_CLK, 6 }
 577 };
 578
 579 static const struct clk_parent_data gcc_xo_sleep_parent_data[] = {
 580         { .fw_name = "xo" },
 581         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 582 };
 583
 584 static const struct parent_map gcc_xo_gpll1_emclk_sleep_map[] = {
 585         { P_XO, 0 },
 586         { P_GPLL1, 1 },
 587         { P_EXT_MCLK, 2 },
 588         { P_SLEEP_CLK, 6 }
 589 };
 590
 591 static const struct clk_parent_data gcc_xo_gpll1_emclk_sleep_parent_data[] = {
 592         { .fw_name = "xo" },
 593         { .hw = &gpll1_vote.hw },
 594         { .fw_name = "ext_mclk", .name = "ext_mclk" },
 595         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 596 };
 597
 598 static const struct clk_parent_data gcc_xo_gpll6_gpll0_parent_data[] = {
 599         { .fw_name = "xo" },
 600         { .hw = &gpll6_vote.hw },
 601         { .hw = &gpll0_vote.hw },
 602 };
 603
 604 static const struct clk_parent_data gcc_xo_gpll6_gpll0a_parent_data[] = {
 605         { .fw_name = "xo" },
 606         { .hw = &gpll6_vote.hw },
 607         { .hw = &gpll0_vote.hw },
 608 };
 609
 610 static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
 611         .cmd_rcgr = 0x27000,
 612         .hid_width = 5,
 613         .parent_map = gcc_xo_gpll0_map,
 614         .clkr.hw.init = &(struct clk_init_data){
 615                 .name = "pcnoc_bfdcd_clk_src",
 616                 .parent_data = gcc_xo_gpll0_parent_data,
 617                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 618                 .ops = &clk_rcg2_ops,
 619         },
 620 };
 621
 622 static struct clk_rcg2 system_noc_bfdcd_clk_src = {
 623         .cmd_rcgr = 0x26004,
 624         .hid_width = 5,
 625         .parent_map = gcc_xo_gpll0_gpll6a_map,
 626         .clkr.hw.init = &(struct clk_init_data){
 627                 .name = "system_noc_bfdcd_clk_src",
 628                 .parent_data = gcc_xo_gpll0_gpll6a_parent_data,
 629                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6a_parent_data),
 630                 .ops = &clk_rcg2_ops,
 631         },
 632 };
 633
 634 static struct clk_rcg2 bimc_ddr_clk_src = {
 635         .cmd_rcgr = 0x32024,
 636         .hid_width = 5,
 637         .parent_map = gcc_xo_gpll0_bimc_map,
 638         .clkr.hw.init = &(struct clk_init_data){
 639                 .name = "bimc_ddr_clk_src",
 640                 .parent_data = gcc_xo_gpll0_bimc_parent_data,
 641                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc_parent_data),
 642                 .ops = &clk_rcg2_ops,
 643                 .flags = CLK_GET_RATE_NOCACHE,
 644         },
 645 };
 646
 647 static struct clk_rcg2 system_mm_noc_bfdcd_clk_src = {
 648         .cmd_rcgr = 0x2600c,
 649         .hid_width = 5,
 650         .parent_map = gcc_xo_gpll0_gpll6a_map,
 651         .clkr.hw.init = &(struct clk_init_data){
 652                 .name = "system_mm_noc_bfdcd_clk_src",
 653                 .parent_data = gcc_xo_gpll0_gpll6a_parent_data,
 654                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6a_parent_data),
 655                 .ops = &clk_rcg2_ops,
 656         },
 657 };
 658
 659 static const struct freq_tbl ftbl_gcc_camss_ahb_clk[] = {
 660         F(40000000, P_GPLL0, 10, 1, 2),
 661         F(80000000, P_GPLL0, 10, 0, 0),
 662         { }
 663 };
 664
 665 static struct clk_rcg2 camss_ahb_clk_src = {
 666         .cmd_rcgr = 0x5a000,
 667         .mnd_width = 8,
 668         .hid_width = 5,
 669         .parent_map = gcc_xo_gpll0_map,
 670         .freq_tbl = ftbl_gcc_camss_ahb_clk,
 671         .clkr.hw.init = &(struct clk_init_data){
 672                 .name = "camss_ahb_clk_src",
 673                 .parent_data = gcc_xo_gpll0_parent_data,
 674                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 675                 .ops = &clk_rcg2_ops,
 676         },
 677 };
 678
 679 static const struct freq_tbl ftbl_apss_ahb_clk[] = {
 680         F(19200000, P_XO, 1, 0, 0),
 681         F(50000000, P_GPLL0, 16, 0, 0),
 682         F(100000000, P_GPLL0, 8, 0, 0),
 683         F(133330000, P_GPLL0, 6, 0, 0),
 684         { }
 685 };
 686
 687 static struct clk_rcg2 apss_ahb_clk_src = {
 688         .cmd_rcgr = 0x46000,
 689         .hid_width = 5,
 690         .parent_map = gcc_xo_gpll0_map,
 691         .freq_tbl = ftbl_apss_ahb_clk,
 692         .clkr.hw.init = &(struct clk_init_data){
 693                 .name = "apss_ahb_clk_src",
 694                 .parent_data = gcc_xo_gpll0_parent_data,
 695                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 696                 .ops = &clk_rcg2_ops,
 697         },
 698 };
 699
 700 static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = {
 701         F(100000000, P_GPLL0, 8, 0,     0),
 702         F(200000000, P_GPLL0, 4, 0,     0),
 703         { }
 704 };
 705
 706 static struct clk_rcg2 csi0_clk_src = {
 707         .cmd_rcgr = 0x4e020,
 708         .hid_width = 5,
 709         .parent_map = gcc_xo_gpll0_map,
 710         .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
 711         .clkr.hw.init = &(struct clk_init_data){
 712                 .name = "csi0_clk_src",
 713                 .parent_data = gcc_xo_gpll0_parent_data,
 714                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 715                 .ops = &clk_rcg2_ops,
 716         },
 717 };
 718
 719 static struct clk_rcg2 csi1_clk_src = {
 720         .cmd_rcgr = 0x4f020,
 721         .hid_width = 5,
 722         .parent_map = gcc_xo_gpll0_map,
 723         .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
 724         .clkr.hw.init = &(struct clk_init_data){
 725                 .name = "csi1_clk_src",
 726                 .parent_data = gcc_xo_gpll0_parent_data,
 727                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 728                 .ops = &clk_rcg2_ops,
 729         },
 730 };
 731
 732 static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
 733         F(19200000, P_XO, 1, 0, 0),
 734         F(50000000, P_GPLL0, 16, 0, 0),
 735         F(80000000, P_GPLL0, 10, 0, 0),
 736         F(100000000, P_GPLL0, 8, 0, 0),
 737         F(160000000, P_GPLL0, 5, 0, 0),
 738         F(200000000, P_GPLL0, 4, 0, 0),
 739         F(220000000, P_GPLL3, 5, 0, 0),
 740         F(266670000, P_GPLL0, 3, 0, 0),
 741         F(310000000, P_GPLL2_AUX, 3, 0, 0),
 742         F(400000000, P_GPLL0, 2, 0, 0),
 743         F(465000000, P_GPLL2_AUX, 2, 0, 0),
 744         F(550000000, P_GPLL3, 2, 0, 0),
 745         { }
 746 };
 747
 748 static struct clk_rcg2 gfx3d_clk_src = {
 749         .cmd_rcgr = 0x59000,
 750         .hid_width = 5,
 751         .parent_map = gcc_xo_gpll0_gpll2a_gpll3_gpll6a_map,
 752         .freq_tbl = ftbl_gcc_oxili_gfx3d_clk,
 753         .clkr.hw.init = &(struct clk_init_data){
 754                 .name = "gfx3d_clk_src",
 755                 .parent_data = gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data,
 756                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data),
 757                 .ops = &clk_rcg2_ops,
 758         },
 759 };
 760
 761 static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] = {
 762         F(50000000, P_GPLL0, 16, 0, 0),
 763         F(80000000, P_GPLL0, 10, 0, 0),
 764         F(100000000, P_GPLL0, 8, 0, 0),
 765         F(160000000, P_GPLL0, 5, 0, 0),
 766         F(177780000, P_GPLL0, 4.5, 0, 0),
 767         F(200000000, P_GPLL0, 4, 0, 0),
 768         F(266670000, P_GPLL0, 3, 0, 0),
 769         F(320000000, P_GPLL0, 2.5, 0, 0),
 770         F(400000000, P_GPLL0, 2, 0, 0),
 771         F(465000000, P_GPLL2, 2, 0, 0),
 772         F(480000000, P_GPLL4, 2.5, 0, 0),
 773         F(600000000, P_GPLL4, 2, 0, 0),
 774         { }
 775 };
 776
 777 static struct clk_rcg2 vfe0_clk_src = {
 778         .cmd_rcgr = 0x58000,
 779         .hid_width = 5,
 780         .parent_map = gcc_xo_gpll0_gpll2_gpll4_map,
 781         .freq_tbl = ftbl_gcc_camss_vfe0_clk,
 782         .clkr.hw.init = &(struct clk_init_data){
 783                 .name = "vfe0_clk_src",
 784                 .parent_data = gcc_xo_gpll0_gpll2_gpll4_parent_data,
 785                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4_parent_data),
 786                 .ops = &clk_rcg2_ops,
 787         },
 788 };
 789
 790 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
 791         F(19200000, P_XO, 1, 0, 0),
 792         F(50000000, P_GPLL0, 16, 0, 0),
 793         { }
 794 };
 795
 796 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 797         .cmd_rcgr = 0x0200c,
 798         .hid_width = 5,
 799         .parent_map = gcc_xo_gpll0_map,
 800         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 801         .clkr.hw.init = &(struct clk_init_data){
 802                 .name = "blsp1_qup1_i2c_apps_clk_src",
 803                 .parent_data = gcc_xo_gpll0_parent_data,
 804                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 805                 .ops = &clk_rcg2_ops,
 806         },
 807 };
 808
 809 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
 810         F(960000, P_XO, 10, 1, 2),
 811         F(4800000, P_XO, 4, 0, 0),
 812         F(9600000, P_XO, 2, 0, 0),
 813         F(16000000, P_GPLL0, 10, 1, 5),
 814         F(19200000, P_XO, 1, 0, 0),
 815         F(25000000, P_GPLL0, 16, 1, 2),
 816         F(50000000, P_GPLL0, 16, 0, 0),
 817         { }
 818 };
 819
 820 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 821         .cmd_rcgr = 0x02024,
 822         .mnd_width = 8,
 823         .hid_width = 5,
 824         .parent_map = gcc_xo_gpll0_map,
 825         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 826         .clkr.hw.init = &(struct clk_init_data){
 827                 .name = "blsp1_qup1_spi_apps_clk_src",
 828                 .parent_data = gcc_xo_gpll0_parent_data,
 829                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 830                 .ops = &clk_rcg2_ops,
 831         },
 832 };
 833
 834 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 835         .cmd_rcgr = 0x03000,
 836         .hid_width = 5,
 837         .parent_map = gcc_xo_gpll0_map,
 838         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 839         .clkr.hw.init = &(struct clk_init_data){
 840                 .name = "blsp1_qup2_i2c_apps_clk_src",
 841                 .parent_data = gcc_xo_gpll0_parent_data,
 842                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 843                 .ops = &clk_rcg2_ops,
 844         },
 845 };
 846
 847 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 848         .cmd_rcgr = 0x03014,
 849         .mnd_width = 8,
 850         .hid_width = 5,
 851         .parent_map = gcc_xo_gpll0_map,
 852         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 853         .clkr.hw.init = &(struct clk_init_data){
 854                 .name = "blsp1_qup2_spi_apps_clk_src",
 855                 .parent_data = gcc_xo_gpll0_parent_data,
 856                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 857                 .ops = &clk_rcg2_ops,
 858         },
 859 };
 860
 861 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 862         .cmd_rcgr = 0x04000,
 863         .hid_width = 5,
 864         .parent_map = gcc_xo_gpll0_map,
 865         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 866         .clkr.hw.init = &(struct clk_init_data){
 867                 .name = "blsp1_qup3_i2c_apps_clk_src",
 868                 .parent_data = gcc_xo_gpll0_parent_data,
 869                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 870                 .ops = &clk_rcg2_ops,
 871         },
 872 };
 873
 874 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 875         .cmd_rcgr = 0x04024,
 876         .mnd_width = 8,
 877         .hid_width = 5,
 878         .parent_map = gcc_xo_gpll0_map,
 879         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 880         .clkr.hw.init = &(struct clk_init_data){
 881                 .name = "blsp1_qup3_spi_apps_clk_src",
 882                 .parent_data = gcc_xo_gpll0_parent_data,
 883                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 884                 .ops = &clk_rcg2_ops,
 885         },
 886 };
 887
 888 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 889         .cmd_rcgr = 0x05000,
 890         .hid_width = 5,
 891         .parent_map = gcc_xo_gpll0_map,
 892         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 893         .clkr.hw.init = &(struct clk_init_data){
 894                 .name = "blsp1_qup4_i2c_apps_clk_src",
 895                 .parent_data = gcc_xo_gpll0_parent_data,
 896                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 897                 .ops = &clk_rcg2_ops,
 898         },
 899 };
 900
 901 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 902         .cmd_rcgr = 0x05024,
 903         .mnd_width = 8,
 904         .hid_width = 5,
 905         .parent_map = gcc_xo_gpll0_map,
 906         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 907         .clkr.hw.init = &(struct clk_init_data){
 908                 .name = "blsp1_qup4_spi_apps_clk_src",
 909                 .parent_data = gcc_xo_gpll0_parent_data,
 910                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 911                 .ops = &clk_rcg2_ops,
 912         },
 913 };
 914
 915 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 916         .cmd_rcgr = 0x06000,
 917         .hid_width = 5,
 918         .parent_map = gcc_xo_gpll0_map,
 919         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 920         .clkr.hw.init = &(struct clk_init_data){
 921                 .name = "blsp1_qup5_i2c_apps_clk_src",
 922                 .parent_data = gcc_xo_gpll0_parent_data,
 923                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 924                 .ops = &clk_rcg2_ops,
 925         },
 926 };
 927
 928 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 929         .cmd_rcgr = 0x06024,
 930         .mnd_width = 8,
 931         .hid_width = 5,
 932         .parent_map = gcc_xo_gpll0_map,
 933         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 934         .clkr.hw.init = &(struct clk_init_data){
 935                 .name = "blsp1_qup5_spi_apps_clk_src",
 936                 .parent_data = gcc_xo_gpll0_parent_data,
 937                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 938                 .ops = &clk_rcg2_ops,
 939         },
 940 };
 941
 942 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 943         .cmd_rcgr = 0x07000,
 944         .hid_width = 5,
 945         .parent_map = gcc_xo_gpll0_map,
 946         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 947         .clkr.hw.init = &(struct clk_init_data){
 948                 .name = "blsp1_qup6_i2c_apps_clk_src",
 949                 .parent_data = gcc_xo_gpll0_parent_data,
 950                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 951                 .ops = &clk_rcg2_ops,
 952         },
 953 };
 954
 955 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 956         .cmd_rcgr = 0x07024,
 957         .mnd_width = 8,
 958         .hid_width = 5,
 959         .parent_map = gcc_xo_gpll0_map,
 960         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 961         .clkr.hw.init = &(struct clk_init_data){
 962                 .name = "blsp1_qup6_spi_apps_clk_src",
 963                 .parent_data = gcc_xo_gpll0_parent_data,
 964                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 965                 .ops = &clk_rcg2_ops,
 966         },
 967 };
 968
 969 static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
 970         F(3686400, P_GPLL0, 1, 72, 15625),
 971         F(7372800, P_GPLL0, 1, 144, 15625),
 972         F(14745600, P_GPLL0, 1, 288, 15625),
 973         F(16000000, P_GPLL0, 10, 1, 5),
 974         F(19200000, P_XO, 1, 0, 0),
 975         F(24000000, P_GPLL0, 1, 3, 100),
 976         F(25000000, P_GPLL0, 16, 1, 2),
 977         F(32000000, P_GPLL0, 1, 1, 25),
 978         F(40000000, P_GPLL0, 1, 1, 20),
 979         F(46400000, P_GPLL0, 1, 29, 500),
 980         F(48000000, P_GPLL0, 1, 3, 50),
 981         F(51200000, P_GPLL0, 1, 8, 125),
 982         F(56000000, P_GPLL0, 1, 7, 100),
 983         F(58982400, P_GPLL0, 1, 1152, 15625),
 984         F(60000000, P_GPLL0, 1, 3, 40),
 985         { }
 986 };
 987
 988 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 989         .cmd_rcgr = 0x02044,
 990         .mnd_width = 16,
 991         .hid_width = 5,
 992         .parent_map = gcc_xo_gpll0_map,
 993         .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
 994         .clkr.hw.init = &(struct clk_init_data){
 995                 .name = "blsp1_uart1_apps_clk_src",
 996                 .parent_data = gcc_xo_gpll0_parent_data,
 997                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 998                 .ops = &clk_rcg2_ops,
 999         },
1000 };
1001
1002 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
1003         .cmd_rcgr = 0x03034,
1004         .mnd_width = 16,
1005         .hid_width = 5,
1006         .parent_map = gcc_xo_gpll0_map,
1007         .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
1008         .clkr.hw.init = &(struct clk_init_data){
1009                 .name = "blsp1_uart2_apps_clk_src",
1010                 .parent_data = gcc_xo_gpll0_parent_data,
1011                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
1012                 .ops = &clk_rcg2_ops,
1013         },
1014 };
1015
1016 static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = {
1017         F(19200000, P_XO, 1, 0, 0),
1018         F(37500000, P_GPLL0, 1, 3, 64),
1019         { }
1020 };
1021
1022 static struct clk_rcg2 cci_clk_src = {
1023         .cmd_rcgr = 0x51000,
1024         .mnd_width = 8,
1025         .hid_width = 5,
1026         .parent_map = gcc_xo_gpll0a_map,
1027         .freq_tbl = ftbl_gcc_camss_cci_clk,
1028         .clkr.hw.init = &(struct clk_init_data){
1029                 .name = "cci_clk_src",
1030                 .parent_data = gcc_xo_gpll0a_parent_data,
1031                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_parent_data),
1032                 .ops = &clk_rcg2_ops,
1033         },
1034 };
1035
1036 static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = {
1037         F(100000000, P_GPLL0, 8, 0, 0),
1038         F(200000000, P_GPLL0, 4, 0, 0),
1039         { }
1040 };
1041
1042 static struct clk_rcg2 camss_gp0_clk_src = {
1043         .cmd_rcgr = 0x54000,
1044         .mnd_width = 8,
1045         .hid_width = 5,
1046         .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
1047         .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
1048         .clkr.hw.init = &(struct clk_init_data){
1049                 .name = "camss_gp0_clk_src",
1050                 .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
1051                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
1052                 .ops = &clk_rcg2_ops,
1053         },
1054 };
1055
1056 static struct clk_rcg2 camss_gp1_clk_src = {
1057         .cmd_rcgr = 0x55000,
1058         .mnd_width = 8,
1059         .hid_width = 5,
1060         .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
1061         .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
1062         .clkr.hw.init = &(struct clk_init_data){
1063                 .name = "camss_gp1_clk_src",
1064                 .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
1065                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
1066                 .ops = &clk_rcg2_ops,
1067         },
1068 };
1069
1070 static const struct freq_tbl ftbl_gcc_camss_jpeg0_clk[] = {
1071         F(133330000, P_GPLL0, 6, 0,     0),
1072         F(266670000, P_GPLL0, 3, 0,     0),
1073         F(320000000, P_GPLL0, 2.5, 0, 0),
1074         { }
1075 };
1076
1077 static struct clk_rcg2 jpeg0_clk_src = {
1078         .cmd_rcgr = 0x57000,
1079         .hid_width = 5,
1080         .parent_map = gcc_xo_gpll0_map,
1081         .freq_tbl = ftbl_gcc_camss_jpeg0_clk,
1082         .clkr.hw.init = &(struct clk_init_data){
1083                 .name = "jpeg0_clk_src",
1084                 .parent_data = gcc_xo_gpll0_parent_data,
1085                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
1086                 .ops = &clk_rcg2_ops,
1087         },
1088 };
1089
1090 static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = {
1091         F(24000000, P_GPLL0, 1, 1, 45),
1092         F(66670000, P_GPLL0, 12, 0, 0),
1093         { }
1094 };
1095
1096 static struct clk_rcg2 mclk0_clk_src = {
1097         .cmd_rcgr = 0x52000,
1098         .mnd_width = 8,
1099         .hid_width = 5,
1100         .parent_map = gcc_xo_gpll0_gpll1a_gpll6_sleep_map,
1101         .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
1102         .clkr.hw.init = &(struct clk_init_data){
1103                 .name = "mclk0_clk_src",
1104                 .parent_data = gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data,
1105                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data),
1106                 .ops = &clk_rcg2_ops,
1107         },
1108 };
1109
1110 static struct clk_rcg2 mclk1_clk_src = {
1111         .cmd_rcgr = 0x53000,
1112         .mnd_width = 8,
1113         .hid_width = 5,
1114         .parent_map = gcc_xo_gpll0_gpll1a_gpll6_sleep_map,
1115         .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
1116         .clkr.hw.init = &(struct clk_init_data){
1117                 .name = "mclk1_clk_src",
1118                 .parent_data = gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data,
1119                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data),
1120                 .ops = &clk_rcg2_ops,
1121         },
1122 };
1123
1124 static const struct freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = {
1125         F(100000000, P_GPLL0, 8, 0,     0),
1126         F(200000000, P_GPLL0, 4, 0,     0),
1127         { }
1128 };
1129
1130 static struct clk_rcg2 csi0phytimer_clk_src = {
1131         .cmd_rcgr = 0x4e000,
1132         .hid_width = 5,
1133         .parent_map = gcc_xo_gpll0_gpll1a_map,
1134         .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
1135         .clkr.hw.init = &(struct clk_init_data){
1136                 .name = "csi0phytimer_clk_src",
1137                 .parent_data = gcc_xo_gpll0_gpll1a_parent_data,
1138                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_parent_data),
1139                 .ops = &clk_rcg2_ops,
1140         },
1141 };
1142
1143 static struct clk_rcg2 csi1phytimer_clk_src = {
1144         .cmd_rcgr = 0x4f000,
1145         .hid_width = 5,
1146         .parent_map = gcc_xo_gpll0_gpll1a_map,
1147         .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
1148         .clkr.hw.init = &(struct clk_init_data){
1149                 .name = "csi1phytimer_clk_src",
1150                 .parent_data = gcc_xo_gpll0_gpll1a_parent_data,
1151                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_parent_data),
1152                 .ops = &clk_rcg2_ops,
1153         },
1154 };
1155
1156 static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = {
1157         F(160000000, P_GPLL0, 5, 0, 0),
1158         F(200000000, P_GPLL0, 4, 0, 0),
1159         F(228570000, P_GPLL0, 3.5, 0, 0),
1160         F(266670000, P_GPLL0, 3, 0, 0),
1161         F(320000000, P_GPLL0, 2.5, 0, 0),
1162         F(465000000, P_GPLL2, 2, 0, 0),
1163         { }
1164 };
1165
1166 static struct clk_rcg2 cpp_clk_src = {
1167         .cmd_rcgr = 0x58018,
1168         .hid_width = 5,
1169         .parent_map = gcc_xo_gpll0_gpll2_map,
1170         .freq_tbl = ftbl_gcc_camss_cpp_clk,
1171         .clkr.hw.init = &(struct clk_init_data){
1172                 .name = "cpp_clk_src",
1173                 .parent_data = gcc_xo_gpll0_gpll2_parent_data,
1174                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_parent_data),
1175                 .ops = &clk_rcg2_ops,
1176         },
1177 };
1178
1179 static const struct freq_tbl ftbl_gcc_crypto_clk[] = {
1180         F(50000000, P_GPLL0, 16, 0, 0),
1181         F(80000000, P_GPLL0, 10, 0, 0),
1182         F(100000000, P_GPLL0, 8, 0, 0),
1183         F(160000000, P_GPLL0, 5, 0, 0),
1184         { }
1185 };
1186
1187 /* This is not in the documentation but is in the downstream driver */
1188 static struct clk_rcg2 crypto_clk_src = {
1189         .cmd_rcgr = 0x16004,
1190         .hid_width = 5,
1191         .parent_map = gcc_xo_gpll0_map,
1192         .freq_tbl = ftbl_gcc_crypto_clk,
1193         .clkr.hw.init = &(struct clk_init_data){
1194                 .name = "crypto_clk_src",
1195                 .parent_data = gcc_xo_gpll0_parent_data,
1196                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
1197                 .ops = &clk_rcg2_ops,
1198         },
1199 };
1200
1201 static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = {
1202         F(19200000, P_XO, 1, 0, 0),
1203         { }
1204 };
1205
1206 static struct clk_rcg2 gp1_clk_src = {
1207         .cmd_rcgr = 0x08004,
1208         .mnd_width = 8,
1209         .hid_width = 5,
1210         .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
1211         .freq_tbl = ftbl_gcc_gp1_3_clk,
1212         .clkr.hw.init = &(struct clk_init_data){
1213                 .name = "gp1_clk_src",
1214                 .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
1215                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
1216                 .ops = &clk_rcg2_ops,
1217         },
1218 };
1219
1220 static struct clk_rcg2 gp2_clk_src = {
1221         .cmd_rcgr = 0x09004,
1222         .mnd_width = 8,
1223         .hid_width = 5,
1224         .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
1225         .freq_tbl = ftbl_gcc_gp1_3_clk,
1226         .clkr.hw.init = &(struct clk_init_data){
1227                 .name = "gp2_clk_src",
1228                 .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
1229                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
1230                 .ops = &clk_rcg2_ops,
1231         },
1232 };
1233
1234 static struct clk_rcg2 gp3_clk_src = {
1235         .cmd_rcgr = 0x0a004,
1236         .mnd_width = 8,
1237         .hid_width = 5,
1238         .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
1239         .freq_tbl = ftbl_gcc_gp1_3_clk,
1240         .clkr.hw.init = &(struct clk_init_data){
1241                 .name = "gp3_clk_src",
1242                 .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
1243                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
1244                 .ops = &clk_rcg2_ops,
1245         },
1246 };
1247
1248 static struct clk_rcg2 byte0_clk_src = {
1249         .cmd_rcgr = 0x4d044,
1250         .hid_width = 5,
1251         .parent_map = gcc_xo_gpll0a_dsibyte_map,
1252         .clkr.hw.init = &(struct clk_init_data){
1253                 .name = "byte0_clk_src",
1254                 .parent_data = gcc_xo_gpll0a_dsibyte_parent_data,
1255                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsibyte_parent_data),
1256                 .ops = &clk_byte2_ops,
1257                 .flags = CLK_SET_RATE_PARENT,
1258         },
1259 };
1260
1261 static struct clk_rcg2 byte1_clk_src = {
1262         .cmd_rcgr = 0x4d0b0,
1263         .hid_width = 5,
1264         .parent_map = gcc_xo_gpll0a_dsibyte_map,
1265         .clkr.hw.init = &(struct clk_init_data){
1266                 .name = "byte1_clk_src",
1267                 .parent_data = gcc_xo_gpll0a_dsibyte_parent_data,
1268                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsibyte_parent_data),
1269                 .ops = &clk_byte2_ops,
1270                 .flags = CLK_SET_RATE_PARENT,
1271         },
1272 };
1273
1274 static const struct freq_tbl ftbl_gcc_mdss_esc_clk[] = {
1275         F(19200000, P_XO, 1, 0, 0),
1276         { }
1277 };
1278
1279 static struct clk_rcg2 esc0_clk_src = {
1280         .cmd_rcgr = 0x4d060,
1281         .hid_width = 5,
1282         .parent_map = gcc_xo_dsibyte_map,
1283         .freq_tbl = ftbl_gcc_mdss_esc_clk,
1284         .clkr.hw.init = &(struct clk_init_data){
1285                 .name = "esc0_clk_src",
1286                 .parent_data = gcc_xo_dsibyte_parent_data,
1287                 .num_parents = ARRAY_SIZE(gcc_xo_dsibyte_parent_data),
1288                 .ops = &clk_rcg2_ops,
1289         },
1290 };
1291
1292 static struct clk_rcg2 esc1_clk_src = {
1293         .cmd_rcgr = 0x4d0a8,
1294         .hid_width = 5,
1295         .parent_map = gcc_xo_dsibyte_map,
1296         .freq_tbl = ftbl_gcc_mdss_esc_clk,
1297         .clkr.hw.init = &(struct clk_init_data){
1298                 .name = "esc1_clk_src",
1299                 .parent_data = gcc_xo_dsibyte_parent_data,
1300                 .num_parents = ARRAY_SIZE(gcc_xo_dsibyte_parent_data),
1301                 .ops = &clk_rcg2_ops,
1302         },
1303 };
1304
1305 static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
1306         F(50000000, P_GPLL0_AUX, 16, 0, 0),
1307         F(80000000, P_GPLL0_AUX, 10, 0, 0),
1308         F(100000000, P_GPLL0_AUX, 8, 0, 0),
1309         F(145500000, P_GPLL0_AUX, 5.5, 0, 0),
1310         F(153600000, P_GPLL0, 4, 0, 0),
1311         F(160000000, P_GPLL0_AUX, 5, 0, 0),
1312         F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
1313         F(200000000, P_GPLL0_AUX, 4, 0, 0),
1314         F(266670000, P_GPLL0_AUX, 3, 0, 0),
1315         F(307200000, P_GPLL1, 2, 0, 0),
1316         F(366670000, P_GPLL3_AUX, 3, 0, 0),
1317         { }
1318 };
1319
1320 static struct clk_rcg2 mdp_clk_src = {
1321         .cmd_rcgr = 0x4d014,
1322         .hid_width = 5,
1323         .parent_map = gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_map,
1324         .freq_tbl = ftbl_gcc_mdss_mdp_clk,
1325         .clkr.hw.init = &(struct clk_init_data){
1326                 .name = "mdp_clk_src",
1327                 .parent_data = gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data,
1328                 .num_parents = ARRAY_SIZE(gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data),
1329                 .ops = &clk_rcg2_ops,
1330         },
1331 };
1332
1333 static struct clk_rcg2 pclk0_clk_src = {
1334         .cmd_rcgr = 0x4d000,
1335         .mnd_width = 8,
1336         .hid_width = 5,
1337         .parent_map = gcc_xo_gpll0a_dsiphy_map,
1338         .clkr.hw.init = &(struct clk_init_data){
1339                 .name = "pclk0_clk_src",
1340                 .parent_data = gcc_xo_gpll0a_dsiphy_parent_data,
1341                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsiphy_parent_data),
1342                 .ops = &clk_pixel_ops,
1343                 .flags = CLK_SET_RATE_PARENT,
1344         },
1345 };
1346
1347 static struct clk_rcg2 pclk1_clk_src = {
1348         .cmd_rcgr = 0x4d0b8,
1349         .mnd_width = 8,
1350         .hid_width = 5,
1351         .parent_map = gcc_xo_gpll0a_dsiphy_map,
1352         .clkr.hw.init = &(struct clk_init_data){
1353                 .name = "pclk1_clk_src",
1354                 .parent_data = gcc_xo_gpll0a_dsiphy_parent_data,
1355                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsiphy_parent_data),
1356                 .ops = &clk_pixel_ops,
1357                 .flags = CLK_SET_RATE_PARENT,
1358         },
1359 };
1360
1361 static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
1362         F(19200000, P_XO, 1, 0, 0),
1363         { }
1364 };
1365
1366 static struct clk_rcg2 vsync_clk_src = {
1367         .cmd_rcgr = 0x4d02c,
1368         .hid_width = 5,
1369         .parent_map = gcc_xo_gpll0a_map,
1370         .freq_tbl = ftbl_gcc_mdss_vsync_clk,
1371         .clkr.hw.init = &(struct clk_init_data){
1372                 .name = "vsync_clk_src",
1373                 .parent_data = gcc_xo_gpll0a_parent_data,
1374                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_parent_data),
1375                 .ops = &clk_rcg2_ops,
1376         },
1377 };
1378
1379 static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
1380         F(64000000, P_GPLL0, 12.5, 0, 0),
1381         { }
1382 };
1383
1384 /* This is not in the documentation but is in the downstream driver */
1385 static struct clk_rcg2 pdm2_clk_src = {
1386         .cmd_rcgr = 0x44010,
1387         .hid_width = 5,
1388         .parent_map = gcc_xo_gpll0_map,
1389         .freq_tbl = ftbl_gcc_pdm2_clk,
1390         .clkr.hw.init = &(struct clk_init_data){
1391                 .name = "pdm2_clk_src",
1392                 .parent_data = gcc_xo_gpll0_parent_data,
1393                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
1394                 .ops = &clk_rcg2_ops,
1395         },
1396 };
1397
1398 static const struct freq_tbl ftbl_gcc_sdcc_apps_clk[] = {
1399         F(144000, P_XO, 16, 3, 25),
1400         F(400000, P_XO, 12, 1, 4),
1401         F(20000000, P_GPLL0, 10, 1, 4),
1402         F(25000000, P_GPLL0, 16, 1, 2),
1403         F(50000000, P_GPLL0, 16, 0, 0),
1404         F(100000000, P_GPLL0, 8, 0, 0),
1405         F(177770000, P_GPLL0, 4.5, 0, 0),
1406         F(200000000, P_GPLL0, 4, 0, 0),
1407         { }
1408 };
1409
1410 static struct clk_rcg2 sdcc1_apps_clk_src = {
1411         .cmd_rcgr = 0x42004,
1412         .mnd_width = 8,
1413         .hid_width = 5,
1414         .parent_map = gcc_xo_gpll0_map,
1415         .freq_tbl = ftbl_gcc_sdcc_apps_clk,
1416         .clkr.hw.init = &(struct clk_init_data){
1417                 .name = "sdcc1_apps_clk_src",
1418                 .parent_data = gcc_xo_gpll0_parent_data,
1419                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
1420                 .ops = &clk_rcg2_floor_ops,
1421         },
1422 };
1423
1424 static struct clk_rcg2 sdcc2_apps_clk_src = {
1425         .cmd_rcgr = 0x43004,
1426         .mnd_width = 8,
1427         .hid_width = 5,
1428         .parent_map = gcc_xo_gpll0_map,
1429         .freq_tbl = ftbl_gcc_sdcc_apps_clk,
1430         .clkr.hw.init = &(struct clk_init_data){
1431                 .name = "sdcc2_apps_clk_src",
1432                 .parent_data = gcc_xo_gpll0_parent_data,
1433                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
1434                 .ops = &clk_rcg2_floor_ops,
1435         },
1436 };
1437
1438 static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = {
1439         F(154285000, P_GPLL6, 7, 0, 0),
1440         F(320000000, P_GPLL0, 2.5, 0, 0),
1441         F(400000000, P_GPLL0, 2, 0, 0),
1442         { }
1443 };
1444
1445 static struct clk_rcg2 apss_tcu_clk_src = {
1446         .cmd_rcgr = 0x1207c,
1447         .hid_width = 5,
1448         .parent_map = gcc_xo_gpll0_gpll5a_gpll6_bimc_map,
1449         .freq_tbl = ftbl_gcc_apss_tcu_clk,
1450         .clkr.hw.init = &(struct clk_init_data){
1451                 .name = "apss_tcu_clk_src",
1452                 .parent_data = gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data,
1453                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data),
1454                 .ops = &clk_rcg2_ops,
1455         },
1456 };
1457
1458 static const struct freq_tbl ftbl_gcc_bimc_gpu_clk[] = {
1459         F(19200000, P_XO, 1, 0, 0),
1460         F(100000000, P_GPLL0, 8, 0, 0),
1461         F(200000000, P_GPLL0, 4, 0, 0),
1462         F(266500000, P_BIMC, 4, 0, 0),
1463         F(400000000, P_GPLL0, 2, 0, 0),
1464         F(533000000, P_BIMC, 2, 0, 0),
1465         { }
1466 };
1467
1468 static struct clk_rcg2 bimc_gpu_clk_src = {
1469         .cmd_rcgr = 0x31028,
1470         .hid_width = 5,
1471         .parent_map = gcc_xo_gpll0_gpll5a_gpll6_bimc_map,
1472         .freq_tbl = ftbl_gcc_bimc_gpu_clk,
1473         .clkr.hw.init = &(struct clk_init_data){
1474                 .name = "bimc_gpu_clk_src",
1475                 .parent_data = gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data,
1476                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data),
1477                 .flags = CLK_GET_RATE_NOCACHE,
1478                 .ops = &clk_rcg2_ops,
1479         },
1480 };
1481
1482 static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
1483         F(57140000, P_GPLL0, 14, 0, 0),
1484         F(80000000, P_GPLL0, 10, 0, 0),
1485         F(100000000, P_GPLL0, 8, 0, 0),
1486         { }
1487 };
1488
1489 static struct clk_rcg2 usb_hs_system_clk_src = {
1490         .cmd_rcgr = 0x41010,
1491         .hid_width = 5,
1492         .parent_map = gcc_xo_gpll0_map,
1493         .freq_tbl = ftbl_gcc_usb_hs_system_clk,
1494         .clkr.hw.init = &(struct clk_init_data){
1495                 .name = "usb_hs_system_clk_src",
1496                 .parent_data = gcc_xo_gpll0_parent_data,
1497                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
1498                 .ops = &clk_rcg2_ops,
1499         },
1500 };
1501
1502 static const struct freq_tbl ftbl_gcc_usb_fs_system_clk[] = {
1503         F(64000000, P_GPLL0, 12.5, 0, 0),
1504         { }
1505 };
1506
1507 static struct clk_rcg2 usb_fs_system_clk_src = {
1508         .cmd_rcgr = 0x3f010,
1509         .hid_width = 5,
1510         .parent_map = gcc_xo_gpll0_map,
1511         .freq_tbl = ftbl_gcc_usb_fs_system_clk,
1512         .clkr.hw.init = &(struct clk_init_data){
1513                 .name = "usb_fs_system_clk_src",
1514                 .parent_data = gcc_xo_gpll6_gpll0_parent_data,
1515                 .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0_parent_data),
1516                 .ops = &clk_rcg2_ops,
1517         },
1518 };
1519
1520 static const struct freq_tbl ftbl_gcc_usb_fs_ic_clk[] = {
1521         F(60000000, P_GPLL6, 1, 1, 18),
1522         { }
1523 };
1524
1525 static struct clk_rcg2 usb_fs_ic_clk_src = {
1526         .cmd_rcgr = 0x3f034,
1527         .hid_width = 5,
1528         .parent_map = gcc_xo_gpll0_map,
1529         .freq_tbl = ftbl_gcc_usb_fs_ic_clk,
1530         .clkr.hw.init = &(struct clk_init_data){
1531                 .name = "usb_fs_ic_clk_src",
1532                 .parent_data = gcc_xo_gpll6_gpll0a_parent_data,
1533                 .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0a_parent_data),
1534                 .ops = &clk_rcg2_ops,
1535         },
1536 };
1537
1538 static const struct freq_tbl ftbl_gcc_ultaudio_ahb_clk[] = {
1539         F(3200000, P_XO, 6, 0, 0),
1540         F(6400000, P_XO, 3, 0, 0),
1541         F(9600000, P_XO, 2, 0, 0),
1542         F(19200000, P_XO, 1, 0, 0),
1543         F(40000000, P_GPLL0, 10, 1, 2),
1544         F(66670000, P_GPLL0, 12, 0, 0),
1545         F(80000000, P_GPLL0, 10, 0, 0),
1546         F(100000000, P_GPLL0, 8, 0, 0),
1547         { }
1548 };
1549
1550 static struct clk_rcg2 ultaudio_ahbfabric_clk_src = {
1551         .cmd_rcgr = 0x1c010,
1552         .hid_width = 5,
1553         .mnd_width = 8,
1554         .parent_map = gcc_xo_gpll0_gpll1_sleep_map,
1555         .freq_tbl = ftbl_gcc_ultaudio_ahb_clk,
1556         .clkr.hw.init = &(struct clk_init_data){
1557                 .name = "ultaudio_ahbfabric_clk_src",
1558                 .parent_data = gcc_xo_gpll0_gpll1_sleep_parent_data,
1559                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep_parent_data),
1560                 .ops = &clk_rcg2_ops,
1561         },
1562 };
1563
1564 static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_clk = {
1565         .halt_reg = 0x1c028,
1566         .clkr = {
1567                 .enable_reg = 0x1c028,
1568                 .enable_mask = BIT(0),
1569                 .hw.init = &(struct clk_init_data){
1570                         .name = "gcc_ultaudio_ahbfabric_ixfabric_clk",
1571                         .parent_hws = (const struct clk_hw*[]){
1572                                 &ultaudio_ahbfabric_clk_src.clkr.hw,
1573                         },
1574                         .num_parents = 1,
1575                         .flags = CLK_SET_RATE_PARENT,
1576                         .ops = &clk_branch2_ops,
1577                 },
1578         },
1579 };
1580
1581 static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk = {
1582         .halt_reg = 0x1c024,
1583         .clkr = {
1584                 .enable_reg = 0x1c024,
1585                 .enable_mask = BIT(0),
1586                 .hw.init = &(struct clk_init_data){
1587                         .name = "gcc_ultaudio_ahbfabric_ixfabric_lpm_clk",
1588                         .parent_hws = (const struct clk_hw*[]){
1589                                 &ultaudio_ahbfabric_clk_src.clkr.hw,
1590                         },
1591                         .num_parents = 1,
1592                         .flags = CLK_SET_RATE_PARENT,
1593                         .ops = &clk_branch2_ops,
1594                 },
1595         },
1596 };
1597
1598 static const struct freq_tbl ftbl_gcc_ultaudio_lpaif_i2s_clk[] = {
1599         F(128000, P_XO, 10, 1, 15),
1600         F(256000, P_XO, 5, 1, 15),
1601         F(384000, P_XO, 5, 1, 10),
1602         F(512000, P_XO, 5, 2, 15),
1603         F(576000, P_XO, 5, 3, 20),
1604         F(705600, P_GPLL1, 16, 1, 80),
1605         F(768000, P_XO, 5, 1, 5),
1606         F(800000, P_XO, 5, 5, 24),
1607         F(1024000, P_XO, 5, 4, 15),
1608         F(1152000, P_XO, 1, 3, 50),
1609         F(1411200, P_GPLL1, 16, 1, 40),
1610         F(1536000, P_XO, 1, 2, 25),
1611         F(1600000, P_XO, 12, 0, 0),
1612         F(1728000, P_XO, 5, 9, 20),
1613         F(2048000, P_XO, 5, 8, 15),
1614         F(2304000, P_XO, 5, 3, 5),
1615         F(2400000, P_XO, 8, 0, 0),
1616         F(2822400, P_GPLL1, 16, 1, 20),
1617         F(3072000, P_XO, 5, 4, 5),
1618         F(4096000, P_GPLL1, 9, 2, 49),
1619         F(4800000, P_XO, 4, 0, 0),
1620         F(5644800, P_GPLL1, 16, 1, 10),
1621         F(6144000, P_GPLL1, 7, 1, 21),
1622         F(8192000, P_GPLL1, 9, 4, 49),
1623         F(9600000, P_XO, 2, 0, 0),
1624         F(11289600, P_GPLL1, 16, 1, 5),
1625         F(12288000, P_GPLL1, 7, 2, 21),
1626         { }
1627 };
1628
1629 static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = {
1630         .cmd_rcgr = 0x1c054,
1631         .hid_width = 5,
1632         .mnd_width = 8,
1633         .parent_map = gcc_xo_gpll1_epi2s_emclk_sleep_map,
1634         .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1635         .clkr.hw.init = &(struct clk_init_data){
1636                 .name = "ultaudio_lpaif_pri_i2s_clk_src",
1637                 .parent_data = gcc_xo_gpll1_epi2s_emclk_sleep_parent_data,
1638                 .num_parents = ARRAY_SIZE(gcc_xo_gpll1_epi2s_emclk_sleep_parent_data),
1639                 .ops = &clk_rcg2_ops,
1640         },
1641 };
1642
1643 static struct clk_branch gcc_ultaudio_lpaif_pri_i2s_clk = {
1644         .halt_reg = 0x1c068,
1645         .clkr = {
1646                 .enable_reg = 0x1c068,
1647                 .enable_mask = BIT(0),
1648                 .hw.init = &(struct clk_init_data){
1649                         .name = "gcc_ultaudio_lpaif_pri_i2s_clk",
1650                         .parent_hws = (const struct clk_hw*[]){
1651                                 &ultaudio_lpaif_pri_i2s_clk_src.clkr.hw,
1652                         },
1653                         .num_parents = 1,
1654                         .flags = CLK_SET_RATE_PARENT,
1655                         .ops = &clk_branch2_ops,
1656                 },
1657         },
1658 };
1659
1660 static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = {
1661         .cmd_rcgr = 0x1c06c,
1662         .hid_width = 5,
1663         .mnd_width = 8,
1664         .parent_map = gcc_xo_gpll1_esi2s_emclk_sleep_map,
1665         .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1666         .clkr.hw.init = &(struct clk_init_data){
1667                 .name = "ultaudio_lpaif_sec_i2s_clk_src",
1668                 .parent_data = gcc_xo_gpll1_esi2s_emclk_sleep_parent_data,
1669                 .num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep_parent_data),
1670                 .ops = &clk_rcg2_ops,
1671         },
1672 };
1673
1674 static struct clk_branch gcc_ultaudio_lpaif_sec_i2s_clk = {
1675         .halt_reg = 0x1c080,
1676         .clkr = {
1677                 .enable_reg = 0x1c080,
1678                 .enable_mask = BIT(0),
1679                 .hw.init = &(struct clk_init_data){
1680                         .name = "gcc_ultaudio_lpaif_sec_i2s_clk",
1681                         .parent_hws = (const struct clk_hw*[]){
1682                                 &ultaudio_lpaif_sec_i2s_clk_src.clkr.hw,
1683                         },
1684                         .num_parents = 1,
1685                         .flags = CLK_SET_RATE_PARENT,
1686                         .ops = &clk_branch2_ops,
1687                 },
1688         },
1689 };
1690
1691 static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = {
1692         .cmd_rcgr = 0x1c084,
1693         .hid_width = 5,
1694         .mnd_width = 8,
1695         .parent_map = gcc_xo_gpll1_emclk_sleep_map,
1696         .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1697         .clkr.hw.init = &(struct clk_init_data){
1698                 .name = "ultaudio_lpaif_aux_i2s_clk_src",
1699                 .parent_data = gcc_xo_gpll1_esi2s_emclk_sleep_parent_data,
1700                 .num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep_parent_data),
1701                 .ops = &clk_rcg2_ops,
1702         },
1703 };
1704
1705 static struct clk_branch gcc_ultaudio_lpaif_aux_i2s_clk = {
1706         .halt_reg = 0x1c098,
1707         .clkr = {
1708                 .enable_reg = 0x1c098,
1709                 .enable_mask = BIT(0),
1710                 .hw.init = &(struct clk_init_data){
1711                         .name = "gcc_ultaudio_lpaif_aux_i2s_clk",
1712                         .parent_hws = (const struct clk_hw*[]){
1713                                 &ultaudio_lpaif_aux_i2s_clk_src.clkr.hw,
1714                         },
1715                         .num_parents = 1,
1716                         .flags = CLK_SET_RATE_PARENT,
1717                         .ops = &clk_branch2_ops,
1718                 },
1719         },
1720 };
1721
1722 static const struct freq_tbl ftbl_gcc_ultaudio_xo_clk[] = {
1723         F(19200000, P_XO, 1, 0, 0),
1724         { }
1725 };
1726
1727 static struct clk_rcg2 ultaudio_xo_clk_src = {
1728         .cmd_rcgr = 0x1c034,
1729         .hid_width = 5,
1730         .parent_map = gcc_xo_sleep_map,
1731         .freq_tbl = ftbl_gcc_ultaudio_xo_clk,
1732         .clkr.hw.init = &(struct clk_init_data){
1733                 .name = "ultaudio_xo_clk_src",
1734                 .parent_data = gcc_xo_sleep_parent_data,
1735                 .num_parents = ARRAY_SIZE(gcc_xo_sleep_parent_data),
1736                 .ops = &clk_rcg2_ops,
1737         },
1738 };
1739
1740 static struct clk_branch gcc_ultaudio_avsync_xo_clk = {
1741         .halt_reg = 0x1c04c,
1742         .clkr = {
1743                 .enable_reg = 0x1c04c,
1744                 .enable_mask = BIT(0),
1745                 .hw.init = &(struct clk_init_data){
1746                         .name = "gcc_ultaudio_avsync_xo_clk",
1747                         .parent_hws = (const struct clk_hw*[]){
1748                                 &ultaudio_xo_clk_src.clkr.hw,
1749                         },
1750                         .num_parents = 1,
1751                         .flags = CLK_SET_RATE_PARENT,
1752                         .ops = &clk_branch2_ops,
1753                 },
1754         },
1755 };
1756
1757 static struct clk_branch gcc_ultaudio_stc_xo_clk = {
1758         .halt_reg = 0x1c050,
1759         .clkr = {
1760                 .enable_reg = 0x1c050,
1761                 .enable_mask = BIT(0),
1762                 .hw.init = &(struct clk_init_data){
1763                         .name = "gcc_ultaudio_stc_xo_clk",
1764                         .parent_hws = (const struct clk_hw*[]){
1765                                 &ultaudio_xo_clk_src.clkr.hw,
1766                         },
1767                         .num_parents = 1,
1768                         .flags = CLK_SET_RATE_PARENT,
1769                         .ops = &clk_branch2_ops,
1770                 },
1771         },
1772 };
1773
1774 static const struct freq_tbl ftbl_codec_clk[] = {
1775         F(9600000, P_XO, 2, 0, 0),
1776         F(12288000, P_XO, 1, 16, 25),
1777         F(19200000, P_XO, 1, 0, 0),
1778         F(11289600, P_EXT_MCLK, 1, 0, 0),
1779         { }
1780 };
1781
1782 static struct clk_rcg2 codec_digcodec_clk_src = {
1783         .cmd_rcgr = 0x1c09c,
1784         .mnd_width = 8,
1785         .hid_width = 5,
1786         .parent_map = gcc_xo_gpll1_emclk_sleep_map,
1787         .freq_tbl = ftbl_codec_clk,
1788         .clkr.hw.init = &(struct clk_init_data){
1789                 .name = "codec_digcodec_clk_src",
1790                 .parent_data = gcc_xo_gpll1_emclk_sleep_parent_data,
1791                 .num_parents = ARRAY_SIZE(gcc_xo_gpll1_emclk_sleep_parent_data),
1792                 .ops = &clk_rcg2_ops,
1793         },
1794 };
1795
1796 static struct clk_branch gcc_codec_digcodec_clk = {
1797         .halt_reg = 0x1c0b0,
1798         .clkr = {
1799                 .enable_reg = 0x1c0b0,
1800                 .enable_mask = BIT(0),
1801                 .hw.init = &(struct clk_init_data){
1802                         .name = "gcc_ultaudio_codec_digcodec_clk",
1803                         .parent_hws = (const struct clk_hw*[]){
1804                                 &codec_digcodec_clk_src.clkr.hw,
1805                         },
1806                         .num_parents = 1,
1807                         .flags = CLK_SET_RATE_PARENT,
1808                         .ops = &clk_branch2_ops,
1809                 },
1810         },
1811 };
1812
1813 static struct clk_branch gcc_ultaudio_pcnoc_mport_clk = {
1814         .halt_reg = 0x1c000,
1815         .clkr = {
1816                 .enable_reg = 0x1c000,
1817                 .enable_mask = BIT(0),
1818                 .hw.init = &(struct clk_init_data){
1819                         .name = "gcc_ultaudio_pcnoc_mport_clk",
1820                         .parent_hws = (const struct clk_hw*[]){
1821                                 &pcnoc_bfdcd_clk_src.clkr.hw,
1822                         },
1823                         .num_parents = 1,
1824                         .ops = &clk_branch2_ops,
1825                 },
1826         },
1827 };
1828
1829 static struct clk_branch gcc_ultaudio_pcnoc_sway_clk = {
1830         .halt_reg = 0x1c004,
1831         .clkr = {
1832                 .enable_reg = 0x1c004,
1833                 .enable_mask = BIT(0),
1834                 .hw.init = &(struct clk_init_data){
1835                         .name = "gcc_ultaudio_pcnoc_sway_clk",
1836                         .parent_hws = (const struct clk_hw*[]){
1837                                 &pcnoc_bfdcd_clk_src.clkr.hw,
1838                         },
1839                         .num_parents = 1,
1840                         .ops = &clk_branch2_ops,
1841                 },
1842         },
1843 };
1844
1845 static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = {
1846         F(133330000, P_GPLL0, 6, 0, 0),
1847         F(200000000, P_GPLL0, 4, 0, 0),
1848         F(266670000, P_GPLL0, 3, 0, 0),
1849         { }
1850 };
1851
1852 static struct clk_rcg2 vcodec0_clk_src = {
1853         .cmd_rcgr = 0x4C000,
1854         .mnd_width = 8,
1855         .hid_width = 5,
1856         .parent_map = gcc_xo_gpll0_map,
1857         .freq_tbl = ftbl_gcc_venus0_vcodec0_clk,
1858         .clkr.hw.init = &(struct clk_init_data){
1859                 .name = "vcodec0_clk_src",
1860                 .parent_data = gcc_xo_gpll0_parent_data,
1861                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
1862                 .ops = &clk_rcg2_ops,
1863         },
1864 };
1865
1866 static struct clk_branch gcc_blsp1_ahb_clk = {
1867         .halt_reg = 0x01008,
1868         .halt_check = BRANCH_HALT_VOTED,
1869         .clkr = {
1870                 .enable_reg = 0x45004,
1871                 .enable_mask = BIT(10),
1872                 .hw.init = &(struct clk_init_data){
1873                         .name = "gcc_blsp1_ahb_clk",
1874                         .parent_hws = (const struct clk_hw*[]){
1875                                 &pcnoc_bfdcd_clk_src.clkr.hw,
1876                         },
1877                         .num_parents = 1,
1878                         .ops = &clk_branch2_ops,
1879                 },
1880         },
1881 };
1882
1883 static struct clk_branch gcc_blsp1_sleep_clk = {
1884         .halt_reg = 0x01004,
1885         .clkr = {
1886                 .enable_reg = 0x01004,
1887                 .enable_mask = BIT(0),
1888                 .hw.init = &(struct clk_init_data){
1889                         .name = "gcc_blsp1_sleep_clk",
1890                         .ops = &clk_branch2_ops,
1891                 },
1892         },
1893 };
1894
1895 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1896         .halt_reg = 0x02008,
1897         .clkr = {
1898                 .enable_reg = 0x02008,
1899                 .enable_mask = BIT(0),
1900                 .hw.init = &(struct clk_init_data){
1901                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
1902                         .parent_hws = (const struct clk_hw*[]){
1903                                 &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
1904                         },
1905                         .num_parents = 1,
1906                         .flags = CLK_SET_RATE_PARENT,
1907                         .ops = &clk_branch2_ops,
1908                 },
1909         },
1910 };
1911
1912 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1913         .halt_reg = 0x02004,
1914         .clkr = {
1915                 .enable_reg = 0x02004,
1916                 .enable_mask = BIT(0),
1917                 .hw.init = &(struct clk_init_data){
1918                         .name = "gcc_blsp1_qup1_spi_apps_clk",
1919                         .parent_hws = (const struct clk_hw*[]){
1920                                 &blsp1_qup1_spi_apps_clk_src.clkr.hw,
1921                         },
1922                         .num_parents = 1,
1923                         .flags = CLK_SET_RATE_PARENT,
1924                         .ops = &clk_branch2_ops,
1925                 },
1926         },
1927 };
1928
1929 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1930         .halt_reg = 0x03010,
1931         .clkr = {
1932                 .enable_reg = 0x03010,
1933                 .enable_mask = BIT(0),
1934                 .hw.init = &(struct clk_init_data){
1935                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
1936                         .parent_hws = (const struct clk_hw*[]){
1937                                 &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
1938                         },
1939                         .num_parents = 1,
1940                         .flags = CLK_SET_RATE_PARENT,
1941                         .ops = &clk_branch2_ops,
1942                 },
1943         },
1944 };
1945
1946 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1947         .halt_reg = 0x0300c,
1948         .clkr = {
1949                 .enable_reg = 0x0300c,
1950                 .enable_mask = BIT(0),
1951                 .hw.init = &(struct clk_init_data){
1952                         .name = "gcc_blsp1_qup2_spi_apps_clk",
1953                         .parent_hws = (const struct clk_hw*[]){
1954                                 &blsp1_qup2_spi_apps_clk_src.clkr.hw,
1955                         },
1956                         .num_parents = 1,
1957                         .flags = CLK_SET_RATE_PARENT,
1958                         .ops = &clk_branch2_ops,
1959                 },
1960         },
1961 };
1962
1963 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1964         .halt_reg = 0x04020,
1965         .clkr = {
1966                 .enable_reg = 0x04020,
1967                 .enable_mask = BIT(0),
1968                 .hw.init = &(struct clk_init_data){
1969                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
1970                         .parent_hws = (const struct clk_hw*[]){
1971                                 &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
1972                         },
1973                         .num_parents = 1,
1974                         .flags = CLK_SET_RATE_PARENT,
1975                         .ops = &clk_branch2_ops,
1976                 },
1977         },
1978 };
1979
1980 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1981         .halt_reg = 0x0401c,
1982         .clkr = {
1983                 .enable_reg = 0x0401c,
1984                 .enable_mask = BIT(0),
1985                 .hw.init = &(struct clk_init_data){
1986                         .name = "gcc_blsp1_qup3_spi_apps_clk",
1987                         .parent_hws = (const struct clk_hw*[]){
1988                                 &blsp1_qup3_spi_apps_clk_src.clkr.hw,
1989                         },
1990                         .num_parents = 1,
1991                         .flags = CLK_SET_RATE_PARENT,
1992                         .ops = &clk_branch2_ops,
1993                 },
1994         },
1995 };
1996
1997 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1998         .halt_reg = 0x05020,
1999         .clkr = {
2000                 .enable_reg = 0x05020,
2001                 .enable_mask = BIT(0),
2002                 .hw.init = &(struct clk_init_data){
2003                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
2004                         .parent_hws = (const struct clk_hw*[]){
2005                                 &blsp1_qup4_i2c_apps_clk_src.clkr.hw,
2006                         },
2007                         .num_parents = 1,
2008                         .flags = CLK_SET_RATE_PARENT,
2009                         .ops = &clk_branch2_ops,
2010                 },
2011         },
2012 };
2013
2014 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
2015         .halt_reg = 0x0501c,
2016         .clkr = {
2017                 .enable_reg = 0x0501c,
2018                 .enable_mask = BIT(0),
2019                 .hw.init = &(struct clk_init_data){
2020                         .name = "gcc_blsp1_qup4_spi_apps_clk",
2021                         .parent_hws = (const struct clk_hw*[]){
2022                                 &blsp1_qup4_spi_apps_clk_src.clkr.hw,
2023                         },
2024                         .num_parents = 1,
2025                         .flags = CLK_SET_RATE_PARENT,
2026                         .ops = &clk_branch2_ops,
2027                 },
2028         },
2029 };
2030
2031 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
2032         .halt_reg = 0x06020,
2033         .clkr = {
2034                 .enable_reg = 0x06020,
2035                 .enable_mask = BIT(0),
2036                 .hw.init = &(struct clk_init_data){
2037                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
2038                         .parent_hws = (const struct clk_hw*[]){
2039                                 &blsp1_qup5_i2c_apps_clk_src.clkr.hw,
2040                         },
2041                         .num_parents = 1,
2042                         .flags = CLK_SET_RATE_PARENT,
2043                         .ops = &clk_branch2_ops,
2044                 },
2045         },
2046 };
2047
2048 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
2049         .halt_reg = 0x0601c,
2050         .clkr = {
2051                 .enable_reg = 0x0601c,
2052                 .enable_mask = BIT(0),
2053                 .hw.init = &(struct clk_init_data){
2054                         .name = "gcc_blsp1_qup5_spi_apps_clk",
2055                         .parent_hws = (const struct clk_hw*[]){
2056                                 &blsp1_qup5_spi_apps_clk_src.clkr.hw,
2057                         },
2058                         .num_parents = 1,
2059                         .flags = CLK_SET_RATE_PARENT,
2060                         .ops = &clk_branch2_ops,
2061                 },
2062         },
2063 };
2064
2065 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
2066         .halt_reg = 0x07020,
2067         .clkr = {
2068                 .enable_reg = 0x07020,
2069                 .enable_mask = BIT(0),
2070                 .hw.init = &(struct clk_init_data){
2071                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
2072                         .parent_hws = (const struct clk_hw*[]){
2073                                 &blsp1_qup6_i2c_apps_clk_src.clkr.hw,
2074                         },
2075                         .num_parents = 1,
2076                         .flags = CLK_SET_RATE_PARENT,
2077                         .ops = &clk_branch2_ops,
2078                 },
2079         },
2080 };
2081
2082 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
2083         .halt_reg = 0x0701c,
2084         .clkr = {
2085                 .enable_reg = 0x0701c,
2086                 .enable_mask = BIT(0),
2087                 .hw.init = &(struct clk_init_data){
2088                         .name = "gcc_blsp1_qup6_spi_apps_clk",
2089                         .parent_hws = (const struct clk_hw*[]){
2090                                 &blsp1_qup6_spi_apps_clk_src.clkr.hw,
2091                         },
2092                         .num_parents = 1,
2093                         .flags = CLK_SET_RATE_PARENT,
2094                         .ops = &clk_branch2_ops,
2095                 },
2096         },
2097 };
2098
2099 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
2100         .halt_reg = 0x0203c,
2101         .clkr = {
2102                 .enable_reg = 0x0203c,
2103                 .enable_mask = BIT(0),
2104                 .hw.init = &(struct clk_init_data){
2105                         .name = "gcc_blsp1_uart1_apps_clk",
2106                         .parent_hws = (const struct clk_hw*[]){
2107                                 &blsp1_uart1_apps_clk_src.clkr.hw,
2108                         },
2109                         .num_parents = 1,
2110                         .flags = CLK_SET_RATE_PARENT,
2111                         .ops = &clk_branch2_ops,
2112                 },
2113         },
2114 };
2115
2116 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
2117         .halt_reg = 0x0302c,
2118         .clkr = {
2119                 .enable_reg = 0x0302c,
2120                 .enable_mask = BIT(0),
2121                 .hw.init = &(struct clk_init_data){
2122                         .name = "gcc_blsp1_uart2_apps_clk",
2123                         .parent_hws = (const struct clk_hw*[]){
2124                                 &blsp1_uart2_apps_clk_src.clkr.hw,
2125                         },
2126                         .num_parents = 1,
2127                         .flags = CLK_SET_RATE_PARENT,
2128                         .ops = &clk_branch2_ops,
2129                 },
2130         },
2131 };
2132
2133 static struct clk_branch gcc_boot_rom_ahb_clk = {
2134         .halt_reg = 0x1300c,
2135         .halt_check = BRANCH_HALT_VOTED,
2136         .clkr = {
2137                 .enable_reg = 0x45004,
2138                 .enable_mask = BIT(7),
2139                 .hw.init = &(struct clk_init_data){
2140                         .name = "gcc_boot_rom_ahb_clk",
2141                         .parent_hws = (const struct clk_hw*[]){
2142                                 &pcnoc_bfdcd_clk_src.clkr.hw,
2143                         },
2144                         .num_parents = 1,
2145                         .ops = &clk_branch2_ops,
2146                 },
2147         },
2148 };
2149
2150 static struct clk_branch gcc_camss_cci_ahb_clk = {
2151         .halt_reg = 0x5101c,
2152         .clkr = {
2153                 .enable_reg = 0x5101c,
2154                 .enable_mask = BIT(0),
2155                 .hw.init = &(struct clk_init_data){
2156                         .name = "gcc_camss_cci_ahb_clk",
2157                         .parent_hws = (const struct clk_hw*[]){
2158                                 &camss_ahb_clk_src.clkr.hw,
2159                         },
2160                         .num_parents = 1,
2161                         .flags = CLK_SET_RATE_PARENT,
2162                         .ops = &clk_branch2_ops,
2163                 },
2164         },
2165 };
2166
2167 static struct clk_branch gcc_camss_cci_clk = {
2168         .halt_reg = 0x51018,
2169         .clkr = {
2170                 .enable_reg = 0x51018,
2171                 .enable_mask = BIT(0),
2172                 .hw.init = &(struct clk_init_data){
2173                         .name = "gcc_camss_cci_clk",
2174                         .parent_hws = (const struct clk_hw*[]){
2175                                 &cci_clk_src.clkr.hw,
2176                         },
2177                         .num_parents = 1,
2178                         .flags = CLK_SET_RATE_PARENT,
2179                         .ops = &clk_branch2_ops,
2180                 },
2181         },
2182 };
2183
2184 static struct clk_branch gcc_camss_csi0_ahb_clk = {
2185         .halt_reg = 0x4e040,
2186         .clkr = {
2187                 .enable_reg = 0x4e040,
2188                 .enable_mask = BIT(0),
2189                 .hw.init = &(struct clk_init_data){
2190                         .name = "gcc_camss_csi0_ahb_clk",
2191                         .parent_hws = (const struct clk_hw*[]){
2192                                 &camss_ahb_clk_src.clkr.hw,
2193                         },
2194                         .num_parents = 1,
2195                         .flags = CLK_SET_RATE_PARENT,
2196                         .ops = &clk_branch2_ops,
2197                 },
2198         },
2199 };
2200
2201 static struct clk_branch gcc_camss_csi0_clk = {
2202         .halt_reg = 0x4e03c,
2203         .clkr = {
2204                 .enable_reg = 0x4e03c,
2205                 .enable_mask = BIT(0),
2206                 .hw.init = &(struct clk_init_data){
2207                         .name = "gcc_camss_csi0_clk",
2208                         .parent_hws = (const struct clk_hw*[]){
2209                                 &csi0_clk_src.clkr.hw,
2210                         },
2211                         .num_parents = 1,
2212                         .flags = CLK_SET_RATE_PARENT,
2213                         .ops = &clk_branch2_ops,
2214                 },
2215         },
2216 };
2217
2218 static struct clk_branch gcc_camss_csi0phy_clk = {
2219         .halt_reg = 0x4e048,
2220         .clkr = {
2221                 .enable_reg = 0x4e048,
2222                 .enable_mask = BIT(0),
2223                 .hw.init = &(struct clk_init_data){
2224                         .name = "gcc_camss_csi0phy_clk",
2225                         .parent_hws = (const struct clk_hw*[]){
2226                                 &csi0_clk_src.clkr.hw,
2227                         },
2228                         .num_parents = 1,
2229                         .flags = CLK_SET_RATE_PARENT,
2230                         .ops = &clk_branch2_ops,
2231                 },
2232         },
2233 };
2234
2235 static struct clk_branch gcc_camss_csi0pix_clk = {
2236         .halt_reg = 0x4e058,
2237         .clkr = {
2238                 .enable_reg = 0x4e058,
2239                 .enable_mask = BIT(0),
2240                 .hw.init = &(struct clk_init_data){
2241                         .name = "gcc_camss_csi0pix_clk",
2242                         .parent_hws = (const struct clk_hw*[]){
2243                                 &csi0_clk_src.clkr.hw,
2244                         },
2245                         .num_parents = 1,
2246                         .flags = CLK_SET_RATE_PARENT,
2247                         .ops = &clk_branch2_ops,
2248                 },
2249         },
2250 };
2251
2252 static struct clk_branch gcc_camss_csi0rdi_clk = {
2253         .halt_reg = 0x4e050,
2254         .clkr = {
2255                 .enable_reg = 0x4e050,
2256                 .enable_mask = BIT(0),
2257                 .hw.init = &(struct clk_init_data){
2258                         .name = "gcc_camss_csi0rdi_clk",
2259                         .parent_hws = (const struct clk_hw*[]){
2260                                 &csi0_clk_src.clkr.hw,
2261                         },
2262                         .num_parents = 1,
2263                         .flags = CLK_SET_RATE_PARENT,
2264                         .ops = &clk_branch2_ops,
2265                 },
2266         },
2267 };
2268
2269 static struct clk_branch gcc_camss_csi1_ahb_clk = {
2270         .halt_reg = 0x4f040,
2271         .clkr = {
2272                 .enable_reg = 0x4f040,
2273                 .enable_mask = BIT(0),
2274                 .hw.init = &(struct clk_init_data){
2275                         .name = "gcc_camss_csi1_ahb_clk",
2276                         .parent_hws = (const struct clk_hw*[]){
2277                                 &camss_ahb_clk_src.clkr.hw,
2278                         },
2279                         .num_parents = 1,
2280                         .flags = CLK_SET_RATE_PARENT,
2281                         .ops = &clk_branch2_ops,
2282                 },
2283         },
2284 };
2285
2286 static struct clk_branch gcc_camss_csi1_clk = {
2287         .halt_reg = 0x4f03c,
2288         .clkr = {
2289                 .enable_reg = 0x4f03c,
2290                 .enable_mask = BIT(0),
2291                 .hw.init = &(struct clk_init_data){
2292                         .name = "gcc_camss_csi1_clk",
2293                         .parent_hws = (const struct clk_hw*[]){
2294                                 &csi1_clk_src.clkr.hw,
2295                         },
2296                         .num_parents = 1,
2297                         .flags = CLK_SET_RATE_PARENT,
2298                         .ops = &clk_branch2_ops,
2299                 },
2300         },
2301 };
2302
2303 static struct clk_branch gcc_camss_csi1phy_clk = {
2304         .halt_reg = 0x4f048,
2305         .clkr = {
2306                 .enable_reg = 0x4f048,
2307                 .enable_mask = BIT(0),
2308                 .hw.init = &(struct clk_init_data){
2309                         .name = "gcc_camss_csi1phy_clk",
2310                         .parent_hws = (const struct clk_hw*[]){
2311                                 &csi1_clk_src.clkr.hw,
2312                         },
2313                         .num_parents = 1,
2314                         .flags = CLK_SET_RATE_PARENT,
2315                         .ops = &clk_branch2_ops,
2316                 },
2317         },
2318 };
2319
2320 static struct clk_branch gcc_camss_csi1pix_clk = {
2321         .halt_reg = 0x4f058,
2322         .clkr = {
2323                 .enable_reg = 0x4f058,
2324                 .enable_mask = BIT(0),
2325                 .hw.init = &(struct clk_init_data){
2326                         .name = "gcc_camss_csi1pix_clk",
2327                         .parent_hws = (const struct clk_hw*[]){
2328                                 &csi1_clk_src.clkr.hw,
2329                         },
2330                         .num_parents = 1,
2331                         .flags = CLK_SET_RATE_PARENT,
2332                         .ops = &clk_branch2_ops,
2333                 },
2334         },
2335 };
2336
2337 static struct clk_branch gcc_camss_csi1rdi_clk = {
2338         .halt_reg = 0x4f050,
2339         .clkr = {
2340                 .enable_reg = 0x4f050,
2341                 .enable_mask = BIT(0),
2342                 .hw.init = &(struct clk_init_data){
2343                         .name = "gcc_camss_csi1rdi_clk",
2344                         .parent_hws = (const struct clk_hw*[]){
2345                                 &csi1_clk_src.clkr.hw,
2346                         },
2347                         .num_parents = 1,
2348                         .flags = CLK_SET_RATE_PARENT,
2349                         .ops = &clk_branch2_ops,
2350                 },
2351         },
2352 };
2353
2354 static struct clk_branch gcc_camss_csi_vfe0_clk = {
2355         .halt_reg = 0x58050,
2356         .clkr = {
2357                 .enable_reg = 0x58050,
2358                 .enable_mask = BIT(0),
2359                 .hw.init = &(struct clk_init_data){
2360                         .name = "gcc_camss_csi_vfe0_clk",
2361                         .parent_hws = (const struct clk_hw*[]){
2362                                 &vfe0_clk_src.clkr.hw,
2363                         },
2364                         .num_parents = 1,
2365                         .flags = CLK_SET_RATE_PARENT,
2366                         .ops = &clk_branch2_ops,
2367                 },
2368         },
2369 };
2370
2371 static struct clk_branch gcc_camss_gp0_clk = {
2372         .halt_reg = 0x54018,
2373         .clkr = {
2374                 .enable_reg = 0x54018,
2375                 .enable_mask = BIT(0),
2376                 .hw.init = &(struct clk_init_data){
2377                         .name = "gcc_camss_gp0_clk",
2378                         .parent_hws = (const struct clk_hw*[]){
2379                                 &camss_gp0_clk_src.clkr.hw,
2380                         },
2381                         .num_parents = 1,
2382                         .flags = CLK_SET_RATE_PARENT,
2383                         .ops = &clk_branch2_ops,
2384                 },
2385         },
2386 };
2387
2388 static struct clk_branch gcc_camss_gp1_clk = {
2389         .halt_reg = 0x55018,
2390         .clkr = {
2391                 .enable_reg = 0x55018,
2392                 .enable_mask = BIT(0),
2393                 .hw.init = &(struct clk_init_data){
2394                         .name = "gcc_camss_gp1_clk",
2395                         .parent_hws = (const struct clk_hw*[]){
2396                                 &camss_gp1_clk_src.clkr.hw,
2397                         },
2398                         .num_parents = 1,
2399                         .flags = CLK_SET_RATE_PARENT,
2400                         .ops = &clk_branch2_ops,
2401                 },
2402         },
2403 };
2404
2405 static struct clk_branch gcc_camss_ispif_ahb_clk = {
2406         .halt_reg = 0x50004,
2407         .clkr = {
2408                 .enable_reg = 0x50004,
2409                 .enable_mask = BIT(0),
2410                 .hw.init = &(struct clk_init_data){
2411                         .name = "gcc_camss_ispif_ahb_clk",
2412                         .parent_hws = (const struct clk_hw*[]){
2413                                 &camss_ahb_clk_src.clkr.hw,
2414                         },
2415                         .num_parents = 1,
2416                         .flags = CLK_SET_RATE_PARENT,
2417                         .ops = &clk_branch2_ops,
2418                 },
2419         },
2420 };
2421
2422 static struct clk_branch gcc_camss_jpeg0_clk = {
2423         .halt_reg = 0x57020,
2424         .clkr = {
2425                 .enable_reg = 0x57020,
2426                 .enable_mask = BIT(0),
2427                 .hw.init = &(struct clk_init_data){
2428                         .name = "gcc_camss_jpeg0_clk",
2429                         .parent_hws = (const struct clk_hw*[]){
2430                                 &jpeg0_clk_src.clkr.hw,
2431                         },
2432                         .num_parents = 1,
2433                         .flags = CLK_SET_RATE_PARENT,
2434                         .ops = &clk_branch2_ops,
2435                 },
2436         },
2437 };
2438
2439 static struct clk_branch gcc_camss_jpeg_ahb_clk = {
2440         .halt_reg = 0x57024,
2441         .clkr = {
2442                 .enable_reg = 0x57024,
2443                 .enable_mask = BIT(0),
2444                 .hw.init = &(struct clk_init_data){
2445                         .name = "gcc_camss_jpeg_ahb_clk",
2446                         .parent_hws = (const struct clk_hw*[]){
2447                                 &camss_ahb_clk_src.clkr.hw,
2448                         },
2449                         .num_parents = 1,
2450                         .flags = CLK_SET_RATE_PARENT,
2451                         .ops = &clk_branch2_ops,
2452                 },
2453         },
2454 };
2455
2456 static struct clk_branch gcc_camss_jpeg_axi_clk = {
2457         .halt_reg = 0x57028,
2458         .clkr = {
2459                 .enable_reg = 0x57028,
2460                 .enable_mask = BIT(0),
2461                 .hw.init = &(struct clk_init_data){
2462                         .name = "gcc_camss_jpeg_axi_clk",
2463                         .parent_hws = (const struct clk_hw*[]){
2464                                 &system_mm_noc_bfdcd_clk_src.clkr.hw,
2465                         },
2466                         .num_parents = 1,
2467                         .flags = CLK_SET_RATE_PARENT,
2468                         .ops = &clk_branch2_ops,
2469                 },
2470         },
2471 };
2472
2473 static struct clk_branch gcc_camss_mclk0_clk = {
2474         .halt_reg = 0x52018,
2475         .clkr = {
2476                 .enable_reg = 0x52018,
2477                 .enable_mask = BIT(0),
2478                 .hw.init = &(struct clk_init_data){
2479                         .name = "gcc_camss_mclk0_clk",
2480                         .parent_hws = (const struct clk_hw*[]){
2481                                 &mclk0_clk_src.clkr.hw,
2482                         },
2483                         .num_parents = 1,
2484                         .flags = CLK_SET_RATE_PARENT,
2485                         .ops = &clk_branch2_ops,
2486                 },
2487         },
2488 };
2489
2490 static struct clk_branch gcc_camss_mclk1_clk = {
2491         .halt_reg = 0x53018,
2492         .clkr = {
2493                 .enable_reg = 0x53018,
2494                 .enable_mask = BIT(0),
2495                 .hw.init = &(struct clk_init_data){
2496                         .name = "gcc_camss_mclk1_clk",
2497                         .parent_hws = (const struct clk_hw*[]){
2498                                 &mclk1_clk_src.clkr.hw,
2499                         },
2500                         .num_parents = 1,
2501                         .flags = CLK_SET_RATE_PARENT,
2502                         .ops = &clk_branch2_ops,
2503                 },
2504         },
2505 };
2506
2507 static struct clk_branch gcc_camss_micro_ahb_clk = {
2508         .halt_reg = 0x5600c,
2509         .clkr = {
2510                 .enable_reg = 0x5600c,
2511                 .enable_mask = BIT(0),
2512                 .hw.init = &(struct clk_init_data){
2513                         .name = "gcc_camss_micro_ahb_clk",
2514                         .parent_hws = (const struct clk_hw*[]){
2515                                 &camss_ahb_clk_src.clkr.hw,
2516                         },
2517                         .num_parents = 1,
2518                         .flags = CLK_SET_RATE_PARENT,
2519                         .ops = &clk_branch2_ops,
2520                 },
2521         },
2522 };
2523
2524 static struct clk_branch gcc_camss_csi0phytimer_clk = {
2525         .halt_reg = 0x4e01c,
2526         .clkr = {
2527                 .enable_reg = 0x4e01c,
2528                 .enable_mask = BIT(0),
2529                 .hw.init = &(struct clk_init_data){
2530                         .name = "gcc_camss_csi0phytimer_clk",
2531                         .parent_hws = (const struct clk_hw*[]){
2532                                 &csi0phytimer_clk_src.clkr.hw,
2533                         },
2534                         .num_parents = 1,
2535                         .flags = CLK_SET_RATE_PARENT,
2536                         .ops = &clk_branch2_ops,
2537                 },
2538         },
2539 };
2540
2541 static struct clk_branch gcc_camss_csi1phytimer_clk = {
2542         .halt_reg = 0x4f01c,
2543         .clkr = {
2544                 .enable_reg = 0x4f01c,
2545                 .enable_mask = BIT(0),
2546                 .hw.init = &(struct clk_init_data){
2547                         .name = "gcc_camss_csi1phytimer_clk",
2548                         .parent_hws = (const struct clk_hw*[]){
2549                                 &csi1phytimer_clk_src.clkr.hw,
2550                         },
2551                         .num_parents = 1,
2552                         .flags = CLK_SET_RATE_PARENT,
2553                         .ops = &clk_branch2_ops,
2554                 },
2555         },
2556 };
2557
2558 static struct clk_branch gcc_camss_ahb_clk = {
2559         .halt_reg = 0x5a014,
2560         .clkr = {
2561                 .enable_reg = 0x5a014,
2562                 .enable_mask = BIT(0),
2563                 .hw.init = &(struct clk_init_data){
2564                         .name = "gcc_camss_ahb_clk",
2565                         .parent_hws = (const struct clk_hw*[]){
2566                                 &camss_ahb_clk_src.clkr.hw,
2567                         },
2568                         .num_parents = 1,
2569                         .flags = CLK_SET_RATE_PARENT,
2570                         .ops = &clk_branch2_ops,
2571                 },
2572         },
2573 };
2574
2575 static struct clk_branch gcc_camss_top_ahb_clk = {
2576         .halt_reg = 0x56004,
2577         .clkr = {
2578                 .enable_reg = 0x56004,
2579                 .enable_mask = BIT(0),
2580                 .hw.init = &(struct clk_init_data){
2581                         .name = "gcc_camss_top_ahb_clk",
2582                         .parent_hws = (const struct clk_hw*[]){
2583                                 &pcnoc_bfdcd_clk_src.clkr.hw,
2584                         },
2585                         .num_parents = 1,
2586                         .flags = CLK_SET_RATE_PARENT,
2587                         .ops = &clk_branch2_ops,
2588                 },
2589         },
2590 };
2591
2592 static struct clk_branch gcc_camss_cpp_ahb_clk = {
2593         .halt_reg = 0x58040,
2594         .clkr = {
2595                 .enable_reg = 0x58040,
2596                 .enable_mask = BIT(0),
2597                 .hw.init = &(struct clk_init_data){
2598                         .name = "gcc_camss_cpp_ahb_clk",
2599                         .parent_hws = (const struct clk_hw*[]){
2600                                 &camss_ahb_clk_src.clkr.hw,
2601                         },
2602                         .num_parents = 1,
2603                         .flags = CLK_SET_RATE_PARENT,
2604                         .ops = &clk_branch2_ops,
2605                 },
2606         },
2607 };
2608
2609 static struct clk_branch gcc_camss_cpp_clk = {
2610         .halt_reg = 0x5803c,
2611         .clkr = {
2612                 .enable_reg = 0x5803c,
2613                 .enable_mask = BIT(0),
2614                 .hw.init = &(struct clk_init_data){
2615                         .name = "gcc_camss_cpp_clk",
2616                         .parent_hws = (const struct clk_hw*[]){
2617                                 &cpp_clk_src.clkr.hw,
2618                         },
2619                         .num_parents = 1,
2620                         .flags = CLK_SET_RATE_PARENT,
2621                         .ops = &clk_branch2_ops,
2622                 },
2623         },
2624 };
2625
2626 static struct clk_branch gcc_camss_vfe0_clk = {
2627         .halt_reg = 0x58038,
2628         .clkr = {
2629                 .enable_reg = 0x58038,
2630                 .enable_mask = BIT(0),
2631                 .hw.init = &(struct clk_init_data){
2632                         .name = "gcc_camss_vfe0_clk",
2633                         .parent_hws = (const struct clk_hw*[]){
2634                                 &vfe0_clk_src.clkr.hw,
2635                         },
2636                         .num_parents = 1,
2637                         .flags = CLK_SET_RATE_PARENT,
2638                         .ops = &clk_branch2_ops,
2639                 },
2640         },
2641 };
2642
2643 static struct clk_branch gcc_camss_vfe_ahb_clk = {
2644         .halt_reg = 0x58044,
2645         .clkr = {
2646                 .enable_reg = 0x58044,
2647                 .enable_mask = BIT(0),
2648                 .hw.init = &(struct clk_init_data){
2649                         .name = "gcc_camss_vfe_ahb_clk",
2650                         .parent_hws = (const struct clk_hw*[]){
2651                                 &camss_ahb_clk_src.clkr.hw,
2652                         },
2653                         .num_parents = 1,
2654                         .flags = CLK_SET_RATE_PARENT,
2655                         .ops = &clk_branch2_ops,
2656                 },
2657         },
2658 };
2659
2660 static struct clk_branch gcc_camss_vfe_axi_clk = {
2661         .halt_reg = 0x58048,
2662         .clkr = {
2663                 .enable_reg = 0x58048,
2664                 .enable_mask = BIT(0),
2665                 .hw.init = &(struct clk_init_data){
2666                         .name = "gcc_camss_vfe_axi_clk",
2667                         .parent_hws = (const struct clk_hw*[]){
2668                                 &system_mm_noc_bfdcd_clk_src.clkr.hw,
2669                         },
2670                         .num_parents = 1,
2671                         .flags = CLK_SET_RATE_PARENT,
2672                         .ops = &clk_branch2_ops,
2673                 },
2674         },
2675 };
2676
2677 static struct clk_branch gcc_crypto_ahb_clk = {
2678         .halt_reg = 0x16024,
2679         .halt_check = BRANCH_HALT_VOTED,
2680         .clkr = {
2681                 .enable_reg = 0x45004,
2682                 .enable_mask = BIT(0),
2683                 .hw.init = &(struct clk_init_data){
2684                         .name = "gcc_crypto_ahb_clk",
2685                         .parent_hws = (const struct clk_hw*[]){
2686                                 &pcnoc_bfdcd_clk_src.clkr.hw,
2687                         },
2688                         .num_parents = 1,
2689                         .flags = CLK_SET_RATE_PARENT,
2690                         .ops = &clk_branch2_ops,
2691                 },
2692         },
2693 };
2694
2695 static struct clk_branch gcc_crypto_axi_clk = {
2696         .halt_reg = 0x16020,
2697         .halt_check = BRANCH_HALT_VOTED,
2698         .clkr = {
2699                 .enable_reg = 0x45004,
2700                 .enable_mask = BIT(1),
2701                 .hw.init = &(struct clk_init_data){
2702                         .name = "gcc_crypto_axi_clk",
2703                         .parent_hws = (const struct clk_hw*[]){
2704                                 &pcnoc_bfdcd_clk_src.clkr.hw,
2705                         },
2706                         .num_parents = 1,
2707                         .flags = CLK_SET_RATE_PARENT,
2708                         .ops = &clk_branch2_ops,
2709                 },
2710         },
2711 };
2712
2713 static struct clk_branch gcc_crypto_clk = {
2714         .halt_reg = 0x1601c,
2715         .halt_check = BRANCH_HALT_VOTED,
2716         .clkr = {
2717                 .enable_reg = 0x45004,
2718                 .enable_mask = BIT(2),
2719                 .hw.init = &(struct clk_init_data){
2720                         .name = "gcc_crypto_clk",
2721                         .parent_hws = (const struct clk_hw*[]){
2722                                 &crypto_clk_src.clkr.hw,
2723                         },
2724                         .num_parents = 1,
2725                         .flags = CLK_SET_RATE_PARENT,
2726                         .ops = &clk_branch2_ops,
2727                 },
2728         },
2729 };
2730
2731 static struct clk_branch gcc_oxili_gmem_clk = {
2732         .halt_reg = 0x59024,
2733         .clkr = {
2734                 .enable_reg = 0x59024,
2735                 .enable_mask = BIT(0),
2736                 .hw.init = &(struct clk_init_data){
2737                         .name = "gcc_oxili_gmem_clk",
2738                         .parent_hws = (const struct clk_hw*[]){
2739                                 &gfx3d_clk_src.clkr.hw,
2740                         },
2741                         .num_parents = 1,
2742                         .flags = CLK_SET_RATE_PARENT,
2743                         .ops = &clk_branch2_ops,
2744                 },
2745         },
2746 };
2747
2748 static struct clk_branch gcc_gp1_clk = {
2749         .halt_reg = 0x08000,
2750         .clkr = {
2751                 .enable_reg = 0x08000,
2752                 .enable_mask = BIT(0),
2753                 .hw.init = &(struct clk_init_data){
2754                         .name = "gcc_gp1_clk",
2755                         .parent_hws = (const struct clk_hw*[]){
2756                                 &gp1_clk_src.clkr.hw,
2757                         },
2758                         .num_parents = 1,
2759                         .flags = CLK_SET_RATE_PARENT,
2760                         .ops = &clk_branch2_ops,
2761                 },
2762         },
2763 };
2764
2765 static struct clk_branch gcc_gp2_clk = {
2766         .halt_reg = 0x09000,
2767         .clkr = {
2768                 .enable_reg = 0x09000,
2769                 .enable_mask = BIT(0),
2770                 .hw.init = &(struct clk_init_data){
2771                         .name = "gcc_gp2_clk",
2772                         .parent_hws = (const struct clk_hw*[]){
2773                                 &gp2_clk_src.clkr.hw,
2774                         },
2775                         .num_parents = 1,
2776                         .flags = CLK_SET_RATE_PARENT,
2777                         .ops = &clk_branch2_ops,
2778                 },
2779         },
2780 };
2781
2782 static struct clk_branch gcc_gp3_clk = {
2783         .halt_reg = 0x0a000,
2784         .clkr = {
2785                 .enable_reg = 0x0a000,
2786                 .enable_mask = BIT(0),
2787                 .hw.init = &(struct clk_init_data){
2788                         .name = "gcc_gp3_clk",
2789                         .parent_hws = (const struct clk_hw*[]){
2790                                 &gp3_clk_src.clkr.hw,
2791                         },
2792                         .num_parents = 1,
2793                         .flags = CLK_SET_RATE_PARENT,
2794                         .ops = &clk_branch2_ops,
2795                 },
2796         },
2797 };
2798
2799 static struct clk_branch gcc_mdss_ahb_clk = {
2800         .halt_reg = 0x4d07c,
2801         .clkr = {
2802                 .enable_reg = 0x4d07c,
2803                 .enable_mask = BIT(0),
2804                 .hw.init = &(struct clk_init_data){
2805                         .name = "gcc_mdss_ahb_clk",
2806                         .parent_hws = (const struct clk_hw*[]){
2807                                 &pcnoc_bfdcd_clk_src.clkr.hw,
2808                         },
2809                         .num_parents = 1,
2810                         .flags = CLK_SET_RATE_PARENT,
2811                         .ops = &clk_branch2_ops,
2812                 },
2813         },
2814 };
2815
2816 static struct clk_branch gcc_mdss_axi_clk = {
2817         .halt_reg = 0x4d080,
2818         .clkr = {
2819                 .enable_reg = 0x4d080,
2820                 .enable_mask = BIT(0),
2821                 .hw.init = &(struct clk_init_data){
2822                         .name = "gcc_mdss_axi_clk",
2823                         .parent_hws = (const struct clk_hw*[]){
2824                                 &system_mm_noc_bfdcd_clk_src.clkr.hw,
2825                         },
2826                         .num_parents = 1,
2827                         .flags = CLK_SET_RATE_PARENT,
2828                         .ops = &clk_branch2_ops,
2829                 },
2830         },
2831 };
2832
2833 static struct clk_branch gcc_mdss_byte0_clk = {
2834         .halt_reg = 0x4d094,
2835         .clkr = {
2836                 .enable_reg = 0x4d094,
2837                 .enable_mask = BIT(0),
2838                 .hw.init = &(struct clk_init_data){
2839                         .name = "gcc_mdss_byte0_clk",
2840                         .parent_hws = (const struct clk_hw*[]){
2841                                 &byte0_clk_src.clkr.hw,
2842                         },
2843                         .num_parents = 1,
2844                         .flags = CLK_SET_RATE_PARENT,
2845                         .ops = &clk_branch2_ops,
2846                 },
2847         },
2848 };
2849
2850 static struct clk_branch gcc_mdss_byte1_clk = {
2851         .halt_reg = 0x4d0a0,
2852         .clkr = {
2853                 .enable_reg = 0x4d0a0,
2854                 .enable_mask = BIT(0),
2855                 .hw.init = &(struct clk_init_data){
2856                         .name = "gcc_mdss_byte1_clk",
2857                         .parent_hws = (const struct clk_hw*[]){
2858                                 &byte1_clk_src.clkr.hw,
2859                         },
2860                         .num_parents = 1,
2861                         .flags = CLK_SET_RATE_PARENT,
2862                         .ops = &clk_branch2_ops,
2863                 },
2864         },
2865 };
2866
2867 static struct clk_branch gcc_mdss_esc0_clk = {
2868         .halt_reg = 0x4d098,
2869         .clkr = {
2870                 .enable_reg = 0x4d098,
2871                 .enable_mask = BIT(0),
2872                 .hw.init = &(struct clk_init_data){
2873                         .name = "gcc_mdss_esc0_clk",
2874                         .parent_hws = (const struct clk_hw*[]){
2875                                 &esc0_clk_src.clkr.hw,
2876                         },
2877                         .num_parents = 1,
2878                         .flags = CLK_SET_RATE_PARENT,
2879                         .ops = &clk_branch2_ops,
2880                 },
2881         },
2882 };
2883
2884 static struct clk_branch gcc_mdss_esc1_clk = {
2885         .halt_reg = 0x4d09c,
2886         .clkr = {
2887                 .enable_reg = 0x4d09c,
2888                 .enable_mask = BIT(0),
2889                 .hw.init = &(struct clk_init_data){
2890                         .name = "gcc_mdss_esc1_clk",
2891                         .parent_hws = (const struct clk_hw*[]){
2892                                 &esc1_clk_src.clkr.hw,
2893                         },
2894                         .num_parents = 1,
2895                         .flags = CLK_SET_RATE_PARENT,
2896                         .ops = &clk_branch2_ops,
2897                 },
2898         },
2899 };
2900
2901 static struct clk_branch gcc_mdss_mdp_clk = {
2902         .halt_reg = 0x4D088,
2903         .clkr = {
2904                 .enable_reg = 0x4D088,
2905                 .enable_mask = BIT(0),
2906                 .hw.init = &(struct clk_init_data){
2907                         .name = "gcc_mdss_mdp_clk",
2908                         .parent_hws = (const struct clk_hw*[]){
2909                                 &mdp_clk_src.clkr.hw,
2910                         },
2911                         .num_parents = 1,
2912                         .flags = CLK_SET_RATE_PARENT,
2913                         .ops = &clk_branch2_ops,
2914                 },
2915         },
2916 };
2917
2918 static struct clk_branch gcc_mdss_pclk0_clk = {
2919         .halt_reg = 0x4d084,
2920         .clkr = {
2921                 .enable_reg = 0x4d084,
2922                 .enable_mask = BIT(0),
2923                 .hw.init = &(struct clk_init_data){
2924                         .name = "gcc_mdss_pclk0_clk",
2925                         .parent_hws = (const struct clk_hw*[]){
2926                                 &pclk0_clk_src.clkr.hw,
2927                         },
2928                         .num_parents = 1,
2929                         .flags = CLK_SET_RATE_PARENT,
2930                         .ops = &clk_branch2_ops,
2931                 },
2932         },
2933 };
2934
2935 static struct clk_branch gcc_mdss_pclk1_clk = {
2936         .halt_reg = 0x4d0a4,
2937         .clkr = {
2938                 .enable_reg = 0x4d0a4,
2939                 .enable_mask = BIT(0),
2940                 .hw.init = &(struct clk_init_data){
2941                         .name = "gcc_mdss_pclk1_clk",
2942                         .parent_hws = (const struct clk_hw*[]){
2943                                 &pclk1_clk_src.clkr.hw,
2944                         },
2945                         .num_parents = 1,
2946                         .flags = CLK_SET_RATE_PARENT,
2947                         .ops = &clk_branch2_ops,
2948                 },
2949         },
2950 };
2951
2952 static struct clk_branch gcc_mdss_vsync_clk = {
2953         .halt_reg = 0x4d090,
2954         .clkr = {
2955                 .enable_reg = 0x4d090,
2956                 .enable_mask = BIT(0),
2957                 .hw.init = &(struct clk_init_data){
2958                         .name = "gcc_mdss_vsync_clk",
2959                         .parent_hws = (const struct clk_hw*[]){
2960                                 &vsync_clk_src.clkr.hw,
2961                         },
2962                         .num_parents = 1,
2963                         .flags = CLK_SET_RATE_PARENT,
2964                         .ops = &clk_branch2_ops,
2965                 },
2966         },
2967 };
2968
2969 static struct clk_branch gcc_mss_cfg_ahb_clk = {
2970         .halt_reg = 0x49000,
2971         .clkr = {
2972                 .enable_reg = 0x49000,
2973                 .enable_mask = BIT(0),
2974                 .hw.init = &(struct clk_init_data){
2975                         .name = "gcc_mss_cfg_ahb_clk",
2976                         .parent_hws = (const struct clk_hw*[]){
2977                                 &pcnoc_bfdcd_clk_src.clkr.hw,
2978                         },
2979                         .num_parents = 1,
2980                         .flags = CLK_SET_RATE_PARENT,
2981                         .ops = &clk_branch2_ops,
2982                 },
2983         },
2984 };
2985
2986 static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
2987         .halt_reg = 0x49004,
2988         .clkr = {
2989                 .enable_reg = 0x49004,
2990                 .enable_mask = BIT(0),
2991                 .hw.init = &(struct clk_init_data){
2992                         .name = "gcc_mss_q6_bimc_axi_clk",
2993                         .parent_hws = (const struct clk_hw*[]){
2994                                 &bimc_ddr_clk_src.clkr.hw,
2995                         },
2996                         .num_parents = 1,
2997                         .flags = CLK_SET_RATE_PARENT,
2998                         .ops = &clk_branch2_ops,
2999                 },
3000         },
3001 };
3002
3003 static struct clk_branch gcc_oxili_ahb_clk = {
3004         .halt_reg = 0x59028,
3005         .clkr = {
3006                 .enable_reg = 0x59028,
3007                 .enable_mask = BIT(0),
3008                 .hw.init = &(struct clk_init_data){
3009                         .name = "gcc_oxili_ahb_clk",
3010                         .parent_hws = (const struct clk_hw*[]){
3011                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3012                         },
3013                         .num_parents = 1,
3014                         .flags = CLK_SET_RATE_PARENT,
3015                         .ops = &clk_branch2_ops,
3016                 },
3017         },
3018 };
3019
3020 static struct clk_branch gcc_oxili_gfx3d_clk = {
3021         .halt_reg = 0x59020,
3022         .clkr = {
3023                 .enable_reg = 0x59020,
3024                 .enable_mask = BIT(0),
3025                 .hw.init = &(struct clk_init_data){
3026                         .name = "gcc_oxili_gfx3d_clk",
3027                         .parent_hws = (const struct clk_hw*[]){
3028                                 &gfx3d_clk_src.clkr.hw,
3029                         },
3030                         .num_parents = 1,
3031                         .flags = CLK_SET_RATE_PARENT,
3032                         .ops = &clk_branch2_ops,
3033                 },
3034         },
3035 };
3036
3037 static struct clk_branch gcc_pdm2_clk = {
3038         .halt_reg = 0x4400c,
3039         .clkr = {
3040                 .enable_reg = 0x4400c,
3041                 .enable_mask = BIT(0),
3042                 .hw.init = &(struct clk_init_data){
3043                         .name = "gcc_pdm2_clk",
3044                         .parent_hws = (const struct clk_hw*[]){
3045                                 &pdm2_clk_src.clkr.hw,
3046                         },
3047                         .num_parents = 1,
3048                         .flags = CLK_SET_RATE_PARENT,
3049                         .ops = &clk_branch2_ops,
3050                 },
3051         },
3052 };
3053
3054 static struct clk_branch gcc_pdm_ahb_clk = {
3055         .halt_reg = 0x44004,
3056         .clkr = {
3057                 .enable_reg = 0x44004,
3058                 .enable_mask = BIT(0),
3059                 .hw.init = &(struct clk_init_data){
3060                         .name = "gcc_pdm_ahb_clk",
3061                         .parent_hws = (const struct clk_hw*[]){
3062                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3063                         },
3064                         .num_parents = 1,
3065                         .flags = CLK_SET_RATE_PARENT,
3066                         .ops = &clk_branch2_ops,
3067                 },
3068         },
3069 };
3070
3071 static struct clk_branch gcc_prng_ahb_clk = {
3072         .halt_reg = 0x13004,
3073         .halt_check = BRANCH_HALT_VOTED,
3074         .clkr = {
3075                 .enable_reg = 0x45004,
3076                 .enable_mask = BIT(8),
3077                 .hw.init = &(struct clk_init_data){
3078                         .name = "gcc_prng_ahb_clk",
3079                         .parent_hws = (const struct clk_hw*[]){
3080                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3081                         },
3082                         .num_parents = 1,
3083                         .ops = &clk_branch2_ops,
3084                 },
3085         },
3086 };
3087
3088 static struct clk_branch gcc_sdcc1_ahb_clk = {
3089         .halt_reg = 0x4201c,
3090         .clkr = {
3091                 .enable_reg = 0x4201c,
3092                 .enable_mask = BIT(0),
3093                 .hw.init = &(struct clk_init_data){
3094                         .name = "gcc_sdcc1_ahb_clk",
3095                         .parent_hws = (const struct clk_hw*[]){
3096                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3097                         },
3098                         .num_parents = 1,
3099                         .flags = CLK_SET_RATE_PARENT,
3100                         .ops = &clk_branch2_ops,
3101                 },
3102         },
3103 };
3104
3105 static struct clk_branch gcc_sdcc1_apps_clk = {
3106         .halt_reg = 0x42018,
3107         .clkr = {
3108                 .enable_reg = 0x42018,
3109                 .enable_mask = BIT(0),
3110                 .hw.init = &(struct clk_init_data){
3111                         .name = "gcc_sdcc1_apps_clk",
3112                         .parent_hws = (const struct clk_hw*[]){
3113                                 &sdcc1_apps_clk_src.clkr.hw,
3114                         },
3115                         .num_parents = 1,
3116                         .flags = CLK_SET_RATE_PARENT,
3117                         .ops = &clk_branch2_ops,
3118                 },
3119         },
3120 };
3121
3122 static struct clk_branch gcc_sdcc2_ahb_clk = {
3123         .halt_reg = 0x4301c,
3124         .clkr = {
3125                 .enable_reg = 0x4301c,
3126                 .enable_mask = BIT(0),
3127                 .hw.init = &(struct clk_init_data){
3128                         .name = "gcc_sdcc2_ahb_clk",
3129                         .parent_hws = (const struct clk_hw*[]){
3130                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3131                         },
3132                         .num_parents = 1,
3133                         .flags = CLK_SET_RATE_PARENT,
3134                         .ops = &clk_branch2_ops,
3135                 },
3136         },
3137 };
3138
3139 static struct clk_branch gcc_sdcc2_apps_clk = {
3140         .halt_reg = 0x43018,
3141         .clkr = {
3142                 .enable_reg = 0x43018,
3143                 .enable_mask = BIT(0),
3144                 .hw.init = &(struct clk_init_data){
3145                         .name = "gcc_sdcc2_apps_clk",
3146                         .parent_hws = (const struct clk_hw*[]){
3147                                 &sdcc2_apps_clk_src.clkr.hw,
3148                         },
3149                         .num_parents = 1,
3150                         .flags = CLK_SET_RATE_PARENT,
3151                         .ops = &clk_branch2_ops,
3152                 },
3153         },
3154 };
3155
3156 static struct clk_branch gcc_apss_tcu_clk = {
3157         .halt_reg = 0x12018,
3158         .halt_check = BRANCH_HALT_VOTED,
3159         .clkr = {
3160                 .enable_reg = 0x4500c,
3161                 .enable_mask = BIT(1),
3162                 .hw.init = &(struct clk_init_data){
3163                         .name = "gcc_apss_tcu_clk",
3164                         .parent_hws = (const struct clk_hw*[]){
3165                                 &bimc_ddr_clk_src.clkr.hw,
3166                         },
3167                         .num_parents = 1,
3168                         .ops = &clk_branch2_ops,
3169                 },
3170         },
3171 };
3172
3173 static struct clk_branch gcc_gfx_tcu_clk = {
3174         .halt_reg = 0x12020,
3175         .halt_check = BRANCH_HALT_VOTED,
3176         .clkr = {
3177                 .enable_reg = 0x4500c,
3178                 .enable_mask = BIT(2),
3179                 .hw.init = &(struct clk_init_data){
3180                         .name = "gcc_gfx_tcu_clk",
3181                         .parent_hws = (const struct clk_hw*[]){
3182                                 &bimc_ddr_clk_src.clkr.hw,
3183                         },
3184                         .num_parents = 1,
3185                         .ops = &clk_branch2_ops,
3186                 },
3187         },
3188 };
3189
3190 static struct clk_branch gcc_gfx_tbu_clk = {
3191         .halt_reg = 0x12010,
3192         .halt_check = BRANCH_HALT_VOTED,
3193         .clkr = {
3194                 .enable_reg = 0x4500c,
3195                 .enable_mask = BIT(3),
3196                 .hw.init = &(struct clk_init_data){
3197                         .name = "gcc_gfx_tbu_clk",
3198                         .parent_hws = (const struct clk_hw*[]){
3199                                 &bimc_ddr_clk_src.clkr.hw,
3200                         },
3201                         .num_parents = 1,
3202                         .ops = &clk_branch2_ops,
3203                 },
3204         },
3205 };
3206
3207 static struct clk_branch gcc_mdp_tbu_clk = {
3208         .halt_reg = 0x1201c,
3209         .halt_check = BRANCH_HALT_VOTED,
3210         .clkr = {
3211                 .enable_reg = 0x4500c,
3212                 .enable_mask = BIT(4),
3213                 .hw.init = &(struct clk_init_data){
3214                         .name = "gcc_mdp_tbu_clk",
3215                         .parent_hws = (const struct clk_hw*[]){
3216                                 &system_mm_noc_bfdcd_clk_src.clkr.hw,
3217                         },
3218                         .num_parents = 1,
3219                         .flags = CLK_SET_RATE_PARENT,
3220                         .ops = &clk_branch2_ops,
3221                 },
3222         },
3223 };
3224
3225 static struct clk_branch gcc_venus_tbu_clk = {
3226         .halt_reg = 0x12014,
3227         .halt_check = BRANCH_HALT_VOTED,
3228         .clkr = {
3229                 .enable_reg = 0x4500c,
3230                 .enable_mask = BIT(5),
3231                 .hw.init = &(struct clk_init_data){
3232                         .name = "gcc_venus_tbu_clk",
3233                         .parent_hws = (const struct clk_hw*[]){
3234                                 &system_mm_noc_bfdcd_clk_src.clkr.hw,
3235                         },
3236                         .num_parents = 1,
3237                         .flags = CLK_SET_RATE_PARENT,
3238                         .ops = &clk_branch2_ops,
3239                 },
3240         },
3241 };
3242
3243 static struct clk_branch gcc_vfe_tbu_clk = {
3244         .halt_reg = 0x1203c,
3245         .halt_check = BRANCH_HALT_VOTED,
3246         .clkr = {
3247                 .enable_reg = 0x4500c,
3248                 .enable_mask = BIT(9),
3249                 .hw.init = &(struct clk_init_data){
3250                         .name = "gcc_vfe_tbu_clk",
3251                         .parent_hws = (const struct clk_hw*[]){
3252                                 &system_mm_noc_bfdcd_clk_src.clkr.hw,
3253                         },
3254                         .num_parents = 1,
3255                         .flags = CLK_SET_RATE_PARENT,
3256                         .ops = &clk_branch2_ops,
3257                 },
3258         },
3259 };
3260
3261 static struct clk_branch gcc_jpeg_tbu_clk = {
3262         .halt_reg = 0x12034,
3263         .halt_check = BRANCH_HALT_VOTED,
3264         .clkr = {
3265                 .enable_reg = 0x4500c,
3266                 .enable_mask = BIT(10),
3267                 .hw.init = &(struct clk_init_data){
3268                         .name = "gcc_jpeg_tbu_clk",
3269                         .parent_hws = (const struct clk_hw*[]){
3270                                 &system_mm_noc_bfdcd_clk_src.clkr.hw,
3271                         },
3272                         .num_parents = 1,
3273                         .flags = CLK_SET_RATE_PARENT,
3274                         .ops = &clk_branch2_ops,
3275                 },
3276         },
3277 };
3278
3279 static struct clk_branch gcc_smmu_cfg_clk = {
3280         .halt_reg = 0x12038,
3281         .halt_check = BRANCH_HALT_VOTED,
3282         .clkr = {
3283                 .enable_reg = 0x4500c,
3284                 .enable_mask = BIT(12),
3285                 .hw.init = &(struct clk_init_data){
3286                         .name = "gcc_smmu_cfg_clk",
3287                         .parent_hws = (const struct clk_hw*[]){
3288                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3289                         },
3290                         .num_parents = 1,
3291                         .flags = CLK_SET_RATE_PARENT,
3292                         .ops = &clk_branch2_ops,
3293                 },
3294         },
3295 };
3296
3297 static struct clk_branch gcc_gtcu_ahb_clk = {
3298         .halt_reg = 0x12044,
3299         .halt_check = BRANCH_HALT_VOTED,
3300         .clkr = {
3301                 .enable_reg = 0x4500c,
3302                 .enable_mask = BIT(13),
3303                 .hw.init = &(struct clk_init_data){
3304                         .name = "gcc_gtcu_ahb_clk",
3305                         .parent_hws = (const struct clk_hw*[]){
3306                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3307                         },
3308                         .num_parents = 1,
3309                         .flags = CLK_SET_RATE_PARENT,
3310                         .ops = &clk_branch2_ops,
3311                 },
3312         },
3313 };
3314
3315 static struct clk_branch gcc_cpp_tbu_clk = {
3316         .halt_reg = 0x12040,
3317         .halt_check = BRANCH_HALT_VOTED,
3318         .clkr = {
3319                 .enable_reg = 0x4500c,
3320                 .enable_mask = BIT(14),
3321                 .hw.init = &(struct clk_init_data){
3322                         .name = "gcc_cpp_tbu_clk",
3323                         .parent_hws = (const struct clk_hw*[]){
3324                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3325                         },
3326                         .num_parents = 1,
3327                         .flags = CLK_SET_RATE_PARENT,
3328                         .ops = &clk_branch2_ops,
3329                 },
3330         },
3331 };
3332
3333 static struct clk_branch gcc_mdp_rt_tbu_clk = {
3334         .halt_reg = 0x1201c,
3335         .halt_check = BRANCH_HALT_VOTED,
3336         .clkr = {
3337                 .enable_reg = 0x4500c,
3338                 .enable_mask = BIT(15),
3339                 .hw.init = &(struct clk_init_data){
3340                         .name = "gcc_mdp_rt_tbu_clk",
3341                         .parent_hws = (const struct clk_hw*[]){
3342                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3343                         },
3344                         .num_parents = 1,
3345                         .flags = CLK_SET_RATE_PARENT,
3346                         .ops = &clk_branch2_ops,
3347                 },
3348         },
3349 };
3350
3351 static struct clk_branch gcc_bimc_gfx_clk = {
3352         .halt_reg = 0x31024,
3353         .clkr = {
3354                 .enable_reg = 0x31024,
3355                 .enable_mask = BIT(0),
3356                 .hw.init = &(struct clk_init_data){
3357                         .name = "gcc_bimc_gfx_clk",
3358                         .parent_hws = (const struct clk_hw*[]){
3359                                 &bimc_gpu_clk_src.clkr.hw,
3360                         },
3361                         .num_parents = 1,
3362                         .flags = CLK_SET_RATE_PARENT,
3363                         .ops = &clk_branch2_ops,
3364                 },
3365         },
3366 };
3367
3368 static struct clk_branch gcc_bimc_gpu_clk = {
3369         .halt_reg = 0x31040,
3370         .clkr = {
3371                 .enable_reg = 0x31040,
3372                 .enable_mask = BIT(0),
3373                 .hw.init = &(struct clk_init_data){
3374                         .name = "gcc_bimc_gpu_clk",
3375                         .parent_hws = (const struct clk_hw*[]){
3376                                 &bimc_gpu_clk_src.clkr.hw,
3377                         },
3378                         .num_parents = 1,
3379                         .flags = CLK_SET_RATE_PARENT,
3380                         .ops = &clk_branch2_ops,
3381                 },
3382         },
3383 };
3384
3385 static struct clk_branch gcc_usb2a_phy_sleep_clk = {
3386         .halt_reg = 0x4102c,
3387         .clkr = {
3388                 .enable_reg = 0x4102c,
3389                 .enable_mask = BIT(0),
3390                 .hw.init = &(struct clk_init_data){
3391                         .name = "gcc_usb2a_phy_sleep_clk",
3392                         .ops = &clk_branch2_ops,
3393                 },
3394         },
3395 };
3396
3397 static struct clk_branch gcc_usb_fs_ahb_clk = {
3398         .halt_reg = 0x3f008,
3399         .clkr = {
3400                 .enable_reg = 0x3f008,
3401                 .enable_mask = BIT(0),
3402                 .hw.init = &(struct clk_init_data){
3403                         .name = "gcc_usb_fs_ahb_clk",
3404                         .parent_hws = (const struct clk_hw*[]){
3405                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3406                         },
3407                         .num_parents = 1,
3408                         .flags = CLK_SET_RATE_PARENT,
3409                         .ops = &clk_branch2_ops,
3410                 },
3411         },
3412 };
3413
3414 static struct clk_branch gcc_usb_fs_ic_clk = {
3415         .halt_reg = 0x3f030,
3416         .clkr = {
3417                 .enable_reg = 0x3f030,
3418                 .enable_mask = BIT(0),
3419                 .hw.init = &(struct clk_init_data){
3420                         .name = "gcc_usb_fs_ic_clk",
3421                         .parent_hws = (const struct clk_hw*[]){
3422                                 &usb_fs_ic_clk_src.clkr.hw,
3423                         },
3424                         .num_parents = 1,
3425                         .flags = CLK_SET_RATE_PARENT,
3426                         .ops = &clk_branch2_ops,
3427                 },
3428         },
3429 };
3430
3431 static struct clk_branch gcc_usb_fs_system_clk = {
3432         .halt_reg = 0x3f004,
3433         .clkr = {
3434                 .enable_reg = 0x3f004,
3435                 .enable_mask = BIT(0),
3436                 .hw.init = &(struct clk_init_data){
3437                         .name = "gcc_usb_fs_system_clk",
3438                         .parent_hws = (const struct clk_hw*[]){
3439                                 &usb_fs_system_clk_src.clkr.hw,
3440                         },
3441                         .num_parents = 1,
3442                         .flags = CLK_SET_RATE_PARENT,
3443                         .ops = &clk_branch2_ops,
3444                 },
3445         },
3446 };
3447
3448 static struct clk_branch gcc_usb_hs_ahb_clk = {
3449         .halt_reg = 0x41008,
3450         .clkr = {
3451                 .enable_reg = 0x41008,
3452                 .enable_mask = BIT(0),
3453                 .hw.init = &(struct clk_init_data){
3454                         .name = "gcc_usb_hs_ahb_clk",
3455                         .parent_hws = (const struct clk_hw*[]){
3456                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3457                         },
3458                         .num_parents = 1,
3459                         .flags = CLK_SET_RATE_PARENT,
3460                         .ops = &clk_branch2_ops,
3461                 },
3462         },
3463 };
3464
3465 static struct clk_branch gcc_usb_hs_system_clk = {
3466         .halt_reg = 0x41004,
3467         .clkr = {
3468                 .enable_reg = 0x41004,
3469                 .enable_mask = BIT(0),
3470                 .hw.init = &(struct clk_init_data){
3471                         .name = "gcc_usb_hs_system_clk",
3472                         .parent_hws = (const struct clk_hw*[]){
3473                                 &usb_hs_system_clk_src.clkr.hw,
3474                         },
3475                         .num_parents = 1,
3476                         .flags = CLK_SET_RATE_PARENT,
3477                         .ops = &clk_branch2_ops,
3478                 },
3479         },
3480 };
3481
3482 static struct clk_branch gcc_venus0_ahb_clk = {
3483         .halt_reg = 0x4c020,
3484         .clkr = {
3485                 .enable_reg = 0x4c020,
3486                 .enable_mask = BIT(0),
3487                 .hw.init = &(struct clk_init_data){
3488                         .name = "gcc_venus0_ahb_clk",
3489                         .parent_hws = (const struct clk_hw*[]){
3490                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3491                         },
3492                         .num_parents = 1,
3493                         .flags = CLK_SET_RATE_PARENT,
3494                         .ops = &clk_branch2_ops,
3495                 },
3496         },
3497 };
3498
3499 static struct clk_branch gcc_venus0_axi_clk = {
3500         .halt_reg = 0x4c024,
3501         .clkr = {
3502                 .enable_reg = 0x4c024,
3503                 .enable_mask = BIT(0),
3504                 .hw.init = &(struct clk_init_data){
3505                         .name = "gcc_venus0_axi_clk",
3506                         .parent_hws = (const struct clk_hw*[]){
3507                                 &system_mm_noc_bfdcd_clk_src.clkr.hw,
3508                         },
3509                         .num_parents = 1,
3510                         .flags = CLK_SET_RATE_PARENT,
3511                         .ops = &clk_branch2_ops,
3512                 },
3513         },
3514 };
3515
3516 static struct clk_branch gcc_venus0_vcodec0_clk = {
3517         .halt_reg = 0x4c01c,
3518         .clkr = {
3519                 .enable_reg = 0x4c01c,
3520                 .enable_mask = BIT(0),
3521                 .hw.init = &(struct clk_init_data){
3522                         .name = "gcc_venus0_vcodec0_clk",
3523                         .parent_hws = (const struct clk_hw*[]){
3524                                 &vcodec0_clk_src.clkr.hw,
3525                         },
3526                         .num_parents = 1,
3527                         .flags = CLK_SET_RATE_PARENT,
3528                         .ops = &clk_branch2_ops,
3529                 },
3530         },
3531 };
3532
3533 static struct clk_branch gcc_venus0_core0_vcodec0_clk = {
3534         .halt_reg = 0x4c02c,
3535         .clkr = {
3536                 .enable_reg = 0x4c02c,
3537                 .enable_mask = BIT(0),
3538                 .hw.init = &(struct clk_init_data){
3539                         .name = "gcc_venus0_core0_vcodec0_clk",
3540                         .parent_hws = (const struct clk_hw*[]){
3541                                 &vcodec0_clk_src.clkr.hw,
3542                         },
3543                         .num_parents = 1,
3544                         .flags = CLK_SET_RATE_PARENT,
3545                         .ops = &clk_branch2_ops,
3546                 },
3547         },
3548 };
3549
3550 static struct clk_branch gcc_venus0_core1_vcodec0_clk = {
3551         .halt_reg = 0x4c034,
3552         .clkr = {
3553                 .enable_reg = 0x4c034,
3554                 .enable_mask = BIT(0),
3555                 .hw.init = &(struct clk_init_data){
3556                         .name = "gcc_venus0_core1_vcodec0_clk",
3557                         .parent_hws = (const struct clk_hw*[]){
3558                                 &vcodec0_clk_src.clkr.hw,
3559                         },
3560                         .num_parents = 1,
3561                         .flags = CLK_SET_RATE_PARENT,
3562                         .ops = &clk_branch2_ops,
3563                 },
3564         },
3565 };
3566
3567 static struct clk_branch gcc_oxili_timer_clk = {
3568         .halt_reg = 0x59040,
3569         .clkr = {
3570                 .enable_reg = 0x59040,
3571                 .enable_mask = BIT(0),
3572                 .hw.init = &(struct clk_init_data){
3573                         .name = "gcc_oxili_timer_clk",
3574                         .ops = &clk_branch2_ops,
3575                 },
3576         },
3577 };
3578
3579 static struct gdsc venus_gdsc = {
3580         .gdscr = 0x4c018,
3581         .pd = {
3582                 .name = "venus",
3583         },
3584         .pwrsts = PWRSTS_OFF_ON,
3585 };
3586
3587 static struct gdsc mdss_gdsc = {
3588         .gdscr = 0x4d078,
3589         .pd = {
3590                 .name = "mdss",
3591         },
3592         .pwrsts = PWRSTS_OFF_ON,
3593 };
3594
3595 static struct gdsc jpeg_gdsc = {
3596         .gdscr = 0x5701c,
3597         .pd = {
3598                 .name = "jpeg",
3599         },
3600         .pwrsts = PWRSTS_OFF_ON,
3601 };
3602
3603 static struct gdsc vfe_gdsc = {
3604         .gdscr = 0x58034,
3605         .pd = {
3606                 .name = "vfe",
3607         },
3608         .pwrsts = PWRSTS_OFF_ON,
3609 };
3610
3611 static struct gdsc oxili_gdsc = {
3612         .gdscr = 0x5901c,
3613         .pd = {
3614                 .name = "oxili",
3615         },
3616         .pwrsts = PWRSTS_OFF_ON,
3617 };
3618
3619 static struct gdsc venus_core0_gdsc = {
3620         .gdscr = 0x4c028,
3621         .pd = {
3622                 .name = "venus_core0",
3623         },
3624         .pwrsts = PWRSTS_OFF_ON,
3625 };
3626
3627 static struct gdsc venus_core1_gdsc = {
3628         .gdscr = 0x4c030,
3629         .pd = {
3630                 .name = "venus_core1",
3631         },
3632         .pwrsts = PWRSTS_OFF_ON,
3633 };
3634
3635 static struct clk_regmap *gcc_msm8939_clocks[] = {
3636         [GPLL0] = &gpll0.clkr,
3637         [GPLL0_VOTE] = &gpll0_vote,
3638         [BIMC_PLL] = &bimc_pll.clkr,
3639         [BIMC_PLL_VOTE] = &bimc_pll_vote,
3640         [GPLL1] = &gpll1.clkr,
3641         [GPLL1_VOTE] = &gpll1_vote,
3642         [GPLL2] = &gpll2.clkr,
3643         [GPLL2_VOTE] = &gpll2_vote,
3644         [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
3645         [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
3646         [SYSTEM_MM_NOC_BFDCD_CLK_SRC] = &system_mm_noc_bfdcd_clk_src.clkr,
3647         [CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr,
3648         [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
3649         [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3650         [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3651         [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
3652         [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3653         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3654         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3655         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3656         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3657         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3658         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3659         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3660         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3661         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3662         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3663         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3664         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3665         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3666         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3667         [CCI_CLK_SRC] = &cci_clk_src.clkr,
3668         [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3669         [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3670         [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3671         [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3672         [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3673         [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3674         [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3675         [CPP_CLK_SRC] = &cpp_clk_src.clkr,
3676         [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
3677         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
3678         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
3679         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
3680         [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3681         [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3682         [MDP_CLK_SRC] = &mdp_clk_src.clkr,
3683         [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3684         [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
3685         [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3686         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3687         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3688         [APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr,
3689         [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
3690         [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
3691         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3692         [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
3693         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3694         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3695         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3696         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3697         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3698         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3699         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3700         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3701         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3702         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3703         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3704         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3705         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3706         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3707         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3708         [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
3709         [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
3710         [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
3711         [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
3712         [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
3713         [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
3714         [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
3715         [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
3716         [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
3717         [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
3718         [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
3719         [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
3720         [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
3721         [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
3722         [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
3723         [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
3724         [GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
3725         [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
3726         [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
3727         [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
3728         [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
3729         [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
3730         [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
3731         [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
3732         [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
3733         [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
3734         [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
3735         [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
3736         [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
3737         [GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr,
3738         [GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr,
3739         [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
3740         [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
3741         [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
3742         [GCC_OXILI_GMEM_CLK] = &gcc_oxili_gmem_clk.clkr,
3743         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3744         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3745         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3746         [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
3747         [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
3748         [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
3749         [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
3750         [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
3751         [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
3752         [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
3753         [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3754         [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
3755         [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
3756         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3757         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3758         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3759         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3760         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3761         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3762         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3763         [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
3764         [GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
3765         [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
3766         [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
3767         [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
3768         [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
3769         [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
3770         [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
3771         [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
3772         [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
3773         [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
3774         [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
3775         [BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr,
3776         [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
3777         [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
3778         [BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr,
3779         [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
3780         [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
3781         [ULTAUDIO_AHBFABRIC_CLK_SRC] = &ultaudio_ahbfabric_clk_src.clkr,
3782         [ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC] = &ultaudio_lpaif_pri_i2s_clk_src.clkr,
3783         [ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC] = &ultaudio_lpaif_sec_i2s_clk_src.clkr,
3784         [ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC] = &ultaudio_lpaif_aux_i2s_clk_src.clkr,
3785         [ULTAUDIO_XO_CLK_SRC] = &ultaudio_xo_clk_src.clkr,
3786         [CODEC_DIGCODEC_CLK_SRC] = &codec_digcodec_clk_src.clkr,
3787         [GCC_ULTAUDIO_PCNOC_MPORT_CLK] = &gcc_ultaudio_pcnoc_mport_clk.clkr,
3788         [GCC_ULTAUDIO_PCNOC_SWAY_CLK] = &gcc_ultaudio_pcnoc_sway_clk.clkr,
3789         [GCC_ULTAUDIO_AVSYNC_XO_CLK] = &gcc_ultaudio_avsync_xo_clk.clkr,
3790         [GCC_ULTAUDIO_STC_XO_CLK] = &gcc_ultaudio_stc_xo_clk.clkr,
3791         [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_clk.clkr,
3792         [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_lpm_clk.clkr,
3793         [GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK] = &gcc_ultaudio_lpaif_pri_i2s_clk.clkr,
3794         [GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK] = &gcc_ultaudio_lpaif_sec_i2s_clk.clkr,
3795         [GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK] = &gcc_ultaudio_lpaif_aux_i2s_clk.clkr,
3796         [GCC_CODEC_DIGCODEC_CLK] = &gcc_codec_digcodec_clk.clkr,
3797         [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
3798         [GPLL3] = &gpll3.clkr,
3799         [GPLL3_VOTE] = &gpll3_vote,
3800         [GPLL4] = &gpll4.clkr,
3801         [GPLL4_VOTE] = &gpll4_vote,
3802         [GPLL5] = &gpll5.clkr,
3803         [GPLL5_VOTE] = &gpll5_vote,
3804         [GPLL6] = &gpll6.clkr,
3805         [GPLL6_VOTE] = &gpll6_vote,
3806         [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
3807         [GCC_MDSS_BYTE1_CLK] = &gcc_mdss_byte1_clk.clkr,
3808         [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
3809         [GCC_MDSS_ESC1_CLK] = &gcc_mdss_esc1_clk.clkr,
3810         [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
3811         [GCC_MDSS_PCLK1_CLK] = &gcc_mdss_pclk1_clk.clkr,
3812         [GCC_GFX_TBU_CLK] = &gcc_gfx_tbu_clk.clkr,
3813         [GCC_CPP_TBU_CLK] = &gcc_cpp_tbu_clk.clkr,
3814         [GCC_MDP_RT_TBU_CLK] = &gcc_mdp_rt_tbu_clk.clkr,
3815         [USB_FS_SYSTEM_CLK_SRC] = &usb_fs_system_clk_src.clkr,
3816         [USB_FS_IC_CLK_SRC] = &usb_fs_ic_clk_src.clkr,
3817         [GCC_USB_FS_AHB_CLK] = &gcc_usb_fs_ahb_clk.clkr,
3818         [GCC_USB_FS_IC_CLK] = &gcc_usb_fs_ic_clk.clkr,
3819         [GCC_USB_FS_SYSTEM_CLK] = &gcc_usb_fs_system_clk.clkr,
3820         [GCC_VENUS0_CORE0_VCODEC0_CLK] = &gcc_venus0_core0_vcodec0_clk.clkr,
3821         [GCC_VENUS0_CORE1_VCODEC0_CLK] = &gcc_venus0_core1_vcodec0_clk.clkr,
3822         [GCC_OXILI_TIMER_CLK] = &gcc_oxili_timer_clk.clkr,
3823 };
3824
3825 static struct gdsc *gcc_msm8939_gdscs[] = {
3826         [VENUS_GDSC] = &venus_gdsc,
3827         [MDSS_GDSC] = &mdss_gdsc,
3828         [JPEG_GDSC] = &jpeg_gdsc,
3829         [VFE_GDSC] = &vfe_gdsc,
3830         [OXILI_GDSC] = &oxili_gdsc,
3831         [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
3832         [VENUS_CORE1_GDSC] = &venus_core1_gdsc,
3833 };
3834
3835 static const struct qcom_reset_map gcc_msm8939_resets[] = {
3836         [GCC_BLSP1_BCR] = { 0x01000 },
3837         [GCC_BLSP1_QUP1_BCR] = { 0x02000 },
3838         [GCC_BLSP1_UART1_BCR] = { 0x02038 },
3839         [GCC_BLSP1_QUP2_BCR] = { 0x03008 },
3840         [GCC_BLSP1_UART2_BCR] = { 0x03028 },
3841         [GCC_BLSP1_QUP3_BCR] = { 0x04018 },
3842         [GCC_BLSP1_UART3_BCR] = { 0x04038 },
3843         [GCC_BLSP1_QUP4_BCR] = { 0x05018 },
3844         [GCC_BLSP1_QUP5_BCR] = { 0x06018 },
3845         [GCC_BLSP1_QUP6_BCR] = { 0x07018 },
3846         [GCC_IMEM_BCR] = { 0x0e000 },
3847         [GCC_SMMU_BCR] = { 0x12000 },
3848         [GCC_APSS_TCU_BCR] = { 0x12050 },
3849         [GCC_SMMU_XPU_BCR] = { 0x12054 },
3850         [GCC_PCNOC_TBU_BCR] = { 0x12058 },
3851         [GCC_PRNG_BCR] = { 0x13000 },
3852         [GCC_BOOT_ROM_BCR] = { 0x13008 },
3853         [GCC_CRYPTO_BCR] = { 0x16000 },
3854         [GCC_SEC_CTRL_BCR] = { 0x1a000 },
3855         [GCC_AUDIO_CORE_BCR] = { 0x1c008 },
3856         [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
3857         [GCC_DEHR_BCR] = { 0x1f000 },
3858         [GCC_SYSTEM_NOC_BCR] = { 0x26000 },
3859         [GCC_PCNOC_BCR] = { 0x27018 },
3860         [GCC_TCSR_BCR] = { 0x28000 },
3861         [GCC_QDSS_BCR] = { 0x29000 },
3862         [GCC_DCD_BCR] = { 0x2a000 },
3863         [GCC_MSG_RAM_BCR] = { 0x2b000 },
3864         [GCC_MPM_BCR] = { 0x2c000 },
3865         [GCC_SPMI_BCR] = { 0x2e000 },
3866         [GCC_SPDM_BCR] = { 0x2f000 },
3867         [GCC_MM_SPDM_BCR] = { 0x2f024 },
3868         [GCC_BIMC_BCR] = { 0x31000 },
3869         [GCC_RBCPR_BCR] = { 0x33000 },
3870         [GCC_TLMM_BCR] = { 0x34000 },
3871         [GCC_CAMSS_CSI2_BCR] = { 0x3c038 },
3872         [GCC_CAMSS_CSI2PHY_BCR] = { 0x3c044 },
3873         [GCC_CAMSS_CSI2RDI_BCR] = { 0x3c04c },
3874         [GCC_CAMSS_CSI2PIX_BCR] = { 0x3c054 },
3875         [GCC_USB_FS_BCR] = { 0x3f000 },
3876         [GCC_USB_HS_BCR] = { 0x41000 },
3877         [GCC_USB2A_PHY_BCR] = { 0x41028 },
3878         [GCC_SDCC1_BCR] = { 0x42000 },
3879         [GCC_SDCC2_BCR] = { 0x43000 },
3880         [GCC_PDM_BCR] = { 0x44000 },
3881         [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 },
3882         [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 },
3883         [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 },
3884         [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 },
3885         [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 },
3886         [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 },
3887         [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 },
3888         [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 },
3889         [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 },
3890         [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 },
3891         [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 },
3892         [GCC_MMSS_BCR] = { 0x4b000 },
3893         [GCC_VENUS0_BCR] = { 0x4c014 },
3894         [GCC_MDSS_BCR] = { 0x4d074 },
3895         [GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
3896         [GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
3897         [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
3898         [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
3899         [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
3900         [GCC_CAMSS_PHY1_BCR] = { 0x4f018 },
3901         [GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
3902         [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
3903         [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
3904         [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
3905         [GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
3906         [GCC_BLSP1_QUP4_SPI_APPS_CBCR] = { 0x0501c },
3907         [GCC_CAMSS_CCI_BCR] = { 0x51014 },
3908         [GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
3909         [GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
3910         [GCC_CAMSS_GP0_BCR] = { 0x54014 },
3911         [GCC_CAMSS_GP1_BCR] = { 0x55014 },
3912         [GCC_CAMSS_TOP_BCR] = { 0x56000 },
3913         [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
3914         [GCC_CAMSS_JPEG_BCR] = { 0x57018 },
3915         [GCC_CAMSS_VFE_BCR] = { 0x58030 },
3916         [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
3917         [GCC_OXILI_BCR] = { 0x59018 },
3918         [GCC_GMEM_BCR] = { 0x5902c },
3919         [GCC_CAMSS_AHB_BCR] = { 0x5a018 },
3920         [GCC_CAMSS_MCLK2_BCR] = { 0x5c014 },
3921         [GCC_MDP_TBU_BCR] = { 0x62000 },
3922         [GCC_GFX_TBU_BCR] = { 0x63000 },
3923         [GCC_GFX_TCU_BCR] = { 0x64000 },
3924         [GCC_MSS_TBU_AXI_BCR] = { 0x65000 },
3925         [GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 },
3926         [GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 },
3927         [GCC_GTCU_AHB_BCR] = { 0x68000 },
3928         [GCC_SMMU_CFG_BCR] = { 0x69000 },
3929         [GCC_VFE_TBU_BCR] = { 0x6a000 },
3930         [GCC_VENUS_TBU_BCR] = { 0x6b000 },
3931         [GCC_JPEG_TBU_BCR] = { 0x6c000 },
3932         [GCC_PRONTO_TBU_BCR] = { 0x6d000 },
3933         [GCC_CPP_TBU_BCR] = { 0x6e000 },
3934         [GCC_MDP_RT_TBU_BCR] = { 0x6f000 },
3935         [GCC_SMMU_CATS_BCR] = { 0x7c000 },
3936 };
3937
3938 static const struct regmap_config gcc_msm8939_regmap_config = {
3939         .reg_bits       = 32,
3940         .reg_stride     = 4,
3941         .val_bits       = 32,
3942         .max_register   = 0x80000,
3943         .fast_io        = true,
3944 };
3945
3946 static const struct qcom_cc_desc gcc_msm8939_desc = {
3947         .config = &gcc_msm8939_regmap_config,
3948         .clks = gcc_msm8939_clocks,
3949         .num_clks = ARRAY_SIZE(gcc_msm8939_clocks),
3950         .resets = gcc_msm8939_resets,
3951         .num_resets = ARRAY_SIZE(gcc_msm8939_resets),
3952         .gdscs = gcc_msm8939_gdscs,
3953         .num_gdscs = ARRAY_SIZE(gcc_msm8939_gdscs),
3954 };
3955
3956 static const struct of_device_id gcc_msm8939_match_table[] = {
3957         { .compatible = "qcom,gcc-msm8939" },
3958         { }
3959 };
3960 MODULE_DEVICE_TABLE(of, gcc_msm8939_match_table);
3961
3962 static int gcc_msm8939_probe(struct platform_device *pdev)
3963 {
3964         struct regmap *regmap;
3965
3966         regmap = qcom_cc_map(pdev, &gcc_msm8939_desc);
3967         if (IS_ERR(regmap))
3968                 return PTR_ERR(regmap);
3969
3970         clk_pll_configure_sr_hpm_lp(&gpll3, regmap, &gpll3_config, true);
3971         clk_pll_configure_sr_hpm_lp(&gpll4, regmap, &gpll4_config, true);
3972
3973         return qcom_cc_really_probe(pdev, &gcc_msm8939_desc, regmap);
3974 }
3975
3976 static struct platform_driver gcc_msm8939_driver = {
3977         .probe          = gcc_msm8939_probe,
3978         .driver         = {
3979                 .name   = "gcc-msm8939",
3980                 .of_match_table = gcc_msm8939_match_table,
3981         },
3982 };
3983
3984 static int __init gcc_msm8939_init(void)
3985 {
3986         return platform_driver_register(&gcc_msm8939_driver);
3987 }
3988 core_initcall(gcc_msm8939_init);
3989
3990 static void __exit gcc_msm8939_exit(void)
3991 {
3992         platform_driver_unregister(&gcc_msm8939_driver);
3993 }
3994 module_exit(gcc_msm8939_exit);
3995
3996 MODULE_DESCRIPTION("Qualcomm GCC MSM8939 Driver");
3997 MODULE_LICENSE("GPL v2");