1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2020 Linaro Limited
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/clk-provider.h>
14 #include <linux/regmap.h>
15 #include <linux/reset-controller.h>
17 #include <dt-bindings/clock/qcom,gcc-msm8939.h>
18 #include <dt-bindings/reset/qcom,gcc-msm8939.h>
21 #include "clk-regmap.h"
24 #include "clk-branch.h"
53 static struct clk_pll gpll0 = {
57 .config_reg = 0x21010,
59 .status_reg = 0x2101c,
61 .clkr.hw.init = &(struct clk_init_data){
63 .parent_data = &(const struct clk_parent_data) {
71 static struct clk_regmap gpll0_vote = {
72 .enable_reg = 0x45000,
73 .enable_mask = BIT(0),
74 .hw.init = &(struct clk_init_data){
76 .parent_data = &(const struct clk_parent_data) {
80 .ops = &clk_pll_vote_ops,
84 static struct clk_pll gpll1 = {
88 .config_reg = 0x20010,
90 .status_reg = 0x2001c,
92 .clkr.hw.init = &(struct clk_init_data){
94 .parent_data = &(const struct clk_parent_data) {
102 static struct clk_regmap gpll1_vote = {
103 .enable_reg = 0x45000,
104 .enable_mask = BIT(1),
105 .hw.init = &(struct clk_init_data){
106 .name = "gpll1_vote",
107 .parent_data = &(const struct clk_parent_data) {
108 .hw = &gpll1.clkr.hw,
111 .ops = &clk_pll_vote_ops,
115 static struct clk_pll gpll2 = {
119 .config_reg = 0x4a010,
121 .status_reg = 0x4a01c,
123 .clkr.hw.init = &(struct clk_init_data){
125 .parent_data = &(const struct clk_parent_data) {
133 static struct clk_regmap gpll2_vote = {
134 .enable_reg = 0x45000,
135 .enable_mask = BIT(2),
136 .hw.init = &(struct clk_init_data){
137 .name = "gpll2_vote",
138 .parent_data = &(const struct clk_parent_data) {
139 .hw = &gpll2.clkr.hw,
142 .ops = &clk_pll_vote_ops,
146 static struct clk_pll bimc_pll = {
150 .config_reg = 0x23010,
152 .status_reg = 0x2301c,
154 .clkr.hw.init = &(struct clk_init_data){
156 .parent_data = &(const struct clk_parent_data) {
164 static struct clk_regmap bimc_pll_vote = {
165 .enable_reg = 0x45000,
166 .enable_mask = BIT(3),
167 .hw.init = &(struct clk_init_data){
168 .name = "bimc_pll_vote",
169 .parent_data = &(const struct clk_parent_data) {
170 .hw = &bimc_pll.clkr.hw,
173 .ops = &clk_pll_vote_ops,
177 static struct clk_pll gpll3 = {
181 .config_reg = 0x22010,
183 .status_reg = 0x2201c,
185 .clkr.hw.init = &(struct clk_init_data){
187 .parent_data = &(const struct clk_parent_data) {
195 static struct clk_regmap gpll3_vote = {
196 .enable_reg = 0x45000,
197 .enable_mask = BIT(4),
198 .hw.init = &(struct clk_init_data){
199 .name = "gpll3_vote",
200 .parent_data = &(const struct clk_parent_data) {
201 .hw = &gpll3.clkr.hw,
204 .ops = &clk_pll_vote_ops,
208 /* GPLL3 at 1100 MHz, main output enabled. */
209 static const struct pll_config gpll3_config = {
216 .pre_div_mask = BIT(12),
218 .post_div_mask = BIT(9) | BIT(8),
219 .mn_ena_mask = BIT(24),
220 .main_output_mask = BIT(0),
221 .aux_output_mask = BIT(1),
224 static struct clk_pll gpll4 = {
228 .config_reg = 0x24010,
230 .status_reg = 0x2401c,
232 .clkr.hw.init = &(struct clk_init_data){
234 .parent_data = &(const struct clk_parent_data) {
242 static struct clk_regmap gpll4_vote = {
243 .enable_reg = 0x45000,
244 .enable_mask = BIT(5),
245 .hw.init = &(struct clk_init_data){
246 .name = "gpll4_vote",
247 .parent_data = &(const struct clk_parent_data) {
248 .hw = &gpll4.clkr.hw,
251 .ops = &clk_pll_vote_ops,
255 /* GPLL4 at 1200 MHz, main output enabled. */
256 static struct pll_config gpll4_config = {
263 .pre_div_mask = BIT(12),
265 .post_div_mask = BIT(9) | BIT(8),
266 .mn_ena_mask = BIT(24),
267 .main_output_mask = BIT(0),
270 static struct clk_pll gpll5 = {
274 .config_reg = 0x25010,
276 .status_reg = 0x2501c,
278 .clkr.hw.init = &(struct clk_init_data){
280 .parent_data = &(const struct clk_parent_data) {
288 static struct clk_regmap gpll5_vote = {
289 .enable_reg = 0x45000,
290 .enable_mask = BIT(6),
291 .hw.init = &(struct clk_init_data){
292 .name = "gpll5_vote",
293 .parent_data = &(const struct clk_parent_data) {
294 .hw = &gpll5.clkr.hw,
297 .ops = &clk_pll_vote_ops,
301 static struct clk_pll gpll6 = {
305 .config_reg = 0x37010,
307 .status_reg = 0x3701c,
309 .clkr.hw.init = &(struct clk_init_data){
311 .parent_data = &(const struct clk_parent_data) {
319 static struct clk_regmap gpll6_vote = {
320 .enable_reg = 0x45000,
321 .enable_mask = BIT(7),
322 .hw.init = &(struct clk_init_data){
323 .name = "gpll6_vote",
324 .parent_data = &(const struct clk_parent_data) {
325 .hw = &gpll6.clkr.hw,
328 .ops = &clk_pll_vote_ops,
332 static const struct parent_map gcc_xo_gpll0_map[] = {
337 static const struct clk_parent_data gcc_xo_gpll0_parent_data[] = {
339 { .hw = &gpll0_vote.hw },
342 static const struct parent_map gcc_xo_gpll0_bimc_map[] = {
348 static const struct clk_parent_data gcc_xo_gpll0_bimc_parent_data[] = {
350 { .hw = &gpll0_vote.hw },
351 { .hw = &bimc_pll_vote.hw },
354 static const struct parent_map gcc_xo_gpll0_gpll6a_map[] = {
360 static const struct clk_parent_data gcc_xo_gpll0_gpll6a_parent_data[] = {
362 { .hw = &gpll0_vote.hw },
363 { .hw = &gpll6_vote.hw },
366 static const struct parent_map gcc_xo_gpll0_gpll2a_gpll3_gpll6a_map[] = {
374 static const struct clk_parent_data gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data[] = {
376 { .hw = &gpll0_vote.hw },
377 { .hw = &gpll2_vote.hw },
378 { .hw = &gpll3_vote.hw },
379 { .hw = &gpll6_vote.hw },
382 static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
388 static const struct clk_parent_data gcc_xo_gpll0_gpll2_parent_data[] = {
390 { .hw = &gpll0_vote.hw },
391 { .hw = &gpll2_vote.hw },
394 static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_map[] = {
401 static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4_parent_data[] = {
403 { .hw = &gpll0_vote.hw },
404 { .hw = &gpll2_vote.hw },
405 { .hw = &gpll4_vote.hw },
408 static const struct parent_map gcc_xo_gpll0a_map[] = {
413 static const struct clk_parent_data gcc_xo_gpll0a_parent_data[] = {
415 { .hw = &gpll0_vote.hw },
418 static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = {
425 static const struct clk_parent_data gcc_xo_gpll0_gpll1a_sleep_parent_data[] = {
427 { .hw = &gpll0_vote.hw },
428 { .hw = &gpll1_vote.hw },
429 { .fw_name = "sleep_clk", .name = "sleep_clk" },
432 static const struct parent_map gcc_xo_gpll0_gpll1a_gpll6_sleep_map[] = {
440 static const struct clk_parent_data gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data[] = {
442 { .hw = &gpll0_vote.hw },
443 { .hw = &gpll1_vote.hw },
444 { .hw = &gpll6_vote.hw },
445 { .fw_name = "sleep_clk", .name = "sleep_clk" },
448 static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = {
454 static const struct clk_parent_data gcc_xo_gpll0_gpll1a_parent_data[] = {
456 { .hw = &gpll0_vote.hw },
457 { .hw = &gpll1_vote.hw },
460 static const struct parent_map gcc_xo_dsibyte_map[] = {
462 { P_DSI0_PHYPLL_BYTE, 2 },
465 static const struct clk_parent_data gcc_xo_dsibyte_parent_data[] = {
467 { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
470 static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = {
473 { P_DSI0_PHYPLL_BYTE, 1 },
476 static const struct clk_parent_data gcc_xo_gpll0a_dsibyte_parent_data[] = {
478 { .hw = &gpll0_vote.hw },
479 { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
482 static const struct parent_map gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_map[] = {
485 { P_DSI0_PHYPLL_DSI, 2 },
491 static const struct clk_parent_data gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data[] = {
493 { .hw = &gpll1_vote.hw },
494 { .fw_name = "dsi0pll", .name = "dsi0pll" },
495 { .hw = &gpll6_vote.hw },
496 { .hw = &gpll3_vote.hw },
497 { .hw = &gpll0_vote.hw },
500 static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = {
503 { P_DSI0_PHYPLL_DSI, 1 },
506 static const struct clk_parent_data gcc_xo_gpll0a_dsiphy_parent_data[] = {
508 { .hw = &gpll0_vote.hw },
509 { .fw_name = "dsi0pll", .name = "dsi0pll" },
512 static const struct parent_map gcc_xo_gpll0_gpll5a_gpll6_bimc_map[] = {
520 static const struct clk_parent_data gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data[] = {
522 { .hw = &gpll0_vote.hw },
523 { .hw = &gpll5_vote.hw },
524 { .hw = &gpll6_vote.hw },
525 { .hw = &bimc_pll_vote.hw },
528 static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = {
535 static const struct clk_parent_data gcc_xo_gpll0_gpll1_sleep_parent_data[] = {
537 { .hw = &gpll0_vote.hw },
538 { .hw = &gpll1_vote.hw },
539 { .fw_name = "sleep_clk", .name = "sleep_clk" },
542 static const struct parent_map gcc_xo_gpll1_epi2s_emclk_sleep_map[] = {
545 { P_EXT_PRI_I2S, 2 },
550 static const struct clk_parent_data gcc_xo_gpll1_epi2s_emclk_sleep_parent_data[] = {
552 { .hw = &gpll0_vote.hw },
553 { .fw_name = "ext_pri_i2s", .name = "ext_pri_i2s" },
554 { .fw_name = "ext_mclk", .name = "ext_mclk" },
555 { .fw_name = "sleep_clk", .name = "sleep_clk" },
558 static const struct parent_map gcc_xo_gpll1_esi2s_emclk_sleep_map[] = {
561 { P_EXT_SEC_I2S, 2 },
566 static const struct clk_parent_data gcc_xo_gpll1_esi2s_emclk_sleep_parent_data[] = {
568 { .hw = &gpll1_vote.hw },
569 { .fw_name = "ext_sec_i2s", .name = "ext_sec_i2s" },
570 { .fw_name = "ext_mclk", .name = "ext_mclk" },
571 { .fw_name = "sleep_clk", .name = "sleep_clk" },
574 static const struct parent_map gcc_xo_sleep_map[] = {
579 static const struct clk_parent_data gcc_xo_sleep_parent_data[] = {
581 { .fw_name = "sleep_clk", .name = "sleep_clk" },
584 static const struct parent_map gcc_xo_gpll1_emclk_sleep_map[] = {
591 static const struct clk_parent_data gcc_xo_gpll1_emclk_sleep_parent_data[] = {
593 { .hw = &gpll1_vote.hw },
594 { .fw_name = "ext_mclk", .name = "ext_mclk" },
595 { .fw_name = "sleep_clk", .name = "sleep_clk" },
598 static const struct clk_parent_data gcc_xo_gpll6_gpll0_parent_data[] = {
600 { .hw = &gpll6_vote.hw },
601 { .hw = &gpll0_vote.hw },
604 static const struct clk_parent_data gcc_xo_gpll6_gpll0a_parent_data[] = {
606 { .hw = &gpll6_vote.hw },
607 { .hw = &gpll0_vote.hw },
610 static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
613 .parent_map = gcc_xo_gpll0_map,
614 .clkr.hw.init = &(struct clk_init_data){
615 .name = "pcnoc_bfdcd_clk_src",
616 .parent_data = gcc_xo_gpll0_parent_data,
618 .ops = &clk_rcg2_ops,
622 static struct clk_rcg2 system_noc_bfdcd_clk_src = {
625 .parent_map = gcc_xo_gpll0_gpll6a_map,
626 .clkr.hw.init = &(struct clk_init_data){
627 .name = "system_noc_bfdcd_clk_src",
628 .parent_data = gcc_xo_gpll0_gpll6a_parent_data,
630 .ops = &clk_rcg2_ops,
634 static struct clk_rcg2 bimc_ddr_clk_src = {
637 .parent_map = gcc_xo_gpll0_bimc_map,
638 .clkr.hw.init = &(struct clk_init_data){
639 .name = "bimc_ddr_clk_src",
640 .parent_data = gcc_xo_gpll0_bimc_parent_data,
642 .ops = &clk_rcg2_ops,
643 .flags = CLK_GET_RATE_NOCACHE,
647 static struct clk_rcg2 system_mm_noc_bfdcd_clk_src = {
650 .parent_map = gcc_xo_gpll0_gpll6a_map,
651 .clkr.hw.init = &(struct clk_init_data){
652 .name = "system_mm_noc_bfdcd_clk_src",
653 .parent_data = gcc_xo_gpll0_gpll6a_parent_data,
655 .ops = &clk_rcg2_ops,
659 static const struct freq_tbl ftbl_gcc_camss_ahb_clk[] = {
660 F(40000000, P_GPLL0, 10, 1, 2),
661 F(80000000, P_GPLL0, 10, 0, 0),
665 static struct clk_rcg2 camss_ahb_clk_src = {
669 .parent_map = gcc_xo_gpll0_map,
670 .freq_tbl = ftbl_gcc_camss_ahb_clk,
671 .clkr.hw.init = &(struct clk_init_data){
672 .name = "camss_ahb_clk_src",
673 .parent_data = gcc_xo_gpll0_parent_data,
675 .ops = &clk_rcg2_ops,
679 static const struct freq_tbl ftbl_apss_ahb_clk[] = {
680 F(19200000, P_XO, 1, 0, 0),
681 F(50000000, P_GPLL0, 16, 0, 0),
682 F(100000000, P_GPLL0, 8, 0, 0),
683 F(133330000, P_GPLL0, 6, 0, 0),
687 static struct clk_rcg2 apss_ahb_clk_src = {
690 .parent_map = gcc_xo_gpll0_map,
691 .freq_tbl = ftbl_apss_ahb_clk,
692 .clkr.hw.init = &(struct clk_init_data){
693 .name = "apss_ahb_clk_src",
694 .parent_data = gcc_xo_gpll0_parent_data,
696 .ops = &clk_rcg2_ops,
700 static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = {
701 F(100000000, P_GPLL0, 8, 0, 0),
702 F(200000000, P_GPLL0, 4, 0, 0),
706 static struct clk_rcg2 csi0_clk_src = {
709 .parent_map = gcc_xo_gpll0_map,
710 .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
711 .clkr.hw.init = &(struct clk_init_data){
712 .name = "csi0_clk_src",
713 .parent_data = gcc_xo_gpll0_parent_data,
715 .ops = &clk_rcg2_ops,
719 static struct clk_rcg2 csi1_clk_src = {
722 .parent_map = gcc_xo_gpll0_map,
723 .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
724 .clkr.hw.init = &(struct clk_init_data){
725 .name = "csi1_clk_src",
726 .parent_data = gcc_xo_gpll0_parent_data,
728 .ops = &clk_rcg2_ops,
732 static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
733 F(19200000, P_XO, 1, 0, 0),
734 F(50000000, P_GPLL0, 16, 0, 0),
735 F(80000000, P_GPLL0, 10, 0, 0),
736 F(100000000, P_GPLL0, 8, 0, 0),
737 F(160000000, P_GPLL0, 5, 0, 0),
738 F(200000000, P_GPLL0, 4, 0, 0),
739 F(220000000, P_GPLL3, 5, 0, 0),
740 F(266670000, P_GPLL0, 3, 0, 0),
741 F(310000000, P_GPLL2_AUX, 3, 0, 0),
742 F(400000000, P_GPLL0, 2, 0, 0),
743 F(465000000, P_GPLL2_AUX, 2, 0, 0),
744 F(550000000, P_GPLL3, 2, 0, 0),
748 static struct clk_rcg2 gfx3d_clk_src = {
751 .parent_map = gcc_xo_gpll0_gpll2a_gpll3_gpll6a_map,
752 .freq_tbl = ftbl_gcc_oxili_gfx3d_clk,
753 .clkr.hw.init = &(struct clk_init_data){
754 .name = "gfx3d_clk_src",
755 .parent_data = gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data,
757 .ops = &clk_rcg2_ops,
761 static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] = {
762 F(50000000, P_GPLL0, 16, 0, 0),
763 F(80000000, P_GPLL0, 10, 0, 0),
764 F(100000000, P_GPLL0, 8, 0, 0),
765 F(160000000, P_GPLL0, 5, 0, 0),
766 F(177780000, P_GPLL0, 4.5, 0, 0),
767 F(200000000, P_GPLL0, 4, 0, 0),
768 F(266670000, P_GPLL0, 3, 0, 0),
769 F(320000000, P_GPLL0, 2.5, 0, 0),
770 F(400000000, P_GPLL0, 2, 0, 0),
771 F(465000000, P_GPLL2, 2, 0, 0),
772 F(480000000, P_GPLL4, 2.5, 0, 0),
773 F(600000000, P_GPLL4, 2, 0, 0),
777 static struct clk_rcg2 vfe0_clk_src = {
780 .parent_map = gcc_xo_gpll0_gpll2_gpll4_map,
781 .freq_tbl = ftbl_gcc_camss_vfe0_clk,
782 .clkr.hw.init = &(struct clk_init_data){
783 .name = "vfe0_clk_src",
784 .parent_data = gcc_xo_gpll0_gpll2_gpll4_parent_data,
786 .ops = &clk_rcg2_ops,
790 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
791 F(19200000, P_XO, 1, 0, 0),
792 F(50000000, P_GPLL0, 16, 0, 0),
796 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
799 .parent_map = gcc_xo_gpll0_map,
800 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
801 .clkr.hw.init = &(struct clk_init_data){
802 .name = "blsp1_qup1_i2c_apps_clk_src",
803 .parent_data = gcc_xo_gpll0_parent_data,
805 .ops = &clk_rcg2_ops,
809 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
810 F(960000, P_XO, 10, 1, 2),
811 F(4800000, P_XO, 4, 0, 0),
812 F(9600000, P_XO, 2, 0, 0),
813 F(16000000, P_GPLL0, 10, 1, 5),
814 F(19200000, P_XO, 1, 0, 0),
815 F(25000000, P_GPLL0, 16, 1, 2),
816 F(50000000, P_GPLL0, 16, 0, 0),
820 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
824 .parent_map = gcc_xo_gpll0_map,
825 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
826 .clkr.hw.init = &(struct clk_init_data){
827 .name = "blsp1_qup1_spi_apps_clk_src",
828 .parent_data = gcc_xo_gpll0_parent_data,
830 .ops = &clk_rcg2_ops,
834 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
837 .parent_map = gcc_xo_gpll0_map,
838 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
839 .clkr.hw.init = &(struct clk_init_data){
840 .name = "blsp1_qup2_i2c_apps_clk_src",
841 .parent_data = gcc_xo_gpll0_parent_data,
843 .ops = &clk_rcg2_ops,
847 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
851 .parent_map = gcc_xo_gpll0_map,
852 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
853 .clkr.hw.init = &(struct clk_init_data){
854 .name = "blsp1_qup2_spi_apps_clk_src",
855 .parent_data = gcc_xo_gpll0_parent_data,
857 .ops = &clk_rcg2_ops,
861 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
864 .parent_map = gcc_xo_gpll0_map,
865 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
866 .clkr.hw.init = &(struct clk_init_data){
867 .name = "blsp1_qup3_i2c_apps_clk_src",
868 .parent_data = gcc_xo_gpll0_parent_data,
870 .ops = &clk_rcg2_ops,
874 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
878 .parent_map = gcc_xo_gpll0_map,
879 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
880 .clkr.hw.init = &(struct clk_init_data){
881 .name = "blsp1_qup3_spi_apps_clk_src",
882 .parent_data = gcc_xo_gpll0_parent_data,
884 .ops = &clk_rcg2_ops,
888 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
891 .parent_map = gcc_xo_gpll0_map,
892 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
893 .clkr.hw.init = &(struct clk_init_data){
894 .name = "blsp1_qup4_i2c_apps_clk_src",
895 .parent_data = gcc_xo_gpll0_parent_data,
897 .ops = &clk_rcg2_ops,
901 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
905 .parent_map = gcc_xo_gpll0_map,
906 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
907 .clkr.hw.init = &(struct clk_init_data){
908 .name = "blsp1_qup4_spi_apps_clk_src",
909 .parent_data = gcc_xo_gpll0_parent_data,
911 .ops = &clk_rcg2_ops,
915 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
918 .parent_map = gcc_xo_gpll0_map,
919 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
920 .clkr.hw.init = &(struct clk_init_data){
921 .name = "blsp1_qup5_i2c_apps_clk_src",
922 .parent_data = gcc_xo_gpll0_parent_data,
924 .ops = &clk_rcg2_ops,
928 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
932 .parent_map = gcc_xo_gpll0_map,
933 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
934 .clkr.hw.init = &(struct clk_init_data){
935 .name = "blsp1_qup5_spi_apps_clk_src",
936 .parent_data = gcc_xo_gpll0_parent_data,
938 .ops = &clk_rcg2_ops,
942 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
945 .parent_map = gcc_xo_gpll0_map,
946 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
947 .clkr.hw.init = &(struct clk_init_data){
948 .name = "blsp1_qup6_i2c_apps_clk_src",
949 .parent_data = gcc_xo_gpll0_parent_data,
951 .ops = &clk_rcg2_ops,
955 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
959 .parent_map = gcc_xo_gpll0_map,
960 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
961 .clkr.hw.init = &(struct clk_init_data){
962 .name = "blsp1_qup6_spi_apps_clk_src",
963 .parent_data = gcc_xo_gpll0_parent_data,
965 .ops = &clk_rcg2_ops,
969 static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
970 F(3686400, P_GPLL0, 1, 72, 15625),
971 F(7372800, P_GPLL0, 1, 144, 15625),
972 F(14745600, P_GPLL0, 1, 288, 15625),
973 F(16000000, P_GPLL0, 10, 1, 5),
974 F(19200000, P_XO, 1, 0, 0),
975 F(24000000, P_GPLL0, 1, 3, 100),
976 F(25000000, P_GPLL0, 16, 1, 2),
977 F(32000000, P_GPLL0, 1, 1, 25),
978 F(40000000, P_GPLL0, 1, 1, 20),
979 F(46400000, P_GPLL0, 1, 29, 500),
980 F(48000000, P_GPLL0, 1, 3, 50),
981 F(51200000, P_GPLL0, 1, 8, 125),
982 F(56000000, P_GPLL0, 1, 7, 100),
983 F(58982400, P_GPLL0, 1, 1152, 15625),
984 F(60000000, P_GPLL0, 1, 3, 40),
988 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
992 .parent_map = gcc_xo_gpll0_map,
993 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
994 .clkr.hw.init = &(struct clk_init_data){
995 .name = "blsp1_uart1_apps_clk_src",
996 .parent_data = gcc_xo_gpll0_parent_data,
998 .ops = &clk_rcg2_ops,
1002 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
1003 .cmd_rcgr = 0x03034,
1006 .parent_map = gcc_xo_gpll0_map,
1007 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
1008 .clkr.hw.init = &(struct clk_init_data){
1009 .name = "blsp1_uart2_apps_clk_src",
1010 .parent_data = gcc_xo_gpll0_parent_data,
1012 .ops = &clk_rcg2_ops,
1016 static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = {
1017 F(19200000, P_XO, 1, 0, 0),
1018 F(37500000, P_GPLL0, 1, 3, 64),
1022 static struct clk_rcg2 cci_clk_src = {
1023 .cmd_rcgr = 0x51000,
1026 .parent_map = gcc_xo_gpll0a_map,
1027 .freq_tbl = ftbl_gcc_camss_cci_clk,
1028 .clkr.hw.init = &(struct clk_init_data){
1029 .name = "cci_clk_src",
1030 .parent_data = gcc_xo_gpll0a_parent_data,
1032 .ops = &clk_rcg2_ops,
1036 static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = {
1037 F(100000000, P_GPLL0, 8, 0, 0),
1038 F(200000000, P_GPLL0, 4, 0, 0),
1042 static struct clk_rcg2 camss_gp0_clk_src = {
1043 .cmd_rcgr = 0x54000,
1046 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
1047 .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
1048 .clkr.hw.init = &(struct clk_init_data){
1049 .name = "camss_gp0_clk_src",
1050 .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
1052 .ops = &clk_rcg2_ops,
1056 static struct clk_rcg2 camss_gp1_clk_src = {
1057 .cmd_rcgr = 0x55000,
1060 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
1061 .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
1062 .clkr.hw.init = &(struct clk_init_data){
1063 .name = "camss_gp1_clk_src",
1064 .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
1066 .ops = &clk_rcg2_ops,
1070 static const struct freq_tbl ftbl_gcc_camss_jpeg0_clk[] = {
1071 F(133330000, P_GPLL0, 6, 0, 0),
1072 F(266670000, P_GPLL0, 3, 0, 0),
1073 F(320000000, P_GPLL0, 2.5, 0, 0),
1077 static struct clk_rcg2 jpeg0_clk_src = {
1078 .cmd_rcgr = 0x57000,
1080 .parent_map = gcc_xo_gpll0_map,
1081 .freq_tbl = ftbl_gcc_camss_jpeg0_clk,
1082 .clkr.hw.init = &(struct clk_init_data){
1083 .name = "jpeg0_clk_src",
1084 .parent_data = gcc_xo_gpll0_parent_data,
1086 .ops = &clk_rcg2_ops,
1090 static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = {
1091 F(24000000, P_GPLL0, 1, 1, 45),
1092 F(66670000, P_GPLL0, 12, 0, 0),
1096 static struct clk_rcg2 mclk0_clk_src = {
1097 .cmd_rcgr = 0x52000,
1100 .parent_map = gcc_xo_gpll0_gpll1a_gpll6_sleep_map,
1101 .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
1102 .clkr.hw.init = &(struct clk_init_data){
1103 .name = "mclk0_clk_src",
1104 .parent_data = gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data,
1106 .ops = &clk_rcg2_ops,
1110 static struct clk_rcg2 mclk1_clk_src = {
1111 .cmd_rcgr = 0x53000,
1114 .parent_map = gcc_xo_gpll0_gpll1a_gpll6_sleep_map,
1115 .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
1116 .clkr.hw.init = &(struct clk_init_data){
1117 .name = "mclk1_clk_src",
1118 .parent_data = gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data,
1120 .ops = &clk_rcg2_ops,
1124 static const struct freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = {
1125 F(100000000, P_GPLL0, 8, 0, 0),
1126 F(200000000, P_GPLL0, 4, 0, 0),
1130 static struct clk_rcg2 csi0phytimer_clk_src = {
1131 .cmd_rcgr = 0x4e000,
1133 .parent_map = gcc_xo_gpll0_gpll1a_map,
1134 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
1135 .clkr.hw.init = &(struct clk_init_data){
1136 .name = "csi0phytimer_clk_src",
1137 .parent_data = gcc_xo_gpll0_gpll1a_parent_data,
1139 .ops = &clk_rcg2_ops,
1143 static struct clk_rcg2 csi1phytimer_clk_src = {
1144 .cmd_rcgr = 0x4f000,
1146 .parent_map = gcc_xo_gpll0_gpll1a_map,
1147 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
1148 .clkr.hw.init = &(struct clk_init_data){
1149 .name = "csi1phytimer_clk_src",
1150 .parent_data = gcc_xo_gpll0_gpll1a_parent_data,
1152 .ops = &clk_rcg2_ops,
1156 static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = {
1157 F(160000000, P_GPLL0, 5, 0, 0),
1158 F(200000000, P_GPLL0, 4, 0, 0),
1159 F(228570000, P_GPLL0, 3.5, 0, 0),
1160 F(266670000, P_GPLL0, 3, 0, 0),
1161 F(320000000, P_GPLL0, 2.5, 0, 0),
1162 F(465000000, P_GPLL2, 2, 0, 0),
1166 static struct clk_rcg2 cpp_clk_src = {
1167 .cmd_rcgr = 0x58018,
1169 .parent_map = gcc_xo_gpll0_gpll2_map,
1170 .freq_tbl = ftbl_gcc_camss_cpp_clk,
1171 .clkr.hw.init = &(struct clk_init_data){
1172 .name = "cpp_clk_src",
1173 .parent_data = gcc_xo_gpll0_gpll2_parent_data,
1175 .ops = &clk_rcg2_ops,
1179 static const struct freq_tbl ftbl_gcc_crypto_clk[] = {
1180 F(50000000, P_GPLL0, 16, 0, 0),
1181 F(80000000, P_GPLL0, 10, 0, 0),
1182 F(100000000, P_GPLL0, 8, 0, 0),
1183 F(160000000, P_GPLL0, 5, 0, 0),
1187 /* This is not in the documentation but is in the downstream driver */
1188 static struct clk_rcg2 crypto_clk_src = {
1189 .cmd_rcgr = 0x16004,
1191 .parent_map = gcc_xo_gpll0_map,
1192 .freq_tbl = ftbl_gcc_crypto_clk,
1193 .clkr.hw.init = &(struct clk_init_data){
1194 .name = "crypto_clk_src",
1195 .parent_data = gcc_xo_gpll0_parent_data,
1197 .ops = &clk_rcg2_ops,
1201 static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = {
1202 F(19200000, P_XO, 1, 0, 0),
1206 static struct clk_rcg2 gp1_clk_src = {
1207 .cmd_rcgr = 0x08004,
1210 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
1211 .freq_tbl = ftbl_gcc_gp1_3_clk,
1212 .clkr.hw.init = &(struct clk_init_data){
1213 .name = "gp1_clk_src",
1214 .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
1216 .ops = &clk_rcg2_ops,
1220 static struct clk_rcg2 gp2_clk_src = {
1221 .cmd_rcgr = 0x09004,
1224 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
1225 .freq_tbl = ftbl_gcc_gp1_3_clk,
1226 .clkr.hw.init = &(struct clk_init_data){
1227 .name = "gp2_clk_src",
1228 .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
1230 .ops = &clk_rcg2_ops,
1234 static struct clk_rcg2 gp3_clk_src = {
1235 .cmd_rcgr = 0x0a004,
1238 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
1239 .freq_tbl = ftbl_gcc_gp1_3_clk,
1240 .clkr.hw.init = &(struct clk_init_data){
1241 .name = "gp3_clk_src",
1242 .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
1244 .ops = &clk_rcg2_ops,
1248 static struct clk_rcg2 byte0_clk_src = {
1249 .cmd_rcgr = 0x4d044,
1251 .parent_map = gcc_xo_gpll0a_dsibyte_map,
1252 .clkr.hw.init = &(struct clk_init_data){
1253 .name = "byte0_clk_src",
1254 .parent_data = gcc_xo_gpll0a_dsibyte_parent_data,
1256 .ops = &clk_byte2_ops,
1257 .flags = CLK_SET_RATE_PARENT,
1261 static struct clk_rcg2 byte1_clk_src = {
1262 .cmd_rcgr = 0x4d0b0,
1264 .parent_map = gcc_xo_gpll0a_dsibyte_map,
1265 .clkr.hw.init = &(struct clk_init_data){
1266 .name = "byte1_clk_src",
1267 .parent_data = gcc_xo_gpll0a_dsibyte_parent_data,
1269 .ops = &clk_byte2_ops,
1270 .flags = CLK_SET_RATE_PARENT,
1274 static const struct freq_tbl ftbl_gcc_mdss_esc_clk[] = {
1275 F(19200000, P_XO, 1, 0, 0),
1279 static struct clk_rcg2 esc0_clk_src = {
1280 .cmd_rcgr = 0x4d060,
1282 .parent_map = gcc_xo_dsibyte_map,
1283 .freq_tbl = ftbl_gcc_mdss_esc_clk,
1284 .clkr.hw.init = &(struct clk_init_data){
1285 .name = "esc0_clk_src",
1286 .parent_data = gcc_xo_dsibyte_parent_data,
1288 .ops = &clk_rcg2_ops,
1292 static struct clk_rcg2 esc1_clk_src = {
1293 .cmd_rcgr = 0x4d0a8,
1295 .parent_map = gcc_xo_dsibyte_map,
1296 .freq_tbl = ftbl_gcc_mdss_esc_clk,
1297 .clkr.hw.init = &(struct clk_init_data){
1298 .name = "esc1_clk_src",
1299 .parent_data = gcc_xo_dsibyte_parent_data,
1301 .ops = &clk_rcg2_ops,
1305 static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
1306 F(50000000, P_GPLL0_AUX, 16, 0, 0),
1307 F(80000000, P_GPLL0_AUX, 10, 0, 0),
1308 F(100000000, P_GPLL0_AUX, 8, 0, 0),
1309 F(145500000, P_GPLL0_AUX, 5.5, 0, 0),
1310 F(153600000, P_GPLL0, 4, 0, 0),
1311 F(160000000, P_GPLL0_AUX, 5, 0, 0),
1312 F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
1313 F(200000000, P_GPLL0_AUX, 4, 0, 0),
1314 F(266670000, P_GPLL0_AUX, 3, 0, 0),
1315 F(307200000, P_GPLL1, 2, 0, 0),
1316 F(366670000, P_GPLL3_AUX, 3, 0, 0),
1320 static struct clk_rcg2 mdp_clk_src = {
1321 .cmd_rcgr = 0x4d014,
1323 .parent_map = gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_map,
1324 .freq_tbl = ftbl_gcc_mdss_mdp_clk,
1325 .clkr.hw.init = &(struct clk_init_data){
1326 .name = "mdp_clk_src",
1327 .parent_data = gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data,
1329 .ops = &clk_rcg2_ops,
1333 static struct clk_rcg2 pclk0_clk_src = {
1334 .cmd_rcgr = 0x4d000,
1337 .parent_map = gcc_xo_gpll0a_dsiphy_map,
1338 .clkr.hw.init = &(struct clk_init_data){
1339 .name = "pclk0_clk_src",
1340 .parent_data = gcc_xo_gpll0a_dsiphy_parent_data,
1342 .ops = &clk_pixel_ops,
1343 .flags = CLK_SET_RATE_PARENT,
1347 static struct clk_rcg2 pclk1_clk_src = {
1348 .cmd_rcgr = 0x4d0b8,
1351 .parent_map = gcc_xo_gpll0a_dsiphy_map,
1352 .clkr.hw.init = &(struct clk_init_data){
1353 .name = "pclk1_clk_src",
1354 .parent_data = gcc_xo_gpll0a_dsiphy_parent_data,
1356 .ops = &clk_pixel_ops,
1357 .flags = CLK_SET_RATE_PARENT,
1361 static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
1362 F(19200000, P_XO, 1, 0, 0),
1366 static struct clk_rcg2 vsync_clk_src = {
1367 .cmd_rcgr = 0x4d02c,
1369 .parent_map = gcc_xo_gpll0a_map,
1370 .freq_tbl = ftbl_gcc_mdss_vsync_clk,
1371 .clkr.hw.init = &(struct clk_init_data){
1372 .name = "vsync_clk_src",
1373 .parent_data = gcc_xo_gpll0a_parent_data,
1375 .ops = &clk_rcg2_ops,
1379 static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
1380 F(64000000, P_GPLL0, 12.5, 0, 0),
1384 /* This is not in the documentation but is in the downstream driver */
1385 static struct clk_rcg2 pdm2_clk_src = {
1386 .cmd_rcgr = 0x44010,
1388 .parent_map = gcc_xo_gpll0_map,
1389 .freq_tbl = ftbl_gcc_pdm2_clk,
1390 .clkr.hw.init = &(struct clk_init_data){
1391 .name = "pdm2_clk_src",
1392 .parent_data = gcc_xo_gpll0_parent_data,
1394 .ops = &clk_rcg2_ops,
1398 static const struct freq_tbl ftbl_gcc_sdcc_apps_clk[] = {
1399 F(144000, P_XO, 16, 3, 25),
1400 F(400000, P_XO, 12, 1, 4),
1401 F(20000000, P_GPLL0, 10, 1, 4),
1402 F(25000000, P_GPLL0, 16, 1, 2),
1403 F(50000000, P_GPLL0, 16, 0, 0),
1404 F(100000000, P_GPLL0, 8, 0, 0),
1405 F(177770000, P_GPLL0, 4.5, 0, 0),
1406 F(200000000, P_GPLL0, 4, 0, 0),
1410 static struct clk_rcg2 sdcc1_apps_clk_src = {
1411 .cmd_rcgr = 0x42004,
1414 .parent_map = gcc_xo_gpll0_map,
1415 .freq_tbl = ftbl_gcc_sdcc_apps_clk,
1416 .clkr.hw.init = &(struct clk_init_data){
1417 .name = "sdcc1_apps_clk_src",
1418 .parent_data = gcc_xo_gpll0_parent_data,
1420 .ops = &clk_rcg2_floor_ops,
1424 static struct clk_rcg2 sdcc2_apps_clk_src = {
1425 .cmd_rcgr = 0x43004,
1428 .parent_map = gcc_xo_gpll0_map,
1429 .freq_tbl = ftbl_gcc_sdcc_apps_clk,
1430 .clkr.hw.init = &(struct clk_init_data){
1431 .name = "sdcc2_apps_clk_src",
1432 .parent_data = gcc_xo_gpll0_parent_data,
1434 .ops = &clk_rcg2_floor_ops,
1438 static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = {
1439 F(154285000, P_GPLL6, 7, 0, 0),
1440 F(320000000, P_GPLL0, 2.5, 0, 0),
1441 F(400000000, P_GPLL0, 2, 0, 0),
1445 static struct clk_rcg2 apss_tcu_clk_src = {
1446 .cmd_rcgr = 0x1207c,
1448 .parent_map = gcc_xo_gpll0_gpll5a_gpll6_bimc_map,
1449 .freq_tbl = ftbl_gcc_apss_tcu_clk,
1450 .clkr.hw.init = &(struct clk_init_data){
1451 .name = "apss_tcu_clk_src",
1452 .parent_data = gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data,
1454 .ops = &clk_rcg2_ops,
1458 static const struct freq_tbl ftbl_gcc_bimc_gpu_clk[] = {
1459 F(19200000, P_XO, 1, 0, 0),
1460 F(100000000, P_GPLL0, 8, 0, 0),
1461 F(200000000, P_GPLL0, 4, 0, 0),
1462 F(266500000, P_BIMC, 4, 0, 0),
1463 F(400000000, P_GPLL0, 2, 0, 0),
1464 F(533000000, P_BIMC, 2, 0, 0),
1468 static struct clk_rcg2 bimc_gpu_clk_src = {
1469 .cmd_rcgr = 0x31028,
1471 .parent_map = gcc_xo_gpll0_gpll5a_gpll6_bimc_map,
1472 .freq_tbl = ftbl_gcc_bimc_gpu_clk,
1473 .clkr.hw.init = &(struct clk_init_data){
1474 .name = "bimc_gpu_clk_src",
1475 .parent_data = gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data,
1477 .flags = CLK_GET_RATE_NOCACHE,
1478 .ops = &clk_rcg2_ops,
1482 static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
1483 F(57140000, P_GPLL0, 14, 0, 0),
1484 F(80000000, P_GPLL0, 10, 0, 0),
1485 F(100000000, P_GPLL0, 8, 0, 0),
1489 static struct clk_rcg2 usb_hs_system_clk_src = {
1490 .cmd_rcgr = 0x41010,
1492 .parent_map = gcc_xo_gpll0_map,
1493 .freq_tbl = ftbl_gcc_usb_hs_system_clk,
1494 .clkr.hw.init = &(struct clk_init_data){
1495 .name = "usb_hs_system_clk_src",
1496 .parent_data = gcc_xo_gpll0_parent_data,
1498 .ops = &clk_rcg2_ops,
1502 static const struct freq_tbl ftbl_gcc_usb_fs_system_clk[] = {
1503 F(64000000, P_GPLL0, 12.5, 0, 0),
1507 static struct clk_rcg2 usb_fs_system_clk_src = {
1508 .cmd_rcgr = 0x3f010,
1510 .parent_map = gcc_xo_gpll0_map,
1511 .freq_tbl = ftbl_gcc_usb_fs_system_clk,
1512 .clkr.hw.init = &(struct clk_init_data){
1513 .name = "usb_fs_system_clk_src",
1514 .parent_data = gcc_xo_gpll6_gpll0_parent_data,
1516 .ops = &clk_rcg2_ops,
1520 static const struct freq_tbl ftbl_gcc_usb_fs_ic_clk[] = {
1521 F(60000000, P_GPLL6, 1, 1, 18),
1525 static struct clk_rcg2 usb_fs_ic_clk_src = {
1526 .cmd_rcgr = 0x3f034,
1528 .parent_map = gcc_xo_gpll0_map,
1529 .freq_tbl = ftbl_gcc_usb_fs_ic_clk,
1530 .clkr.hw.init = &(struct clk_init_data){
1531 .name = "usb_fs_ic_clk_src",
1532 .parent_data = gcc_xo_gpll6_gpll0a_parent_data,
1534 .ops = &clk_rcg2_ops,
1538 static const struct freq_tbl ftbl_gcc_ultaudio_ahb_clk[] = {
1539 F(3200000, P_XO, 6, 0, 0),
1540 F(6400000, P_XO, 3, 0, 0),
1541 F(9600000, P_XO, 2, 0, 0),
1542 F(19200000, P_XO, 1, 0, 0),
1543 F(40000000, P_GPLL0, 10, 1, 2),
1544 F(66670000, P_GPLL0, 12, 0, 0),
1545 F(80000000, P_GPLL0, 10, 0, 0),
1546 F(100000000, P_GPLL0, 8, 0, 0),
1550 static struct clk_rcg2 ultaudio_ahbfabric_clk_src = {
1551 .cmd_rcgr = 0x1c010,
1554 .parent_map = gcc_xo_gpll0_gpll1_sleep_map,
1555 .freq_tbl = ftbl_gcc_ultaudio_ahb_clk,
1556 .clkr.hw.init = &(struct clk_init_data){
1557 .name = "ultaudio_ahbfabric_clk_src",
1558 .parent_data = gcc_xo_gpll0_gpll1_sleep_parent_data,
1560 .ops = &clk_rcg2_ops,
1564 static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_clk = {
1565 .halt_reg = 0x1c028,
1567 .enable_reg = 0x1c028,
1568 .enable_mask = BIT(0),
1569 .hw.init = &(struct clk_init_data){
1570 .name = "gcc_ultaudio_ahbfabric_ixfabric_clk",
1571 .parent_data = &(const struct clk_parent_data){
1572 .hw = &ultaudio_ahbfabric_clk_src.clkr.hw,
1575 .flags = CLK_SET_RATE_PARENT,
1576 .ops = &clk_branch2_ops,
1581 static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk = {
1582 .halt_reg = 0x1c024,
1584 .enable_reg = 0x1c024,
1585 .enable_mask = BIT(0),
1586 .hw.init = &(struct clk_init_data){
1587 .name = "gcc_ultaudio_ahbfabric_ixfabric_lpm_clk",
1588 .parent_data = &(const struct clk_parent_data){
1589 .hw = &ultaudio_ahbfabric_clk_src.clkr.hw,
1592 .flags = CLK_SET_RATE_PARENT,
1593 .ops = &clk_branch2_ops,
1598 static const struct freq_tbl ftbl_gcc_ultaudio_lpaif_i2s_clk[] = {
1599 F(128000, P_XO, 10, 1, 15),
1600 F(256000, P_XO, 5, 1, 15),
1601 F(384000, P_XO, 5, 1, 10),
1602 F(512000, P_XO, 5, 2, 15),
1603 F(576000, P_XO, 5, 3, 20),
1604 F(705600, P_GPLL1, 16, 1, 80),
1605 F(768000, P_XO, 5, 1, 5),
1606 F(800000, P_XO, 5, 5, 24),
1607 F(1024000, P_XO, 5, 4, 15),
1608 F(1152000, P_XO, 1, 3, 50),
1609 F(1411200, P_GPLL1, 16, 1, 40),
1610 F(1536000, P_XO, 1, 2, 25),
1611 F(1600000, P_XO, 12, 0, 0),
1612 F(1728000, P_XO, 5, 9, 20),
1613 F(2048000, P_XO, 5, 8, 15),
1614 F(2304000, P_XO, 5, 3, 5),
1615 F(2400000, P_XO, 8, 0, 0),
1616 F(2822400, P_GPLL1, 16, 1, 20),
1617 F(3072000, P_XO, 5, 4, 5),
1618 F(4096000, P_GPLL1, 9, 2, 49),
1619 F(4800000, P_XO, 4, 0, 0),
1620 F(5644800, P_GPLL1, 16, 1, 10),
1621 F(6144000, P_GPLL1, 7, 1, 21),
1622 F(8192000, P_GPLL1, 9, 4, 49),
1623 F(9600000, P_XO, 2, 0, 0),
1624 F(11289600, P_GPLL1, 16, 1, 5),
1625 F(12288000, P_GPLL1, 7, 2, 21),
1629 static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = {
1630 .cmd_rcgr = 0x1c054,
1633 .parent_map = gcc_xo_gpll1_epi2s_emclk_sleep_map,
1634 .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1635 .clkr.hw.init = &(struct clk_init_data){
1636 .name = "ultaudio_lpaif_pri_i2s_clk_src",
1637 .parent_data = gcc_xo_gpll1_epi2s_emclk_sleep_parent_data,
1639 .ops = &clk_rcg2_ops,
1643 static struct clk_branch gcc_ultaudio_lpaif_pri_i2s_clk = {
1644 .halt_reg = 0x1c068,
1646 .enable_reg = 0x1c068,
1647 .enable_mask = BIT(0),
1648 .hw.init = &(struct clk_init_data){
1649 .name = "gcc_ultaudio_lpaif_pri_i2s_clk",
1650 .parent_data = &(const struct clk_parent_data){
1651 .hw = &ultaudio_lpaif_pri_i2s_clk_src.clkr.hw,
1654 .flags = CLK_SET_RATE_PARENT,
1655 .ops = &clk_branch2_ops,
1660 static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = {
1661 .cmd_rcgr = 0x1c06c,
1664 .parent_map = gcc_xo_gpll1_esi2s_emclk_sleep_map,
1665 .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1666 .clkr.hw.init = &(struct clk_init_data){
1667 .name = "ultaudio_lpaif_sec_i2s_clk_src",
1668 .parent_data = gcc_xo_gpll1_esi2s_emclk_sleep_parent_data,
1670 .ops = &clk_rcg2_ops,
1674 static struct clk_branch gcc_ultaudio_lpaif_sec_i2s_clk = {
1675 .halt_reg = 0x1c080,
1677 .enable_reg = 0x1c080,
1678 .enable_mask = BIT(0),
1679 .hw.init = &(struct clk_init_data){
1680 .name = "gcc_ultaudio_lpaif_sec_i2s_clk",
1681 .parent_data = &(const struct clk_parent_data){
1682 .hw = &ultaudio_lpaif_sec_i2s_clk_src.clkr.hw,
1685 .flags = CLK_SET_RATE_PARENT,
1686 .ops = &clk_branch2_ops,
1691 static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = {
1692 .cmd_rcgr = 0x1c084,
1695 .parent_map = gcc_xo_gpll1_emclk_sleep_map,
1696 .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1697 .clkr.hw.init = &(struct clk_init_data){
1698 .name = "ultaudio_lpaif_aux_i2s_clk_src",
1699 .parent_data = gcc_xo_gpll1_esi2s_emclk_sleep_parent_data,
1701 .ops = &clk_rcg2_ops,
1705 static struct clk_branch gcc_ultaudio_lpaif_aux_i2s_clk = {
1706 .halt_reg = 0x1c098,
1708 .enable_reg = 0x1c098,
1709 .enable_mask = BIT(0),
1710 .hw.init = &(struct clk_init_data){
1711 .name = "gcc_ultaudio_lpaif_aux_i2s_clk",
1712 .parent_data = &(const struct clk_parent_data){
1713 .hw = &ultaudio_lpaif_aux_i2s_clk_src.clkr.hw,
1716 .flags = CLK_SET_RATE_PARENT,
1717 .ops = &clk_branch2_ops,
1722 static const struct freq_tbl ftbl_gcc_ultaudio_xo_clk[] = {
1723 F(19200000, P_XO, 1, 0, 0),
1727 static struct clk_rcg2 ultaudio_xo_clk_src = {
1728 .cmd_rcgr = 0x1c034,
1730 .parent_map = gcc_xo_sleep_map,
1731 .freq_tbl = ftbl_gcc_ultaudio_xo_clk,
1732 .clkr.hw.init = &(struct clk_init_data){
1733 .name = "ultaudio_xo_clk_src",
1734 .parent_data = gcc_xo_sleep_parent_data,
1736 .ops = &clk_rcg2_ops,
1740 static struct clk_branch gcc_ultaudio_avsync_xo_clk = {
1741 .halt_reg = 0x1c04c,
1743 .enable_reg = 0x1c04c,
1744 .enable_mask = BIT(0),
1745 .hw.init = &(struct clk_init_data){
1746 .name = "gcc_ultaudio_avsync_xo_clk",
1747 .parent_data = &(const struct clk_parent_data){
1748 .hw = &ultaudio_xo_clk_src.clkr.hw,
1751 .flags = CLK_SET_RATE_PARENT,
1752 .ops = &clk_branch2_ops,
1757 static struct clk_branch gcc_ultaudio_stc_xo_clk = {
1758 .halt_reg = 0x1c050,
1760 .enable_reg = 0x1c050,
1761 .enable_mask = BIT(0),
1762 .hw.init = &(struct clk_init_data){
1763 .name = "gcc_ultaudio_stc_xo_clk",
1764 .parent_data = &(const struct clk_parent_data){
1765 .hw = &ultaudio_xo_clk_src.clkr.hw,
1768 .flags = CLK_SET_RATE_PARENT,
1769 .ops = &clk_branch2_ops,
1774 static const struct freq_tbl ftbl_codec_clk[] = {
1775 F(9600000, P_XO, 2, 0, 0),
1776 F(12288000, P_XO, 1, 16, 25),
1777 F(19200000, P_XO, 1, 0, 0),
1778 F(11289600, P_EXT_MCLK, 1, 0, 0),
1782 static struct clk_rcg2 codec_digcodec_clk_src = {
1783 .cmd_rcgr = 0x1c09c,
1786 .parent_map = gcc_xo_gpll1_emclk_sleep_map,
1787 .freq_tbl = ftbl_codec_clk,
1788 .clkr.hw.init = &(struct clk_init_data){
1789 .name = "codec_digcodec_clk_src",
1790 .parent_data = gcc_xo_gpll1_emclk_sleep_parent_data,
1792 .ops = &clk_rcg2_ops,
1796 static struct clk_branch gcc_codec_digcodec_clk = {
1797 .halt_reg = 0x1c0b0,
1799 .enable_reg = 0x1c0b0,
1800 .enable_mask = BIT(0),
1801 .hw.init = &(struct clk_init_data){
1802 .name = "gcc_ultaudio_codec_digcodec_clk",
1803 .parent_data = &(const struct clk_parent_data){
1804 .hw = &codec_digcodec_clk_src.clkr.hw,
1807 .flags = CLK_SET_RATE_PARENT,
1808 .ops = &clk_branch2_ops,
1813 static struct clk_branch gcc_ultaudio_pcnoc_mport_clk = {
1814 .halt_reg = 0x1c000,
1816 .enable_reg = 0x1c000,
1817 .enable_mask = BIT(0),
1818 .hw.init = &(struct clk_init_data){
1819 .name = "gcc_ultaudio_pcnoc_mport_clk",
1820 .parent_data = &(const struct clk_parent_data){
1821 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
1824 .ops = &clk_branch2_ops,
1829 static struct clk_branch gcc_ultaudio_pcnoc_sway_clk = {
1830 .halt_reg = 0x1c004,
1832 .enable_reg = 0x1c004,
1833 .enable_mask = BIT(0),
1834 .hw.init = &(struct clk_init_data){
1835 .name = "gcc_ultaudio_pcnoc_sway_clk",
1836 .parent_data = &(const struct clk_parent_data){
1837 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
1840 .ops = &clk_branch2_ops,
1845 static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = {
1846 F(133330000, P_GPLL0, 6, 0, 0),
1847 F(200000000, P_GPLL0, 4, 0, 0),
1848 F(266670000, P_GPLL0, 3, 0, 0),
1852 static struct clk_rcg2 vcodec0_clk_src = {
1853 .cmd_rcgr = 0x4C000,
1856 .parent_map = gcc_xo_gpll0_map,
1857 .freq_tbl = ftbl_gcc_venus0_vcodec0_clk,
1858 .clkr.hw.init = &(struct clk_init_data){
1859 .name = "vcodec0_clk_src",
1860 .parent_data = gcc_xo_gpll0_parent_data,
1862 .ops = &clk_rcg2_ops,
1866 static struct clk_branch gcc_blsp1_ahb_clk = {
1867 .halt_reg = 0x01008,
1868 .halt_check = BRANCH_HALT_VOTED,
1870 .enable_reg = 0x45004,
1871 .enable_mask = BIT(10),
1872 .hw.init = &(struct clk_init_data){
1873 .name = "gcc_blsp1_ahb_clk",
1874 .parent_data = &(const struct clk_parent_data){
1875 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
1878 .ops = &clk_branch2_ops,
1883 static struct clk_branch gcc_blsp1_sleep_clk = {
1884 .halt_reg = 0x01004,
1886 .enable_reg = 0x01004,
1887 .enable_mask = BIT(0),
1888 .hw.init = &(struct clk_init_data){
1889 .name = "gcc_blsp1_sleep_clk",
1890 .ops = &clk_branch2_ops,
1895 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1896 .halt_reg = 0x02008,
1898 .enable_reg = 0x02008,
1899 .enable_mask = BIT(0),
1900 .hw.init = &(struct clk_init_data){
1901 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1902 .parent_data = &(const struct clk_parent_data){
1903 .hw = &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
1906 .flags = CLK_SET_RATE_PARENT,
1907 .ops = &clk_branch2_ops,
1912 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1913 .halt_reg = 0x02004,
1915 .enable_reg = 0x02004,
1916 .enable_mask = BIT(0),
1917 .hw.init = &(struct clk_init_data){
1918 .name = "gcc_blsp1_qup1_spi_apps_clk",
1919 .parent_data = &(const struct clk_parent_data){
1920 .hw = &blsp1_qup1_spi_apps_clk_src.clkr.hw,
1923 .flags = CLK_SET_RATE_PARENT,
1924 .ops = &clk_branch2_ops,
1929 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1930 .halt_reg = 0x03010,
1932 .enable_reg = 0x03010,
1933 .enable_mask = BIT(0),
1934 .hw.init = &(struct clk_init_data){
1935 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1936 .parent_data = &(const struct clk_parent_data){
1937 .hw = &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
1940 .flags = CLK_SET_RATE_PARENT,
1941 .ops = &clk_branch2_ops,
1946 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1947 .halt_reg = 0x0300c,
1949 .enable_reg = 0x0300c,
1950 .enable_mask = BIT(0),
1951 .hw.init = &(struct clk_init_data){
1952 .name = "gcc_blsp1_qup2_spi_apps_clk",
1953 .parent_data = &(const struct clk_parent_data){
1954 .hw = &blsp1_qup2_spi_apps_clk_src.clkr.hw,
1957 .flags = CLK_SET_RATE_PARENT,
1958 .ops = &clk_branch2_ops,
1963 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1964 .halt_reg = 0x04020,
1966 .enable_reg = 0x04020,
1967 .enable_mask = BIT(0),
1968 .hw.init = &(struct clk_init_data){
1969 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1970 .parent_data = &(const struct clk_parent_data){
1971 .hw = &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
1974 .flags = CLK_SET_RATE_PARENT,
1975 .ops = &clk_branch2_ops,
1980 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1981 .halt_reg = 0x0401c,
1983 .enable_reg = 0x0401c,
1984 .enable_mask = BIT(0),
1985 .hw.init = &(struct clk_init_data){
1986 .name = "gcc_blsp1_qup3_spi_apps_clk",
1987 .parent_data = &(const struct clk_parent_data){
1988 .hw = &blsp1_qup3_spi_apps_clk_src.clkr.hw,
1991 .flags = CLK_SET_RATE_PARENT,
1992 .ops = &clk_branch2_ops,
1997 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1998 .halt_reg = 0x05020,
2000 .enable_reg = 0x05020,
2001 .enable_mask = BIT(0),
2002 .hw.init = &(struct clk_init_data){
2003 .name = "gcc_blsp1_qup4_i2c_apps_clk",
2004 .parent_data = &(const struct clk_parent_data){
2005 .hw = &blsp1_qup4_i2c_apps_clk_src.clkr.hw,
2008 .flags = CLK_SET_RATE_PARENT,
2009 .ops = &clk_branch2_ops,
2014 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
2015 .halt_reg = 0x0501c,
2017 .enable_reg = 0x0501c,
2018 .enable_mask = BIT(0),
2019 .hw.init = &(struct clk_init_data){
2020 .name = "gcc_blsp1_qup4_spi_apps_clk",
2021 .parent_data = &(const struct clk_parent_data){
2022 .hw = &blsp1_qup4_spi_apps_clk_src.clkr.hw,
2025 .flags = CLK_SET_RATE_PARENT,
2026 .ops = &clk_branch2_ops,
2031 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
2032 .halt_reg = 0x06020,
2034 .enable_reg = 0x06020,
2035 .enable_mask = BIT(0),
2036 .hw.init = &(struct clk_init_data){
2037 .name = "gcc_blsp1_qup5_i2c_apps_clk",
2038 .parent_data = &(const struct clk_parent_data){
2039 .hw = &blsp1_qup5_i2c_apps_clk_src.clkr.hw,
2042 .flags = CLK_SET_RATE_PARENT,
2043 .ops = &clk_branch2_ops,
2048 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
2049 .halt_reg = 0x0601c,
2051 .enable_reg = 0x0601c,
2052 .enable_mask = BIT(0),
2053 .hw.init = &(struct clk_init_data){
2054 .name = "gcc_blsp1_qup5_spi_apps_clk",
2055 .parent_data = &(const struct clk_parent_data){
2056 .hw = &blsp1_qup5_spi_apps_clk_src.clkr.hw,
2059 .flags = CLK_SET_RATE_PARENT,
2060 .ops = &clk_branch2_ops,
2065 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
2066 .halt_reg = 0x07020,
2068 .enable_reg = 0x07020,
2069 .enable_mask = BIT(0),
2070 .hw.init = &(struct clk_init_data){
2071 .name = "gcc_blsp1_qup6_i2c_apps_clk",
2072 .parent_data = &(const struct clk_parent_data){
2073 .hw = &blsp1_qup6_i2c_apps_clk_src.clkr.hw,
2076 .flags = CLK_SET_RATE_PARENT,
2077 .ops = &clk_branch2_ops,
2082 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
2083 .halt_reg = 0x0701c,
2085 .enable_reg = 0x0701c,
2086 .enable_mask = BIT(0),
2087 .hw.init = &(struct clk_init_data){
2088 .name = "gcc_blsp1_qup6_spi_apps_clk",
2089 .parent_data = &(const struct clk_parent_data){
2090 .hw = &blsp1_qup6_spi_apps_clk_src.clkr.hw,
2093 .flags = CLK_SET_RATE_PARENT,
2094 .ops = &clk_branch2_ops,
2099 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
2100 .halt_reg = 0x0203c,
2102 .enable_reg = 0x0203c,
2103 .enable_mask = BIT(0),
2104 .hw.init = &(struct clk_init_data){
2105 .name = "gcc_blsp1_uart1_apps_clk",
2106 .parent_data = &(const struct clk_parent_data){
2107 .hw = &blsp1_uart1_apps_clk_src.clkr.hw,
2110 .flags = CLK_SET_RATE_PARENT,
2111 .ops = &clk_branch2_ops,
2116 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
2117 .halt_reg = 0x0302c,
2119 .enable_reg = 0x0302c,
2120 .enable_mask = BIT(0),
2121 .hw.init = &(struct clk_init_data){
2122 .name = "gcc_blsp1_uart2_apps_clk",
2123 .parent_data = &(const struct clk_parent_data){
2124 .hw = &blsp1_uart2_apps_clk_src.clkr.hw,
2127 .flags = CLK_SET_RATE_PARENT,
2128 .ops = &clk_branch2_ops,
2133 static struct clk_branch gcc_boot_rom_ahb_clk = {
2134 .halt_reg = 0x1300c,
2135 .halt_check = BRANCH_HALT_VOTED,
2137 .enable_reg = 0x45004,
2138 .enable_mask = BIT(7),
2139 .hw.init = &(struct clk_init_data){
2140 .name = "gcc_boot_rom_ahb_clk",
2141 .parent_data = &(const struct clk_parent_data){
2142 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
2145 .ops = &clk_branch2_ops,
2150 static struct clk_branch gcc_camss_cci_ahb_clk = {
2151 .halt_reg = 0x5101c,
2153 .enable_reg = 0x5101c,
2154 .enable_mask = BIT(0),
2155 .hw.init = &(struct clk_init_data){
2156 .name = "gcc_camss_cci_ahb_clk",
2157 .parent_data = &(const struct clk_parent_data){
2158 .hw = &camss_ahb_clk_src.clkr.hw,
2161 .flags = CLK_SET_RATE_PARENT,
2162 .ops = &clk_branch2_ops,
2167 static struct clk_branch gcc_camss_cci_clk = {
2168 .halt_reg = 0x51018,
2170 .enable_reg = 0x51018,
2171 .enable_mask = BIT(0),
2172 .hw.init = &(struct clk_init_data){
2173 .name = "gcc_camss_cci_clk",
2174 .parent_data = &(const struct clk_parent_data){
2175 .hw = &cci_clk_src.clkr.hw,
2178 .flags = CLK_SET_RATE_PARENT,
2179 .ops = &clk_branch2_ops,
2184 static struct clk_branch gcc_camss_csi0_ahb_clk = {
2185 .halt_reg = 0x4e040,
2187 .enable_reg = 0x4e040,
2188 .enable_mask = BIT(0),
2189 .hw.init = &(struct clk_init_data){
2190 .name = "gcc_camss_csi0_ahb_clk",
2191 .parent_data = &(const struct clk_parent_data){
2192 .hw = &camss_ahb_clk_src.clkr.hw,
2195 .flags = CLK_SET_RATE_PARENT,
2196 .ops = &clk_branch2_ops,
2201 static struct clk_branch gcc_camss_csi0_clk = {
2202 .halt_reg = 0x4e03c,
2204 .enable_reg = 0x4e03c,
2205 .enable_mask = BIT(0),
2206 .hw.init = &(struct clk_init_data){
2207 .name = "gcc_camss_csi0_clk",
2208 .parent_data = &(const struct clk_parent_data){
2209 .hw = &csi0_clk_src.clkr.hw,
2212 .flags = CLK_SET_RATE_PARENT,
2213 .ops = &clk_branch2_ops,
2218 static struct clk_branch gcc_camss_csi0phy_clk = {
2219 .halt_reg = 0x4e048,
2221 .enable_reg = 0x4e048,
2222 .enable_mask = BIT(0),
2223 .hw.init = &(struct clk_init_data){
2224 .name = "gcc_camss_csi0phy_clk",
2225 .parent_data = &(const struct clk_parent_data){
2226 .hw = &csi0_clk_src.clkr.hw,
2229 .flags = CLK_SET_RATE_PARENT,
2230 .ops = &clk_branch2_ops,
2235 static struct clk_branch gcc_camss_csi0pix_clk = {
2236 .halt_reg = 0x4e058,
2238 .enable_reg = 0x4e058,
2239 .enable_mask = BIT(0),
2240 .hw.init = &(struct clk_init_data){
2241 .name = "gcc_camss_csi0pix_clk",
2242 .parent_data = &(const struct clk_parent_data){
2243 .hw = &csi0_clk_src.clkr.hw,
2246 .flags = CLK_SET_RATE_PARENT,
2247 .ops = &clk_branch2_ops,
2252 static struct clk_branch gcc_camss_csi0rdi_clk = {
2253 .halt_reg = 0x4e050,
2255 .enable_reg = 0x4e050,
2256 .enable_mask = BIT(0),
2257 .hw.init = &(struct clk_init_data){
2258 .name = "gcc_camss_csi0rdi_clk",
2259 .parent_data = &(const struct clk_parent_data){
2260 .hw = &csi0_clk_src.clkr.hw,
2263 .flags = CLK_SET_RATE_PARENT,
2264 .ops = &clk_branch2_ops,
2269 static struct clk_branch gcc_camss_csi1_ahb_clk = {
2270 .halt_reg = 0x4f040,
2272 .enable_reg = 0x4f040,
2273 .enable_mask = BIT(0),
2274 .hw.init = &(struct clk_init_data){
2275 .name = "gcc_camss_csi1_ahb_clk",
2276 .parent_data = &(const struct clk_parent_data){
2277 .hw = &camss_ahb_clk_src.clkr.hw,
2280 .flags = CLK_SET_RATE_PARENT,
2281 .ops = &clk_branch2_ops,
2286 static struct clk_branch gcc_camss_csi1_clk = {
2287 .halt_reg = 0x4f03c,
2289 .enable_reg = 0x4f03c,
2290 .enable_mask = BIT(0),
2291 .hw.init = &(struct clk_init_data){
2292 .name = "gcc_camss_csi1_clk",
2293 .parent_data = &(const struct clk_parent_data){
2294 .hw = &csi1_clk_src.clkr.hw,
2297 .flags = CLK_SET_RATE_PARENT,
2298 .ops = &clk_branch2_ops,
2303 static struct clk_branch gcc_camss_csi1phy_clk = {
2304 .halt_reg = 0x4f048,
2306 .enable_reg = 0x4f048,
2307 .enable_mask = BIT(0),
2308 .hw.init = &(struct clk_init_data){
2309 .name = "gcc_camss_csi1phy_clk",
2310 .parent_data = &(const struct clk_parent_data){
2311 .hw = &csi1_clk_src.clkr.hw,
2314 .flags = CLK_SET_RATE_PARENT,
2315 .ops = &clk_branch2_ops,
2320 static struct clk_branch gcc_camss_csi1pix_clk = {
2321 .halt_reg = 0x4f058,
2323 .enable_reg = 0x4f058,
2324 .enable_mask = BIT(0),
2325 .hw.init = &(struct clk_init_data){
2326 .name = "gcc_camss_csi1pix_clk",
2327 .parent_data = &(const struct clk_parent_data){
2328 .hw = &csi1_clk_src.clkr.hw,
2331 .flags = CLK_SET_RATE_PARENT,
2332 .ops = &clk_branch2_ops,
2337 static struct clk_branch gcc_camss_csi1rdi_clk = {
2338 .halt_reg = 0x4f050,
2340 .enable_reg = 0x4f050,
2341 .enable_mask = BIT(0),
2342 .hw.init = &(struct clk_init_data){
2343 .name = "gcc_camss_csi1rdi_clk",
2344 .parent_data = &(const struct clk_parent_data){
2345 .hw = &csi1_clk_src.clkr.hw,
2348 .flags = CLK_SET_RATE_PARENT,
2349 .ops = &clk_branch2_ops,
2354 static struct clk_branch gcc_camss_csi_vfe0_clk = {
2355 .halt_reg = 0x58050,
2357 .enable_reg = 0x58050,
2358 .enable_mask = BIT(0),
2359 .hw.init = &(struct clk_init_data){
2360 .name = "gcc_camss_csi_vfe0_clk",
2361 .parent_data = &(const struct clk_parent_data){
2362 .hw = &vfe0_clk_src.clkr.hw,
2365 .flags = CLK_SET_RATE_PARENT,
2366 .ops = &clk_branch2_ops,
2371 static struct clk_branch gcc_camss_gp0_clk = {
2372 .halt_reg = 0x54018,
2374 .enable_reg = 0x54018,
2375 .enable_mask = BIT(0),
2376 .hw.init = &(struct clk_init_data){
2377 .name = "gcc_camss_gp0_clk",
2378 .parent_data = &(const struct clk_parent_data){
2379 .hw = &camss_gp0_clk_src.clkr.hw,
2382 .flags = CLK_SET_RATE_PARENT,
2383 .ops = &clk_branch2_ops,
2388 static struct clk_branch gcc_camss_gp1_clk = {
2389 .halt_reg = 0x55018,
2391 .enable_reg = 0x55018,
2392 .enable_mask = BIT(0),
2393 .hw.init = &(struct clk_init_data){
2394 .name = "gcc_camss_gp1_clk",
2395 .parent_data = &(const struct clk_parent_data){
2396 .hw = &camss_gp1_clk_src.clkr.hw,
2399 .flags = CLK_SET_RATE_PARENT,
2400 .ops = &clk_branch2_ops,
2405 static struct clk_branch gcc_camss_ispif_ahb_clk = {
2406 .halt_reg = 0x50004,
2408 .enable_reg = 0x50004,
2409 .enable_mask = BIT(0),
2410 .hw.init = &(struct clk_init_data){
2411 .name = "gcc_camss_ispif_ahb_clk",
2412 .parent_data = &(const struct clk_parent_data){
2413 .hw = &camss_ahb_clk_src.clkr.hw,
2416 .flags = CLK_SET_RATE_PARENT,
2417 .ops = &clk_branch2_ops,
2422 static struct clk_branch gcc_camss_jpeg0_clk = {
2423 .halt_reg = 0x57020,
2425 .enable_reg = 0x57020,
2426 .enable_mask = BIT(0),
2427 .hw.init = &(struct clk_init_data){
2428 .name = "gcc_camss_jpeg0_clk",
2429 .parent_data = &(const struct clk_parent_data){
2430 .hw = &jpeg0_clk_src.clkr.hw,
2433 .flags = CLK_SET_RATE_PARENT,
2434 .ops = &clk_branch2_ops,
2439 static struct clk_branch gcc_camss_jpeg_ahb_clk = {
2440 .halt_reg = 0x57024,
2442 .enable_reg = 0x57024,
2443 .enable_mask = BIT(0),
2444 .hw.init = &(struct clk_init_data){
2445 .name = "gcc_camss_jpeg_ahb_clk",
2446 .parent_data = &(const struct clk_parent_data){
2447 .hw = &camss_ahb_clk_src.clkr.hw,
2450 .flags = CLK_SET_RATE_PARENT,
2451 .ops = &clk_branch2_ops,
2456 static struct clk_branch gcc_camss_jpeg_axi_clk = {
2457 .halt_reg = 0x57028,
2459 .enable_reg = 0x57028,
2460 .enable_mask = BIT(0),
2461 .hw.init = &(struct clk_init_data){
2462 .name = "gcc_camss_jpeg_axi_clk",
2463 .parent_data = &(const struct clk_parent_data){
2464 .hw = &system_mm_noc_bfdcd_clk_src.clkr.hw,
2467 .flags = CLK_SET_RATE_PARENT,
2468 .ops = &clk_branch2_ops,
2473 static struct clk_branch gcc_camss_mclk0_clk = {
2474 .halt_reg = 0x52018,
2476 .enable_reg = 0x52018,
2477 .enable_mask = BIT(0),
2478 .hw.init = &(struct clk_init_data){
2479 .name = "gcc_camss_mclk0_clk",
2480 .parent_data = &(const struct clk_parent_data){
2481 .hw = &mclk0_clk_src.clkr.hw,
2484 .flags = CLK_SET_RATE_PARENT,
2485 .ops = &clk_branch2_ops,
2490 static struct clk_branch gcc_camss_mclk1_clk = {
2491 .halt_reg = 0x53018,
2493 .enable_reg = 0x53018,
2494 .enable_mask = BIT(0),
2495 .hw.init = &(struct clk_init_data){
2496 .name = "gcc_camss_mclk1_clk",
2497 .parent_data = &(const struct clk_parent_data){
2498 .hw = &mclk1_clk_src.clkr.hw,
2501 .flags = CLK_SET_RATE_PARENT,
2502 .ops = &clk_branch2_ops,
2507 static struct clk_branch gcc_camss_micro_ahb_clk = {
2508 .halt_reg = 0x5600c,
2510 .enable_reg = 0x5600c,
2511 .enable_mask = BIT(0),
2512 .hw.init = &(struct clk_init_data){
2513 .name = "gcc_camss_micro_ahb_clk",
2514 .parent_data = &(const struct clk_parent_data){
2515 .hw = &camss_ahb_clk_src.clkr.hw,
2518 .flags = CLK_SET_RATE_PARENT,
2519 .ops = &clk_branch2_ops,
2524 static struct clk_branch gcc_camss_csi0phytimer_clk = {
2525 .halt_reg = 0x4e01c,
2527 .enable_reg = 0x4e01c,
2528 .enable_mask = BIT(0),
2529 .hw.init = &(struct clk_init_data){
2530 .name = "gcc_camss_csi0phytimer_clk",
2531 .parent_data = &(const struct clk_parent_data){
2532 .hw = &csi0phytimer_clk_src.clkr.hw,
2535 .flags = CLK_SET_RATE_PARENT,
2536 .ops = &clk_branch2_ops,
2541 static struct clk_branch gcc_camss_csi1phytimer_clk = {
2542 .halt_reg = 0x4f01c,
2544 .enable_reg = 0x4f01c,
2545 .enable_mask = BIT(0),
2546 .hw.init = &(struct clk_init_data){
2547 .name = "gcc_camss_csi1phytimer_clk",
2548 .parent_data = &(const struct clk_parent_data){
2549 .hw = &csi1phytimer_clk_src.clkr.hw,
2552 .flags = CLK_SET_RATE_PARENT,
2553 .ops = &clk_branch2_ops,
2558 static struct clk_branch gcc_camss_ahb_clk = {
2559 .halt_reg = 0x5a014,
2561 .enable_reg = 0x5a014,
2562 .enable_mask = BIT(0),
2563 .hw.init = &(struct clk_init_data){
2564 .name = "gcc_camss_ahb_clk",
2565 .parent_data = &(const struct clk_parent_data){
2566 .hw = &camss_ahb_clk_src.clkr.hw,
2569 .flags = CLK_SET_RATE_PARENT,
2570 .ops = &clk_branch2_ops,
2575 static struct clk_branch gcc_camss_top_ahb_clk = {
2576 .halt_reg = 0x56004,
2578 .enable_reg = 0x56004,
2579 .enable_mask = BIT(0),
2580 .hw.init = &(struct clk_init_data){
2581 .name = "gcc_camss_top_ahb_clk",
2582 .parent_data = &(const struct clk_parent_data){
2583 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
2586 .flags = CLK_SET_RATE_PARENT,
2587 .ops = &clk_branch2_ops,
2592 static struct clk_branch gcc_camss_cpp_ahb_clk = {
2593 .halt_reg = 0x58040,
2595 .enable_reg = 0x58040,
2596 .enable_mask = BIT(0),
2597 .hw.init = &(struct clk_init_data){
2598 .name = "gcc_camss_cpp_ahb_clk",
2599 .parent_data = &(const struct clk_parent_data){
2600 .hw = &camss_ahb_clk_src.clkr.hw,
2603 .flags = CLK_SET_RATE_PARENT,
2604 .ops = &clk_branch2_ops,
2609 static struct clk_branch gcc_camss_cpp_clk = {
2610 .halt_reg = 0x5803c,
2612 .enable_reg = 0x5803c,
2613 .enable_mask = BIT(0),
2614 .hw.init = &(struct clk_init_data){
2615 .name = "gcc_camss_cpp_clk",
2616 .parent_data = &(const struct clk_parent_data){
2617 .hw = &cpp_clk_src.clkr.hw,
2620 .flags = CLK_SET_RATE_PARENT,
2621 .ops = &clk_branch2_ops,
2626 static struct clk_branch gcc_camss_vfe0_clk = {
2627 .halt_reg = 0x58038,
2629 .enable_reg = 0x58038,
2630 .enable_mask = BIT(0),
2631 .hw.init = &(struct clk_init_data){
2632 .name = "gcc_camss_vfe0_clk",
2633 .parent_data = &(const struct clk_parent_data){
2634 .hw = &vfe0_clk_src.clkr.hw,
2637 .flags = CLK_SET_RATE_PARENT,
2638 .ops = &clk_branch2_ops,
2643 static struct clk_branch gcc_camss_vfe_ahb_clk = {
2644 .halt_reg = 0x58044,
2646 .enable_reg = 0x58044,
2647 .enable_mask = BIT(0),
2648 .hw.init = &(struct clk_init_data){
2649 .name = "gcc_camss_vfe_ahb_clk",
2650 .parent_data = &(const struct clk_parent_data){
2651 .hw = &camss_ahb_clk_src.clkr.hw,
2654 .flags = CLK_SET_RATE_PARENT,
2655 .ops = &clk_branch2_ops,
2660 static struct clk_branch gcc_camss_vfe_axi_clk = {
2661 .halt_reg = 0x58048,
2663 .enable_reg = 0x58048,
2664 .enable_mask = BIT(0),
2665 .hw.init = &(struct clk_init_data){
2666 .name = "gcc_camss_vfe_axi_clk",
2667 .parent_data = &(const struct clk_parent_data){
2668 .hw = &system_mm_noc_bfdcd_clk_src.clkr.hw,
2671 .flags = CLK_SET_RATE_PARENT,
2672 .ops = &clk_branch2_ops,
2677 static struct clk_branch gcc_crypto_ahb_clk = {
2678 .halt_reg = 0x16024,
2679 .halt_check = BRANCH_HALT_VOTED,
2681 .enable_reg = 0x45004,
2682 .enable_mask = BIT(0),
2683 .hw.init = &(struct clk_init_data){
2684 .name = "gcc_crypto_ahb_clk",
2685 .parent_data = &(const struct clk_parent_data){
2686 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
2689 .flags = CLK_SET_RATE_PARENT,
2690 .ops = &clk_branch2_ops,
2695 static struct clk_branch gcc_crypto_axi_clk = {
2696 .halt_reg = 0x16020,
2697 .halt_check = BRANCH_HALT_VOTED,
2699 .enable_reg = 0x45004,
2700 .enable_mask = BIT(1),
2701 .hw.init = &(struct clk_init_data){
2702 .name = "gcc_crypto_axi_clk",
2703 .parent_data = &(const struct clk_parent_data){
2704 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
2707 .flags = CLK_SET_RATE_PARENT,
2708 .ops = &clk_branch2_ops,
2713 static struct clk_branch gcc_crypto_clk = {
2714 .halt_reg = 0x1601c,
2715 .halt_check = BRANCH_HALT_VOTED,
2717 .enable_reg = 0x45004,
2718 .enable_mask = BIT(2),
2719 .hw.init = &(struct clk_init_data){
2720 .name = "gcc_crypto_clk",
2721 .parent_data = &(const struct clk_parent_data){
2722 .hw = &crypto_clk_src.clkr.hw,
2725 .flags = CLK_SET_RATE_PARENT,
2726 .ops = &clk_branch2_ops,
2731 static struct clk_branch gcc_oxili_gmem_clk = {
2732 .halt_reg = 0x59024,
2734 .enable_reg = 0x59024,
2735 .enable_mask = BIT(0),
2736 .hw.init = &(struct clk_init_data){
2737 .name = "gcc_oxili_gmem_clk",
2738 .parent_data = &(const struct clk_parent_data){
2739 .hw = &gfx3d_clk_src.clkr.hw,
2742 .flags = CLK_SET_RATE_PARENT,
2743 .ops = &clk_branch2_ops,
2748 static struct clk_branch gcc_gp1_clk = {
2749 .halt_reg = 0x08000,
2751 .enable_reg = 0x08000,
2752 .enable_mask = BIT(0),
2753 .hw.init = &(struct clk_init_data){
2754 .name = "gcc_gp1_clk",
2755 .parent_data = &(const struct clk_parent_data){
2756 .hw = &gp1_clk_src.clkr.hw,
2759 .flags = CLK_SET_RATE_PARENT,
2760 .ops = &clk_branch2_ops,
2765 static struct clk_branch gcc_gp2_clk = {
2766 .halt_reg = 0x09000,
2768 .enable_reg = 0x09000,
2769 .enable_mask = BIT(0),
2770 .hw.init = &(struct clk_init_data){
2771 .name = "gcc_gp2_clk",
2772 .parent_data = &(const struct clk_parent_data){
2773 .hw = &gp2_clk_src.clkr.hw,
2776 .flags = CLK_SET_RATE_PARENT,
2777 .ops = &clk_branch2_ops,
2782 static struct clk_branch gcc_gp3_clk = {
2783 .halt_reg = 0x0a000,
2785 .enable_reg = 0x0a000,
2786 .enable_mask = BIT(0),
2787 .hw.init = &(struct clk_init_data){
2788 .name = "gcc_gp3_clk",
2789 .parent_data = &(const struct clk_parent_data){
2790 .hw = &gp3_clk_src.clkr.hw,
2793 .flags = CLK_SET_RATE_PARENT,
2794 .ops = &clk_branch2_ops,
2799 static struct clk_branch gcc_mdss_ahb_clk = {
2800 .halt_reg = 0x4d07c,
2802 .enable_reg = 0x4d07c,
2803 .enable_mask = BIT(0),
2804 .hw.init = &(struct clk_init_data){
2805 .name = "gcc_mdss_ahb_clk",
2806 .parent_data = &(const struct clk_parent_data){
2807 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
2810 .flags = CLK_SET_RATE_PARENT,
2811 .ops = &clk_branch2_ops,
2816 static struct clk_branch gcc_mdss_axi_clk = {
2817 .halt_reg = 0x4d080,
2819 .enable_reg = 0x4d080,
2820 .enable_mask = BIT(0),
2821 .hw.init = &(struct clk_init_data){
2822 .name = "gcc_mdss_axi_clk",
2823 .parent_data = &(const struct clk_parent_data){
2824 .hw = &system_mm_noc_bfdcd_clk_src.clkr.hw,
2827 .flags = CLK_SET_RATE_PARENT,
2828 .ops = &clk_branch2_ops,
2833 static struct clk_branch gcc_mdss_byte0_clk = {
2834 .halt_reg = 0x4d094,
2836 .enable_reg = 0x4d094,
2837 .enable_mask = BIT(0),
2838 .hw.init = &(struct clk_init_data){
2839 .name = "gcc_mdss_byte0_clk",
2840 .parent_data = &(const struct clk_parent_data){
2841 .hw = &byte0_clk_src.clkr.hw,
2844 .flags = CLK_SET_RATE_PARENT,
2845 .ops = &clk_branch2_ops,
2850 static struct clk_branch gcc_mdss_byte1_clk = {
2851 .halt_reg = 0x4d0a0,
2853 .enable_reg = 0x4d0a0,
2854 .enable_mask = BIT(0),
2855 .hw.init = &(struct clk_init_data){
2856 .name = "gcc_mdss_byte1_clk",
2857 .parent_data = &(const struct clk_parent_data){
2858 .hw = &byte1_clk_src.clkr.hw,
2861 .flags = CLK_SET_RATE_PARENT,
2862 .ops = &clk_branch2_ops,
2867 static struct clk_branch gcc_mdss_esc0_clk = {
2868 .halt_reg = 0x4d098,
2870 .enable_reg = 0x4d098,
2871 .enable_mask = BIT(0),
2872 .hw.init = &(struct clk_init_data){
2873 .name = "gcc_mdss_esc0_clk",
2874 .parent_data = &(const struct clk_parent_data){
2875 .hw = &esc0_clk_src.clkr.hw,
2878 .flags = CLK_SET_RATE_PARENT,
2879 .ops = &clk_branch2_ops,
2884 static struct clk_branch gcc_mdss_esc1_clk = {
2885 .halt_reg = 0x4d09c,
2887 .enable_reg = 0x4d09c,
2888 .enable_mask = BIT(0),
2889 .hw.init = &(struct clk_init_data){
2890 .name = "gcc_mdss_esc1_clk",
2891 .parent_data = &(const struct clk_parent_data){
2892 .hw = &esc1_clk_src.clkr.hw,
2895 .flags = CLK_SET_RATE_PARENT,
2896 .ops = &clk_branch2_ops,
2901 static struct clk_branch gcc_mdss_mdp_clk = {
2902 .halt_reg = 0x4D088,
2904 .enable_reg = 0x4D088,
2905 .enable_mask = BIT(0),
2906 .hw.init = &(struct clk_init_data){
2907 .name = "gcc_mdss_mdp_clk",
2908 .parent_data = &(const struct clk_parent_data){
2909 .hw = &mdp_clk_src.clkr.hw,
2912 .flags = CLK_SET_RATE_PARENT,
2913 .ops = &clk_branch2_ops,
2918 static struct clk_branch gcc_mdss_pclk0_clk = {
2919 .halt_reg = 0x4d084,
2921 .enable_reg = 0x4d084,
2922 .enable_mask = BIT(0),
2923 .hw.init = &(struct clk_init_data){
2924 .name = "gcc_mdss_pclk0_clk",
2925 .parent_data = &(const struct clk_parent_data){
2926 .hw = &pclk0_clk_src.clkr.hw,
2929 .flags = CLK_SET_RATE_PARENT,
2930 .ops = &clk_branch2_ops,
2935 static struct clk_branch gcc_mdss_pclk1_clk = {
2936 .halt_reg = 0x4d0a4,
2938 .enable_reg = 0x4d0a4,
2939 .enable_mask = BIT(0),
2940 .hw.init = &(struct clk_init_data){
2941 .name = "gcc_mdss_pclk1_clk",
2942 .parent_data = &(const struct clk_parent_data){
2943 .hw = &pclk1_clk_src.clkr.hw,
2946 .flags = CLK_SET_RATE_PARENT,
2947 .ops = &clk_branch2_ops,
2952 static struct clk_branch gcc_mdss_vsync_clk = {
2953 .halt_reg = 0x4d090,
2955 .enable_reg = 0x4d090,
2956 .enable_mask = BIT(0),
2957 .hw.init = &(struct clk_init_data){
2958 .name = "gcc_mdss_vsync_clk",
2959 .parent_data = &(const struct clk_parent_data){
2960 .hw = &vsync_clk_src.clkr.hw,
2963 .flags = CLK_SET_RATE_PARENT,
2964 .ops = &clk_branch2_ops,
2969 static struct clk_branch gcc_mss_cfg_ahb_clk = {
2970 .halt_reg = 0x49000,
2972 .enable_reg = 0x49000,
2973 .enable_mask = BIT(0),
2974 .hw.init = &(struct clk_init_data){
2975 .name = "gcc_mss_cfg_ahb_clk",
2976 .parent_data = &(const struct clk_parent_data){
2977 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
2980 .flags = CLK_SET_RATE_PARENT,
2981 .ops = &clk_branch2_ops,
2986 static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
2987 .halt_reg = 0x49004,
2989 .enable_reg = 0x49004,
2990 .enable_mask = BIT(0),
2991 .hw.init = &(struct clk_init_data){
2992 .name = "gcc_mss_q6_bimc_axi_clk",
2993 .parent_data = &(const struct clk_parent_data){
2994 .hw = &bimc_ddr_clk_src.clkr.hw,
2997 .flags = CLK_SET_RATE_PARENT,
2998 .ops = &clk_branch2_ops,
3003 static struct clk_branch gcc_oxili_ahb_clk = {
3004 .halt_reg = 0x59028,
3006 .enable_reg = 0x59028,
3007 .enable_mask = BIT(0),
3008 .hw.init = &(struct clk_init_data){
3009 .name = "gcc_oxili_ahb_clk",
3010 .parent_data = &(const struct clk_parent_data){
3011 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3014 .flags = CLK_SET_RATE_PARENT,
3015 .ops = &clk_branch2_ops,
3020 static struct clk_branch gcc_oxili_gfx3d_clk = {
3021 .halt_reg = 0x59020,
3023 .enable_reg = 0x59020,
3024 .enable_mask = BIT(0),
3025 .hw.init = &(struct clk_init_data){
3026 .name = "gcc_oxili_gfx3d_clk",
3027 .parent_data = &(const struct clk_parent_data){
3028 .hw = &gfx3d_clk_src.clkr.hw,
3031 .flags = CLK_SET_RATE_PARENT,
3032 .ops = &clk_branch2_ops,
3037 static struct clk_branch gcc_pdm2_clk = {
3038 .halt_reg = 0x4400c,
3040 .enable_reg = 0x4400c,
3041 .enable_mask = BIT(0),
3042 .hw.init = &(struct clk_init_data){
3043 .name = "gcc_pdm2_clk",
3044 .parent_data = &(const struct clk_parent_data){
3045 .hw = &pdm2_clk_src.clkr.hw,
3048 .flags = CLK_SET_RATE_PARENT,
3049 .ops = &clk_branch2_ops,
3054 static struct clk_branch gcc_pdm_ahb_clk = {
3055 .halt_reg = 0x44004,
3057 .enable_reg = 0x44004,
3058 .enable_mask = BIT(0),
3059 .hw.init = &(struct clk_init_data){
3060 .name = "gcc_pdm_ahb_clk",
3061 .parent_data = &(const struct clk_parent_data){
3062 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3065 .flags = CLK_SET_RATE_PARENT,
3066 .ops = &clk_branch2_ops,
3071 static struct clk_branch gcc_prng_ahb_clk = {
3072 .halt_reg = 0x13004,
3073 .halt_check = BRANCH_HALT_VOTED,
3075 .enable_reg = 0x45004,
3076 .enable_mask = BIT(8),
3077 .hw.init = &(struct clk_init_data){
3078 .name = "gcc_prng_ahb_clk",
3079 .parent_data = &(const struct clk_parent_data){
3080 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3083 .ops = &clk_branch2_ops,
3088 static struct clk_branch gcc_sdcc1_ahb_clk = {
3089 .halt_reg = 0x4201c,
3091 .enable_reg = 0x4201c,
3092 .enable_mask = BIT(0),
3093 .hw.init = &(struct clk_init_data){
3094 .name = "gcc_sdcc1_ahb_clk",
3095 .parent_data = &(const struct clk_parent_data){
3096 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3099 .flags = CLK_SET_RATE_PARENT,
3100 .ops = &clk_branch2_ops,
3105 static struct clk_branch gcc_sdcc1_apps_clk = {
3106 .halt_reg = 0x42018,
3108 .enable_reg = 0x42018,
3109 .enable_mask = BIT(0),
3110 .hw.init = &(struct clk_init_data){
3111 .name = "gcc_sdcc1_apps_clk",
3112 .parent_data = &(const struct clk_parent_data){
3113 .hw = &sdcc1_apps_clk_src.clkr.hw,
3116 .flags = CLK_SET_RATE_PARENT,
3117 .ops = &clk_branch2_ops,
3122 static struct clk_branch gcc_sdcc2_ahb_clk = {
3123 .halt_reg = 0x4301c,
3125 .enable_reg = 0x4301c,
3126 .enable_mask = BIT(0),
3127 .hw.init = &(struct clk_init_data){
3128 .name = "gcc_sdcc2_ahb_clk",
3129 .parent_data = &(const struct clk_parent_data){
3130 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3133 .flags = CLK_SET_RATE_PARENT,
3134 .ops = &clk_branch2_ops,
3139 static struct clk_branch gcc_sdcc2_apps_clk = {
3140 .halt_reg = 0x43018,
3142 .enable_reg = 0x43018,
3143 .enable_mask = BIT(0),
3144 .hw.init = &(struct clk_init_data){
3145 .name = "gcc_sdcc2_apps_clk",
3146 .parent_data = &(const struct clk_parent_data){
3147 .hw = &sdcc2_apps_clk_src.clkr.hw,
3150 .flags = CLK_SET_RATE_PARENT,
3151 .ops = &clk_branch2_ops,
3156 static struct clk_branch gcc_apss_tcu_clk = {
3157 .halt_reg = 0x12018,
3158 .halt_check = BRANCH_HALT_VOTED,
3160 .enable_reg = 0x4500c,
3161 .enable_mask = BIT(1),
3162 .hw.init = &(struct clk_init_data){
3163 .name = "gcc_apss_tcu_clk",
3164 .parent_data = &(const struct clk_parent_data){
3165 .hw = &bimc_ddr_clk_src.clkr.hw,
3168 .ops = &clk_branch2_ops,
3173 static struct clk_branch gcc_gfx_tcu_clk = {
3174 .halt_reg = 0x12020,
3175 .halt_check = BRANCH_HALT_VOTED,
3177 .enable_reg = 0x4500c,
3178 .enable_mask = BIT(2),
3179 .hw.init = &(struct clk_init_data){
3180 .name = "gcc_gfx_tcu_clk",
3181 .parent_data = &(const struct clk_parent_data){
3182 .hw = &bimc_ddr_clk_src.clkr.hw,
3185 .ops = &clk_branch2_ops,
3190 static struct clk_branch gcc_gfx_tbu_clk = {
3191 .halt_reg = 0x12010,
3192 .halt_check = BRANCH_HALT_VOTED,
3194 .enable_reg = 0x4500c,
3195 .enable_mask = BIT(3),
3196 .hw.init = &(struct clk_init_data){
3197 .name = "gcc_gfx_tbu_clk",
3198 .parent_data = &(const struct clk_parent_data){
3199 .hw = &bimc_ddr_clk_src.clkr.hw,
3202 .ops = &clk_branch2_ops,
3207 static struct clk_branch gcc_mdp_tbu_clk = {
3208 .halt_reg = 0x1201c,
3209 .halt_check = BRANCH_HALT_VOTED,
3211 .enable_reg = 0x4500c,
3212 .enable_mask = BIT(4),
3213 .hw.init = &(struct clk_init_data){
3214 .name = "gcc_mdp_tbu_clk",
3215 .parent_data = &(const struct clk_parent_data){
3216 .hw = &system_mm_noc_bfdcd_clk_src.clkr.hw,
3219 .flags = CLK_SET_RATE_PARENT,
3220 .ops = &clk_branch2_ops,
3225 static struct clk_branch gcc_venus_tbu_clk = {
3226 .halt_reg = 0x12014,
3227 .halt_check = BRANCH_HALT_VOTED,
3229 .enable_reg = 0x4500c,
3230 .enable_mask = BIT(5),
3231 .hw.init = &(struct clk_init_data){
3232 .name = "gcc_venus_tbu_clk",
3233 .parent_data = &(const struct clk_parent_data){
3234 .hw = &system_mm_noc_bfdcd_clk_src.clkr.hw,
3237 .flags = CLK_SET_RATE_PARENT,
3238 .ops = &clk_branch2_ops,
3243 static struct clk_branch gcc_vfe_tbu_clk = {
3244 .halt_reg = 0x1203c,
3245 .halt_check = BRANCH_HALT_VOTED,
3247 .enable_reg = 0x4500c,
3248 .enable_mask = BIT(9),
3249 .hw.init = &(struct clk_init_data){
3250 .name = "gcc_vfe_tbu_clk",
3251 .parent_data = &(const struct clk_parent_data){
3252 .hw = &system_mm_noc_bfdcd_clk_src.clkr.hw,
3255 .flags = CLK_SET_RATE_PARENT,
3256 .ops = &clk_branch2_ops,
3261 static struct clk_branch gcc_jpeg_tbu_clk = {
3262 .halt_reg = 0x12034,
3263 .halt_check = BRANCH_HALT_VOTED,
3265 .enable_reg = 0x4500c,
3266 .enable_mask = BIT(10),
3267 .hw.init = &(struct clk_init_data){
3268 .name = "gcc_jpeg_tbu_clk",
3269 .parent_data = &(const struct clk_parent_data){
3270 .hw = &system_mm_noc_bfdcd_clk_src.clkr.hw,
3273 .flags = CLK_SET_RATE_PARENT,
3274 .ops = &clk_branch2_ops,
3279 static struct clk_branch gcc_smmu_cfg_clk = {
3280 .halt_reg = 0x12038,
3281 .halt_check = BRANCH_HALT_VOTED,
3283 .enable_reg = 0x4500c,
3284 .enable_mask = BIT(12),
3285 .hw.init = &(struct clk_init_data){
3286 .name = "gcc_smmu_cfg_clk",
3287 .parent_data = &(const struct clk_parent_data){
3288 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3291 .flags = CLK_SET_RATE_PARENT,
3292 .ops = &clk_branch2_ops,
3297 static struct clk_branch gcc_gtcu_ahb_clk = {
3298 .halt_reg = 0x12044,
3299 .halt_check = BRANCH_HALT_VOTED,
3301 .enable_reg = 0x4500c,
3302 .enable_mask = BIT(13),
3303 .hw.init = &(struct clk_init_data){
3304 .name = "gcc_gtcu_ahb_clk",
3305 .parent_data = &(const struct clk_parent_data){
3306 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3309 .flags = CLK_SET_RATE_PARENT,
3310 .ops = &clk_branch2_ops,
3315 static struct clk_branch gcc_cpp_tbu_clk = {
3316 .halt_reg = 0x12040,
3317 .halt_check = BRANCH_HALT_VOTED,
3319 .enable_reg = 0x4500c,
3320 .enable_mask = BIT(14),
3321 .hw.init = &(struct clk_init_data){
3322 .name = "gcc_cpp_tbu_clk",
3323 .parent_data = &(const struct clk_parent_data){
3324 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3327 .flags = CLK_SET_RATE_PARENT,
3328 .ops = &clk_branch2_ops,
3333 static struct clk_branch gcc_mdp_rt_tbu_clk = {
3334 .halt_reg = 0x1201c,
3335 .halt_check = BRANCH_HALT_VOTED,
3337 .enable_reg = 0x4500c,
3338 .enable_mask = BIT(15),
3339 .hw.init = &(struct clk_init_data){
3340 .name = "gcc_mdp_rt_tbu_clk",
3341 .parent_data = &(const struct clk_parent_data){
3342 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3345 .flags = CLK_SET_RATE_PARENT,
3346 .ops = &clk_branch2_ops,
3351 static struct clk_branch gcc_bimc_gfx_clk = {
3352 .halt_reg = 0x31024,
3354 .enable_reg = 0x31024,
3355 .enable_mask = BIT(0),
3356 .hw.init = &(struct clk_init_data){
3357 .name = "gcc_bimc_gfx_clk",
3358 .parent_data = &(const struct clk_parent_data){
3359 .hw = &bimc_gpu_clk_src.clkr.hw,
3362 .flags = CLK_SET_RATE_PARENT,
3363 .ops = &clk_branch2_ops,
3368 static struct clk_branch gcc_bimc_gpu_clk = {
3369 .halt_reg = 0x31040,
3371 .enable_reg = 0x31040,
3372 .enable_mask = BIT(0),
3373 .hw.init = &(struct clk_init_data){
3374 .name = "gcc_bimc_gpu_clk",
3375 .parent_data = &(const struct clk_parent_data){
3376 .hw = &bimc_gpu_clk_src.clkr.hw,
3379 .flags = CLK_SET_RATE_PARENT,
3380 .ops = &clk_branch2_ops,
3385 static struct clk_branch gcc_usb2a_phy_sleep_clk = {
3386 .halt_reg = 0x4102c,
3388 .enable_reg = 0x4102c,
3389 .enable_mask = BIT(0),
3390 .hw.init = &(struct clk_init_data){
3391 .name = "gcc_usb2a_phy_sleep_clk",
3392 .ops = &clk_branch2_ops,
3397 static struct clk_branch gcc_usb_fs_ahb_clk = {
3398 .halt_reg = 0x3f008,
3400 .enable_reg = 0x3f008,
3401 .enable_mask = BIT(0),
3402 .hw.init = &(struct clk_init_data){
3403 .name = "gcc_usb_fs_ahb_clk",
3404 .parent_data = &(const struct clk_parent_data){
3405 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3408 .flags = CLK_SET_RATE_PARENT,
3409 .ops = &clk_branch2_ops,
3414 static struct clk_branch gcc_usb_fs_ic_clk = {
3415 .halt_reg = 0x3f030,
3417 .enable_reg = 0x3f030,
3418 .enable_mask = BIT(0),
3419 .hw.init = &(struct clk_init_data){
3420 .name = "gcc_usb_fs_ic_clk",
3421 .parent_data = &(const struct clk_parent_data){
3422 .hw = &usb_fs_ic_clk_src.clkr.hw,
3425 .flags = CLK_SET_RATE_PARENT,
3426 .ops = &clk_branch2_ops,
3431 static struct clk_branch gcc_usb_fs_system_clk = {
3432 .halt_reg = 0x3f004,
3434 .enable_reg = 0x3f004,
3435 .enable_mask = BIT(0),
3436 .hw.init = &(struct clk_init_data){
3437 .name = "gcc_usb_fs_system_clk",
3438 .parent_data = &(const struct clk_parent_data){
3439 .hw = &usb_fs_system_clk_src.clkr.hw,
3442 .flags = CLK_SET_RATE_PARENT,
3443 .ops = &clk_branch2_ops,
3448 static struct clk_branch gcc_usb_hs_ahb_clk = {
3449 .halt_reg = 0x41008,
3451 .enable_reg = 0x41008,
3452 .enable_mask = BIT(0),
3453 .hw.init = &(struct clk_init_data){
3454 .name = "gcc_usb_hs_ahb_clk",
3455 .parent_data = &(const struct clk_parent_data){
3456 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3459 .flags = CLK_SET_RATE_PARENT,
3460 .ops = &clk_branch2_ops,
3465 static struct clk_branch gcc_usb_hs_system_clk = {
3466 .halt_reg = 0x41004,
3468 .enable_reg = 0x41004,
3469 .enable_mask = BIT(0),
3470 .hw.init = &(struct clk_init_data){
3471 .name = "gcc_usb_hs_system_clk",
3472 .parent_data = &(const struct clk_parent_data){
3473 .hw = &usb_hs_system_clk_src.clkr.hw,
3476 .flags = CLK_SET_RATE_PARENT,
3477 .ops = &clk_branch2_ops,
3482 static struct clk_branch gcc_venus0_ahb_clk = {
3483 .halt_reg = 0x4c020,
3485 .enable_reg = 0x4c020,
3486 .enable_mask = BIT(0),
3487 .hw.init = &(struct clk_init_data){
3488 .name = "gcc_venus0_ahb_clk",
3489 .parent_data = &(const struct clk_parent_data){
3490 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3493 .flags = CLK_SET_RATE_PARENT,
3494 .ops = &clk_branch2_ops,
3499 static struct clk_branch gcc_venus0_axi_clk = {
3500 .halt_reg = 0x4c024,
3502 .enable_reg = 0x4c024,
3503 .enable_mask = BIT(0),
3504 .hw.init = &(struct clk_init_data){
3505 .name = "gcc_venus0_axi_clk",
3506 .parent_data = &(const struct clk_parent_data){
3507 .hw = &system_mm_noc_bfdcd_clk_src.clkr.hw,
3510 .flags = CLK_SET_RATE_PARENT,
3511 .ops = &clk_branch2_ops,
3516 static struct clk_branch gcc_venus0_vcodec0_clk = {
3517 .halt_reg = 0x4c01c,
3519 .enable_reg = 0x4c01c,
3520 .enable_mask = BIT(0),
3521 .hw.init = &(struct clk_init_data){
3522 .name = "gcc_venus0_vcodec0_clk",
3523 .parent_data = &(const struct clk_parent_data){
3524 .hw = &vcodec0_clk_src.clkr.hw,
3527 .flags = CLK_SET_RATE_PARENT,
3528 .ops = &clk_branch2_ops,
3533 static struct clk_branch gcc_venus0_core0_vcodec0_clk = {
3534 .halt_reg = 0x4c02c,
3536 .enable_reg = 0x4c02c,
3537 .enable_mask = BIT(0),
3538 .hw.init = &(struct clk_init_data){
3539 .name = "gcc_venus0_core0_vcodec0_clk",
3540 .parent_data = &(const struct clk_parent_data){
3541 .hw = &vcodec0_clk_src.clkr.hw,
3544 .flags = CLK_SET_RATE_PARENT,
3545 .ops = &clk_branch2_ops,
3550 static struct clk_branch gcc_venus0_core1_vcodec0_clk = {
3551 .halt_reg = 0x4c034,
3553 .enable_reg = 0x4c034,
3554 .enable_mask = BIT(0),
3555 .hw.init = &(struct clk_init_data){
3556 .name = "gcc_venus0_core1_vcodec0_clk",
3557 .parent_data = &(const struct clk_parent_data){
3558 .hw = &vcodec0_clk_src.clkr.hw,
3561 .flags = CLK_SET_RATE_PARENT,
3562 .ops = &clk_branch2_ops,
3567 static struct clk_branch gcc_oxili_timer_clk = {
3568 .halt_reg = 0x59040,
3570 .enable_reg = 0x59040,
3571 .enable_mask = BIT(0),
3572 .hw.init = &(struct clk_init_data){
3573 .name = "gcc_oxili_timer_clk",
3574 .ops = &clk_branch2_ops,
3579 static struct gdsc venus_gdsc = {
3584 .pwrsts = PWRSTS_OFF_ON,
3587 static struct gdsc mdss_gdsc = {
3592 .pwrsts = PWRSTS_OFF_ON,
3595 static struct gdsc jpeg_gdsc = {
3600 .pwrsts = PWRSTS_OFF_ON,
3603 static struct gdsc vfe_gdsc = {
3608 .pwrsts = PWRSTS_OFF_ON,
3611 static struct gdsc oxili_gdsc = {
3616 .pwrsts = PWRSTS_OFF_ON,
3619 static struct gdsc venus_core0_gdsc = {
3622 .name = "venus_core0",
3624 .pwrsts = PWRSTS_OFF_ON,
3627 static struct gdsc venus_core1_gdsc = {
3630 .name = "venus_core1",
3632 .pwrsts = PWRSTS_OFF_ON,
3635 static struct clk_regmap *gcc_msm8939_clocks[] = {
3636 [GPLL0] = &gpll0.clkr,
3637 [GPLL0_VOTE] = &gpll0_vote,
3638 [BIMC_PLL] = &bimc_pll.clkr,
3639 [BIMC_PLL_VOTE] = &bimc_pll_vote,
3640 [GPLL1] = &gpll1.clkr,
3641 [GPLL1_VOTE] = &gpll1_vote,
3642 [GPLL2] = &gpll2.clkr,
3643 [GPLL2_VOTE] = &gpll2_vote,
3644 [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
3645 [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
3646 [SYSTEM_MM_NOC_BFDCD_CLK_SRC] = &system_mm_noc_bfdcd_clk_src.clkr,
3647 [CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr,
3648 [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
3649 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3650 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3651 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
3652 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3653 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3654 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3655 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3656 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3657 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3658 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3659 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3660 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3661 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3662 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3663 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3664 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3665 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3666 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3667 [CCI_CLK_SRC] = &cci_clk_src.clkr,
3668 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3669 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3670 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3671 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3672 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3673 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3674 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3675 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
3676 [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
3677 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
3678 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
3679 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
3680 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3681 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3682 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
3683 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3684 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
3685 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3686 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3687 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3688 [APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr,
3689 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
3690 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
3691 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3692 [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
3693 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3694 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3695 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3696 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3697 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3698 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3699 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3700 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3701 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3702 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3703 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3704 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3705 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3706 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3707 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3708 [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
3709 [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
3710 [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
3711 [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
3712 [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
3713 [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
3714 [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
3715 [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
3716 [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
3717 [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
3718 [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
3719 [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
3720 [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
3721 [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
3722 [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
3723 [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
3724 [GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
3725 [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
3726 [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
3727 [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
3728 [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
3729 [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
3730 [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
3731 [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
3732 [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
3733 [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
3734 [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
3735 [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
3736 [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
3737 [GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr,
3738 [GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr,
3739 [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
3740 [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
3741 [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
3742 [GCC_OXILI_GMEM_CLK] = &gcc_oxili_gmem_clk.clkr,
3743 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3744 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3745 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3746 [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
3747 [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
3748 [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
3749 [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
3750 [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
3751 [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
3752 [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
3753 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3754 [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
3755 [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
3756 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3757 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3758 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3759 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3760 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3761 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3762 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3763 [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
3764 [GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
3765 [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
3766 [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
3767 [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
3768 [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
3769 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
3770 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
3771 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
3772 [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
3773 [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
3774 [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
3775 [BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr,
3776 [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
3777 [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
3778 [BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr,
3779 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
3780 [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
3781 [ULTAUDIO_AHBFABRIC_CLK_SRC] = &ultaudio_ahbfabric_clk_src.clkr,
3782 [ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC] = &ultaudio_lpaif_pri_i2s_clk_src.clkr,
3783 [ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC] = &ultaudio_lpaif_sec_i2s_clk_src.clkr,
3784 [ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC] = &ultaudio_lpaif_aux_i2s_clk_src.clkr,
3785 [ULTAUDIO_XO_CLK_SRC] = &ultaudio_xo_clk_src.clkr,
3786 [CODEC_DIGCODEC_CLK_SRC] = &codec_digcodec_clk_src.clkr,
3787 [GCC_ULTAUDIO_PCNOC_MPORT_CLK] = &gcc_ultaudio_pcnoc_mport_clk.clkr,
3788 [GCC_ULTAUDIO_PCNOC_SWAY_CLK] = &gcc_ultaudio_pcnoc_sway_clk.clkr,
3789 [GCC_ULTAUDIO_AVSYNC_XO_CLK] = &gcc_ultaudio_avsync_xo_clk.clkr,
3790 [GCC_ULTAUDIO_STC_XO_CLK] = &gcc_ultaudio_stc_xo_clk.clkr,
3791 [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_clk.clkr,
3792 [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_lpm_clk.clkr,
3793 [GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK] = &gcc_ultaudio_lpaif_pri_i2s_clk.clkr,
3794 [GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK] = &gcc_ultaudio_lpaif_sec_i2s_clk.clkr,
3795 [GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK] = &gcc_ultaudio_lpaif_aux_i2s_clk.clkr,
3796 [GCC_CODEC_DIGCODEC_CLK] = &gcc_codec_digcodec_clk.clkr,
3797 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
3798 [GPLL3] = &gpll3.clkr,
3799 [GPLL3_VOTE] = &gpll3_vote,
3800 [GPLL4] = &gpll4.clkr,
3801 [GPLL4_VOTE] = &gpll4_vote,
3802 [GPLL5] = &gpll5.clkr,
3803 [GPLL5_VOTE] = &gpll5_vote,
3804 [GPLL6] = &gpll6.clkr,
3805 [GPLL6_VOTE] = &gpll6_vote,
3806 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
3807 [GCC_MDSS_BYTE1_CLK] = &gcc_mdss_byte1_clk.clkr,
3808 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
3809 [GCC_MDSS_ESC1_CLK] = &gcc_mdss_esc1_clk.clkr,
3810 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
3811 [GCC_MDSS_PCLK1_CLK] = &gcc_mdss_pclk1_clk.clkr,
3812 [GCC_GFX_TBU_CLK] = &gcc_gfx_tbu_clk.clkr,
3813 [GCC_CPP_TBU_CLK] = &gcc_cpp_tbu_clk.clkr,
3814 [GCC_MDP_RT_TBU_CLK] = &gcc_mdp_rt_tbu_clk.clkr,
3815 [USB_FS_SYSTEM_CLK_SRC] = &usb_fs_system_clk_src.clkr,
3816 [USB_FS_IC_CLK_SRC] = &usb_fs_ic_clk_src.clkr,
3817 [GCC_USB_FS_AHB_CLK] = &gcc_usb_fs_ahb_clk.clkr,
3818 [GCC_USB_FS_IC_CLK] = &gcc_usb_fs_ic_clk.clkr,
3819 [GCC_USB_FS_SYSTEM_CLK] = &gcc_usb_fs_system_clk.clkr,
3820 [GCC_VENUS0_CORE0_VCODEC0_CLK] = &gcc_venus0_core0_vcodec0_clk.clkr,
3821 [GCC_VENUS0_CORE1_VCODEC0_CLK] = &gcc_venus0_core1_vcodec0_clk.clkr,
3822 [GCC_OXILI_TIMER_CLK] = &gcc_oxili_timer_clk.clkr,
3825 static struct gdsc *gcc_msm8939_gdscs[] = {
3826 [VENUS_GDSC] = &venus_gdsc,
3827 [MDSS_GDSC] = &mdss_gdsc,
3828 [JPEG_GDSC] = &jpeg_gdsc,
3829 [VFE_GDSC] = &vfe_gdsc,
3830 [OXILI_GDSC] = &oxili_gdsc,
3831 [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
3832 [VENUS_CORE1_GDSC] = &venus_core1_gdsc,
3835 static const struct qcom_reset_map gcc_msm8939_resets[] = {
3836 [GCC_BLSP1_BCR] = { 0x01000 },
3837 [GCC_BLSP1_QUP1_BCR] = { 0x02000 },
3838 [GCC_BLSP1_UART1_BCR] = { 0x02038 },
3839 [GCC_BLSP1_QUP2_BCR] = { 0x03008 },
3840 [GCC_BLSP1_UART2_BCR] = { 0x03028 },
3841 [GCC_BLSP1_QUP3_BCR] = { 0x04018 },
3842 [GCC_BLSP1_UART3_BCR] = { 0x04038 },
3843 [GCC_BLSP1_QUP4_BCR] = { 0x05018 },
3844 [GCC_BLSP1_QUP5_BCR] = { 0x06018 },
3845 [GCC_BLSP1_QUP6_BCR] = { 0x07018 },
3846 [GCC_IMEM_BCR] = { 0x0e000 },
3847 [GCC_SMMU_BCR] = { 0x12000 },
3848 [GCC_APSS_TCU_BCR] = { 0x12050 },
3849 [GCC_SMMU_XPU_BCR] = { 0x12054 },
3850 [GCC_PCNOC_TBU_BCR] = { 0x12058 },
3851 [GCC_PRNG_BCR] = { 0x13000 },
3852 [GCC_BOOT_ROM_BCR] = { 0x13008 },
3853 [GCC_CRYPTO_BCR] = { 0x16000 },
3854 [GCC_SEC_CTRL_BCR] = { 0x1a000 },
3855 [GCC_AUDIO_CORE_BCR] = { 0x1c008 },
3856 [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
3857 [GCC_DEHR_BCR] = { 0x1f000 },
3858 [GCC_SYSTEM_NOC_BCR] = { 0x26000 },
3859 [GCC_PCNOC_BCR] = { 0x27018 },
3860 [GCC_TCSR_BCR] = { 0x28000 },
3861 [GCC_QDSS_BCR] = { 0x29000 },
3862 [GCC_DCD_BCR] = { 0x2a000 },
3863 [GCC_MSG_RAM_BCR] = { 0x2b000 },
3864 [GCC_MPM_BCR] = { 0x2c000 },
3865 [GCC_SPMI_BCR] = { 0x2e000 },
3866 [GCC_SPDM_BCR] = { 0x2f000 },
3867 [GCC_MM_SPDM_BCR] = { 0x2f024 },
3868 [GCC_BIMC_BCR] = { 0x31000 },
3869 [GCC_RBCPR_BCR] = { 0x33000 },
3870 [GCC_TLMM_BCR] = { 0x34000 },
3871 [GCC_CAMSS_CSI2_BCR] = { 0x3c038 },
3872 [GCC_CAMSS_CSI2PHY_BCR] = { 0x3c044 },
3873 [GCC_CAMSS_CSI2RDI_BCR] = { 0x3c04c },
3874 [GCC_CAMSS_CSI2PIX_BCR] = { 0x3c054 },
3875 [GCC_USB_FS_BCR] = { 0x3f000 },
3876 [GCC_USB_HS_BCR] = { 0x41000 },
3877 [GCC_USB2A_PHY_BCR] = { 0x41028 },
3878 [GCC_SDCC1_BCR] = { 0x42000 },
3879 [GCC_SDCC2_BCR] = { 0x43000 },
3880 [GCC_PDM_BCR] = { 0x44000 },
3881 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 },
3882 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 },
3883 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 },
3884 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 },
3885 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 },
3886 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 },
3887 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 },
3888 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 },
3889 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 },
3890 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 },
3891 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 },
3892 [GCC_MMSS_BCR] = { 0x4b000 },
3893 [GCC_VENUS0_BCR] = { 0x4c014 },
3894 [GCC_MDSS_BCR] = { 0x4d074 },
3895 [GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
3896 [GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
3897 [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
3898 [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
3899 [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
3900 [GCC_CAMSS_PHY1_BCR] = { 0x4f018 },
3901 [GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
3902 [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
3903 [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
3904 [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
3905 [GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
3906 [GCC_BLSP1_QUP4_SPI_APPS_CBCR] = { 0x0501c },
3907 [GCC_CAMSS_CCI_BCR] = { 0x51014 },
3908 [GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
3909 [GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
3910 [GCC_CAMSS_GP0_BCR] = { 0x54014 },
3911 [GCC_CAMSS_GP1_BCR] = { 0x55014 },
3912 [GCC_CAMSS_TOP_BCR] = { 0x56000 },
3913 [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
3914 [GCC_CAMSS_JPEG_BCR] = { 0x57018 },
3915 [GCC_CAMSS_VFE_BCR] = { 0x58030 },
3916 [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
3917 [GCC_OXILI_BCR] = { 0x59018 },
3918 [GCC_GMEM_BCR] = { 0x5902c },
3919 [GCC_CAMSS_AHB_BCR] = { 0x5a018 },
3920 [GCC_CAMSS_MCLK2_BCR] = { 0x5c014 },
3921 [GCC_MDP_TBU_BCR] = { 0x62000 },
3922 [GCC_GFX_TBU_BCR] = { 0x63000 },
3923 [GCC_GFX_TCU_BCR] = { 0x64000 },
3924 [GCC_MSS_TBU_AXI_BCR] = { 0x65000 },
3925 [GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 },
3926 [GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 },
3927 [GCC_GTCU_AHB_BCR] = { 0x68000 },
3928 [GCC_SMMU_CFG_BCR] = { 0x69000 },
3929 [GCC_VFE_TBU_BCR] = { 0x6a000 },
3930 [GCC_VENUS_TBU_BCR] = { 0x6b000 },
3931 [GCC_JPEG_TBU_BCR] = { 0x6c000 },
3932 [GCC_PRONTO_TBU_BCR] = { 0x6d000 },
3933 [GCC_CPP_TBU_BCR] = { 0x6e000 },
3934 [GCC_MDP_RT_TBU_BCR] = { 0x6f000 },
3935 [GCC_SMMU_CATS_BCR] = { 0x7c000 },
3938 static const struct regmap_config gcc_msm8939_regmap_config = {
3942 .max_register = 0x80000,
3946 static const struct qcom_cc_desc gcc_msm8939_desc = {
3947 .config = &gcc_msm8939_regmap_config,
3948 .clks = gcc_msm8939_clocks,
3949 .num_clks = ARRAY_SIZE(gcc_msm8939_clocks),
3950 .resets = gcc_msm8939_resets,
3951 .num_resets = ARRAY_SIZE(gcc_msm8939_resets),
3952 .gdscs = gcc_msm8939_gdscs,
3953 .num_gdscs = ARRAY_SIZE(gcc_msm8939_gdscs),
3956 static const struct of_device_id gcc_msm8939_match_table[] = {
3957 { .compatible = "qcom,gcc-msm8939" },
3960 MODULE_DEVICE_TABLE(of, gcc_msm8939_match_table);
3962 static int gcc_msm8939_probe(struct platform_device *pdev)
3964 struct regmap *regmap;
3966 regmap = qcom_cc_map(pdev, &gcc_msm8939_desc);
3968 return PTR_ERR(regmap);
3970 clk_pll_configure_sr_hpm_lp(&gpll3, regmap, &gpll3_config, true);
3971 clk_pll_configure_sr_hpm_lp(&gpll4, regmap, &gpll4_config, true);
3973 return qcom_cc_really_probe(pdev, &gcc_msm8939_desc, regmap);
3976 static struct platform_driver gcc_msm8939_driver = {
3977 .probe = gcc_msm8939_probe,
3979 .name = "gcc-msm8939",
3980 .of_match_table = gcc_msm8939_match_table,
3984 static int __init gcc_msm8939_init(void)
3986 return platform_driver_register(&gcc_msm8939_driver);
3988 core_initcall(gcc_msm8939_init);
3990 static void __exit gcc_msm8939_exit(void)
3992 platform_driver_unregister(&gcc_msm8939_driver);
3994 module_exit(gcc_msm8939_exit);
3996 MODULE_DESCRIPTION("Qualcomm GCC MSM8939 Driver");
3997 MODULE_LICENSE("GPL v2");