1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2015 Linaro Limited
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/clk-provider.h>
14 #include <linux/regmap.h>
15 #include <linux/reset-controller.h>
17 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
18 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
21 #include "clk-regmap.h"
24 #include "clk-branch.h"
45 static const struct parent_map gcc_xo_gpll0_map[] = {
50 static const char * const gcc_xo_gpll0[] = {
55 static const struct parent_map gcc_xo_gpll0_bimc_map[] = {
61 static const char * const gcc_xo_gpll0_bimc[] = {
67 static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2a_map[] = {
74 static const char * const gcc_xo_gpll0a_gpll1_gpll2a[] = {
81 static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
87 static const char * const gcc_xo_gpll0_gpll2[] = {
93 static const struct parent_map gcc_xo_gpll0a_map[] = {
98 static const char * const gcc_xo_gpll0a[] = {
103 static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = {
110 static const char * const gcc_xo_gpll0_gpll1a_sleep[] = {
117 static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = {
123 static const char * const gcc_xo_gpll0_gpll1a[] = {
129 static const struct parent_map gcc_xo_dsibyte_map[] = {
131 { P_DSI0_PHYPLL_BYTE, 2 },
134 static const char * const gcc_xo_dsibyte[] = {
139 static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = {
142 { P_DSI0_PHYPLL_BYTE, 1 },
145 static const char * const gcc_xo_gpll0a_dsibyte[] = {
151 static const struct parent_map gcc_xo_gpll0_dsiphy_map[] = {
154 { P_DSI0_PHYPLL_DSI, 2 },
157 static const char * const gcc_xo_gpll0_dsiphy[] = {
163 static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = {
166 { P_DSI0_PHYPLL_DSI, 1 },
169 static const char * const gcc_xo_gpll0a_dsiphy[] = {
175 static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2_map[] = {
182 static const char * const gcc_xo_gpll0a_gpll1_gpll2[] = {
189 static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = {
196 static const char * const gcc_xo_gpll0_gpll1_sleep[] = {
203 static const struct parent_map gcc_xo_gpll1_epi2s_emclk_sleep_map[] = {
206 { P_EXT_PRI_I2S, 2 },
211 static const char * const gcc_xo_gpll1_epi2s_emclk_sleep[] = {
219 static const struct parent_map gcc_xo_gpll1_esi2s_emclk_sleep_map[] = {
222 { P_EXT_SEC_I2S, 2 },
227 static const char * const gcc_xo_gpll1_esi2s_emclk_sleep[] = {
235 static const struct parent_map gcc_xo_sleep_map[] = {
240 static const char * const gcc_xo_sleep[] = {
245 static const struct parent_map gcc_xo_gpll1_emclk_sleep_map[] = {
252 static const char * const gcc_xo_gpll1_emclk_sleep[] = {
259 static struct clk_pll gpll0 = {
263 .config_reg = 0x21010,
265 .status_reg = 0x2101c,
267 .clkr.hw.init = &(struct clk_init_data){
269 .parent_names = (const char *[]){ "xo" },
275 static struct clk_regmap gpll0_vote = {
276 .enable_reg = 0x45000,
277 .enable_mask = BIT(0),
278 .hw.init = &(struct clk_init_data){
279 .name = "gpll0_vote",
280 .parent_names = (const char *[]){ "gpll0" },
282 .ops = &clk_pll_vote_ops,
286 static struct clk_pll gpll1 = {
290 .config_reg = 0x20010,
292 .status_reg = 0x2001c,
294 .clkr.hw.init = &(struct clk_init_data){
296 .parent_names = (const char *[]){ "xo" },
302 static struct clk_regmap gpll1_vote = {
303 .enable_reg = 0x45000,
304 .enable_mask = BIT(1),
305 .hw.init = &(struct clk_init_data){
306 .name = "gpll1_vote",
307 .parent_names = (const char *[]){ "gpll1" },
309 .ops = &clk_pll_vote_ops,
313 static struct clk_pll gpll2 = {
317 .config_reg = 0x4a010,
319 .status_reg = 0x4a01c,
321 .clkr.hw.init = &(struct clk_init_data){
323 .parent_names = (const char *[]){ "xo" },
329 static struct clk_regmap gpll2_vote = {
330 .enable_reg = 0x45000,
331 .enable_mask = BIT(2),
332 .hw.init = &(struct clk_init_data){
333 .name = "gpll2_vote",
334 .parent_names = (const char *[]){ "gpll2" },
336 .ops = &clk_pll_vote_ops,
340 static struct clk_pll bimc_pll = {
344 .config_reg = 0x23010,
346 .status_reg = 0x2301c,
348 .clkr.hw.init = &(struct clk_init_data){
350 .parent_names = (const char *[]){ "xo" },
356 static struct clk_regmap bimc_pll_vote = {
357 .enable_reg = 0x45000,
358 .enable_mask = BIT(3),
359 .hw.init = &(struct clk_init_data){
360 .name = "bimc_pll_vote",
361 .parent_names = (const char *[]){ "bimc_pll" },
363 .ops = &clk_pll_vote_ops,
367 static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
370 .parent_map = gcc_xo_gpll0_bimc_map,
371 .clkr.hw.init = &(struct clk_init_data){
372 .name = "pcnoc_bfdcd_clk_src",
373 .parent_names = gcc_xo_gpll0_bimc,
375 .ops = &clk_rcg2_ops,
379 static struct clk_rcg2 system_noc_bfdcd_clk_src = {
382 .parent_map = gcc_xo_gpll0_bimc_map,
383 .clkr.hw.init = &(struct clk_init_data){
384 .name = "system_noc_bfdcd_clk_src",
385 .parent_names = gcc_xo_gpll0_bimc,
387 .ops = &clk_rcg2_ops,
391 static const struct freq_tbl ftbl_gcc_camss_ahb_clk[] = {
392 F(40000000, P_GPLL0, 10, 1, 2),
393 F(80000000, P_GPLL0, 10, 0, 0),
397 static struct clk_rcg2 camss_ahb_clk_src = {
401 .parent_map = gcc_xo_gpll0_map,
402 .freq_tbl = ftbl_gcc_camss_ahb_clk,
403 .clkr.hw.init = &(struct clk_init_data){
404 .name = "camss_ahb_clk_src",
405 .parent_names = gcc_xo_gpll0,
407 .ops = &clk_rcg2_ops,
411 static const struct freq_tbl ftbl_apss_ahb_clk[] = {
412 F(19200000, P_XO, 1, 0, 0),
413 F(50000000, P_GPLL0, 16, 0, 0),
414 F(100000000, P_GPLL0, 8, 0, 0),
415 F(133330000, P_GPLL0, 6, 0, 0),
419 static struct clk_rcg2 apss_ahb_clk_src = {
422 .parent_map = gcc_xo_gpll0_map,
423 .freq_tbl = ftbl_apss_ahb_clk,
424 .clkr.hw.init = &(struct clk_init_data){
425 .name = "apss_ahb_clk_src",
426 .parent_names = gcc_xo_gpll0,
428 .ops = &clk_rcg2_ops,
432 static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = {
433 F(100000000, P_GPLL0, 8, 0, 0),
434 F(200000000, P_GPLL0, 4, 0, 0),
438 static struct clk_rcg2 csi0_clk_src = {
441 .parent_map = gcc_xo_gpll0_map,
442 .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
443 .clkr.hw.init = &(struct clk_init_data){
444 .name = "csi0_clk_src",
445 .parent_names = gcc_xo_gpll0,
447 .ops = &clk_rcg2_ops,
451 static struct clk_rcg2 csi1_clk_src = {
454 .parent_map = gcc_xo_gpll0_map,
455 .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
456 .clkr.hw.init = &(struct clk_init_data){
457 .name = "csi1_clk_src",
458 .parent_names = gcc_xo_gpll0,
460 .ops = &clk_rcg2_ops,
464 static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
465 F(19200000, P_XO, 1, 0, 0),
466 F(50000000, P_GPLL0_AUX, 16, 0, 0),
467 F(80000000, P_GPLL0_AUX, 10, 0, 0),
468 F(100000000, P_GPLL0_AUX, 8, 0, 0),
469 F(160000000, P_GPLL0_AUX, 5, 0, 0),
470 F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
471 F(200000000, P_GPLL0_AUX, 4, 0, 0),
472 F(266670000, P_GPLL0_AUX, 3, 0, 0),
473 F(294912000, P_GPLL1, 3, 0, 0),
474 F(310000000, P_GPLL2, 3, 0, 0),
475 F(400000000, P_GPLL0_AUX, 2, 0, 0),
479 static struct clk_rcg2 gfx3d_clk_src = {
482 .parent_map = gcc_xo_gpll0a_gpll1_gpll2a_map,
483 .freq_tbl = ftbl_gcc_oxili_gfx3d_clk,
484 .clkr.hw.init = &(struct clk_init_data){
485 .name = "gfx3d_clk_src",
486 .parent_names = gcc_xo_gpll0a_gpll1_gpll2a,
488 .ops = &clk_rcg2_ops,
492 static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] = {
493 F(50000000, P_GPLL0, 16, 0, 0),
494 F(80000000, P_GPLL0, 10, 0, 0),
495 F(100000000, P_GPLL0, 8, 0, 0),
496 F(160000000, P_GPLL0, 5, 0, 0),
497 F(177780000, P_GPLL0, 4.5, 0, 0),
498 F(200000000, P_GPLL0, 4, 0, 0),
499 F(266670000, P_GPLL0, 3, 0, 0),
500 F(320000000, P_GPLL0, 2.5, 0, 0),
501 F(400000000, P_GPLL0, 2, 0, 0),
502 F(465000000, P_GPLL2, 2, 0, 0),
506 static struct clk_rcg2 vfe0_clk_src = {
509 .parent_map = gcc_xo_gpll0_gpll2_map,
510 .freq_tbl = ftbl_gcc_camss_vfe0_clk,
511 .clkr.hw.init = &(struct clk_init_data){
512 .name = "vfe0_clk_src",
513 .parent_names = gcc_xo_gpll0_gpll2,
515 .ops = &clk_rcg2_ops,
519 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
520 F(19200000, P_XO, 1, 0, 0),
521 F(50000000, P_GPLL0, 16, 0, 0),
525 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
528 .parent_map = gcc_xo_gpll0_map,
529 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
530 .clkr.hw.init = &(struct clk_init_data){
531 .name = "blsp1_qup1_i2c_apps_clk_src",
532 .parent_names = gcc_xo_gpll0,
534 .ops = &clk_rcg2_ops,
538 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
539 F(100000, P_XO, 16, 2, 24),
540 F(250000, P_XO, 16, 5, 24),
541 F(500000, P_XO, 8, 5, 24),
542 F(960000, P_XO, 10, 1, 2),
543 F(1000000, P_XO, 4, 5, 24),
544 F(4800000, P_XO, 4, 0, 0),
545 F(9600000, P_XO, 2, 0, 0),
546 F(16000000, P_GPLL0, 10, 1, 5),
547 F(19200000, P_XO, 1, 0, 0),
548 F(25000000, P_GPLL0, 16, 1, 2),
549 F(50000000, P_GPLL0, 16, 0, 0),
553 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
557 .parent_map = gcc_xo_gpll0_map,
558 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
559 .clkr.hw.init = &(struct clk_init_data){
560 .name = "blsp1_qup1_spi_apps_clk_src",
561 .parent_names = gcc_xo_gpll0,
563 .ops = &clk_rcg2_ops,
567 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
570 .parent_map = gcc_xo_gpll0_map,
571 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
572 .clkr.hw.init = &(struct clk_init_data){
573 .name = "blsp1_qup2_i2c_apps_clk_src",
574 .parent_names = gcc_xo_gpll0,
576 .ops = &clk_rcg2_ops,
580 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
584 .parent_map = gcc_xo_gpll0_map,
585 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
586 .clkr.hw.init = &(struct clk_init_data){
587 .name = "blsp1_qup2_spi_apps_clk_src",
588 .parent_names = gcc_xo_gpll0,
590 .ops = &clk_rcg2_ops,
594 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
597 .parent_map = gcc_xo_gpll0_map,
598 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
599 .clkr.hw.init = &(struct clk_init_data){
600 .name = "blsp1_qup3_i2c_apps_clk_src",
601 .parent_names = gcc_xo_gpll0,
603 .ops = &clk_rcg2_ops,
607 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
611 .parent_map = gcc_xo_gpll0_map,
612 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
613 .clkr.hw.init = &(struct clk_init_data){
614 .name = "blsp1_qup3_spi_apps_clk_src",
615 .parent_names = gcc_xo_gpll0,
617 .ops = &clk_rcg2_ops,
621 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
624 .parent_map = gcc_xo_gpll0_map,
625 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
626 .clkr.hw.init = &(struct clk_init_data){
627 .name = "blsp1_qup4_i2c_apps_clk_src",
628 .parent_names = gcc_xo_gpll0,
630 .ops = &clk_rcg2_ops,
634 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
638 .parent_map = gcc_xo_gpll0_map,
639 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
640 .clkr.hw.init = &(struct clk_init_data){
641 .name = "blsp1_qup4_spi_apps_clk_src",
642 .parent_names = gcc_xo_gpll0,
644 .ops = &clk_rcg2_ops,
648 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
651 .parent_map = gcc_xo_gpll0_map,
652 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
653 .clkr.hw.init = &(struct clk_init_data){
654 .name = "blsp1_qup5_i2c_apps_clk_src",
655 .parent_names = gcc_xo_gpll0,
657 .ops = &clk_rcg2_ops,
661 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
665 .parent_map = gcc_xo_gpll0_map,
666 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
667 .clkr.hw.init = &(struct clk_init_data){
668 .name = "blsp1_qup5_spi_apps_clk_src",
669 .parent_names = gcc_xo_gpll0,
671 .ops = &clk_rcg2_ops,
675 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
678 .parent_map = gcc_xo_gpll0_map,
679 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
680 .clkr.hw.init = &(struct clk_init_data){
681 .name = "blsp1_qup6_i2c_apps_clk_src",
682 .parent_names = gcc_xo_gpll0,
684 .ops = &clk_rcg2_ops,
688 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
692 .parent_map = gcc_xo_gpll0_map,
693 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
694 .clkr.hw.init = &(struct clk_init_data){
695 .name = "blsp1_qup6_spi_apps_clk_src",
696 .parent_names = gcc_xo_gpll0,
698 .ops = &clk_rcg2_ops,
702 static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
703 F(3686400, P_GPLL0, 1, 72, 15625),
704 F(7372800, P_GPLL0, 1, 144, 15625),
705 F(14745600, P_GPLL0, 1, 288, 15625),
706 F(16000000, P_GPLL0, 10, 1, 5),
707 F(19200000, P_XO, 1, 0, 0),
708 F(24000000, P_GPLL0, 1, 3, 100),
709 F(25000000, P_GPLL0, 16, 1, 2),
710 F(32000000, P_GPLL0, 1, 1, 25),
711 F(40000000, P_GPLL0, 1, 1, 20),
712 F(46400000, P_GPLL0, 1, 29, 500),
713 F(48000000, P_GPLL0, 1, 3, 50),
714 F(51200000, P_GPLL0, 1, 8, 125),
715 F(56000000, P_GPLL0, 1, 7, 100),
716 F(58982400, P_GPLL0, 1, 1152, 15625),
717 F(60000000, P_GPLL0, 1, 3, 40),
721 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
725 .parent_map = gcc_xo_gpll0_map,
726 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
727 .clkr.hw.init = &(struct clk_init_data){
728 .name = "blsp1_uart1_apps_clk_src",
729 .parent_names = gcc_xo_gpll0,
731 .ops = &clk_rcg2_ops,
735 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
739 .parent_map = gcc_xo_gpll0_map,
740 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
741 .clkr.hw.init = &(struct clk_init_data){
742 .name = "blsp1_uart2_apps_clk_src",
743 .parent_names = gcc_xo_gpll0,
745 .ops = &clk_rcg2_ops,
749 static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = {
750 F(19200000, P_XO, 1, 0, 0),
754 static struct clk_rcg2 cci_clk_src = {
758 .parent_map = gcc_xo_gpll0a_map,
759 .freq_tbl = ftbl_gcc_camss_cci_clk,
760 .clkr.hw.init = &(struct clk_init_data){
761 .name = "cci_clk_src",
762 .parent_names = gcc_xo_gpll0a,
764 .ops = &clk_rcg2_ops,
769 * This is a frequency table for "General Purpose" clocks.
770 * These clocks can be muxed to the SoC pins and may be used by
771 * external devices. They're often used as PWM source.
773 * See comment at ftbl_gcc_gp1_3_clk.
775 static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = {
776 F(10000, P_XO, 16, 1, 120),
777 F(100000, P_XO, 16, 1, 12),
778 F(500000, P_GPLL0, 16, 1, 100),
779 F(1000000, P_GPLL0, 16, 1, 50),
780 F(2500000, P_GPLL0, 16, 1, 20),
781 F(5000000, P_GPLL0, 16, 1, 10),
782 F(100000000, P_GPLL0, 8, 0, 0),
783 F(200000000, P_GPLL0, 4, 0, 0),
787 static struct clk_rcg2 camss_gp0_clk_src = {
791 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
792 .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
793 .clkr.hw.init = &(struct clk_init_data){
794 .name = "camss_gp0_clk_src",
795 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
797 .ops = &clk_rcg2_ops,
801 static struct clk_rcg2 camss_gp1_clk_src = {
805 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
806 .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
807 .clkr.hw.init = &(struct clk_init_data){
808 .name = "camss_gp1_clk_src",
809 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
811 .ops = &clk_rcg2_ops,
815 static const struct freq_tbl ftbl_gcc_camss_jpeg0_clk[] = {
816 F(133330000, P_GPLL0, 6, 0, 0),
817 F(266670000, P_GPLL0, 3, 0, 0),
818 F(320000000, P_GPLL0, 2.5, 0, 0),
822 static struct clk_rcg2 jpeg0_clk_src = {
825 .parent_map = gcc_xo_gpll0_map,
826 .freq_tbl = ftbl_gcc_camss_jpeg0_clk,
827 .clkr.hw.init = &(struct clk_init_data){
828 .name = "jpeg0_clk_src",
829 .parent_names = gcc_xo_gpll0,
831 .ops = &clk_rcg2_ops,
835 static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = {
836 F(9600000, P_XO, 2, 0, 0),
837 F(23880000, P_GPLL0, 1, 2, 67),
838 F(66670000, P_GPLL0, 12, 0, 0),
842 static struct clk_rcg2 mclk0_clk_src = {
846 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
847 .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
848 .clkr.hw.init = &(struct clk_init_data){
849 .name = "mclk0_clk_src",
850 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
852 .ops = &clk_rcg2_ops,
856 static struct clk_rcg2 mclk1_clk_src = {
860 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
861 .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
862 .clkr.hw.init = &(struct clk_init_data){
863 .name = "mclk1_clk_src",
864 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
866 .ops = &clk_rcg2_ops,
870 static const struct freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = {
871 F(100000000, P_GPLL0, 8, 0, 0),
872 F(200000000, P_GPLL0, 4, 0, 0),
876 static struct clk_rcg2 csi0phytimer_clk_src = {
879 .parent_map = gcc_xo_gpll0_gpll1a_map,
880 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
881 .clkr.hw.init = &(struct clk_init_data){
882 .name = "csi0phytimer_clk_src",
883 .parent_names = gcc_xo_gpll0_gpll1a,
885 .ops = &clk_rcg2_ops,
889 static struct clk_rcg2 csi1phytimer_clk_src = {
892 .parent_map = gcc_xo_gpll0_gpll1a_map,
893 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
894 .clkr.hw.init = &(struct clk_init_data){
895 .name = "csi1phytimer_clk_src",
896 .parent_names = gcc_xo_gpll0_gpll1a,
898 .ops = &clk_rcg2_ops,
902 static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = {
903 F(160000000, P_GPLL0, 5, 0, 0),
904 F(320000000, P_GPLL0, 2.5, 0, 0),
905 F(465000000, P_GPLL2, 2, 0, 0),
909 static struct clk_rcg2 cpp_clk_src = {
912 .parent_map = gcc_xo_gpll0_gpll2_map,
913 .freq_tbl = ftbl_gcc_camss_cpp_clk,
914 .clkr.hw.init = &(struct clk_init_data){
915 .name = "cpp_clk_src",
916 .parent_names = gcc_xo_gpll0_gpll2,
918 .ops = &clk_rcg2_ops,
922 static const struct freq_tbl ftbl_gcc_crypto_clk[] = {
923 F(50000000, P_GPLL0, 16, 0, 0),
924 F(80000000, P_GPLL0, 10, 0, 0),
925 F(100000000, P_GPLL0, 8, 0, 0),
926 F(160000000, P_GPLL0, 5, 0, 0),
930 static struct clk_rcg2 crypto_clk_src = {
933 .parent_map = gcc_xo_gpll0_map,
934 .freq_tbl = ftbl_gcc_crypto_clk,
935 .clkr.hw.init = &(struct clk_init_data){
936 .name = "crypto_clk_src",
937 .parent_names = gcc_xo_gpll0,
939 .ops = &clk_rcg2_ops,
944 * This is a frequency table for "General Purpose" clocks.
945 * These clocks can be muxed to the SoC pins and may be used by
946 * external devices. They're often used as PWM source.
948 * Please note that MND divider must be enabled for duty-cycle
949 * control to be possible. (M != N) Also since D register is configured
950 * with a value multiplied by 2, and duty cycle is calculated as
952 * DutyCycle = ----------------
954 * (where W = .mnd_width)
955 * N must be half or less than maximum value for the register.
956 * Otherwise duty-cycle control would be limited.
957 * (e.g. for 8-bit NMD N should be less than 128)
959 static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = {
960 F(10000, P_XO, 16, 1, 120),
961 F(100000, P_XO, 16, 1, 12),
962 F(500000, P_GPLL0, 16, 1, 100),
963 F(1000000, P_GPLL0, 16, 1, 50),
964 F(2500000, P_GPLL0, 16, 1, 20),
965 F(5000000, P_GPLL0, 16, 1, 10),
966 F(19200000, P_XO, 1, 0, 0),
970 static struct clk_rcg2 gp1_clk_src = {
974 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
975 .freq_tbl = ftbl_gcc_gp1_3_clk,
976 .clkr.hw.init = &(struct clk_init_data){
977 .name = "gp1_clk_src",
978 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
980 .ops = &clk_rcg2_ops,
984 static struct clk_rcg2 gp2_clk_src = {
988 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
989 .freq_tbl = ftbl_gcc_gp1_3_clk,
990 .clkr.hw.init = &(struct clk_init_data){
991 .name = "gp2_clk_src",
992 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
994 .ops = &clk_rcg2_ops,
998 static struct clk_rcg2 gp3_clk_src = {
1002 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
1003 .freq_tbl = ftbl_gcc_gp1_3_clk,
1004 .clkr.hw.init = &(struct clk_init_data){
1005 .name = "gp3_clk_src",
1006 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
1008 .ops = &clk_rcg2_ops,
1012 static struct clk_rcg2 byte0_clk_src = {
1013 .cmd_rcgr = 0x4d044,
1015 .parent_map = gcc_xo_gpll0a_dsibyte_map,
1016 .clkr.hw.init = &(struct clk_init_data){
1017 .name = "byte0_clk_src",
1018 .parent_names = gcc_xo_gpll0a_dsibyte,
1020 .ops = &clk_byte2_ops,
1021 .flags = CLK_SET_RATE_PARENT,
1025 static const struct freq_tbl ftbl_gcc_mdss_esc0_clk[] = {
1026 F(19200000, P_XO, 1, 0, 0),
1030 static struct clk_rcg2 esc0_clk_src = {
1031 .cmd_rcgr = 0x4d05c,
1033 .parent_map = gcc_xo_dsibyte_map,
1034 .freq_tbl = ftbl_gcc_mdss_esc0_clk,
1035 .clkr.hw.init = &(struct clk_init_data){
1036 .name = "esc0_clk_src",
1037 .parent_names = gcc_xo_dsibyte,
1039 .ops = &clk_rcg2_ops,
1043 static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
1044 F(50000000, P_GPLL0, 16, 0, 0),
1045 F(80000000, P_GPLL0, 10, 0, 0),
1046 F(100000000, P_GPLL0, 8, 0, 0),
1047 F(160000000, P_GPLL0, 5, 0, 0),
1048 F(177780000, P_GPLL0, 4.5, 0, 0),
1049 F(200000000, P_GPLL0, 4, 0, 0),
1050 F(266670000, P_GPLL0, 3, 0, 0),
1051 F(320000000, P_GPLL0, 2.5, 0, 0),
1055 static struct clk_rcg2 mdp_clk_src = {
1056 .cmd_rcgr = 0x4d014,
1058 .parent_map = gcc_xo_gpll0_dsiphy_map,
1059 .freq_tbl = ftbl_gcc_mdss_mdp_clk,
1060 .clkr.hw.init = &(struct clk_init_data){
1061 .name = "mdp_clk_src",
1062 .parent_names = gcc_xo_gpll0_dsiphy,
1064 .ops = &clk_rcg2_ops,
1068 static struct clk_rcg2 pclk0_clk_src = {
1069 .cmd_rcgr = 0x4d000,
1072 .parent_map = gcc_xo_gpll0a_dsiphy_map,
1073 .clkr.hw.init = &(struct clk_init_data){
1074 .name = "pclk0_clk_src",
1075 .parent_names = gcc_xo_gpll0a_dsiphy,
1077 .ops = &clk_pixel_ops,
1078 .flags = CLK_SET_RATE_PARENT,
1082 static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
1083 F(19200000, P_XO, 1, 0, 0),
1087 static struct clk_rcg2 vsync_clk_src = {
1088 .cmd_rcgr = 0x4d02c,
1090 .parent_map = gcc_xo_gpll0a_map,
1091 .freq_tbl = ftbl_gcc_mdss_vsync_clk,
1092 .clkr.hw.init = &(struct clk_init_data){
1093 .name = "vsync_clk_src",
1094 .parent_names = gcc_xo_gpll0a,
1096 .ops = &clk_rcg2_ops,
1100 static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
1101 F(64000000, P_GPLL0, 12.5, 0, 0),
1105 static struct clk_rcg2 pdm2_clk_src = {
1106 .cmd_rcgr = 0x44010,
1108 .parent_map = gcc_xo_gpll0_map,
1109 .freq_tbl = ftbl_gcc_pdm2_clk,
1110 .clkr.hw.init = &(struct clk_init_data){
1111 .name = "pdm2_clk_src",
1112 .parent_names = gcc_xo_gpll0,
1114 .ops = &clk_rcg2_ops,
1118 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
1119 F(144000, P_XO, 16, 3, 25),
1120 F(400000, P_XO, 12, 1, 4),
1121 F(20000000, P_GPLL0, 10, 1, 4),
1122 F(25000000, P_GPLL0, 16, 1, 2),
1123 F(50000000, P_GPLL0, 16, 0, 0),
1124 F(100000000, P_GPLL0, 8, 0, 0),
1125 F(177770000, P_GPLL0, 4.5, 0, 0),
1129 static struct clk_rcg2 sdcc1_apps_clk_src = {
1130 .cmd_rcgr = 0x42004,
1133 .parent_map = gcc_xo_gpll0_map,
1134 .freq_tbl = ftbl_gcc_sdcc1_apps_clk,
1135 .clkr.hw.init = &(struct clk_init_data){
1136 .name = "sdcc1_apps_clk_src",
1137 .parent_names = gcc_xo_gpll0,
1139 .ops = &clk_rcg2_floor_ops,
1143 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk[] = {
1144 F(144000, P_XO, 16, 3, 25),
1145 F(400000, P_XO, 12, 1, 4),
1146 F(20000000, P_GPLL0, 10, 1, 4),
1147 F(25000000, P_GPLL0, 16, 1, 2),
1148 F(50000000, P_GPLL0, 16, 0, 0),
1149 F(100000000, P_GPLL0, 8, 0, 0),
1150 F(200000000, P_GPLL0, 4, 0, 0),
1154 static struct clk_rcg2 sdcc2_apps_clk_src = {
1155 .cmd_rcgr = 0x43004,
1158 .parent_map = gcc_xo_gpll0_map,
1159 .freq_tbl = ftbl_gcc_sdcc2_apps_clk,
1160 .clkr.hw.init = &(struct clk_init_data){
1161 .name = "sdcc2_apps_clk_src",
1162 .parent_names = gcc_xo_gpll0,
1164 .ops = &clk_rcg2_floor_ops,
1168 static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = {
1169 F(155000000, P_GPLL2, 6, 0, 0),
1170 F(310000000, P_GPLL2, 3, 0, 0),
1171 F(400000000, P_GPLL0, 2, 0, 0),
1175 static struct clk_rcg2 apss_tcu_clk_src = {
1176 .cmd_rcgr = 0x1207c,
1178 .parent_map = gcc_xo_gpll0a_gpll1_gpll2_map,
1179 .freq_tbl = ftbl_gcc_apss_tcu_clk,
1180 .clkr.hw.init = &(struct clk_init_data){
1181 .name = "apss_tcu_clk_src",
1182 .parent_names = gcc_xo_gpll0a_gpll1_gpll2,
1184 .ops = &clk_rcg2_ops,
1188 static const struct freq_tbl ftbl_gcc_bimc_gpu_clk[] = {
1189 F(19200000, P_XO, 1, 0, 0),
1190 F(100000000, P_GPLL0, 8, 0, 0),
1191 F(200000000, P_GPLL0, 4, 0, 0),
1192 F(266500000, P_BIMC, 4, 0, 0),
1193 F(400000000, P_GPLL0, 2, 0, 0),
1194 F(533000000, P_BIMC, 2, 0, 0),
1198 static struct clk_rcg2 bimc_gpu_clk_src = {
1199 .cmd_rcgr = 0x31028,
1201 .parent_map = gcc_xo_gpll0_bimc_map,
1202 .freq_tbl = ftbl_gcc_bimc_gpu_clk,
1203 .clkr.hw.init = &(struct clk_init_data){
1204 .name = "bimc_gpu_clk_src",
1205 .parent_names = gcc_xo_gpll0_bimc,
1207 .flags = CLK_GET_RATE_NOCACHE,
1208 .ops = &clk_rcg2_ops,
1212 static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
1213 F(80000000, P_GPLL0, 10, 0, 0),
1217 static struct clk_rcg2 usb_hs_system_clk_src = {
1218 .cmd_rcgr = 0x41010,
1220 .parent_map = gcc_xo_gpll0_map,
1221 .freq_tbl = ftbl_gcc_usb_hs_system_clk,
1222 .clkr.hw.init = &(struct clk_init_data){
1223 .name = "usb_hs_system_clk_src",
1224 .parent_names = gcc_xo_gpll0,
1226 .ops = &clk_rcg2_ops,
1230 static const struct freq_tbl ftbl_gcc_ultaudio_ahb_clk[] = {
1231 F(3200000, P_XO, 6, 0, 0),
1232 F(6400000, P_XO, 3, 0, 0),
1233 F(9600000, P_XO, 2, 0, 0),
1234 F(19200000, P_XO, 1, 0, 0),
1235 F(40000000, P_GPLL0, 10, 1, 2),
1236 F(66670000, P_GPLL0, 12, 0, 0),
1237 F(80000000, P_GPLL0, 10, 0, 0),
1238 F(100000000, P_GPLL0, 8, 0, 0),
1242 static struct clk_rcg2 ultaudio_ahbfabric_clk_src = {
1243 .cmd_rcgr = 0x1c010,
1246 .parent_map = gcc_xo_gpll0_gpll1_sleep_map,
1247 .freq_tbl = ftbl_gcc_ultaudio_ahb_clk,
1248 .clkr.hw.init = &(struct clk_init_data){
1249 .name = "ultaudio_ahbfabric_clk_src",
1250 .parent_names = gcc_xo_gpll0_gpll1_sleep,
1252 .ops = &clk_rcg2_ops,
1256 static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_clk = {
1257 .halt_reg = 0x1c028,
1259 .enable_reg = 0x1c028,
1260 .enable_mask = BIT(0),
1261 .hw.init = &(struct clk_init_data){
1262 .name = "gcc_ultaudio_ahbfabric_ixfabric_clk",
1263 .parent_names = (const char *[]){
1264 "ultaudio_ahbfabric_clk_src",
1267 .flags = CLK_SET_RATE_PARENT,
1268 .ops = &clk_branch2_ops,
1273 static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk = {
1274 .halt_reg = 0x1c024,
1276 .enable_reg = 0x1c024,
1277 .enable_mask = BIT(0),
1278 .hw.init = &(struct clk_init_data){
1279 .name = "gcc_ultaudio_ahbfabric_ixfabric_lpm_clk",
1280 .parent_names = (const char *[]){
1281 "ultaudio_ahbfabric_clk_src",
1284 .flags = CLK_SET_RATE_PARENT,
1285 .ops = &clk_branch2_ops,
1290 static const struct freq_tbl ftbl_gcc_ultaudio_lpaif_i2s_clk[] = {
1291 F(128000, P_XO, 10, 1, 15),
1292 F(256000, P_XO, 5, 1, 15),
1293 F(384000, P_XO, 5, 1, 10),
1294 F(512000, P_XO, 5, 2, 15),
1295 F(576000, P_XO, 5, 3, 20),
1296 F(705600, P_GPLL1, 16, 1, 80),
1297 F(768000, P_XO, 5, 1, 5),
1298 F(800000, P_XO, 5, 5, 24),
1299 F(1024000, P_XO, 5, 4, 15),
1300 F(1152000, P_XO, 1, 3, 50),
1301 F(1411200, P_GPLL1, 16, 1, 40),
1302 F(1536000, P_XO, 1, 2, 25),
1303 F(1600000, P_XO, 12, 0, 0),
1304 F(1728000, P_XO, 5, 9, 20),
1305 F(2048000, P_XO, 5, 8, 15),
1306 F(2304000, P_XO, 5, 3, 5),
1307 F(2400000, P_XO, 8, 0, 0),
1308 F(2822400, P_GPLL1, 16, 1, 20),
1309 F(3072000, P_XO, 5, 4, 5),
1310 F(4096000, P_GPLL1, 9, 2, 49),
1311 F(4800000, P_XO, 4, 0, 0),
1312 F(5644800, P_GPLL1, 16, 1, 10),
1313 F(6144000, P_GPLL1, 7, 1, 21),
1314 F(8192000, P_GPLL1, 9, 4, 49),
1315 F(9600000, P_XO, 2, 0, 0),
1316 F(11289600, P_GPLL1, 16, 1, 5),
1317 F(12288000, P_GPLL1, 7, 2, 21),
1321 static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = {
1322 .cmd_rcgr = 0x1c054,
1325 .parent_map = gcc_xo_gpll1_epi2s_emclk_sleep_map,
1326 .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1327 .clkr.hw.init = &(struct clk_init_data){
1328 .name = "ultaudio_lpaif_pri_i2s_clk_src",
1329 .parent_names = gcc_xo_gpll1_epi2s_emclk_sleep,
1331 .ops = &clk_rcg2_ops,
1335 static struct clk_branch gcc_ultaudio_lpaif_pri_i2s_clk = {
1336 .halt_reg = 0x1c068,
1338 .enable_reg = 0x1c068,
1339 .enable_mask = BIT(0),
1340 .hw.init = &(struct clk_init_data){
1341 .name = "gcc_ultaudio_lpaif_pri_i2s_clk",
1342 .parent_names = (const char *[]){
1343 "ultaudio_lpaif_pri_i2s_clk_src",
1346 .flags = CLK_SET_RATE_PARENT,
1347 .ops = &clk_branch2_ops,
1352 static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = {
1353 .cmd_rcgr = 0x1c06c,
1356 .parent_map = gcc_xo_gpll1_esi2s_emclk_sleep_map,
1357 .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1358 .clkr.hw.init = &(struct clk_init_data){
1359 .name = "ultaudio_lpaif_sec_i2s_clk_src",
1360 .parent_names = gcc_xo_gpll1_esi2s_emclk_sleep,
1362 .ops = &clk_rcg2_ops,
1366 static struct clk_branch gcc_ultaudio_lpaif_sec_i2s_clk = {
1367 .halt_reg = 0x1c080,
1369 .enable_reg = 0x1c080,
1370 .enable_mask = BIT(0),
1371 .hw.init = &(struct clk_init_data){
1372 .name = "gcc_ultaudio_lpaif_sec_i2s_clk",
1373 .parent_names = (const char *[]){
1374 "ultaudio_lpaif_sec_i2s_clk_src",
1377 .flags = CLK_SET_RATE_PARENT,
1378 .ops = &clk_branch2_ops,
1383 static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = {
1384 .cmd_rcgr = 0x1c084,
1387 .parent_map = gcc_xo_gpll1_emclk_sleep_map,
1388 .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1389 .clkr.hw.init = &(struct clk_init_data){
1390 .name = "ultaudio_lpaif_aux_i2s_clk_src",
1391 .parent_names = gcc_xo_gpll1_esi2s_emclk_sleep,
1393 .ops = &clk_rcg2_ops,
1397 static struct clk_branch gcc_ultaudio_lpaif_aux_i2s_clk = {
1398 .halt_reg = 0x1c098,
1400 .enable_reg = 0x1c098,
1401 .enable_mask = BIT(0),
1402 .hw.init = &(struct clk_init_data){
1403 .name = "gcc_ultaudio_lpaif_aux_i2s_clk",
1404 .parent_names = (const char *[]){
1405 "ultaudio_lpaif_aux_i2s_clk_src",
1408 .flags = CLK_SET_RATE_PARENT,
1409 .ops = &clk_branch2_ops,
1414 static const struct freq_tbl ftbl_gcc_ultaudio_xo_clk[] = {
1415 F(19200000, P_XO, 1, 0, 0),
1419 static struct clk_rcg2 ultaudio_xo_clk_src = {
1420 .cmd_rcgr = 0x1c034,
1422 .parent_map = gcc_xo_sleep_map,
1423 .freq_tbl = ftbl_gcc_ultaudio_xo_clk,
1424 .clkr.hw.init = &(struct clk_init_data){
1425 .name = "ultaudio_xo_clk_src",
1426 .parent_names = gcc_xo_sleep,
1428 .ops = &clk_rcg2_ops,
1432 static struct clk_branch gcc_ultaudio_avsync_xo_clk = {
1433 .halt_reg = 0x1c04c,
1435 .enable_reg = 0x1c04c,
1436 .enable_mask = BIT(0),
1437 .hw.init = &(struct clk_init_data){
1438 .name = "gcc_ultaudio_avsync_xo_clk",
1439 .parent_names = (const char *[]){
1440 "ultaudio_xo_clk_src",
1443 .flags = CLK_SET_RATE_PARENT,
1444 .ops = &clk_branch2_ops,
1449 static struct clk_branch gcc_ultaudio_stc_xo_clk = {
1450 .halt_reg = 0x1c050,
1452 .enable_reg = 0x1c050,
1453 .enable_mask = BIT(0),
1454 .hw.init = &(struct clk_init_data){
1455 .name = "gcc_ultaudio_stc_xo_clk",
1456 .parent_names = (const char *[]){
1457 "ultaudio_xo_clk_src",
1460 .flags = CLK_SET_RATE_PARENT,
1461 .ops = &clk_branch2_ops,
1466 static const struct freq_tbl ftbl_codec_clk[] = {
1467 F(9600000, P_XO, 2, 0, 0),
1468 F(12288000, P_XO, 1, 16, 25),
1469 F(19200000, P_XO, 1, 0, 0),
1470 F(11289600, P_EXT_MCLK, 1, 0, 0),
1474 static struct clk_rcg2 codec_digcodec_clk_src = {
1475 .cmd_rcgr = 0x1c09c,
1478 .parent_map = gcc_xo_gpll1_emclk_sleep_map,
1479 .freq_tbl = ftbl_codec_clk,
1480 .clkr.hw.init = &(struct clk_init_data){
1481 .name = "codec_digcodec_clk_src",
1482 .parent_names = gcc_xo_gpll1_emclk_sleep,
1484 .ops = &clk_rcg2_ops,
1488 static struct clk_branch gcc_codec_digcodec_clk = {
1489 .halt_reg = 0x1c0b0,
1491 .enable_reg = 0x1c0b0,
1492 .enable_mask = BIT(0),
1493 .hw.init = &(struct clk_init_data){
1494 .name = "gcc_ultaudio_codec_digcodec_clk",
1495 .parent_names = (const char *[]){
1496 "codec_digcodec_clk_src",
1499 .flags = CLK_SET_RATE_PARENT,
1500 .ops = &clk_branch2_ops,
1505 static struct clk_branch gcc_ultaudio_pcnoc_mport_clk = {
1506 .halt_reg = 0x1c000,
1508 .enable_reg = 0x1c000,
1509 .enable_mask = BIT(0),
1510 .hw.init = &(struct clk_init_data){
1511 .name = "gcc_ultaudio_pcnoc_mport_clk",
1512 .parent_names = (const char *[]){
1513 "pcnoc_bfdcd_clk_src",
1516 .ops = &clk_branch2_ops,
1521 static struct clk_branch gcc_ultaudio_pcnoc_sway_clk = {
1522 .halt_reg = 0x1c004,
1524 .enable_reg = 0x1c004,
1525 .enable_mask = BIT(0),
1526 .hw.init = &(struct clk_init_data){
1527 .name = "gcc_ultaudio_pcnoc_sway_clk",
1528 .parent_names = (const char *[]){
1529 "pcnoc_bfdcd_clk_src",
1532 .ops = &clk_branch2_ops,
1537 static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = {
1538 F(100000000, P_GPLL0, 8, 0, 0),
1539 F(160000000, P_GPLL0, 5, 0, 0),
1540 F(228570000, P_GPLL0, 3.5, 0, 0),
1544 static struct clk_rcg2 vcodec0_clk_src = {
1545 .cmd_rcgr = 0x4C000,
1548 .parent_map = gcc_xo_gpll0_map,
1549 .freq_tbl = ftbl_gcc_venus0_vcodec0_clk,
1550 .clkr.hw.init = &(struct clk_init_data){
1551 .name = "vcodec0_clk_src",
1552 .parent_names = gcc_xo_gpll0,
1554 .ops = &clk_rcg2_ops,
1558 static struct clk_branch gcc_blsp1_ahb_clk = {
1559 .halt_reg = 0x01008,
1560 .halt_check = BRANCH_HALT_VOTED,
1562 .enable_reg = 0x45004,
1563 .enable_mask = BIT(10),
1564 .hw.init = &(struct clk_init_data){
1565 .name = "gcc_blsp1_ahb_clk",
1566 .parent_names = (const char *[]){
1567 "pcnoc_bfdcd_clk_src",
1570 .ops = &clk_branch2_ops,
1575 static struct clk_branch gcc_blsp1_sleep_clk = {
1576 .halt_reg = 0x01004,
1578 .enable_reg = 0x01004,
1579 .enable_mask = BIT(0),
1580 .hw.init = &(struct clk_init_data){
1581 .name = "gcc_blsp1_sleep_clk",
1582 .parent_names = (const char *[]){
1586 .flags = CLK_SET_RATE_PARENT,
1587 .ops = &clk_branch2_ops,
1592 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1593 .halt_reg = 0x02008,
1595 .enable_reg = 0x02008,
1596 .enable_mask = BIT(0),
1597 .hw.init = &(struct clk_init_data){
1598 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1599 .parent_names = (const char *[]){
1600 "blsp1_qup1_i2c_apps_clk_src",
1603 .flags = CLK_SET_RATE_PARENT,
1604 .ops = &clk_branch2_ops,
1609 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1610 .halt_reg = 0x02004,
1612 .enable_reg = 0x02004,
1613 .enable_mask = BIT(0),
1614 .hw.init = &(struct clk_init_data){
1615 .name = "gcc_blsp1_qup1_spi_apps_clk",
1616 .parent_names = (const char *[]){
1617 "blsp1_qup1_spi_apps_clk_src",
1620 .flags = CLK_SET_RATE_PARENT,
1621 .ops = &clk_branch2_ops,
1626 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1627 .halt_reg = 0x03010,
1629 .enable_reg = 0x03010,
1630 .enable_mask = BIT(0),
1631 .hw.init = &(struct clk_init_data){
1632 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1633 .parent_names = (const char *[]){
1634 "blsp1_qup2_i2c_apps_clk_src",
1637 .flags = CLK_SET_RATE_PARENT,
1638 .ops = &clk_branch2_ops,
1643 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1644 .halt_reg = 0x0300c,
1646 .enable_reg = 0x0300c,
1647 .enable_mask = BIT(0),
1648 .hw.init = &(struct clk_init_data){
1649 .name = "gcc_blsp1_qup2_spi_apps_clk",
1650 .parent_names = (const char *[]){
1651 "blsp1_qup2_spi_apps_clk_src",
1654 .flags = CLK_SET_RATE_PARENT,
1655 .ops = &clk_branch2_ops,
1660 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1661 .halt_reg = 0x04020,
1663 .enable_reg = 0x04020,
1664 .enable_mask = BIT(0),
1665 .hw.init = &(struct clk_init_data){
1666 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1667 .parent_names = (const char *[]){
1668 "blsp1_qup3_i2c_apps_clk_src",
1671 .flags = CLK_SET_RATE_PARENT,
1672 .ops = &clk_branch2_ops,
1677 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1678 .halt_reg = 0x0401c,
1680 .enable_reg = 0x0401c,
1681 .enable_mask = BIT(0),
1682 .hw.init = &(struct clk_init_data){
1683 .name = "gcc_blsp1_qup3_spi_apps_clk",
1684 .parent_names = (const char *[]){
1685 "blsp1_qup3_spi_apps_clk_src",
1688 .flags = CLK_SET_RATE_PARENT,
1689 .ops = &clk_branch2_ops,
1694 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1695 .halt_reg = 0x05020,
1697 .enable_reg = 0x05020,
1698 .enable_mask = BIT(0),
1699 .hw.init = &(struct clk_init_data){
1700 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1701 .parent_names = (const char *[]){
1702 "blsp1_qup4_i2c_apps_clk_src",
1705 .flags = CLK_SET_RATE_PARENT,
1706 .ops = &clk_branch2_ops,
1711 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1712 .halt_reg = 0x0501c,
1714 .enable_reg = 0x0501c,
1715 .enable_mask = BIT(0),
1716 .hw.init = &(struct clk_init_data){
1717 .name = "gcc_blsp1_qup4_spi_apps_clk",
1718 .parent_names = (const char *[]){
1719 "blsp1_qup4_spi_apps_clk_src",
1722 .flags = CLK_SET_RATE_PARENT,
1723 .ops = &clk_branch2_ops,
1728 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1729 .halt_reg = 0x06020,
1731 .enable_reg = 0x06020,
1732 .enable_mask = BIT(0),
1733 .hw.init = &(struct clk_init_data){
1734 .name = "gcc_blsp1_qup5_i2c_apps_clk",
1735 .parent_names = (const char *[]){
1736 "blsp1_qup5_i2c_apps_clk_src",
1739 .flags = CLK_SET_RATE_PARENT,
1740 .ops = &clk_branch2_ops,
1745 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1746 .halt_reg = 0x0601c,
1748 .enable_reg = 0x0601c,
1749 .enable_mask = BIT(0),
1750 .hw.init = &(struct clk_init_data){
1751 .name = "gcc_blsp1_qup5_spi_apps_clk",
1752 .parent_names = (const char *[]){
1753 "blsp1_qup5_spi_apps_clk_src",
1756 .flags = CLK_SET_RATE_PARENT,
1757 .ops = &clk_branch2_ops,
1762 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1763 .halt_reg = 0x07020,
1765 .enable_reg = 0x07020,
1766 .enable_mask = BIT(0),
1767 .hw.init = &(struct clk_init_data){
1768 .name = "gcc_blsp1_qup6_i2c_apps_clk",
1769 .parent_names = (const char *[]){
1770 "blsp1_qup6_i2c_apps_clk_src",
1773 .flags = CLK_SET_RATE_PARENT,
1774 .ops = &clk_branch2_ops,
1779 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1780 .halt_reg = 0x0701c,
1782 .enable_reg = 0x0701c,
1783 .enable_mask = BIT(0),
1784 .hw.init = &(struct clk_init_data){
1785 .name = "gcc_blsp1_qup6_spi_apps_clk",
1786 .parent_names = (const char *[]){
1787 "blsp1_qup6_spi_apps_clk_src",
1790 .flags = CLK_SET_RATE_PARENT,
1791 .ops = &clk_branch2_ops,
1796 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1797 .halt_reg = 0x0203c,
1799 .enable_reg = 0x0203c,
1800 .enable_mask = BIT(0),
1801 .hw.init = &(struct clk_init_data){
1802 .name = "gcc_blsp1_uart1_apps_clk",
1803 .parent_names = (const char *[]){
1804 "blsp1_uart1_apps_clk_src",
1807 .flags = CLK_SET_RATE_PARENT,
1808 .ops = &clk_branch2_ops,
1813 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1814 .halt_reg = 0x0302c,
1816 .enable_reg = 0x0302c,
1817 .enable_mask = BIT(0),
1818 .hw.init = &(struct clk_init_data){
1819 .name = "gcc_blsp1_uart2_apps_clk",
1820 .parent_names = (const char *[]){
1821 "blsp1_uart2_apps_clk_src",
1824 .flags = CLK_SET_RATE_PARENT,
1825 .ops = &clk_branch2_ops,
1830 static struct clk_branch gcc_boot_rom_ahb_clk = {
1831 .halt_reg = 0x1300c,
1832 .halt_check = BRANCH_HALT_VOTED,
1834 .enable_reg = 0x45004,
1835 .enable_mask = BIT(7),
1836 .hw.init = &(struct clk_init_data){
1837 .name = "gcc_boot_rom_ahb_clk",
1838 .parent_names = (const char *[]){
1839 "pcnoc_bfdcd_clk_src",
1842 .ops = &clk_branch2_ops,
1847 static struct clk_branch gcc_camss_cci_ahb_clk = {
1848 .halt_reg = 0x5101c,
1850 .enable_reg = 0x5101c,
1851 .enable_mask = BIT(0),
1852 .hw.init = &(struct clk_init_data){
1853 .name = "gcc_camss_cci_ahb_clk",
1854 .parent_names = (const char *[]){
1855 "camss_ahb_clk_src",
1858 .flags = CLK_SET_RATE_PARENT,
1859 .ops = &clk_branch2_ops,
1864 static struct clk_branch gcc_camss_cci_clk = {
1865 .halt_reg = 0x51018,
1867 .enable_reg = 0x51018,
1868 .enable_mask = BIT(0),
1869 .hw.init = &(struct clk_init_data){
1870 .name = "gcc_camss_cci_clk",
1871 .parent_names = (const char *[]){
1875 .flags = CLK_SET_RATE_PARENT,
1876 .ops = &clk_branch2_ops,
1881 static struct clk_branch gcc_camss_csi0_ahb_clk = {
1882 .halt_reg = 0x4e040,
1884 .enable_reg = 0x4e040,
1885 .enable_mask = BIT(0),
1886 .hw.init = &(struct clk_init_data){
1887 .name = "gcc_camss_csi0_ahb_clk",
1888 .parent_names = (const char *[]){
1889 "camss_ahb_clk_src",
1892 .flags = CLK_SET_RATE_PARENT,
1893 .ops = &clk_branch2_ops,
1898 static struct clk_branch gcc_camss_csi0_clk = {
1899 .halt_reg = 0x4e03c,
1901 .enable_reg = 0x4e03c,
1902 .enable_mask = BIT(0),
1903 .hw.init = &(struct clk_init_data){
1904 .name = "gcc_camss_csi0_clk",
1905 .parent_names = (const char *[]){
1909 .flags = CLK_SET_RATE_PARENT,
1910 .ops = &clk_branch2_ops,
1915 static struct clk_branch gcc_camss_csi0phy_clk = {
1916 .halt_reg = 0x4e048,
1918 .enable_reg = 0x4e048,
1919 .enable_mask = BIT(0),
1920 .hw.init = &(struct clk_init_data){
1921 .name = "gcc_camss_csi0phy_clk",
1922 .parent_names = (const char *[]){
1926 .flags = CLK_SET_RATE_PARENT,
1927 .ops = &clk_branch2_ops,
1932 static struct clk_branch gcc_camss_csi0pix_clk = {
1933 .halt_reg = 0x4e058,
1935 .enable_reg = 0x4e058,
1936 .enable_mask = BIT(0),
1937 .hw.init = &(struct clk_init_data){
1938 .name = "gcc_camss_csi0pix_clk",
1939 .parent_names = (const char *[]){
1943 .flags = CLK_SET_RATE_PARENT,
1944 .ops = &clk_branch2_ops,
1949 static struct clk_branch gcc_camss_csi0rdi_clk = {
1950 .halt_reg = 0x4e050,
1952 .enable_reg = 0x4e050,
1953 .enable_mask = BIT(0),
1954 .hw.init = &(struct clk_init_data){
1955 .name = "gcc_camss_csi0rdi_clk",
1956 .parent_names = (const char *[]){
1960 .flags = CLK_SET_RATE_PARENT,
1961 .ops = &clk_branch2_ops,
1966 static struct clk_branch gcc_camss_csi1_ahb_clk = {
1967 .halt_reg = 0x4f040,
1969 .enable_reg = 0x4f040,
1970 .enable_mask = BIT(0),
1971 .hw.init = &(struct clk_init_data){
1972 .name = "gcc_camss_csi1_ahb_clk",
1973 .parent_names = (const char *[]){
1974 "camss_ahb_clk_src",
1977 .flags = CLK_SET_RATE_PARENT,
1978 .ops = &clk_branch2_ops,
1983 static struct clk_branch gcc_camss_csi1_clk = {
1984 .halt_reg = 0x4f03c,
1986 .enable_reg = 0x4f03c,
1987 .enable_mask = BIT(0),
1988 .hw.init = &(struct clk_init_data){
1989 .name = "gcc_camss_csi1_clk",
1990 .parent_names = (const char *[]){
1994 .flags = CLK_SET_RATE_PARENT,
1995 .ops = &clk_branch2_ops,
2000 static struct clk_branch gcc_camss_csi1phy_clk = {
2001 .halt_reg = 0x4f048,
2003 .enable_reg = 0x4f048,
2004 .enable_mask = BIT(0),
2005 .hw.init = &(struct clk_init_data){
2006 .name = "gcc_camss_csi1phy_clk",
2007 .parent_names = (const char *[]){
2011 .flags = CLK_SET_RATE_PARENT,
2012 .ops = &clk_branch2_ops,
2017 static struct clk_branch gcc_camss_csi1pix_clk = {
2018 .halt_reg = 0x4f058,
2020 .enable_reg = 0x4f058,
2021 .enable_mask = BIT(0),
2022 .hw.init = &(struct clk_init_data){
2023 .name = "gcc_camss_csi1pix_clk",
2024 .parent_names = (const char *[]){
2028 .flags = CLK_SET_RATE_PARENT,
2029 .ops = &clk_branch2_ops,
2034 static struct clk_branch gcc_camss_csi1rdi_clk = {
2035 .halt_reg = 0x4f050,
2037 .enable_reg = 0x4f050,
2038 .enable_mask = BIT(0),
2039 .hw.init = &(struct clk_init_data){
2040 .name = "gcc_camss_csi1rdi_clk",
2041 .parent_names = (const char *[]){
2045 .flags = CLK_SET_RATE_PARENT,
2046 .ops = &clk_branch2_ops,
2051 static struct clk_branch gcc_camss_csi_vfe0_clk = {
2052 .halt_reg = 0x58050,
2054 .enable_reg = 0x58050,
2055 .enable_mask = BIT(0),
2056 .hw.init = &(struct clk_init_data){
2057 .name = "gcc_camss_csi_vfe0_clk",
2058 .parent_names = (const char *[]){
2062 .flags = CLK_SET_RATE_PARENT,
2063 .ops = &clk_branch2_ops,
2068 static struct clk_branch gcc_camss_gp0_clk = {
2069 .halt_reg = 0x54018,
2071 .enable_reg = 0x54018,
2072 .enable_mask = BIT(0),
2073 .hw.init = &(struct clk_init_data){
2074 .name = "gcc_camss_gp0_clk",
2075 .parent_names = (const char *[]){
2076 "camss_gp0_clk_src",
2079 .flags = CLK_SET_RATE_PARENT,
2080 .ops = &clk_branch2_ops,
2085 static struct clk_branch gcc_camss_gp1_clk = {
2086 .halt_reg = 0x55018,
2088 .enable_reg = 0x55018,
2089 .enable_mask = BIT(0),
2090 .hw.init = &(struct clk_init_data){
2091 .name = "gcc_camss_gp1_clk",
2092 .parent_names = (const char *[]){
2093 "camss_gp1_clk_src",
2096 .flags = CLK_SET_RATE_PARENT,
2097 .ops = &clk_branch2_ops,
2102 static struct clk_branch gcc_camss_ispif_ahb_clk = {
2103 .halt_reg = 0x50004,
2105 .enable_reg = 0x50004,
2106 .enable_mask = BIT(0),
2107 .hw.init = &(struct clk_init_data){
2108 .name = "gcc_camss_ispif_ahb_clk",
2109 .parent_names = (const char *[]){
2110 "camss_ahb_clk_src",
2113 .flags = CLK_SET_RATE_PARENT,
2114 .ops = &clk_branch2_ops,
2119 static struct clk_branch gcc_camss_jpeg0_clk = {
2120 .halt_reg = 0x57020,
2122 .enable_reg = 0x57020,
2123 .enable_mask = BIT(0),
2124 .hw.init = &(struct clk_init_data){
2125 .name = "gcc_camss_jpeg0_clk",
2126 .parent_names = (const char *[]){
2130 .flags = CLK_SET_RATE_PARENT,
2131 .ops = &clk_branch2_ops,
2136 static struct clk_branch gcc_camss_jpeg_ahb_clk = {
2137 .halt_reg = 0x57024,
2139 .enable_reg = 0x57024,
2140 .enable_mask = BIT(0),
2141 .hw.init = &(struct clk_init_data){
2142 .name = "gcc_camss_jpeg_ahb_clk",
2143 .parent_names = (const char *[]){
2144 "camss_ahb_clk_src",
2147 .flags = CLK_SET_RATE_PARENT,
2148 .ops = &clk_branch2_ops,
2153 static struct clk_branch gcc_camss_jpeg_axi_clk = {
2154 .halt_reg = 0x57028,
2156 .enable_reg = 0x57028,
2157 .enable_mask = BIT(0),
2158 .hw.init = &(struct clk_init_data){
2159 .name = "gcc_camss_jpeg_axi_clk",
2160 .parent_names = (const char *[]){
2161 "system_noc_bfdcd_clk_src",
2164 .flags = CLK_SET_RATE_PARENT,
2165 .ops = &clk_branch2_ops,
2170 static struct clk_branch gcc_camss_mclk0_clk = {
2171 .halt_reg = 0x52018,
2173 .enable_reg = 0x52018,
2174 .enable_mask = BIT(0),
2175 .hw.init = &(struct clk_init_data){
2176 .name = "gcc_camss_mclk0_clk",
2177 .parent_names = (const char *[]){
2181 .flags = CLK_SET_RATE_PARENT,
2182 .ops = &clk_branch2_ops,
2187 static struct clk_branch gcc_camss_mclk1_clk = {
2188 .halt_reg = 0x53018,
2190 .enable_reg = 0x53018,
2191 .enable_mask = BIT(0),
2192 .hw.init = &(struct clk_init_data){
2193 .name = "gcc_camss_mclk1_clk",
2194 .parent_names = (const char *[]){
2198 .flags = CLK_SET_RATE_PARENT,
2199 .ops = &clk_branch2_ops,
2204 static struct clk_branch gcc_camss_micro_ahb_clk = {
2205 .halt_reg = 0x5600c,
2207 .enable_reg = 0x5600c,
2208 .enable_mask = BIT(0),
2209 .hw.init = &(struct clk_init_data){
2210 .name = "gcc_camss_micro_ahb_clk",
2211 .parent_names = (const char *[]){
2212 "camss_ahb_clk_src",
2215 .flags = CLK_SET_RATE_PARENT,
2216 .ops = &clk_branch2_ops,
2221 static struct clk_branch gcc_camss_csi0phytimer_clk = {
2222 .halt_reg = 0x4e01c,
2224 .enable_reg = 0x4e01c,
2225 .enable_mask = BIT(0),
2226 .hw.init = &(struct clk_init_data){
2227 .name = "gcc_camss_csi0phytimer_clk",
2228 .parent_names = (const char *[]){
2229 "csi0phytimer_clk_src",
2232 .flags = CLK_SET_RATE_PARENT,
2233 .ops = &clk_branch2_ops,
2238 static struct clk_branch gcc_camss_csi1phytimer_clk = {
2239 .halt_reg = 0x4f01c,
2241 .enable_reg = 0x4f01c,
2242 .enable_mask = BIT(0),
2243 .hw.init = &(struct clk_init_data){
2244 .name = "gcc_camss_csi1phytimer_clk",
2245 .parent_names = (const char *[]){
2246 "csi1phytimer_clk_src",
2249 .flags = CLK_SET_RATE_PARENT,
2250 .ops = &clk_branch2_ops,
2255 static struct clk_branch gcc_camss_ahb_clk = {
2256 .halt_reg = 0x5a014,
2258 .enable_reg = 0x5a014,
2259 .enable_mask = BIT(0),
2260 .hw.init = &(struct clk_init_data){
2261 .name = "gcc_camss_ahb_clk",
2262 .parent_names = (const char *[]){
2263 "camss_ahb_clk_src",
2266 .flags = CLK_SET_RATE_PARENT,
2267 .ops = &clk_branch2_ops,
2272 static struct clk_branch gcc_camss_top_ahb_clk = {
2273 .halt_reg = 0x56004,
2275 .enable_reg = 0x56004,
2276 .enable_mask = BIT(0),
2277 .hw.init = &(struct clk_init_data){
2278 .name = "gcc_camss_top_ahb_clk",
2279 .parent_names = (const char *[]){
2280 "pcnoc_bfdcd_clk_src",
2283 .flags = CLK_SET_RATE_PARENT,
2284 .ops = &clk_branch2_ops,
2289 static struct clk_branch gcc_camss_cpp_ahb_clk = {
2290 .halt_reg = 0x58040,
2292 .enable_reg = 0x58040,
2293 .enable_mask = BIT(0),
2294 .hw.init = &(struct clk_init_data){
2295 .name = "gcc_camss_cpp_ahb_clk",
2296 .parent_names = (const char *[]){
2297 "camss_ahb_clk_src",
2300 .flags = CLK_SET_RATE_PARENT,
2301 .ops = &clk_branch2_ops,
2306 static struct clk_branch gcc_camss_cpp_clk = {
2307 .halt_reg = 0x5803c,
2309 .enable_reg = 0x5803c,
2310 .enable_mask = BIT(0),
2311 .hw.init = &(struct clk_init_data){
2312 .name = "gcc_camss_cpp_clk",
2313 .parent_names = (const char *[]){
2317 .flags = CLK_SET_RATE_PARENT,
2318 .ops = &clk_branch2_ops,
2323 static struct clk_branch gcc_camss_vfe0_clk = {
2324 .halt_reg = 0x58038,
2326 .enable_reg = 0x58038,
2327 .enable_mask = BIT(0),
2328 .hw.init = &(struct clk_init_data){
2329 .name = "gcc_camss_vfe0_clk",
2330 .parent_names = (const char *[]){
2334 .flags = CLK_SET_RATE_PARENT,
2335 .ops = &clk_branch2_ops,
2340 static struct clk_branch gcc_camss_vfe_ahb_clk = {
2341 .halt_reg = 0x58044,
2343 .enable_reg = 0x58044,
2344 .enable_mask = BIT(0),
2345 .hw.init = &(struct clk_init_data){
2346 .name = "gcc_camss_vfe_ahb_clk",
2347 .parent_names = (const char *[]){
2348 "camss_ahb_clk_src",
2351 .flags = CLK_SET_RATE_PARENT,
2352 .ops = &clk_branch2_ops,
2357 static struct clk_branch gcc_camss_vfe_axi_clk = {
2358 .halt_reg = 0x58048,
2360 .enable_reg = 0x58048,
2361 .enable_mask = BIT(0),
2362 .hw.init = &(struct clk_init_data){
2363 .name = "gcc_camss_vfe_axi_clk",
2364 .parent_names = (const char *[]){
2365 "system_noc_bfdcd_clk_src",
2368 .flags = CLK_SET_RATE_PARENT,
2369 .ops = &clk_branch2_ops,
2374 static struct clk_branch gcc_crypto_ahb_clk = {
2375 .halt_reg = 0x16024,
2376 .halt_check = BRANCH_HALT_VOTED,
2378 .enable_reg = 0x45004,
2379 .enable_mask = BIT(0),
2380 .hw.init = &(struct clk_init_data){
2381 .name = "gcc_crypto_ahb_clk",
2382 .parent_names = (const char *[]){
2383 "pcnoc_bfdcd_clk_src",
2386 .flags = CLK_SET_RATE_PARENT,
2387 .ops = &clk_branch2_ops,
2392 static struct clk_branch gcc_crypto_axi_clk = {
2393 .halt_reg = 0x16020,
2394 .halt_check = BRANCH_HALT_VOTED,
2396 .enable_reg = 0x45004,
2397 .enable_mask = BIT(1),
2398 .hw.init = &(struct clk_init_data){
2399 .name = "gcc_crypto_axi_clk",
2400 .parent_names = (const char *[]){
2401 "pcnoc_bfdcd_clk_src",
2404 .flags = CLK_SET_RATE_PARENT,
2405 .ops = &clk_branch2_ops,
2410 static struct clk_branch gcc_crypto_clk = {
2411 .halt_reg = 0x1601c,
2412 .halt_check = BRANCH_HALT_VOTED,
2414 .enable_reg = 0x45004,
2415 .enable_mask = BIT(2),
2416 .hw.init = &(struct clk_init_data){
2417 .name = "gcc_crypto_clk",
2418 .parent_names = (const char *[]){
2422 .flags = CLK_SET_RATE_PARENT,
2423 .ops = &clk_branch2_ops,
2428 static struct clk_branch gcc_oxili_gmem_clk = {
2429 .halt_reg = 0x59024,
2431 .enable_reg = 0x59024,
2432 .enable_mask = BIT(0),
2433 .hw.init = &(struct clk_init_data){
2434 .name = "gcc_oxili_gmem_clk",
2435 .parent_names = (const char *[]){
2439 .flags = CLK_SET_RATE_PARENT,
2440 .ops = &clk_branch2_ops,
2445 static struct clk_branch gcc_gp1_clk = {
2446 .halt_reg = 0x08000,
2448 .enable_reg = 0x08000,
2449 .enable_mask = BIT(0),
2450 .hw.init = &(struct clk_init_data){
2451 .name = "gcc_gp1_clk",
2452 .parent_names = (const char *[]){
2456 .flags = CLK_SET_RATE_PARENT,
2457 .ops = &clk_branch2_ops,
2462 static struct clk_branch gcc_gp2_clk = {
2463 .halt_reg = 0x09000,
2465 .enable_reg = 0x09000,
2466 .enable_mask = BIT(0),
2467 .hw.init = &(struct clk_init_data){
2468 .name = "gcc_gp2_clk",
2469 .parent_names = (const char *[]){
2473 .flags = CLK_SET_RATE_PARENT,
2474 .ops = &clk_branch2_ops,
2479 static struct clk_branch gcc_gp3_clk = {
2480 .halt_reg = 0x0a000,
2482 .enable_reg = 0x0a000,
2483 .enable_mask = BIT(0),
2484 .hw.init = &(struct clk_init_data){
2485 .name = "gcc_gp3_clk",
2486 .parent_names = (const char *[]){
2490 .flags = CLK_SET_RATE_PARENT,
2491 .ops = &clk_branch2_ops,
2496 static struct clk_branch gcc_mdss_ahb_clk = {
2497 .halt_reg = 0x4d07c,
2499 .enable_reg = 0x4d07c,
2500 .enable_mask = BIT(0),
2501 .hw.init = &(struct clk_init_data){
2502 .name = "gcc_mdss_ahb_clk",
2503 .parent_names = (const char *[]){
2504 "pcnoc_bfdcd_clk_src",
2507 .flags = CLK_SET_RATE_PARENT,
2508 .ops = &clk_branch2_ops,
2513 static struct clk_branch gcc_mdss_axi_clk = {
2514 .halt_reg = 0x4d080,
2516 .enable_reg = 0x4d080,
2517 .enable_mask = BIT(0),
2518 .hw.init = &(struct clk_init_data){
2519 .name = "gcc_mdss_axi_clk",
2520 .parent_names = (const char *[]){
2521 "system_noc_bfdcd_clk_src",
2524 .flags = CLK_SET_RATE_PARENT,
2525 .ops = &clk_branch2_ops,
2530 static struct clk_branch gcc_mdss_byte0_clk = {
2531 .halt_reg = 0x4d094,
2533 .enable_reg = 0x4d094,
2534 .enable_mask = BIT(0),
2535 .hw.init = &(struct clk_init_data){
2536 .name = "gcc_mdss_byte0_clk",
2537 .parent_names = (const char *[]){
2541 .flags = CLK_SET_RATE_PARENT,
2542 .ops = &clk_branch2_ops,
2547 static struct clk_branch gcc_mdss_esc0_clk = {
2548 .halt_reg = 0x4d098,
2550 .enable_reg = 0x4d098,
2551 .enable_mask = BIT(0),
2552 .hw.init = &(struct clk_init_data){
2553 .name = "gcc_mdss_esc0_clk",
2554 .parent_names = (const char *[]){
2558 .flags = CLK_SET_RATE_PARENT,
2559 .ops = &clk_branch2_ops,
2564 static struct clk_branch gcc_mdss_mdp_clk = {
2565 .halt_reg = 0x4D088,
2567 .enable_reg = 0x4D088,
2568 .enable_mask = BIT(0),
2569 .hw.init = &(struct clk_init_data){
2570 .name = "gcc_mdss_mdp_clk",
2571 .parent_names = (const char *[]){
2575 .flags = CLK_SET_RATE_PARENT,
2576 .ops = &clk_branch2_ops,
2581 static struct clk_branch gcc_mdss_pclk0_clk = {
2582 .halt_reg = 0x4d084,
2584 .enable_reg = 0x4d084,
2585 .enable_mask = BIT(0),
2586 .hw.init = &(struct clk_init_data){
2587 .name = "gcc_mdss_pclk0_clk",
2588 .parent_names = (const char *[]){
2592 .flags = CLK_SET_RATE_PARENT,
2593 .ops = &clk_branch2_ops,
2598 static struct clk_branch gcc_mdss_vsync_clk = {
2599 .halt_reg = 0x4d090,
2601 .enable_reg = 0x4d090,
2602 .enable_mask = BIT(0),
2603 .hw.init = &(struct clk_init_data){
2604 .name = "gcc_mdss_vsync_clk",
2605 .parent_names = (const char *[]){
2609 .flags = CLK_SET_RATE_PARENT,
2610 .ops = &clk_branch2_ops,
2615 static struct clk_branch gcc_mss_cfg_ahb_clk = {
2616 .halt_reg = 0x49000,
2618 .enable_reg = 0x49000,
2619 .enable_mask = BIT(0),
2620 .hw.init = &(struct clk_init_data){
2621 .name = "gcc_mss_cfg_ahb_clk",
2622 .parent_names = (const char *[]){
2623 "pcnoc_bfdcd_clk_src",
2626 .flags = CLK_SET_RATE_PARENT,
2627 .ops = &clk_branch2_ops,
2632 static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
2633 .halt_reg = 0x49004,
2635 .enable_reg = 0x49004,
2636 .enable_mask = BIT(0),
2637 .hw.init = &(struct clk_init_data){
2638 .name = "gcc_mss_q6_bimc_axi_clk",
2639 .parent_names = (const char *[]){
2643 .flags = CLK_SET_RATE_PARENT,
2644 .ops = &clk_branch2_ops,
2649 static struct clk_branch gcc_oxili_ahb_clk = {
2650 .halt_reg = 0x59028,
2652 .enable_reg = 0x59028,
2653 .enable_mask = BIT(0),
2654 .hw.init = &(struct clk_init_data){
2655 .name = "gcc_oxili_ahb_clk",
2656 .parent_names = (const char *[]){
2657 "pcnoc_bfdcd_clk_src",
2660 .flags = CLK_SET_RATE_PARENT,
2661 .ops = &clk_branch2_ops,
2666 static struct clk_branch gcc_oxili_gfx3d_clk = {
2667 .halt_reg = 0x59020,
2669 .enable_reg = 0x59020,
2670 .enable_mask = BIT(0),
2671 .hw.init = &(struct clk_init_data){
2672 .name = "gcc_oxili_gfx3d_clk",
2673 .parent_names = (const char *[]){
2677 .flags = CLK_SET_RATE_PARENT,
2678 .ops = &clk_branch2_ops,
2683 static struct clk_branch gcc_pdm2_clk = {
2684 .halt_reg = 0x4400c,
2686 .enable_reg = 0x4400c,
2687 .enable_mask = BIT(0),
2688 .hw.init = &(struct clk_init_data){
2689 .name = "gcc_pdm2_clk",
2690 .parent_names = (const char *[]){
2694 .flags = CLK_SET_RATE_PARENT,
2695 .ops = &clk_branch2_ops,
2700 static struct clk_branch gcc_pdm_ahb_clk = {
2701 .halt_reg = 0x44004,
2703 .enable_reg = 0x44004,
2704 .enable_mask = BIT(0),
2705 .hw.init = &(struct clk_init_data){
2706 .name = "gcc_pdm_ahb_clk",
2707 .parent_names = (const char *[]){
2708 "pcnoc_bfdcd_clk_src",
2711 .flags = CLK_SET_RATE_PARENT,
2712 .ops = &clk_branch2_ops,
2717 static struct clk_branch gcc_prng_ahb_clk = {
2718 .halt_reg = 0x13004,
2719 .halt_check = BRANCH_HALT_VOTED,
2721 .enable_reg = 0x45004,
2722 .enable_mask = BIT(8),
2723 .hw.init = &(struct clk_init_data){
2724 .name = "gcc_prng_ahb_clk",
2725 .parent_names = (const char *[]){
2726 "pcnoc_bfdcd_clk_src",
2729 .ops = &clk_branch2_ops,
2734 static struct clk_branch gcc_sdcc1_ahb_clk = {
2735 .halt_reg = 0x4201c,
2737 .enable_reg = 0x4201c,
2738 .enable_mask = BIT(0),
2739 .hw.init = &(struct clk_init_data){
2740 .name = "gcc_sdcc1_ahb_clk",
2741 .parent_names = (const char *[]){
2742 "pcnoc_bfdcd_clk_src",
2745 .flags = CLK_SET_RATE_PARENT,
2746 .ops = &clk_branch2_ops,
2751 static struct clk_branch gcc_sdcc1_apps_clk = {
2752 .halt_reg = 0x42018,
2754 .enable_reg = 0x42018,
2755 .enable_mask = BIT(0),
2756 .hw.init = &(struct clk_init_data){
2757 .name = "gcc_sdcc1_apps_clk",
2758 .parent_names = (const char *[]){
2759 "sdcc1_apps_clk_src",
2762 .flags = CLK_SET_RATE_PARENT,
2763 .ops = &clk_branch2_ops,
2768 static struct clk_branch gcc_sdcc2_ahb_clk = {
2769 .halt_reg = 0x4301c,
2771 .enable_reg = 0x4301c,
2772 .enable_mask = BIT(0),
2773 .hw.init = &(struct clk_init_data){
2774 .name = "gcc_sdcc2_ahb_clk",
2775 .parent_names = (const char *[]){
2776 "pcnoc_bfdcd_clk_src",
2779 .flags = CLK_SET_RATE_PARENT,
2780 .ops = &clk_branch2_ops,
2785 static struct clk_branch gcc_sdcc2_apps_clk = {
2786 .halt_reg = 0x43018,
2788 .enable_reg = 0x43018,
2789 .enable_mask = BIT(0),
2790 .hw.init = &(struct clk_init_data){
2791 .name = "gcc_sdcc2_apps_clk",
2792 .parent_names = (const char *[]){
2793 "sdcc2_apps_clk_src",
2796 .flags = CLK_SET_RATE_PARENT,
2797 .ops = &clk_branch2_ops,
2802 static struct clk_rcg2 bimc_ddr_clk_src = {
2803 .cmd_rcgr = 0x32004,
2805 .parent_map = gcc_xo_gpll0_bimc_map,
2806 .clkr.hw.init = &(struct clk_init_data){
2807 .name = "bimc_ddr_clk_src",
2808 .parent_names = gcc_xo_gpll0_bimc,
2810 .ops = &clk_rcg2_ops,
2811 .flags = CLK_GET_RATE_NOCACHE,
2815 static struct clk_branch gcc_apss_tcu_clk = {
2816 .halt_reg = 0x12018,
2818 .enable_reg = 0x4500c,
2819 .enable_mask = BIT(1),
2820 .hw.init = &(struct clk_init_data){
2821 .name = "gcc_apss_tcu_clk",
2822 .parent_names = (const char *[]){
2826 .ops = &clk_branch2_ops,
2831 static struct clk_branch gcc_gfx_tcu_clk = {
2832 .halt_reg = 0x12020,
2834 .enable_reg = 0x4500c,
2835 .enable_mask = BIT(2),
2836 .hw.init = &(struct clk_init_data){
2837 .name = "gcc_gfx_tcu_clk",
2838 .parent_names = (const char *[]){
2842 .ops = &clk_branch2_ops,
2847 static struct clk_branch gcc_gtcu_ahb_clk = {
2848 .halt_reg = 0x12044,
2850 .enable_reg = 0x4500c,
2851 .enable_mask = BIT(13),
2852 .hw.init = &(struct clk_init_data){
2853 .name = "gcc_gtcu_ahb_clk",
2854 .parent_names = (const char *[]){
2855 "pcnoc_bfdcd_clk_src",
2858 .flags = CLK_SET_RATE_PARENT,
2859 .ops = &clk_branch2_ops,
2864 static struct clk_branch gcc_bimc_gfx_clk = {
2865 .halt_reg = 0x31024,
2867 .enable_reg = 0x31024,
2868 .enable_mask = BIT(0),
2869 .hw.init = &(struct clk_init_data){
2870 .name = "gcc_bimc_gfx_clk",
2871 .parent_names = (const char *[]){
2875 .flags = CLK_SET_RATE_PARENT,
2876 .ops = &clk_branch2_ops,
2881 static struct clk_branch gcc_bimc_gpu_clk = {
2882 .halt_reg = 0x31040,
2884 .enable_reg = 0x31040,
2885 .enable_mask = BIT(0),
2886 .hw.init = &(struct clk_init_data){
2887 .name = "gcc_bimc_gpu_clk",
2888 .parent_names = (const char *[]){
2892 .flags = CLK_SET_RATE_PARENT,
2893 .ops = &clk_branch2_ops,
2898 static struct clk_branch gcc_jpeg_tbu_clk = {
2899 .halt_reg = 0x12034,
2901 .enable_reg = 0x4500c,
2902 .enable_mask = BIT(10),
2903 .hw.init = &(struct clk_init_data){
2904 .name = "gcc_jpeg_tbu_clk",
2905 .parent_names = (const char *[]){
2906 "system_noc_bfdcd_clk_src",
2909 .flags = CLK_SET_RATE_PARENT,
2910 .ops = &clk_branch2_ops,
2915 static struct clk_branch gcc_mdp_tbu_clk = {
2916 .halt_reg = 0x1201c,
2918 .enable_reg = 0x4500c,
2919 .enable_mask = BIT(4),
2920 .hw.init = &(struct clk_init_data){
2921 .name = "gcc_mdp_tbu_clk",
2922 .parent_names = (const char *[]){
2923 "system_noc_bfdcd_clk_src",
2926 .flags = CLK_SET_RATE_PARENT,
2927 .ops = &clk_branch2_ops,
2932 static struct clk_branch gcc_smmu_cfg_clk = {
2933 .halt_reg = 0x12038,
2935 .enable_reg = 0x4500c,
2936 .enable_mask = BIT(12),
2937 .hw.init = &(struct clk_init_data){
2938 .name = "gcc_smmu_cfg_clk",
2939 .parent_names = (const char *[]){
2940 "pcnoc_bfdcd_clk_src",
2943 .flags = CLK_SET_RATE_PARENT,
2944 .ops = &clk_branch2_ops,
2949 static struct clk_branch gcc_venus_tbu_clk = {
2950 .halt_reg = 0x12014,
2952 .enable_reg = 0x4500c,
2953 .enable_mask = BIT(5),
2954 .hw.init = &(struct clk_init_data){
2955 .name = "gcc_venus_tbu_clk",
2956 .parent_names = (const char *[]){
2957 "system_noc_bfdcd_clk_src",
2960 .flags = CLK_SET_RATE_PARENT,
2961 .ops = &clk_branch2_ops,
2966 static struct clk_branch gcc_vfe_tbu_clk = {
2967 .halt_reg = 0x1203c,
2969 .enable_reg = 0x4500c,
2970 .enable_mask = BIT(9),
2971 .hw.init = &(struct clk_init_data){
2972 .name = "gcc_vfe_tbu_clk",
2973 .parent_names = (const char *[]){
2974 "system_noc_bfdcd_clk_src",
2977 .flags = CLK_SET_RATE_PARENT,
2978 .ops = &clk_branch2_ops,
2983 static struct clk_branch gcc_usb2a_phy_sleep_clk = {
2984 .halt_reg = 0x4102c,
2986 .enable_reg = 0x4102c,
2987 .enable_mask = BIT(0),
2988 .hw.init = &(struct clk_init_data){
2989 .name = "gcc_usb2a_phy_sleep_clk",
2990 .parent_names = (const char *[]){
2994 .flags = CLK_SET_RATE_PARENT,
2995 .ops = &clk_branch2_ops,
3000 static struct clk_branch gcc_usb_hs_ahb_clk = {
3001 .halt_reg = 0x41008,
3003 .enable_reg = 0x41008,
3004 .enable_mask = BIT(0),
3005 .hw.init = &(struct clk_init_data){
3006 .name = "gcc_usb_hs_ahb_clk",
3007 .parent_names = (const char *[]){
3008 "pcnoc_bfdcd_clk_src",
3011 .flags = CLK_SET_RATE_PARENT,
3012 .ops = &clk_branch2_ops,
3017 static struct clk_branch gcc_usb_hs_system_clk = {
3018 .halt_reg = 0x41004,
3020 .enable_reg = 0x41004,
3021 .enable_mask = BIT(0),
3022 .hw.init = &(struct clk_init_data){
3023 .name = "gcc_usb_hs_system_clk",
3024 .parent_names = (const char *[]){
3025 "usb_hs_system_clk_src",
3028 .flags = CLK_SET_RATE_PARENT,
3029 .ops = &clk_branch2_ops,
3034 static struct clk_branch gcc_venus0_ahb_clk = {
3035 .halt_reg = 0x4c020,
3037 .enable_reg = 0x4c020,
3038 .enable_mask = BIT(0),
3039 .hw.init = &(struct clk_init_data){
3040 .name = "gcc_venus0_ahb_clk",
3041 .parent_names = (const char *[]){
3042 "pcnoc_bfdcd_clk_src",
3045 .flags = CLK_SET_RATE_PARENT,
3046 .ops = &clk_branch2_ops,
3051 static struct clk_branch gcc_venus0_axi_clk = {
3052 .halt_reg = 0x4c024,
3054 .enable_reg = 0x4c024,
3055 .enable_mask = BIT(0),
3056 .hw.init = &(struct clk_init_data){
3057 .name = "gcc_venus0_axi_clk",
3058 .parent_names = (const char *[]){
3059 "system_noc_bfdcd_clk_src",
3062 .flags = CLK_SET_RATE_PARENT,
3063 .ops = &clk_branch2_ops,
3068 static struct clk_branch gcc_venus0_vcodec0_clk = {
3069 .halt_reg = 0x4c01c,
3071 .enable_reg = 0x4c01c,
3072 .enable_mask = BIT(0),
3073 .hw.init = &(struct clk_init_data){
3074 .name = "gcc_venus0_vcodec0_clk",
3075 .parent_names = (const char *[]){
3079 .flags = CLK_SET_RATE_PARENT,
3080 .ops = &clk_branch2_ops,
3085 static struct gdsc venus_gdsc = {
3090 .pwrsts = PWRSTS_OFF_ON,
3093 static struct gdsc mdss_gdsc = {
3098 .pwrsts = PWRSTS_OFF_ON,
3101 static struct gdsc jpeg_gdsc = {
3106 .pwrsts = PWRSTS_OFF_ON,
3109 static struct gdsc vfe_gdsc = {
3114 .pwrsts = PWRSTS_OFF_ON,
3117 static struct gdsc oxili_gdsc = {
3122 .pwrsts = PWRSTS_OFF_ON,
3125 static struct clk_regmap *gcc_msm8916_clocks[] = {
3126 [GPLL0] = &gpll0.clkr,
3127 [GPLL0_VOTE] = &gpll0_vote,
3128 [BIMC_PLL] = &bimc_pll.clkr,
3129 [BIMC_PLL_VOTE] = &bimc_pll_vote,
3130 [GPLL1] = &gpll1.clkr,
3131 [GPLL1_VOTE] = &gpll1_vote,
3132 [GPLL2] = &gpll2.clkr,
3133 [GPLL2_VOTE] = &gpll2_vote,
3134 [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
3135 [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
3136 [CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr,
3137 [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
3138 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3139 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3140 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
3141 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3142 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3143 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3144 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3145 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3146 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3147 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3148 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3149 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3150 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3151 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3152 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3153 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3154 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3155 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3156 [CCI_CLK_SRC] = &cci_clk_src.clkr,
3157 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3158 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3159 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3160 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3161 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3162 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3163 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3164 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
3165 [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
3166 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
3167 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
3168 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
3169 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3170 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3171 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
3172 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3173 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
3174 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3175 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3176 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3177 [APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr,
3178 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
3179 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
3180 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3181 [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
3182 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3183 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3184 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3185 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3186 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3187 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3188 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3189 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3190 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3191 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3192 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3193 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3194 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3195 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3196 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3197 [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
3198 [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
3199 [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
3200 [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
3201 [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
3202 [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
3203 [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
3204 [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
3205 [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
3206 [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
3207 [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
3208 [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
3209 [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
3210 [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
3211 [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
3212 [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
3213 [GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
3214 [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
3215 [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
3216 [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
3217 [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
3218 [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
3219 [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
3220 [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
3221 [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
3222 [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
3223 [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
3224 [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
3225 [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
3226 [GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr,
3227 [GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr,
3228 [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
3229 [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
3230 [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
3231 [GCC_OXILI_GMEM_CLK] = &gcc_oxili_gmem_clk.clkr,
3232 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3233 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3234 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3235 [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
3236 [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
3237 [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
3238 [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
3239 [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
3240 [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
3241 [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
3242 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3243 [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
3244 [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
3245 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3246 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3247 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3248 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3249 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3250 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3251 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3252 [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
3253 [GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
3254 [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
3255 [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
3256 [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
3257 [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
3258 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
3259 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
3260 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
3261 [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
3262 [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
3263 [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
3264 [BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr,
3265 [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
3266 [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
3267 [BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr,
3268 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
3269 [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
3270 [ULTAUDIO_AHBFABRIC_CLK_SRC] = &ultaudio_ahbfabric_clk_src.clkr,
3271 [ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC] = &ultaudio_lpaif_pri_i2s_clk_src.clkr,
3272 [ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC] = &ultaudio_lpaif_sec_i2s_clk_src.clkr,
3273 [ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC] = &ultaudio_lpaif_aux_i2s_clk_src.clkr,
3274 [ULTAUDIO_XO_CLK_SRC] = &ultaudio_xo_clk_src.clkr,
3275 [CODEC_DIGCODEC_CLK_SRC] = &codec_digcodec_clk_src.clkr,
3276 [GCC_ULTAUDIO_PCNOC_MPORT_CLK] = &gcc_ultaudio_pcnoc_mport_clk.clkr,
3277 [GCC_ULTAUDIO_PCNOC_SWAY_CLK] = &gcc_ultaudio_pcnoc_sway_clk.clkr,
3278 [GCC_ULTAUDIO_AVSYNC_XO_CLK] = &gcc_ultaudio_avsync_xo_clk.clkr,
3279 [GCC_ULTAUDIO_STC_XO_CLK] = &gcc_ultaudio_stc_xo_clk.clkr,
3280 [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_clk.clkr,
3281 [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_lpm_clk.clkr,
3282 [GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK] = &gcc_ultaudio_lpaif_pri_i2s_clk.clkr,
3283 [GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK] = &gcc_ultaudio_lpaif_sec_i2s_clk.clkr,
3284 [GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK] = &gcc_ultaudio_lpaif_aux_i2s_clk.clkr,
3285 [GCC_CODEC_DIGCODEC_CLK] = &gcc_codec_digcodec_clk.clkr,
3286 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
3289 static struct gdsc *gcc_msm8916_gdscs[] = {
3290 [VENUS_GDSC] = &venus_gdsc,
3291 [MDSS_GDSC] = &mdss_gdsc,
3292 [JPEG_GDSC] = &jpeg_gdsc,
3293 [VFE_GDSC] = &vfe_gdsc,
3294 [OXILI_GDSC] = &oxili_gdsc,
3297 static const struct qcom_reset_map gcc_msm8916_resets[] = {
3298 [GCC_BLSP1_BCR] = { 0x01000 },
3299 [GCC_BLSP1_QUP1_BCR] = { 0x02000 },
3300 [GCC_BLSP1_UART1_BCR] = { 0x02038 },
3301 [GCC_BLSP1_QUP2_BCR] = { 0x03008 },
3302 [GCC_BLSP1_UART2_BCR] = { 0x03028 },
3303 [GCC_BLSP1_QUP3_BCR] = { 0x04018 },
3304 [GCC_BLSP1_QUP4_BCR] = { 0x05018 },
3305 [GCC_BLSP1_QUP5_BCR] = { 0x06018 },
3306 [GCC_BLSP1_QUP6_BCR] = { 0x07018 },
3307 [GCC_IMEM_BCR] = { 0x0e000 },
3308 [GCC_SMMU_BCR] = { 0x12000 },
3309 [GCC_APSS_TCU_BCR] = { 0x12050 },
3310 [GCC_SMMU_XPU_BCR] = { 0x12054 },
3311 [GCC_PCNOC_TBU_BCR] = { 0x12058 },
3312 [GCC_PRNG_BCR] = { 0x13000 },
3313 [GCC_BOOT_ROM_BCR] = { 0x13008 },
3314 [GCC_CRYPTO_BCR] = { 0x16000 },
3315 [GCC_SEC_CTRL_BCR] = { 0x1a000 },
3316 [GCC_AUDIO_CORE_BCR] = { 0x1c008 },
3317 [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
3318 [GCC_DEHR_BCR] = { 0x1f000 },
3319 [GCC_SYSTEM_NOC_BCR] = { 0x26000 },
3320 [GCC_PCNOC_BCR] = { 0x27018 },
3321 [GCC_TCSR_BCR] = { 0x28000 },
3322 [GCC_QDSS_BCR] = { 0x29000 },
3323 [GCC_DCD_BCR] = { 0x2a000 },
3324 [GCC_MSG_RAM_BCR] = { 0x2b000 },
3325 [GCC_MPM_BCR] = { 0x2c000 },
3326 [GCC_SPMI_BCR] = { 0x2e000 },
3327 [GCC_SPDM_BCR] = { 0x2f000 },
3328 [GCC_MM_SPDM_BCR] = { 0x2f024 },
3329 [GCC_BIMC_BCR] = { 0x31000 },
3330 [GCC_RBCPR_BCR] = { 0x33000 },
3331 [GCC_TLMM_BCR] = { 0x34000 },
3332 [GCC_USB_HS_BCR] = { 0x41000 },
3333 [GCC_USB2A_PHY_BCR] = { 0x41028 },
3334 [GCC_SDCC1_BCR] = { 0x42000 },
3335 [GCC_SDCC2_BCR] = { 0x43000 },
3336 [GCC_PDM_BCR] = { 0x44000 },
3337 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 },
3338 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 },
3339 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 },
3340 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 },
3341 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 },
3342 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 },
3343 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 },
3344 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 },
3345 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 },
3346 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 },
3347 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 },
3348 [GCC_MMSS_BCR] = { 0x4b000 },
3349 [GCC_VENUS0_BCR] = { 0x4c014 },
3350 [GCC_MDSS_BCR] = { 0x4d074 },
3351 [GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
3352 [GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
3353 [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
3354 [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
3355 [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
3356 [GCC_CAMSS_PHY1_BCR] = { 0x4f018 },
3357 [GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
3358 [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
3359 [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
3360 [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
3361 [GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
3362 [GCC_CAMSS_CCI_BCR] = { 0x51014 },
3363 [GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
3364 [GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
3365 [GCC_CAMSS_GP0_BCR] = { 0x54014 },
3366 [GCC_CAMSS_GP1_BCR] = { 0x55014 },
3367 [GCC_CAMSS_TOP_BCR] = { 0x56000 },
3368 [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
3369 [GCC_CAMSS_JPEG_BCR] = { 0x57018 },
3370 [GCC_CAMSS_VFE_BCR] = { 0x58030 },
3371 [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
3372 [GCC_OXILI_BCR] = { 0x59018 },
3373 [GCC_GMEM_BCR] = { 0x5902c },
3374 [GCC_CAMSS_AHB_BCR] = { 0x5a018 },
3375 [GCC_MDP_TBU_BCR] = { 0x62000 },
3376 [GCC_GFX_TBU_BCR] = { 0x63000 },
3377 [GCC_GFX_TCU_BCR] = { 0x64000 },
3378 [GCC_MSS_TBU_AXI_BCR] = { 0x65000 },
3379 [GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 },
3380 [GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 },
3381 [GCC_GTCU_AHB_BCR] = { 0x68000 },
3382 [GCC_SMMU_CFG_BCR] = { 0x69000 },
3383 [GCC_VFE_TBU_BCR] = { 0x6a000 },
3384 [GCC_VENUS_TBU_BCR] = { 0x6b000 },
3385 [GCC_JPEG_TBU_BCR] = { 0x6c000 },
3386 [GCC_PRONTO_TBU_BCR] = { 0x6d000 },
3387 [GCC_SMMU_CATS_BCR] = { 0x7c000 },
3390 static const struct regmap_config gcc_msm8916_regmap_config = {
3394 .max_register = 0x80000,
3398 static const struct qcom_cc_desc gcc_msm8916_desc = {
3399 .config = &gcc_msm8916_regmap_config,
3400 .clks = gcc_msm8916_clocks,
3401 .num_clks = ARRAY_SIZE(gcc_msm8916_clocks),
3402 .resets = gcc_msm8916_resets,
3403 .num_resets = ARRAY_SIZE(gcc_msm8916_resets),
3404 .gdscs = gcc_msm8916_gdscs,
3405 .num_gdscs = ARRAY_SIZE(gcc_msm8916_gdscs),
3408 static const struct of_device_id gcc_msm8916_match_table[] = {
3409 { .compatible = "qcom,gcc-msm8916" },
3412 MODULE_DEVICE_TABLE(of, gcc_msm8916_match_table);
3414 static int gcc_msm8916_probe(struct platform_device *pdev)
3417 struct device *dev = &pdev->dev;
3419 ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000);
3423 ret = qcom_cc_register_sleep_clk(dev);
3427 return qcom_cc_probe(pdev, &gcc_msm8916_desc);
3430 static struct platform_driver gcc_msm8916_driver = {
3431 .probe = gcc_msm8916_probe,
3433 .name = "gcc-msm8916",
3434 .of_match_table = gcc_msm8916_match_table,
3438 static int __init gcc_msm8916_init(void)
3440 return platform_driver_register(&gcc_msm8916_driver);
3442 core_initcall(gcc_msm8916_init);
3444 static void __exit gcc_msm8916_exit(void)
3446 platform_driver_unregister(&gcc_msm8916_driver);
3448 module_exit(gcc_msm8916_exit);
3450 MODULE_DESCRIPTION("Qualcomm GCC MSM8916 Driver");
3451 MODULE_LICENSE("GPL v2");
3452 MODULE_ALIAS("platform:gcc-msm8916");