drivers/clk/qcom/gcc-ipq806x.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/bitops.h>
   8 #include <linux/err.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/of_device.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/regmap.h>
  15 #include <linux/reset-controller.h>
  16
  17 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
  18 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
  19
  20 #include "common.h"
  21 #include "clk-regmap.h"
  22 #include "clk-pll.h"
  23 #include "clk-rcg.h"
  24 #include "clk-branch.h"
  25 #include "clk-hfpll.h"
  26 #include "reset.h"
  27
  28 static const struct clk_parent_data gcc_pxo[] = {
  29         { .fw_name = "pxo", .name = "pxo" },
  30 };
  31
  32 static struct clk_pll pll0 = {
  33         .l_reg = 0x30c4,
  34         .m_reg = 0x30c8,
  35         .n_reg = 0x30cc,
  36         .config_reg = 0x30d4,
  37         .mode_reg = 0x30c0,
  38         .status_reg = 0x30d8,
  39         .status_bit = 16,
  40         .clkr.hw.init = &(struct clk_init_data){
  41                 .name = "pll0",
  42                 .parent_data = gcc_pxo,
  43                 .num_parents = 1,
  44                 .ops = &clk_pll_ops,
  45         },
  46 };
  47
  48 static struct clk_regmap pll0_vote = {
  49         .enable_reg = 0x34c0,
  50         .enable_mask = BIT(0),
  51         .hw.init = &(struct clk_init_data){
  52                 .name = "pll0_vote",
  53                 .parent_hws = (const struct clk_hw*[]){
  54                         &pll0.clkr.hw,
  55                 },
  56                 .num_parents = 1,
  57                 .ops = &clk_pll_vote_ops,
  58         },
  59 };
  60
  61 static struct clk_pll pll3 = {
  62         .l_reg = 0x3164,
  63         .m_reg = 0x3168,
  64         .n_reg = 0x316c,
  65         .config_reg = 0x3174,
  66         .mode_reg = 0x3160,
  67         .status_reg = 0x3178,
  68         .status_bit = 16,
  69         .clkr.hw.init = &(struct clk_init_data){
  70                 .name = "pll3",
  71                 .parent_data = gcc_pxo,
  72                 .num_parents = 1,
  73                 .ops = &clk_pll_ops,
  74         },
  75 };
  76
  77 static struct clk_regmap pll4_vote = {
  78         .enable_reg = 0x34c0,
  79         .enable_mask = BIT(4),
  80         .hw.init = &(struct clk_init_data){
  81                 .name = "pll4_vote",
  82                 .parent_names = (const char *[]){ "pll4" },
  83                 .num_parents = 1,
  84                 .ops = &clk_pll_vote_ops,
  85         },
  86 };
  87
  88 static struct clk_pll pll8 = {
  89         .l_reg = 0x3144,
  90         .m_reg = 0x3148,
  91         .n_reg = 0x314c,
  92         .config_reg = 0x3154,
  93         .mode_reg = 0x3140,
  94         .status_reg = 0x3158,
  95         .status_bit = 16,
  96         .clkr.hw.init = &(struct clk_init_data){
  97                 .name = "pll8",
  98                 .parent_data = gcc_pxo,
  99                 .num_parents = 1,
 100                 .ops = &clk_pll_ops,
 101         },
 102 };
 103
 104 static struct clk_regmap pll8_vote = {
 105         .enable_reg = 0x34c0,
 106         .enable_mask = BIT(8),
 107         .hw.init = &(struct clk_init_data){
 108                 .name = "pll8_vote",
 109                 .parent_hws = (const struct clk_hw*[]){
 110                         &pll8.clkr.hw,
 111                 },
 112                 .num_parents = 1,
 113                 .ops = &clk_pll_vote_ops,
 114         },
 115 };
 116
 117 static struct hfpll_data hfpll0_data = {
 118         .mode_reg = 0x3200,
 119         .l_reg = 0x3208,
 120         .m_reg = 0x320c,
 121         .n_reg = 0x3210,
 122         .config_reg = 0x3204,
 123         .status_reg = 0x321c,
 124         .config_val = 0x7845c665,
 125         .droop_reg = 0x3214,
 126         .droop_val = 0x0108c000,
 127         .min_rate = 600000000UL,
 128         .max_rate = 1800000000UL,
 129 };
 130
 131 static struct clk_hfpll hfpll0 = {
 132         .d = &hfpll0_data,
 133         .clkr.hw.init = &(struct clk_init_data){
 134                 .parent_data = gcc_pxo,
 135                 .num_parents = 1,
 136                 .name = "hfpll0",
 137                 .ops = &clk_ops_hfpll,
 138                 .flags = CLK_IGNORE_UNUSED,
 139         },
 140         .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
 141 };
 142
 143 static struct hfpll_data hfpll1_data = {
 144         .mode_reg = 0x3240,
 145         .l_reg = 0x3248,
 146         .m_reg = 0x324c,
 147         .n_reg = 0x3250,
 148         .config_reg = 0x3244,
 149         .status_reg = 0x325c,
 150         .config_val = 0x7845c665,
 151         .droop_reg = 0x3314,
 152         .droop_val = 0x0108c000,
 153         .min_rate = 600000000UL,
 154         .max_rate = 1800000000UL,
 155 };
 156
 157 static struct clk_hfpll hfpll1 = {
 158         .d = &hfpll1_data,
 159         .clkr.hw.init = &(struct clk_init_data){
 160                 .parent_data = gcc_pxo,
 161                 .num_parents = 1,
 162                 .name = "hfpll1",
 163                 .ops = &clk_ops_hfpll,
 164                 .flags = CLK_IGNORE_UNUSED,
 165         },
 166         .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
 167 };
 168
 169 static struct hfpll_data hfpll_l2_data = {
 170         .mode_reg = 0x3300,
 171         .l_reg = 0x3308,
 172         .m_reg = 0x330c,
 173         .n_reg = 0x3310,
 174         .config_reg = 0x3304,
 175         .status_reg = 0x331c,
 176         .config_val = 0x7845c665,
 177         .droop_reg = 0x3314,
 178         .droop_val = 0x0108c000,
 179         .min_rate = 600000000UL,
 180         .max_rate = 1800000000UL,
 181 };
 182
 183 static struct clk_hfpll hfpll_l2 = {
 184         .d = &hfpll_l2_data,
 185         .clkr.hw.init = &(struct clk_init_data){
 186                 .parent_data = gcc_pxo,
 187                 .num_parents = 1,
 188                 .name = "hfpll_l2",
 189                 .ops = &clk_ops_hfpll,
 190                 .flags = CLK_IGNORE_UNUSED,
 191         },
 192         .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
 193 };
 194
 195 static struct clk_pll pll14 = {
 196         .l_reg = 0x31c4,
 197         .m_reg = 0x31c8,
 198         .n_reg = 0x31cc,
 199         .config_reg = 0x31d4,
 200         .mode_reg = 0x31c0,
 201         .status_reg = 0x31d8,
 202         .status_bit = 16,
 203         .clkr.hw.init = &(struct clk_init_data){
 204                 .name = "pll14",
 205                 .parent_data = gcc_pxo,
 206                 .num_parents = 1,
 207                 .ops = &clk_pll_ops,
 208         },
 209 };
 210
 211 static struct clk_regmap pll14_vote = {
 212         .enable_reg = 0x34c0,
 213         .enable_mask = BIT(14),
 214         .hw.init = &(struct clk_init_data){
 215                 .name = "pll14_vote",
 216                 .parent_hws = (const struct clk_hw*[]){
 217                         &pll14.clkr.hw,
 218                 },
 219                 .num_parents = 1,
 220                 .ops = &clk_pll_vote_ops,
 221         },
 222 };
 223
 224 #define NSS_PLL_RATE(f, _l, _m, _n, i) \
 225         {  \
 226                 .freq = f,  \
 227                 .l = _l, \
 228                 .m = _m, \
 229                 .n = _n, \
 230                 .ibits = i, \
 231         }
 232
 233 static struct pll_freq_tbl pll18_freq_tbl[] = {
 234         NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
 235         NSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625),
 236         NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),
 237         NSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625),
 238 };
 239
 240 static struct clk_pll pll18 = {
 241         .l_reg = 0x31a4,
 242         .m_reg = 0x31a8,
 243         .n_reg = 0x31ac,
 244         .config_reg = 0x31b4,
 245         .mode_reg = 0x31a0,
 246         .status_reg = 0x31b8,
 247         .status_bit = 16,
 248         .post_div_shift = 16,
 249         .post_div_width = 1,
 250         .freq_tbl = pll18_freq_tbl,
 251         .clkr.hw.init = &(struct clk_init_data){
 252                 .name = "pll18",
 253                 .parent_data = gcc_pxo,
 254                 .num_parents = 1,
 255                 .ops = &clk_pll_ops,
 256         },
 257 };
 258
 259 static struct clk_pll pll11 = {
 260         .l_reg = 0x3184,
 261         .m_reg = 0x3188,
 262         .n_reg = 0x318c,
 263         .config_reg = 0x3194,
 264         .mode_reg = 0x3180,
 265         .status_reg = 0x3198,
 266         .status_bit = 16,
 267         .clkr.hw.init = &(struct clk_init_data){
 268                 .name = "pll11",
 269                 .parent_data = &(const struct clk_parent_data){
 270                         .fw_name = "pxo",
 271                 },
 272                 .num_parents = 1,
 273                 .ops = &clk_pll_ops,
 274         },
 275 };
 276
 277 enum {
 278         P_PXO,
 279         P_PLL8,
 280         P_PLL3,
 281         P_PLL0,
 282         P_CXO,
 283         P_PLL14,
 284         P_PLL18,
 285         P_PLL11,
 286 };
 287
 288 static const struct parent_map gcc_pxo_pll8_map[] = {
 289         { P_PXO, 0 },
 290         { P_PLL8, 3 }
 291 };
 292
 293 static const struct clk_parent_data gcc_pxo_pll8[] = {
 294         { .fw_name = "pxo", .name = "pxo" },
 295         { .hw = &pll8_vote.hw },
 296 };
 297
 298 static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
 299         { P_PXO, 0 },
 300         { P_PLL8, 3 },
 301         { P_CXO, 5 }
 302 };
 303
 304 static const struct clk_parent_data gcc_pxo_pll8_cxo[] = {
 305         { .fw_name = "pxo", .name = "pxo" },
 306         { .hw = &pll8_vote.hw },
 307         { .fw_name = "cxo", .name = "cxo" },
 308 };
 309
 310 static const struct parent_map gcc_pxo_pll3_map[] = {
 311         { P_PXO, 0 },
 312         { P_PLL3, 1 }
 313 };
 314
 315 static const struct parent_map gcc_pxo_pll3_sata_map[] = {
 316         { P_PXO, 0 },
 317         { P_PLL3, 6 }
 318 };
 319
 320 static const struct clk_parent_data gcc_pxo_pll3[] = {
 321         { .fw_name = "pxo", .name = "pxo" },
 322         { .hw = &pll3.clkr.hw },
 323 };
 324
 325 static const struct parent_map gcc_pxo_pll8_pll0_map[] = {
 326         { P_PXO, 0 },
 327         { P_PLL8, 3 },
 328         { P_PLL0, 2 }
 329 };
 330
 331 static const struct clk_parent_data gcc_pxo_pll8_pll0[] = {
 332         { .fw_name = "pxo", .name = "pxo" },
 333         { .hw = &pll8_vote.hw },
 334         { .hw = &pll0_vote.hw },
 335 };
 336
 337 static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = {
 338         { P_PXO, 0 },
 339         { P_PLL8, 4 },
 340         { P_PLL0, 2 },
 341         { P_PLL14, 5 },
 342         { P_PLL18, 1 }
 343 };
 344
 345 static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = {
 346         { .fw_name = "pxo", .name = "pxo" },
 347         { .hw = &pll8_vote.hw },
 348         { .hw = &pll0_vote.hw },
 349         { .hw = &pll14.clkr.hw },
 350         { .hw = &pll18.clkr.hw },
 351 };
 352
 353 static const struct parent_map gcc_pxo_pll8_pll0_pll14_pll18_pll11_map[] = {
 354         { P_PXO, 0 },
 355         { P_PLL8, 4 },
 356         { P_PLL0, 2 },
 357         { P_PLL14, 5 },
 358         { P_PLL18, 1 },
 359         { P_PLL11, 3 },
 360 };
 361
 362 static const struct clk_parent_data gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = {
 363         { .fw_name = "pxo" },
 364         { .hw = &pll8_vote.hw },
 365         { .hw = &pll0_vote.hw },
 366         { .hw = &pll14.clkr.hw },
 367         { .hw = &pll18.clkr.hw },
 368         { .hw = &pll11.clkr.hw },
 369
 370 };
 371
 372 static const struct parent_map gcc_pxo_pll3_pll0_pll14_pll18_pll11_map[] = {
 373         { P_PXO, 0 },
 374         { P_PLL3, 6 },
 375         { P_PLL0, 2 },
 376         { P_PLL14, 5 },
 377         { P_PLL18, 1 },
 378         { P_PLL11, 3 },
 379 };
 380
 381 static const struct clk_parent_data gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = {
 382         { .fw_name = "pxo" },
 383         { .hw = &pll3.clkr.hw },
 384         { .hw = &pll0_vote.hw },
 385         { .hw = &pll14.clkr.hw },
 386         { .hw = &pll18.clkr.hw },
 387         { .hw = &pll11.clkr.hw },
 388
 389 };
 390
 391 static struct freq_tbl clk_tbl_gsbi_uart[] = {
 392         {  1843200, P_PLL8, 2,  6, 625 },
 393         {  3686400, P_PLL8, 2, 12, 625 },
 394         {  7372800, P_PLL8, 2, 24, 625 },
 395         { 14745600, P_PLL8, 2, 48, 625 },
 396         { 16000000, P_PLL8, 4,  1,   6 },
 397         { 24000000, P_PLL8, 4,  1,   4 },
 398         { 32000000, P_PLL8, 4,  1,   3 },
 399         { 40000000, P_PLL8, 1,  5,  48 },
 400         { 46400000, P_PLL8, 1, 29, 240 },
 401         { 48000000, P_PLL8, 4,  1,   2 },
 402         { 51200000, P_PLL8, 1,  2,  15 },
 403         { 56000000, P_PLL8, 1,  7,  48 },
 404         { 58982400, P_PLL8, 1, 96, 625 },
 405         { 64000000, P_PLL8, 2,  1,   3 },
 406         { }
 407 };
 408
 409 static struct clk_rcg gsbi1_uart_src = {
 410         .ns_reg = 0x29d4,
 411         .md_reg = 0x29d0,
 412         .mn = {
 413                 .mnctr_en_bit = 8,
 414                 .mnctr_reset_bit = 7,
 415                 .mnctr_mode_shift = 5,
 416                 .n_val_shift = 16,
 417                 .m_val_shift = 16,
 418                 .width = 16,
 419         },
 420         .p = {
 421                 .pre_div_shift = 3,
 422                 .pre_div_width = 2,
 423         },
 424         .s = {
 425                 .src_sel_shift = 0,
 426                 .parent_map = gcc_pxo_pll8_map,
 427         },
 428         .freq_tbl = clk_tbl_gsbi_uart,
 429         .clkr = {
 430                 .enable_reg = 0x29d4,
 431                 .enable_mask = BIT(11),
 432                 .hw.init = &(struct clk_init_data){
 433                         .name = "gsbi1_uart_src",
 434                         .parent_data = gcc_pxo_pll8,
 435                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 436                         .ops = &clk_rcg_ops,
 437                         .flags = CLK_SET_PARENT_GATE,
 438                 },
 439         },
 440 };
 441
 442 static struct clk_branch gsbi1_uart_clk = {
 443         .halt_reg = 0x2fcc,
 444         .halt_bit = 12,
 445         .clkr = {
 446                 .enable_reg = 0x29d4,
 447                 .enable_mask = BIT(9),
 448                 .hw.init = &(struct clk_init_data){
 449                         .name = "gsbi1_uart_clk",
 450                         .parent_hws = (const struct clk_hw*[]){
 451                                 &gsbi1_uart_src.clkr.hw,
 452                         },
 453                         .num_parents = 1,
 454                         .ops = &clk_branch_ops,
 455                         .flags = CLK_SET_RATE_PARENT,
 456                 },
 457         },
 458 };
 459
 460 static struct clk_rcg gsbi2_uart_src = {
 461         .ns_reg = 0x29f4,
 462         .md_reg = 0x29f0,
 463         .mn = {
 464                 .mnctr_en_bit = 8,
 465                 .mnctr_reset_bit = 7,
 466                 .mnctr_mode_shift = 5,
 467                 .n_val_shift = 16,
 468                 .m_val_shift = 16,
 469                 .width = 16,
 470         },
 471         .p = {
 472                 .pre_div_shift = 3,
 473                 .pre_div_width = 2,
 474         },
 475         .s = {
 476                 .src_sel_shift = 0,
 477                 .parent_map = gcc_pxo_pll8_map,
 478         },
 479         .freq_tbl = clk_tbl_gsbi_uart,
 480         .clkr = {
 481                 .enable_reg = 0x29f4,
 482                 .enable_mask = BIT(11),
 483                 .hw.init = &(struct clk_init_data){
 484                         .name = "gsbi2_uart_src",
 485                         .parent_data = gcc_pxo_pll8,
 486                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 487                         .ops = &clk_rcg_ops,
 488                         .flags = CLK_SET_PARENT_GATE,
 489                 },
 490         },
 491 };
 492
 493 static struct clk_branch gsbi2_uart_clk = {
 494         .halt_reg = 0x2fcc,
 495         .halt_bit = 8,
 496         .clkr = {
 497                 .enable_reg = 0x29f4,
 498                 .enable_mask = BIT(9),
 499                 .hw.init = &(struct clk_init_data){
 500                         .name = "gsbi2_uart_clk",
 501                         .parent_hws = (const struct clk_hw*[]){
 502                                 &gsbi2_uart_src.clkr.hw,
 503                         },
 504                         .num_parents = 1,
 505                         .ops = &clk_branch_ops,
 506                         .flags = CLK_SET_RATE_PARENT,
 507                 },
 508         },
 509 };
 510
 511 static struct clk_rcg gsbi4_uart_src = {
 512         .ns_reg = 0x2a34,
 513         .md_reg = 0x2a30,
 514         .mn = {
 515                 .mnctr_en_bit = 8,
 516                 .mnctr_reset_bit = 7,
 517                 .mnctr_mode_shift = 5,
 518                 .n_val_shift = 16,
 519                 .m_val_shift = 16,
 520                 .width = 16,
 521         },
 522         .p = {
 523                 .pre_div_shift = 3,
 524                 .pre_div_width = 2,
 525         },
 526         .s = {
 527                 .src_sel_shift = 0,
 528                 .parent_map = gcc_pxo_pll8_map,
 529         },
 530         .freq_tbl = clk_tbl_gsbi_uart,
 531         .clkr = {
 532                 .enable_reg = 0x2a34,
 533                 .enable_mask = BIT(11),
 534                 .hw.init = &(struct clk_init_data){
 535                         .name = "gsbi4_uart_src",
 536                         .parent_data = gcc_pxo_pll8,
 537                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 538                         .ops = &clk_rcg_ops,
 539                         .flags = CLK_SET_PARENT_GATE,
 540                 },
 541         },
 542 };
 543
 544 static struct clk_branch gsbi4_uart_clk = {
 545         .halt_reg = 0x2fd0,
 546         .halt_bit = 26,
 547         .clkr = {
 548                 .enable_reg = 0x2a34,
 549                 .enable_mask = BIT(9),
 550                 .hw.init = &(struct clk_init_data){
 551                         .name = "gsbi4_uart_clk",
 552                         .parent_hws = (const struct clk_hw*[]){
 553                                 &gsbi4_uart_src.clkr.hw,
 554                         },
 555                         .num_parents = 1,
 556                         .ops = &clk_branch_ops,
 557                         .flags = CLK_SET_RATE_PARENT,
 558                 },
 559         },
 560 };
 561
 562 static struct clk_rcg gsbi5_uart_src = {
 563         .ns_reg = 0x2a54,
 564         .md_reg = 0x2a50,
 565         .mn = {
 566                 .mnctr_en_bit = 8,
 567                 .mnctr_reset_bit = 7,
 568                 .mnctr_mode_shift = 5,
 569                 .n_val_shift = 16,
 570                 .m_val_shift = 16,
 571                 .width = 16,
 572         },
 573         .p = {
 574                 .pre_div_shift = 3,
 575                 .pre_div_width = 2,
 576         },
 577         .s = {
 578                 .src_sel_shift = 0,
 579                 .parent_map = gcc_pxo_pll8_map,
 580         },
 581         .freq_tbl = clk_tbl_gsbi_uart,
 582         .clkr = {
 583                 .enable_reg = 0x2a54,
 584                 .enable_mask = BIT(11),
 585                 .hw.init = &(struct clk_init_data){
 586                         .name = "gsbi5_uart_src",
 587                         .parent_data = gcc_pxo_pll8,
 588                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 589                         .ops = &clk_rcg_ops,
 590                         .flags = CLK_SET_PARENT_GATE,
 591                 },
 592         },
 593 };
 594
 595 static struct clk_branch gsbi5_uart_clk = {
 596         .halt_reg = 0x2fd0,
 597         .halt_bit = 22,
 598         .clkr = {
 599                 .enable_reg = 0x2a54,
 600                 .enable_mask = BIT(9),
 601                 .hw.init = &(struct clk_init_data){
 602                         .name = "gsbi5_uart_clk",
 603                         .parent_hws = (const struct clk_hw*[]){
 604                                 &gsbi5_uart_src.clkr.hw,
 605                         },
 606                         .num_parents = 1,
 607                         .ops = &clk_branch_ops,
 608                         .flags = CLK_SET_RATE_PARENT,
 609                 },
 610         },
 611 };
 612
 613 static struct clk_rcg gsbi6_uart_src = {
 614         .ns_reg = 0x2a74,
 615         .md_reg = 0x2a70,
 616         .mn = {
 617                 .mnctr_en_bit = 8,
 618                 .mnctr_reset_bit = 7,
 619                 .mnctr_mode_shift = 5,
 620                 .n_val_shift = 16,
 621                 .m_val_shift = 16,
 622                 .width = 16,
 623         },
 624         .p = {
 625                 .pre_div_shift = 3,
 626                 .pre_div_width = 2,
 627         },
 628         .s = {
 629                 .src_sel_shift = 0,
 630                 .parent_map = gcc_pxo_pll8_map,
 631         },
 632         .freq_tbl = clk_tbl_gsbi_uart,
 633         .clkr = {
 634                 .enable_reg = 0x2a74,
 635                 .enable_mask = BIT(11),
 636                 .hw.init = &(struct clk_init_data){
 637                         .name = "gsbi6_uart_src",
 638                         .parent_data = gcc_pxo_pll8,
 639                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 640                         .ops = &clk_rcg_ops,
 641                         .flags = CLK_SET_PARENT_GATE,
 642                 },
 643         },
 644 };
 645
 646 static struct clk_branch gsbi6_uart_clk = {
 647         .halt_reg = 0x2fd0,
 648         .halt_bit = 18,
 649         .clkr = {
 650                 .enable_reg = 0x2a74,
 651                 .enable_mask = BIT(9),
 652                 .hw.init = &(struct clk_init_data){
 653                         .name = "gsbi6_uart_clk",
 654                         .parent_hws = (const struct clk_hw*[]){
 655                                 &gsbi6_uart_src.clkr.hw,
 656                         },
 657                         .num_parents = 1,
 658                         .ops = &clk_branch_ops,
 659                         .flags = CLK_SET_RATE_PARENT,
 660                 },
 661         },
 662 };
 663
 664 static struct clk_rcg gsbi7_uart_src = {
 665         .ns_reg = 0x2a94,
 666         .md_reg = 0x2a90,
 667         .mn = {
 668                 .mnctr_en_bit = 8,
 669                 .mnctr_reset_bit = 7,
 670                 .mnctr_mode_shift = 5,
 671                 .n_val_shift = 16,
 672                 .m_val_shift = 16,
 673                 .width = 16,
 674         },
 675         .p = {
 676                 .pre_div_shift = 3,
 677                 .pre_div_width = 2,
 678         },
 679         .s = {
 680                 .src_sel_shift = 0,
 681                 .parent_map = gcc_pxo_pll8_map,
 682         },
 683         .freq_tbl = clk_tbl_gsbi_uart,
 684         .clkr = {
 685                 .enable_reg = 0x2a94,
 686                 .enable_mask = BIT(11),
 687                 .hw.init = &(struct clk_init_data){
 688                         .name = "gsbi7_uart_src",
 689                         .parent_data = gcc_pxo_pll8,
 690                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 691                         .ops = &clk_rcg_ops,
 692                         .flags = CLK_SET_PARENT_GATE,
 693                 },
 694         },
 695 };
 696
 697 static struct clk_branch gsbi7_uart_clk = {
 698         .halt_reg = 0x2fd0,
 699         .halt_bit = 14,
 700         .clkr = {
 701                 .enable_reg = 0x2a94,
 702                 .enable_mask = BIT(9),
 703                 .hw.init = &(struct clk_init_data){
 704                         .name = "gsbi7_uart_clk",
 705                         .parent_hws = (const struct clk_hw*[]){
 706                                 &gsbi7_uart_src.clkr.hw,
 707                         },
 708                         .num_parents = 1,
 709                         .ops = &clk_branch_ops,
 710                         .flags = CLK_SET_RATE_PARENT,
 711                 },
 712         },
 713 };
 714
 715 static struct freq_tbl clk_tbl_gsbi_qup[] = {
 716         {  1100000, P_PXO,  1, 2, 49 },
 717         {  5400000, P_PXO,  1, 1,  5 },
 718         { 10800000, P_PXO,  1, 2,  5 },
 719         { 15060000, P_PLL8, 1, 2, 51 },
 720         { 24000000, P_PLL8, 4, 1,  4 },
 721         { 25000000, P_PXO,  1, 0,  0 },
 722         { 25600000, P_PLL8, 1, 1, 15 },
 723         { 48000000, P_PLL8, 4, 1,  2 },
 724         { 51200000, P_PLL8, 1, 2, 15 },
 725         { }
 726 };
 727
 728 static struct clk_rcg gsbi1_qup_src = {
 729         .ns_reg = 0x29cc,
 730         .md_reg = 0x29c8,
 731         .mn = {
 732                 .mnctr_en_bit = 8,
 733                 .mnctr_reset_bit = 7,
 734                 .mnctr_mode_shift = 5,
 735                 .n_val_shift = 16,
 736                 .m_val_shift = 16,
 737                 .width = 8,
 738         },
 739         .p = {
 740                 .pre_div_shift = 3,
 741                 .pre_div_width = 2,
 742         },
 743         .s = {
 744                 .src_sel_shift = 0,
 745                 .parent_map = gcc_pxo_pll8_map,
 746         },
 747         .freq_tbl = clk_tbl_gsbi_qup,
 748         .clkr = {
 749                 .enable_reg = 0x29cc,
 750                 .enable_mask = BIT(11),
 751                 .hw.init = &(struct clk_init_data){
 752                         .name = "gsbi1_qup_src",
 753                         .parent_data = gcc_pxo_pll8,
 754                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 755                         .ops = &clk_rcg_ops,
 756                         .flags = CLK_SET_PARENT_GATE,
 757                 },
 758         },
 759 };
 760
 761 static struct clk_branch gsbi1_qup_clk = {
 762         .halt_reg = 0x2fcc,
 763         .halt_bit = 11,
 764         .clkr = {
 765                 .enable_reg = 0x29cc,
 766                 .enable_mask = BIT(9),
 767                 .hw.init = &(struct clk_init_data){
 768                         .name = "gsbi1_qup_clk",
 769                         .parent_hws = (const struct clk_hw*[]){
 770                                 &gsbi1_qup_src.clkr.hw,
 771                         },
 772                         .num_parents = 1,
 773                         .ops = &clk_branch_ops,
 774                         .flags = CLK_SET_RATE_PARENT,
 775                 },
 776         },
 777 };
 778
 779 static struct clk_rcg gsbi2_qup_src = {
 780         .ns_reg = 0x29ec,
 781         .md_reg = 0x29e8,
 782         .mn = {
 783                 .mnctr_en_bit = 8,
 784                 .mnctr_reset_bit = 7,
 785                 .mnctr_mode_shift = 5,
 786                 .n_val_shift = 16,
 787                 .m_val_shift = 16,
 788                 .width = 8,
 789         },
 790         .p = {
 791                 .pre_div_shift = 3,
 792                 .pre_div_width = 2,
 793         },
 794         .s = {
 795                 .src_sel_shift = 0,
 796                 .parent_map = gcc_pxo_pll8_map,
 797         },
 798         .freq_tbl = clk_tbl_gsbi_qup,
 799         .clkr = {
 800                 .enable_reg = 0x29ec,
 801                 .enable_mask = BIT(11),
 802                 .hw.init = &(struct clk_init_data){
 803                         .name = "gsbi2_qup_src",
 804                         .parent_data = gcc_pxo_pll8,
 805                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 806                         .ops = &clk_rcg_ops,
 807                         .flags = CLK_SET_PARENT_GATE,
 808                 },
 809         },
 810 };
 811
 812 static struct clk_branch gsbi2_qup_clk = {
 813         .halt_reg = 0x2fcc,
 814         .halt_bit = 6,
 815         .clkr = {
 816                 .enable_reg = 0x29ec,
 817                 .enable_mask = BIT(9),
 818                 .hw.init = &(struct clk_init_data){
 819                         .name = "gsbi2_qup_clk",
 820                         .parent_hws = (const struct clk_hw*[]){
 821                                 &gsbi2_qup_src.clkr.hw,
 822                         },
 823                         .num_parents = 1,
 824                         .ops = &clk_branch_ops,
 825                         .flags = CLK_SET_RATE_PARENT,
 826                 },
 827         },
 828 };
 829
 830 static struct clk_rcg gsbi4_qup_src = {
 831         .ns_reg = 0x2a2c,
 832         .md_reg = 0x2a28,
 833         .mn = {
 834                 .mnctr_en_bit = 8,
 835                 .mnctr_reset_bit = 7,
 836                 .mnctr_mode_shift = 5,
 837                 .n_val_shift = 16,
 838                 .m_val_shift = 16,
 839                 .width = 8,
 840         },
 841         .p = {
 842                 .pre_div_shift = 3,
 843                 .pre_div_width = 2,
 844         },
 845         .s = {
 846                 .src_sel_shift = 0,
 847                 .parent_map = gcc_pxo_pll8_map,
 848         },
 849         .freq_tbl = clk_tbl_gsbi_qup,
 850         .clkr = {
 851                 .enable_reg = 0x2a2c,
 852                 .enable_mask = BIT(11),
 853                 .hw.init = &(struct clk_init_data){
 854                         .name = "gsbi4_qup_src",
 855                         .parent_data = gcc_pxo_pll8,
 856                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 857                         .ops = &clk_rcg_ops,
 858                         .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
 859                 },
 860         },
 861 };
 862
 863 static struct clk_branch gsbi4_qup_clk = {
 864         .halt_reg = 0x2fd0,
 865         .halt_bit = 24,
 866         .clkr = {
 867                 .enable_reg = 0x2a2c,
 868                 .enable_mask = BIT(9),
 869                 .hw.init = &(struct clk_init_data){
 870                         .name = "gsbi4_qup_clk",
 871                         .parent_hws = (const struct clk_hw*[]){
 872                                 &gsbi4_qup_src.clkr.hw,
 873                         },
 874                         .num_parents = 1,
 875                         .ops = &clk_branch_ops,
 876                         .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
 877                 },
 878         },
 879 };
 880
 881 static struct clk_rcg gsbi5_qup_src = {
 882         .ns_reg = 0x2a4c,
 883         .md_reg = 0x2a48,
 884         .mn = {
 885                 .mnctr_en_bit = 8,
 886                 .mnctr_reset_bit = 7,
 887                 .mnctr_mode_shift = 5,
 888                 .n_val_shift = 16,
 889                 .m_val_shift = 16,
 890                 .width = 8,
 891         },
 892         .p = {
 893                 .pre_div_shift = 3,
 894                 .pre_div_width = 2,
 895         },
 896         .s = {
 897                 .src_sel_shift = 0,
 898                 .parent_map = gcc_pxo_pll8_map,
 899         },
 900         .freq_tbl = clk_tbl_gsbi_qup,
 901         .clkr = {
 902                 .enable_reg = 0x2a4c,
 903                 .enable_mask = BIT(11),
 904                 .hw.init = &(struct clk_init_data){
 905                         .name = "gsbi5_qup_src",
 906                         .parent_data = gcc_pxo_pll8,
 907                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 908                         .ops = &clk_rcg_ops,
 909                         .flags = CLK_SET_PARENT_GATE,
 910                 },
 911         },
 912 };
 913
 914 static struct clk_branch gsbi5_qup_clk = {
 915         .halt_reg = 0x2fd0,
 916         .halt_bit = 20,
 917         .clkr = {
 918                 .enable_reg = 0x2a4c,
 919                 .enable_mask = BIT(9),
 920                 .hw.init = &(struct clk_init_data){
 921                         .name = "gsbi5_qup_clk",
 922                         .parent_hws = (const struct clk_hw*[]){
 923                                 &gsbi5_qup_src.clkr.hw,
 924                         },
 925                         .num_parents = 1,
 926                         .ops = &clk_branch_ops,
 927                         .flags = CLK_SET_RATE_PARENT,
 928                 },
 929         },
 930 };
 931
 932 static struct clk_rcg gsbi6_qup_src = {
 933         .ns_reg = 0x2a6c,
 934         .md_reg = 0x2a68,
 935         .mn = {
 936                 .mnctr_en_bit = 8,
 937                 .mnctr_reset_bit = 7,
 938                 .mnctr_mode_shift = 5,
 939                 .n_val_shift = 16,
 940                 .m_val_shift = 16,
 941                 .width = 8,
 942         },
 943         .p = {
 944                 .pre_div_shift = 3,
 945                 .pre_div_width = 2,
 946         },
 947         .s = {
 948                 .src_sel_shift = 0,
 949                 .parent_map = gcc_pxo_pll8_map,
 950         },
 951         .freq_tbl = clk_tbl_gsbi_qup,
 952         .clkr = {
 953                 .enable_reg = 0x2a6c,
 954                 .enable_mask = BIT(11),
 955                 .hw.init = &(struct clk_init_data){
 956                         .name = "gsbi6_qup_src",
 957                         .parent_data = gcc_pxo_pll8,
 958                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 959                         .ops = &clk_rcg_ops,
 960                         .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
 961                 },
 962         },
 963 };
 964
 965 static struct clk_branch gsbi6_qup_clk = {
 966         .halt_reg = 0x2fd0,
 967         .halt_bit = 16,
 968         .clkr = {
 969                 .enable_reg = 0x2a6c,
 970                 .enable_mask = BIT(9),
 971                 .hw.init = &(struct clk_init_data){
 972                         .name = "gsbi6_qup_clk",
 973                         .parent_hws = (const struct clk_hw*[]){
 974                                 &gsbi6_qup_src.clkr.hw,
 975                         },
 976                         .num_parents = 1,
 977                         .ops = &clk_branch_ops,
 978                         .flags = CLK_SET_RATE_PARENT,
 979                 },
 980         },
 981 };
 982
 983 static struct clk_rcg gsbi7_qup_src = {
 984         .ns_reg = 0x2a8c,
 985         .md_reg = 0x2a88,
 986         .mn = {
 987                 .mnctr_en_bit = 8,
 988                 .mnctr_reset_bit = 7,
 989                 .mnctr_mode_shift = 5,
 990                 .n_val_shift = 16,
 991                 .m_val_shift = 16,
 992                 .width = 8,
 993         },
 994         .p = {
 995                 .pre_div_shift = 3,
 996                 .pre_div_width = 2,
 997         },
 998         .s = {
 999                 .src_sel_shift = 0,
1000                 .parent_map = gcc_pxo_pll8_map,
1001         },
1002         .freq_tbl = clk_tbl_gsbi_qup,
1003         .clkr = {
1004                 .enable_reg = 0x2a8c,
1005                 .enable_mask = BIT(11),
1006                 .hw.init = &(struct clk_init_data){
1007                         .name = "gsbi7_qup_src",
1008                         .parent_data = gcc_pxo_pll8,
1009                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1010                         .ops = &clk_rcg_ops,
1011                         .flags = CLK_SET_PARENT_GATE,
1012                 },
1013         },
1014 };
1015
1016 static struct clk_branch gsbi7_qup_clk = {
1017         .halt_reg = 0x2fd0,
1018         .halt_bit = 12,
1019         .clkr = {
1020                 .enable_reg = 0x2a8c,
1021                 .enable_mask = BIT(9),
1022                 .hw.init = &(struct clk_init_data){
1023                         .name = "gsbi7_qup_clk",
1024                         .parent_hws = (const struct clk_hw*[]){
1025                                 &gsbi7_qup_src.clkr.hw,
1026                         },
1027                         .num_parents = 1,
1028                         .ops = &clk_branch_ops,
1029                         .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1030                 },
1031         },
1032 };
1033
1034 static struct clk_branch gsbi1_h_clk = {
1035         .hwcg_reg = 0x29c0,
1036         .hwcg_bit = 6,
1037         .halt_reg = 0x2fcc,
1038         .halt_bit = 13,
1039         .clkr = {
1040                 .enable_reg = 0x29c0,
1041                 .enable_mask = BIT(4),
1042                 .hw.init = &(struct clk_init_data){
1043                         .name = "gsbi1_h_clk",
1044                         .ops = &clk_branch_ops,
1045                 },
1046         },
1047 };
1048
1049 static struct clk_branch gsbi2_h_clk = {
1050         .hwcg_reg = 0x29e0,
1051         .hwcg_bit = 6,
1052         .halt_reg = 0x2fcc,
1053         .halt_bit = 9,
1054         .clkr = {
1055                 .enable_reg = 0x29e0,
1056                 .enable_mask = BIT(4),
1057                 .hw.init = &(struct clk_init_data){
1058                         .name = "gsbi2_h_clk",
1059                         .ops = &clk_branch_ops,
1060                 },
1061         },
1062 };
1063
1064 static struct clk_branch gsbi4_h_clk = {
1065         .hwcg_reg = 0x2a20,
1066         .hwcg_bit = 6,
1067         .halt_reg = 0x2fd0,
1068         .halt_bit = 27,
1069         .clkr = {
1070                 .enable_reg = 0x2a20,
1071                 .enable_mask = BIT(4),
1072                 .hw.init = &(struct clk_init_data){
1073                         .name = "gsbi4_h_clk",
1074                         .ops = &clk_branch_ops,
1075                         .flags = CLK_IGNORE_UNUSED,
1076                 },
1077         },
1078 };
1079
1080 static struct clk_branch gsbi5_h_clk = {
1081         .hwcg_reg = 0x2a40,
1082         .hwcg_bit = 6,
1083         .halt_reg = 0x2fd0,
1084         .halt_bit = 23,
1085         .clkr = {
1086                 .enable_reg = 0x2a40,
1087                 .enable_mask = BIT(4),
1088                 .hw.init = &(struct clk_init_data){
1089                         .name = "gsbi5_h_clk",
1090                         .ops = &clk_branch_ops,
1091                 },
1092         },
1093 };
1094
1095 static struct clk_branch gsbi6_h_clk = {
1096         .hwcg_reg = 0x2a60,
1097         .hwcg_bit = 6,
1098         .halt_reg = 0x2fd0,
1099         .halt_bit = 19,
1100         .clkr = {
1101                 .enable_reg = 0x2a60,
1102                 .enable_mask = BIT(4),
1103                 .hw.init = &(struct clk_init_data){
1104                         .name = "gsbi6_h_clk",
1105                         .ops = &clk_branch_ops,
1106                 },
1107         },
1108 };
1109
1110 static struct clk_branch gsbi7_h_clk = {
1111         .hwcg_reg = 0x2a80,
1112         .hwcg_bit = 6,
1113         .halt_reg = 0x2fd0,
1114         .halt_bit = 15,
1115         .clkr = {
1116                 .enable_reg = 0x2a80,
1117                 .enable_mask = BIT(4),
1118                 .hw.init = &(struct clk_init_data){
1119                         .name = "gsbi7_h_clk",
1120                         .ops = &clk_branch_ops,
1121                 },
1122         },
1123 };
1124
1125 static const struct freq_tbl clk_tbl_gp[] = {
1126         { 12500000, P_PXO,  2, 0, 0 },
1127         { 25000000, P_PXO,  1, 0, 0 },
1128         { 64000000, P_PLL8, 2, 1, 3 },
1129         { 76800000, P_PLL8, 1, 1, 5 },
1130         { 96000000, P_PLL8, 4, 0, 0 },
1131         { 128000000, P_PLL8, 3, 0, 0 },
1132         { 192000000, P_PLL8, 2, 0, 0 },
1133         { }
1134 };
1135
1136 static struct clk_rcg gp0_src = {
1137         .ns_reg = 0x2d24,
1138         .md_reg = 0x2d00,
1139         .mn = {
1140                 .mnctr_en_bit = 8,
1141                 .mnctr_reset_bit = 7,
1142                 .mnctr_mode_shift = 5,
1143                 .n_val_shift = 16,
1144                 .m_val_shift = 16,
1145                 .width = 8,
1146         },
1147         .p = {
1148                 .pre_div_shift = 3,
1149                 .pre_div_width = 2,
1150         },
1151         .s = {
1152                 .src_sel_shift = 0,
1153                 .parent_map = gcc_pxo_pll8_cxo_map,
1154         },
1155         .freq_tbl = clk_tbl_gp,
1156         .clkr = {
1157                 .enable_reg = 0x2d24,
1158                 .enable_mask = BIT(11),
1159                 .hw.init = &(struct clk_init_data){
1160                         .name = "gp0_src",
1161                         .parent_data = gcc_pxo_pll8_cxo,
1162                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
1163                         .ops = &clk_rcg_ops,
1164                         .flags = CLK_SET_PARENT_GATE,
1165                 },
1166         }
1167 };
1168
1169 static struct clk_branch gp0_clk = {
1170         .halt_reg = 0x2fd8,
1171         .halt_bit = 7,
1172         .clkr = {
1173                 .enable_reg = 0x2d24,
1174                 .enable_mask = BIT(9),
1175                 .hw.init = &(struct clk_init_data){
1176                         .name = "gp0_clk",
1177                         .parent_hws = (const struct clk_hw*[]){
1178                                 &gp0_src.clkr.hw,
1179                         },
1180                         .num_parents = 1,
1181                         .ops = &clk_branch_ops,
1182                         .flags = CLK_SET_RATE_PARENT,
1183                 },
1184         },
1185 };
1186
1187 static struct clk_rcg gp1_src = {
1188         .ns_reg = 0x2d44,
1189         .md_reg = 0x2d40,
1190         .mn = {
1191                 .mnctr_en_bit = 8,
1192                 .mnctr_reset_bit = 7,
1193                 .mnctr_mode_shift = 5,
1194                 .n_val_shift = 16,
1195                 .m_val_shift = 16,
1196                 .width = 8,
1197         },
1198         .p = {
1199                 .pre_div_shift = 3,
1200                 .pre_div_width = 2,
1201         },
1202         .s = {
1203                 .src_sel_shift = 0,
1204                 .parent_map = gcc_pxo_pll8_cxo_map,
1205         },
1206         .freq_tbl = clk_tbl_gp,
1207         .clkr = {
1208                 .enable_reg = 0x2d44,
1209                 .enable_mask = BIT(11),
1210                 .hw.init = &(struct clk_init_data){
1211                         .name = "gp1_src",
1212                         .parent_data = gcc_pxo_pll8_cxo,
1213                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
1214                         .ops = &clk_rcg_ops,
1215                         .flags = CLK_SET_RATE_GATE,
1216                 },
1217         }
1218 };
1219
1220 static struct clk_branch gp1_clk = {
1221         .halt_reg = 0x2fd8,
1222         .halt_bit = 6,
1223         .clkr = {
1224                 .enable_reg = 0x2d44,
1225                 .enable_mask = BIT(9),
1226                 .hw.init = &(struct clk_init_data){
1227                         .name = "gp1_clk",
1228                         .parent_hws = (const struct clk_hw*[]){
1229                                 &gp1_src.clkr.hw,
1230                         },
1231                         .num_parents = 1,
1232                         .ops = &clk_branch_ops,
1233                         .flags = CLK_SET_RATE_PARENT,
1234                 },
1235         },
1236 };
1237
1238 static struct clk_rcg gp2_src = {
1239         .ns_reg = 0x2d64,
1240         .md_reg = 0x2d60,
1241         .mn = {
1242                 .mnctr_en_bit = 8,
1243                 .mnctr_reset_bit = 7,
1244                 .mnctr_mode_shift = 5,
1245                 .n_val_shift = 16,
1246                 .m_val_shift = 16,
1247                 .width = 8,
1248         },
1249         .p = {
1250                 .pre_div_shift = 3,
1251                 .pre_div_width = 2,
1252         },
1253         .s = {
1254                 .src_sel_shift = 0,
1255                 .parent_map = gcc_pxo_pll8_cxo_map,
1256         },
1257         .freq_tbl = clk_tbl_gp,
1258         .clkr = {
1259                 .enable_reg = 0x2d64,
1260                 .enable_mask = BIT(11),
1261                 .hw.init = &(struct clk_init_data){
1262                         .name = "gp2_src",
1263                         .parent_data = gcc_pxo_pll8_cxo,
1264                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
1265                         .ops = &clk_rcg_ops,
1266                         .flags = CLK_SET_RATE_GATE,
1267                 },
1268         }
1269 };
1270
1271 static struct clk_branch gp2_clk = {
1272         .halt_reg = 0x2fd8,
1273         .halt_bit = 5,
1274         .clkr = {
1275                 .enable_reg = 0x2d64,
1276                 .enable_mask = BIT(9),
1277                 .hw.init = &(struct clk_init_data){
1278                         .name = "gp2_clk",
1279                         .parent_hws = (const struct clk_hw*[]){
1280                                 &gp2_src.clkr.hw,
1281                         },
1282                         .num_parents = 1,
1283                         .ops = &clk_branch_ops,
1284                         .flags = CLK_SET_RATE_PARENT,
1285                 },
1286         },
1287 };
1288
1289 static struct clk_branch pmem_clk = {
1290         .hwcg_reg = 0x25a0,
1291         .hwcg_bit = 6,
1292         .halt_reg = 0x2fc8,
1293         .halt_bit = 20,
1294         .clkr = {
1295                 .enable_reg = 0x25a0,
1296                 .enable_mask = BIT(4),
1297                 .hw.init = &(struct clk_init_data){
1298                         .name = "pmem_clk",
1299                         .ops = &clk_branch_ops,
1300                 },
1301         },
1302 };
1303
1304 static struct clk_rcg prng_src = {
1305         .ns_reg = 0x2e80,
1306         .p = {
1307                 .pre_div_shift = 3,
1308                 .pre_div_width = 4,
1309         },
1310         .s = {
1311                 .src_sel_shift = 0,
1312                 .parent_map = gcc_pxo_pll8_map,
1313         },
1314         .clkr = {
1315                 .enable_reg = 0x2e80,
1316                 .enable_mask = BIT(11),
1317                 .hw.init = &(struct clk_init_data){
1318                         .name = "prng_src",
1319                         .parent_data = gcc_pxo_pll8,
1320                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1321                         .ops = &clk_rcg_ops,
1322                 },
1323         },
1324 };
1325
1326 static struct clk_branch prng_clk = {
1327         .halt_reg = 0x2fd8,
1328         .halt_check = BRANCH_HALT_VOTED,
1329         .halt_bit = 10,
1330         .clkr = {
1331                 .enable_reg = 0x3080,
1332                 .enable_mask = BIT(10),
1333                 .hw.init = &(struct clk_init_data){
1334                         .name = "prng_clk",
1335                         .parent_hws = (const struct clk_hw*[]){
1336                                 &prng_src.clkr.hw,
1337                         },
1338                         .num_parents = 1,
1339                         .ops = &clk_branch_ops,
1340                 },
1341         },
1342 };
1343
1344 static const struct freq_tbl clk_tbl_sdc[] = {
1345         {    200000, P_PXO,   2, 2, 125 },
1346         {    400000, P_PLL8,  4, 1, 240 },
1347         {  16000000, P_PLL8,  4, 1,   6 },
1348         {  17070000, P_PLL8,  1, 2,  45 },
1349         {  20210000, P_PLL8,  1, 1,  19 },
1350         {  24000000, P_PLL8,  4, 1,   4 },
1351         {  48000000, P_PLL8,  4, 1,   2 },
1352         {  51200000, P_PLL8,  1, 2,  15 },
1353         {  64000000, P_PLL8,  3, 1,   2 },
1354         {  96000000, P_PLL8,  4, 0,   0 },
1355         { 192000000, P_PLL8,  2, 0,   0 },
1356         { }
1357 };
1358
1359 static struct clk_rcg sdc1_src = {
1360         .ns_reg = 0x282c,
1361         .md_reg = 0x2828,
1362         .mn = {
1363                 .mnctr_en_bit = 8,
1364                 .mnctr_reset_bit = 7,
1365                 .mnctr_mode_shift = 5,
1366                 .n_val_shift = 16,
1367                 .m_val_shift = 16,
1368                 .width = 8,
1369         },
1370         .p = {
1371                 .pre_div_shift = 3,
1372                 .pre_div_width = 2,
1373         },
1374         .s = {
1375                 .src_sel_shift = 0,
1376                 .parent_map = gcc_pxo_pll8_map,
1377         },
1378         .freq_tbl = clk_tbl_sdc,
1379         .clkr = {
1380                 .enable_reg = 0x282c,
1381                 .enable_mask = BIT(11),
1382                 .hw.init = &(struct clk_init_data){
1383                         .name = "sdc1_src",
1384                         .parent_data = gcc_pxo_pll8,
1385                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1386                         .ops = &clk_rcg_floor_ops,
1387                 },
1388         }
1389 };
1390
1391 static struct clk_branch sdc1_clk = {
1392         .halt_reg = 0x2fc8,
1393         .halt_bit = 6,
1394         .clkr = {
1395                 .enable_reg = 0x282c,
1396                 .enable_mask = BIT(9),
1397                 .hw.init = &(struct clk_init_data){
1398                         .name = "sdc1_clk",
1399                         .parent_hws = (const struct clk_hw*[]){
1400                                 &sdc1_src.clkr.hw,
1401                         },
1402                         .num_parents = 1,
1403                         .ops = &clk_branch_ops,
1404                         .flags = CLK_SET_RATE_PARENT,
1405                 },
1406         },
1407 };
1408
1409 static struct clk_rcg sdc3_src = {
1410         .ns_reg = 0x286c,
1411         .md_reg = 0x2868,
1412         .mn = {
1413                 .mnctr_en_bit = 8,
1414                 .mnctr_reset_bit = 7,
1415                 .mnctr_mode_shift = 5,
1416                 .n_val_shift = 16,
1417                 .m_val_shift = 16,
1418                 .width = 8,
1419         },
1420         .p = {
1421                 .pre_div_shift = 3,
1422                 .pre_div_width = 2,
1423         },
1424         .s = {
1425                 .src_sel_shift = 0,
1426                 .parent_map = gcc_pxo_pll8_map,
1427         },
1428         .freq_tbl = clk_tbl_sdc,
1429         .clkr = {
1430                 .enable_reg = 0x286c,
1431                 .enable_mask = BIT(11),
1432                 .hw.init = &(struct clk_init_data){
1433                         .name = "sdc3_src",
1434                         .parent_data = gcc_pxo_pll8,
1435                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1436                         .ops = &clk_rcg_ops,
1437                 },
1438         }
1439 };
1440
1441 static struct clk_branch sdc3_clk = {
1442         .halt_reg = 0x2fc8,
1443         .halt_bit = 4,
1444         .clkr = {
1445                 .enable_reg = 0x286c,
1446                 .enable_mask = BIT(9),
1447                 .hw.init = &(struct clk_init_data){
1448                         .name = "sdc3_clk",
1449                         .parent_hws = (const struct clk_hw*[]){
1450                                 &sdc3_src.clkr.hw,
1451                         },
1452                         .num_parents = 1,
1453                         .ops = &clk_branch_ops,
1454                         .flags = CLK_SET_RATE_PARENT,
1455                 },
1456         },
1457 };
1458
1459 static struct clk_branch sdc1_h_clk = {
1460         .hwcg_reg = 0x2820,
1461         .hwcg_bit = 6,
1462         .halt_reg = 0x2fc8,
1463         .halt_bit = 11,
1464         .clkr = {
1465                 .enable_reg = 0x2820,
1466                 .enable_mask = BIT(4),
1467                 .hw.init = &(struct clk_init_data){
1468                         .name = "sdc1_h_clk",
1469                         .ops = &clk_branch_ops,
1470                 },
1471         },
1472 };
1473
1474 static struct clk_branch sdc3_h_clk = {
1475         .hwcg_reg = 0x2860,
1476         .hwcg_bit = 6,
1477         .halt_reg = 0x2fc8,
1478         .halt_bit = 9,
1479         .clkr = {
1480                 .enable_reg = 0x2860,
1481                 .enable_mask = BIT(4),
1482                 .hw.init = &(struct clk_init_data){
1483                         .name = "sdc3_h_clk",
1484                         .ops = &clk_branch_ops,
1485                 },
1486         },
1487 };
1488
1489 static const struct freq_tbl clk_tbl_tsif_ref[] = {
1490         { 105000, P_PXO,  1, 1, 256 },
1491         { }
1492 };
1493
1494 static struct clk_rcg tsif_ref_src = {
1495         .ns_reg = 0x2710,
1496         .md_reg = 0x270c,
1497         .mn = {
1498                 .mnctr_en_bit = 8,
1499                 .mnctr_reset_bit = 7,
1500                 .mnctr_mode_shift = 5,
1501                 .n_val_shift = 16,
1502                 .m_val_shift = 16,
1503                 .width = 16,
1504         },
1505         .p = {
1506                 .pre_div_shift = 3,
1507                 .pre_div_width = 2,
1508         },
1509         .s = {
1510                 .src_sel_shift = 0,
1511                 .parent_map = gcc_pxo_pll8_map,
1512         },
1513         .freq_tbl = clk_tbl_tsif_ref,
1514         .clkr = {
1515                 .enable_reg = 0x2710,
1516                 .enable_mask = BIT(11),
1517                 .hw.init = &(struct clk_init_data){
1518                         .name = "tsif_ref_src",
1519                         .parent_data = gcc_pxo_pll8,
1520                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1521                         .ops = &clk_rcg_ops,
1522                 },
1523         }
1524 };
1525
1526 static struct clk_branch tsif_ref_clk = {
1527         .halt_reg = 0x2fd4,
1528         .halt_bit = 5,
1529         .clkr = {
1530                 .enable_reg = 0x2710,
1531                 .enable_mask = BIT(9),
1532                 .hw.init = &(struct clk_init_data){
1533                         .name = "tsif_ref_clk",
1534                         .parent_hws = (const struct clk_hw*[]){
1535                                 &tsif_ref_src.clkr.hw,
1536                         },
1537                         .num_parents = 1,
1538                         .ops = &clk_branch_ops,
1539                         .flags = CLK_SET_RATE_PARENT,
1540                 },
1541         },
1542 };
1543
1544 static struct clk_branch tsif_h_clk = {
1545         .hwcg_reg = 0x2700,
1546         .hwcg_bit = 6,
1547         .halt_reg = 0x2fd4,
1548         .halt_bit = 7,
1549         .clkr = {
1550                 .enable_reg = 0x2700,
1551                 .enable_mask = BIT(4),
1552                 .hw.init = &(struct clk_init_data){
1553                         .name = "tsif_h_clk",
1554                         .ops = &clk_branch_ops,
1555                 },
1556         },
1557 };
1558
1559 static struct clk_branch dma_bam_h_clk = {
1560         .hwcg_reg = 0x25c0,
1561         .hwcg_bit = 6,
1562         .halt_reg = 0x2fc8,
1563         .halt_bit = 12,
1564         .clkr = {
1565                 .enable_reg = 0x25c0,
1566                 .enable_mask = BIT(4),
1567                 .hw.init = &(struct clk_init_data){
1568                         .name = "dma_bam_h_clk",
1569                         .ops = &clk_branch_ops,
1570                 },
1571         },
1572 };
1573
1574 static struct clk_branch adm0_clk = {
1575         .halt_reg = 0x2fdc,
1576         .halt_check = BRANCH_HALT_VOTED,
1577         .halt_bit = 12,
1578         .clkr = {
1579                 .enable_reg = 0x3080,
1580                 .enable_mask = BIT(2),
1581                 .hw.init = &(struct clk_init_data){
1582                         .name = "adm0_clk",
1583                         .ops = &clk_branch_ops,
1584                 },
1585         },
1586 };
1587
1588 static struct clk_branch adm0_pbus_clk = {
1589         .hwcg_reg = 0x2208,
1590         .hwcg_bit = 6,
1591         .halt_reg = 0x2fdc,
1592         .halt_check = BRANCH_HALT_VOTED,
1593         .halt_bit = 11,
1594         .clkr = {
1595                 .enable_reg = 0x3080,
1596                 .enable_mask = BIT(3),
1597                 .hw.init = &(struct clk_init_data){
1598                         .name = "adm0_pbus_clk",
1599                         .ops = &clk_branch_ops,
1600                 },
1601         },
1602 };
1603
1604 static struct clk_branch pmic_arb0_h_clk = {
1605         .halt_reg = 0x2fd8,
1606         .halt_check = BRANCH_HALT_VOTED,
1607         .halt_bit = 22,
1608         .clkr = {
1609                 .enable_reg = 0x3080,
1610                 .enable_mask = BIT(8),
1611                 .hw.init = &(struct clk_init_data){
1612                         .name = "pmic_arb0_h_clk",
1613                         .ops = &clk_branch_ops,
1614                 },
1615         },
1616 };
1617
1618 static struct clk_branch pmic_arb1_h_clk = {
1619         .halt_reg = 0x2fd8,
1620         .halt_check = BRANCH_HALT_VOTED,
1621         .halt_bit = 21,
1622         .clkr = {
1623                 .enable_reg = 0x3080,
1624                 .enable_mask = BIT(9),
1625                 .hw.init = &(struct clk_init_data){
1626                         .name = "pmic_arb1_h_clk",
1627                         .ops = &clk_branch_ops,
1628                 },
1629         },
1630 };
1631
1632 static struct clk_branch pmic_ssbi2_clk = {
1633         .halt_reg = 0x2fd8,
1634         .halt_check = BRANCH_HALT_VOTED,
1635         .halt_bit = 23,
1636         .clkr = {
1637                 .enable_reg = 0x3080,
1638                 .enable_mask = BIT(7),
1639                 .hw.init = &(struct clk_init_data){
1640                         .name = "pmic_ssbi2_clk",
1641                         .ops = &clk_branch_ops,
1642                 },
1643         },
1644 };
1645
1646 static struct clk_branch rpm_msg_ram_h_clk = {
1647         .hwcg_reg = 0x27e0,
1648         .hwcg_bit = 6,
1649         .halt_reg = 0x2fd8,
1650         .halt_check = BRANCH_HALT_VOTED,
1651         .halt_bit = 12,
1652         .clkr = {
1653                 .enable_reg = 0x3080,
1654                 .enable_mask = BIT(6),
1655                 .hw.init = &(struct clk_init_data){
1656                         .name = "rpm_msg_ram_h_clk",
1657                         .ops = &clk_branch_ops,
1658                 },
1659         },
1660 };
1661
1662 static const struct freq_tbl clk_tbl_pcie_ref[] = {
1663         { 100000000, P_PLL3,  12, 0, 0 },
1664         { }
1665 };
1666
1667 static struct clk_rcg pcie_ref_src = {
1668         .ns_reg = 0x3860,
1669         .p = {
1670                 .pre_div_shift = 3,
1671                 .pre_div_width = 4,
1672         },
1673         .s = {
1674                 .src_sel_shift = 0,
1675                 .parent_map = gcc_pxo_pll3_map,
1676         },
1677         .freq_tbl = clk_tbl_pcie_ref,
1678         .clkr = {
1679                 .enable_reg = 0x3860,
1680                 .enable_mask = BIT(11),
1681                 .hw.init = &(struct clk_init_data){
1682                         .name = "pcie_ref_src",
1683                         .parent_data = gcc_pxo_pll3,
1684                         .num_parents = ARRAY_SIZE(gcc_pxo_pll3),
1685                         .ops = &clk_rcg_ops,
1686                         .flags = CLK_SET_RATE_GATE,
1687                 },
1688         },
1689 };
1690
1691 static struct clk_branch pcie_ref_src_clk = {
1692         .halt_reg = 0x2fdc,
1693         .halt_bit = 30,
1694         .clkr = {
1695                 .enable_reg = 0x3860,
1696                 .enable_mask = BIT(9),
1697                 .hw.init = &(struct clk_init_data){
1698                         .name = "pcie_ref_src_clk",
1699                         .parent_hws = (const struct clk_hw*[]){
1700                                 &pcie_ref_src.clkr.hw,
1701                         },
1702                         .num_parents = 1,
1703                         .ops = &clk_branch_ops,
1704                         .flags = CLK_SET_RATE_PARENT,
1705                 },
1706         },
1707 };
1708
1709 static struct clk_branch pcie_a_clk = {
1710         .halt_reg = 0x2fc0,
1711         .halt_bit = 13,
1712         .clkr = {
1713                 .enable_reg = 0x22c0,
1714                 .enable_mask = BIT(4),
1715                 .hw.init = &(struct clk_init_data){
1716                         .name = "pcie_a_clk",
1717                         .ops = &clk_branch_ops,
1718                 },
1719         },
1720 };
1721
1722 static struct clk_branch pcie_aux_clk = {
1723         .halt_reg = 0x2fdc,
1724         .halt_bit = 31,
1725         .clkr = {
1726                 .enable_reg = 0x22c8,
1727                 .enable_mask = BIT(4),
1728                 .hw.init = &(struct clk_init_data){
1729                         .name = "pcie_aux_clk",
1730                         .ops = &clk_branch_ops,
1731                 },
1732         },
1733 };
1734
1735 static struct clk_branch pcie_h_clk = {
1736         .halt_reg = 0x2fd4,
1737         .halt_bit = 8,
1738         .clkr = {
1739                 .enable_reg = 0x22cc,
1740                 .enable_mask = BIT(4),
1741                 .hw.init = &(struct clk_init_data){
1742                         .name = "pcie_h_clk",
1743                         .ops = &clk_branch_ops,
1744                 },
1745         },
1746 };
1747
1748 static struct clk_branch pcie_phy_clk = {
1749         .halt_reg = 0x2fdc,
1750         .halt_bit = 29,
1751         .clkr = {
1752                 .enable_reg = 0x22d0,
1753                 .enable_mask = BIT(4),
1754                 .hw.init = &(struct clk_init_data){
1755                         .name = "pcie_phy_clk",
1756                         .ops = &clk_branch_ops,
1757                 },
1758         },
1759 };
1760
1761 static struct clk_rcg pcie1_ref_src = {
1762         .ns_reg = 0x3aa0,
1763         .p = {
1764                 .pre_div_shift = 3,
1765                 .pre_div_width = 4,
1766         },
1767         .s = {
1768                 .src_sel_shift = 0,
1769                 .parent_map = gcc_pxo_pll3_map,
1770         },
1771         .freq_tbl = clk_tbl_pcie_ref,
1772         .clkr = {
1773                 .enable_reg = 0x3aa0,
1774                 .enable_mask = BIT(11),
1775                 .hw.init = &(struct clk_init_data){
1776                         .name = "pcie1_ref_src",
1777                         .parent_data = gcc_pxo_pll3,
1778                         .num_parents = ARRAY_SIZE(gcc_pxo_pll3),
1779                         .ops = &clk_rcg_ops,
1780                         .flags = CLK_SET_RATE_GATE,
1781                 },
1782         },
1783 };
1784
1785 static struct clk_branch pcie1_ref_src_clk = {
1786         .halt_reg = 0x2fdc,
1787         .halt_bit = 27,
1788         .clkr = {
1789                 .enable_reg = 0x3aa0,
1790                 .enable_mask = BIT(9),
1791                 .hw.init = &(struct clk_init_data){
1792                         .name = "pcie1_ref_src_clk",
1793                         .parent_hws = (const struct clk_hw*[]){
1794                                 &pcie1_ref_src.clkr.hw,
1795                         },
1796                         .num_parents = 1,
1797                         .ops = &clk_branch_ops,
1798                         .flags = CLK_SET_RATE_PARENT,
1799                 },
1800         },
1801 };
1802
1803 static struct clk_branch pcie1_a_clk = {
1804         .halt_reg = 0x2fc0,
1805         .halt_bit = 10,
1806         .clkr = {
1807                 .enable_reg = 0x3a80,
1808                 .enable_mask = BIT(4),
1809                 .hw.init = &(struct clk_init_data){
1810                         .name = "pcie1_a_clk",
1811                         .ops = &clk_branch_ops,
1812                 },
1813         },
1814 };
1815
1816 static struct clk_branch pcie1_aux_clk = {
1817         .halt_reg = 0x2fdc,
1818         .halt_bit = 28,
1819         .clkr = {
1820                 .enable_reg = 0x3a88,
1821                 .enable_mask = BIT(4),
1822                 .hw.init = &(struct clk_init_data){
1823                         .name = "pcie1_aux_clk",
1824                         .ops = &clk_branch_ops,
1825                 },
1826         },
1827 };
1828
1829 static struct clk_branch pcie1_h_clk = {
1830         .halt_reg = 0x2fd4,
1831         .halt_bit = 9,
1832         .clkr = {
1833                 .enable_reg = 0x3a8c,
1834                 .enable_mask = BIT(4),
1835                 .hw.init = &(struct clk_init_data){
1836                         .name = "pcie1_h_clk",
1837                         .ops = &clk_branch_ops,
1838                 },
1839         },
1840 };
1841
1842 static struct clk_branch pcie1_phy_clk = {
1843         .halt_reg = 0x2fdc,
1844         .halt_bit = 26,
1845         .clkr = {
1846                 .enable_reg = 0x3a90,
1847                 .enable_mask = BIT(4),
1848                 .hw.init = &(struct clk_init_data){
1849                         .name = "pcie1_phy_clk",
1850                         .ops = &clk_branch_ops,
1851                 },
1852         },
1853 };
1854
1855 static struct clk_rcg pcie2_ref_src = {
1856         .ns_reg = 0x3ae0,
1857         .p = {
1858                 .pre_div_shift = 3,
1859                 .pre_div_width = 4,
1860         },
1861         .s = {
1862                 .src_sel_shift = 0,
1863                 .parent_map = gcc_pxo_pll3_map,
1864         },
1865         .freq_tbl = clk_tbl_pcie_ref,
1866         .clkr = {
1867                 .enable_reg = 0x3ae0,
1868                 .enable_mask = BIT(11),
1869                 .hw.init = &(struct clk_init_data){
1870                         .name = "pcie2_ref_src",
1871                         .parent_data = gcc_pxo_pll3,
1872                         .num_parents = ARRAY_SIZE(gcc_pxo_pll3),
1873                         .ops = &clk_rcg_ops,
1874                         .flags = CLK_SET_RATE_GATE,
1875                 },
1876         },
1877 };
1878
1879 static struct clk_branch pcie2_ref_src_clk = {
1880         .halt_reg = 0x2fdc,
1881         .halt_bit = 24,
1882         .clkr = {
1883                 .enable_reg = 0x3ae0,
1884                 .enable_mask = BIT(9),
1885                 .hw.init = &(struct clk_init_data){
1886                         .name = "pcie2_ref_src_clk",
1887                         .parent_hws = (const struct clk_hw*[]){
1888                                 &pcie2_ref_src.clkr.hw,
1889                         },
1890                         .num_parents = 1,
1891                         .ops = &clk_branch_ops,
1892                         .flags = CLK_SET_RATE_PARENT,
1893                 },
1894         },
1895 };
1896
1897 static struct clk_branch pcie2_a_clk = {
1898         .halt_reg = 0x2fc0,
1899         .halt_bit = 9,
1900         .clkr = {
1901                 .enable_reg = 0x3ac0,
1902                 .enable_mask = BIT(4),
1903                 .hw.init = &(struct clk_init_data){
1904                         .name = "pcie2_a_clk",
1905                         .ops = &clk_branch_ops,
1906                 },
1907         },
1908 };
1909
1910 static struct clk_branch pcie2_aux_clk = {
1911         .halt_reg = 0x2fdc,
1912         .halt_bit = 25,
1913         .clkr = {
1914                 .enable_reg = 0x3ac8,
1915                 .enable_mask = BIT(4),
1916                 .hw.init = &(struct clk_init_data){
1917                         .name = "pcie2_aux_clk",
1918                         .ops = &clk_branch_ops,
1919                 },
1920         },
1921 };
1922
1923 static struct clk_branch pcie2_h_clk = {
1924         .halt_reg = 0x2fd4,
1925         .halt_bit = 10,
1926         .clkr = {
1927                 .enable_reg = 0x3acc,
1928                 .enable_mask = BIT(4),
1929                 .hw.init = &(struct clk_init_data){
1930                         .name = "pcie2_h_clk",
1931                         .ops = &clk_branch_ops,
1932                 },
1933         },
1934 };
1935
1936 static struct clk_branch pcie2_phy_clk = {
1937         .halt_reg = 0x2fdc,
1938         .halt_bit = 23,
1939         .clkr = {
1940                 .enable_reg = 0x3ad0,
1941                 .enable_mask = BIT(4),
1942                 .hw.init = &(struct clk_init_data){
1943                         .name = "pcie2_phy_clk",
1944                         .ops = &clk_branch_ops,
1945                 },
1946         },
1947 };
1948
1949 static const struct freq_tbl clk_tbl_sata_ref[] = {
1950         { 100000000, P_PLL3,  12, 0, 0 },
1951         { }
1952 };
1953
1954 static struct clk_rcg sata_ref_src = {
1955         .ns_reg = 0x2c08,
1956         .p = {
1957                 .pre_div_shift = 3,
1958                 .pre_div_width = 4,
1959         },
1960         .s = {
1961                 .src_sel_shift = 0,
1962                 .parent_map = gcc_pxo_pll3_sata_map,
1963         },
1964         .freq_tbl = clk_tbl_sata_ref,
1965         .clkr = {
1966                 .enable_reg = 0x2c08,
1967                 .enable_mask = BIT(7),
1968                 .hw.init = &(struct clk_init_data){
1969                         .name = "sata_ref_src",
1970                         .parent_data = gcc_pxo_pll3,
1971                         .num_parents = ARRAY_SIZE(gcc_pxo_pll3),
1972                         .ops = &clk_rcg_ops,
1973                         .flags = CLK_SET_RATE_GATE,
1974                 },
1975         },
1976 };
1977
1978 static struct clk_branch sata_rxoob_clk = {
1979         .halt_reg = 0x2fdc,
1980         .halt_bit = 20,
1981         .clkr = {
1982                 .enable_reg = 0x2c0c,
1983                 .enable_mask = BIT(4),
1984                 .hw.init = &(struct clk_init_data){
1985                         .name = "sata_rxoob_clk",
1986                         .parent_hws = (const struct clk_hw*[]){
1987                                 &sata_ref_src.clkr.hw,
1988                         },
1989                         .num_parents = 1,
1990                         .ops = &clk_branch_ops,
1991                         .flags = CLK_SET_RATE_PARENT,
1992                 },
1993         },
1994 };
1995
1996 static struct clk_branch sata_pmalive_clk = {
1997         .halt_reg = 0x2fdc,
1998         .halt_bit = 19,
1999         .clkr = {
2000                 .enable_reg = 0x2c10,
2001                 .enable_mask = BIT(4),
2002                 .hw.init = &(struct clk_init_data){
2003                         .name = "sata_pmalive_clk",
2004                         .parent_hws = (const struct clk_hw*[]){
2005                                 &sata_ref_src.clkr.hw,
2006                         },
2007                         .num_parents = 1,
2008                         .ops = &clk_branch_ops,
2009                         .flags = CLK_SET_RATE_PARENT,
2010                 },
2011         },
2012 };
2013
2014 static struct clk_branch sata_phy_ref_clk = {
2015         .halt_reg = 0x2fdc,
2016         .halt_bit = 18,
2017         .clkr = {
2018                 .enable_reg = 0x2c14,
2019                 .enable_mask = BIT(4),
2020                 .hw.init = &(struct clk_init_data){
2021                         .name = "sata_phy_ref_clk",
2022                         .parent_data = gcc_pxo,
2023                         .num_parents = 1,
2024                         .ops = &clk_branch_ops,
2025                 },
2026         },
2027 };
2028
2029 static struct clk_branch sata_a_clk = {
2030         .halt_reg = 0x2fc0,
2031         .halt_bit = 12,
2032         .clkr = {
2033                 .enable_reg = 0x2c20,
2034                 .enable_mask = BIT(4),
2035                 .hw.init = &(struct clk_init_data){
2036                         .name = "sata_a_clk",
2037                         .ops = &clk_branch_ops,
2038                 },
2039         },
2040 };
2041
2042 static struct clk_branch sata_h_clk = {
2043         .halt_reg = 0x2fdc,
2044         .halt_bit = 21,
2045         .clkr = {
2046                 .enable_reg = 0x2c00,
2047                 .enable_mask = BIT(4),
2048                 .hw.init = &(struct clk_init_data){
2049                         .name = "sata_h_clk",
2050                         .ops = &clk_branch_ops,
2051                 },
2052         },
2053 };
2054
2055 static struct clk_branch sfab_sata_s_h_clk = {
2056         .halt_reg = 0x2fc4,
2057         .halt_bit = 14,
2058         .clkr = {
2059                 .enable_reg = 0x2480,
2060                 .enable_mask = BIT(4),
2061                 .hw.init = &(struct clk_init_data){
2062                         .name = "sfab_sata_s_h_clk",
2063                         .ops = &clk_branch_ops,
2064                 },
2065         },
2066 };
2067
2068 static struct clk_branch sata_phy_cfg_clk = {
2069         .halt_reg = 0x2fcc,
2070         .halt_bit = 14,
2071         .clkr = {
2072                 .enable_reg = 0x2c40,
2073                 .enable_mask = BIT(4),
2074                 .hw.init = &(struct clk_init_data){
2075                         .name = "sata_phy_cfg_clk",
2076                         .ops = &clk_branch_ops,
2077                 },
2078         },
2079 };
2080
2081 static const struct freq_tbl clk_tbl_usb30_master[] = {
2082         { 125000000, P_PLL0,  1, 5, 32 },
2083         { }
2084 };
2085
2086 static struct clk_rcg usb30_master_clk_src = {
2087         .ns_reg = 0x3b2c,
2088         .md_reg = 0x3b28,
2089         .mn = {
2090                 .mnctr_en_bit = 8,
2091                 .mnctr_reset_bit = 7,
2092                 .mnctr_mode_shift = 5,
2093                 .n_val_shift = 16,
2094                 .m_val_shift = 16,
2095                 .width = 8,
2096         },
2097         .p = {
2098                 .pre_div_shift = 3,
2099                 .pre_div_width = 2,
2100         },
2101         .s = {
2102                 .src_sel_shift = 0,
2103                 .parent_map = gcc_pxo_pll8_pll0_map,
2104         },
2105         .freq_tbl = clk_tbl_usb30_master,
2106         .clkr = {
2107                 .enable_reg = 0x3b2c,
2108                 .enable_mask = BIT(11),
2109                 .hw.init = &(struct clk_init_data){
2110                         .name = "usb30_master_ref_src",
2111                         .parent_data = gcc_pxo_pll8_pll0,
2112                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
2113                         .ops = &clk_rcg_ops,
2114                         .flags = CLK_SET_RATE_GATE,
2115                 },
2116         },
2117 };
2118
2119 static struct clk_branch usb30_0_branch_clk = {
2120         .halt_reg = 0x2fc4,
2121         .halt_bit = 22,
2122         .clkr = {
2123                 .enable_reg = 0x3b24,
2124                 .enable_mask = BIT(4),
2125                 .hw.init = &(struct clk_init_data){
2126                         .name = "usb30_0_branch_clk",
2127                         .parent_hws = (const struct clk_hw*[]){
2128                                 &usb30_master_clk_src.clkr.hw,
2129                         },
2130                         .num_parents = 1,
2131                         .ops = &clk_branch_ops,
2132                         .flags = CLK_SET_RATE_PARENT,
2133                 },
2134         },
2135 };
2136
2137 static struct clk_branch usb30_1_branch_clk = {
2138         .halt_reg = 0x2fc4,
2139         .halt_bit = 17,
2140         .clkr = {
2141                 .enable_reg = 0x3b34,
2142                 .enable_mask = BIT(4),
2143                 .hw.init = &(struct clk_init_data){
2144                         .name = "usb30_1_branch_clk",
2145                         .parent_hws = (const struct clk_hw*[]){
2146                                 &usb30_master_clk_src.clkr.hw,
2147                         },
2148                         .num_parents = 1,
2149                         .ops = &clk_branch_ops,
2150                         .flags = CLK_SET_RATE_PARENT,
2151                 },
2152         },
2153 };
2154
2155 static const struct freq_tbl clk_tbl_usb30_utmi[] = {
2156         { 60000000, P_PLL8,  1, 5, 32 },
2157         { }
2158 };
2159
2160 static struct clk_rcg usb30_utmi_clk = {
2161         .ns_reg = 0x3b44,
2162         .md_reg = 0x3b40,
2163         .mn = {
2164                 .mnctr_en_bit = 8,
2165                 .mnctr_reset_bit = 7,
2166                 .mnctr_mode_shift = 5,
2167                 .n_val_shift = 16,
2168                 .m_val_shift = 16,
2169                 .width = 8,
2170         },
2171         .p = {
2172                 .pre_div_shift = 3,
2173                 .pre_div_width = 2,
2174         },
2175         .s = {
2176                 .src_sel_shift = 0,
2177                 .parent_map = gcc_pxo_pll8_pll0_map,
2178         },
2179         .freq_tbl = clk_tbl_usb30_utmi,
2180         .clkr = {
2181                 .enable_reg = 0x3b44,
2182                 .enable_mask = BIT(11),
2183                 .hw.init = &(struct clk_init_data){
2184                         .name = "usb30_utmi_clk",
2185                         .parent_data = gcc_pxo_pll8_pll0,
2186                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
2187                         .ops = &clk_rcg_ops,
2188                         .flags = CLK_SET_RATE_GATE,
2189                 },
2190         },
2191 };
2192
2193 static struct clk_branch usb30_0_utmi_clk_ctl = {
2194         .halt_reg = 0x2fc4,
2195         .halt_bit = 21,
2196         .clkr = {
2197                 .enable_reg = 0x3b48,
2198                 .enable_mask = BIT(4),
2199                 .hw.init = &(struct clk_init_data){
2200                         .name = "usb30_0_utmi_clk_ctl",
2201                         .parent_hws = (const struct clk_hw*[]){
2202                                 &usb30_utmi_clk.clkr.hw,
2203                         },
2204                         .num_parents = 1,
2205                         .ops = &clk_branch_ops,
2206                         .flags = CLK_SET_RATE_PARENT,
2207                 },
2208         },
2209 };
2210
2211 static struct clk_branch usb30_1_utmi_clk_ctl = {
2212         .halt_reg = 0x2fc4,
2213         .halt_bit = 15,
2214         .clkr = {
2215                 .enable_reg = 0x3b4c,
2216                 .enable_mask = BIT(4),
2217                 .hw.init = &(struct clk_init_data){
2218                         .name = "usb30_1_utmi_clk_ctl",
2219                         .parent_hws = (const struct clk_hw*[]){
2220                                 &usb30_utmi_clk.clkr.hw,
2221                         },
2222                         .num_parents = 1,
2223                         .ops = &clk_branch_ops,
2224                         .flags = CLK_SET_RATE_PARENT,
2225                 },
2226         },
2227 };
2228
2229 static const struct freq_tbl clk_tbl_usb[] = {
2230         { 60000000, P_PLL8,  1, 5, 32 },
2231         { }
2232 };
2233
2234 static struct clk_rcg usb_hs1_xcvr_clk_src = {
2235         .ns_reg = 0x290C,
2236         .md_reg = 0x2908,
2237         .mn = {
2238                 .mnctr_en_bit = 8,
2239                 .mnctr_reset_bit = 7,
2240                 .mnctr_mode_shift = 5,
2241                 .n_val_shift = 16,
2242                 .m_val_shift = 16,
2243                 .width = 8,
2244         },
2245         .p = {
2246                 .pre_div_shift = 3,
2247                 .pre_div_width = 2,
2248         },
2249         .s = {
2250                 .src_sel_shift = 0,
2251                 .parent_map = gcc_pxo_pll8_pll0_map,
2252         },
2253         .freq_tbl = clk_tbl_usb,
2254         .clkr = {
2255                 .enable_reg = 0x2968,
2256                 .enable_mask = BIT(11),
2257                 .hw.init = &(struct clk_init_data){
2258                         .name = "usb_hs1_xcvr_src",
2259                         .parent_data = gcc_pxo_pll8_pll0,
2260                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
2261                         .ops = &clk_rcg_ops,
2262                         .flags = CLK_SET_RATE_GATE,
2263                 },
2264         },
2265 };
2266
2267 static struct clk_branch usb_hs1_xcvr_clk = {
2268         .halt_reg = 0x2fcc,
2269         .halt_bit = 17,
2270         .clkr = {
2271                 .enable_reg = 0x290c,
2272                 .enable_mask = BIT(9),
2273                 .hw.init = &(struct clk_init_data){
2274                         .name = "usb_hs1_xcvr_clk",
2275                         .parent_hws = (const struct clk_hw*[]){
2276                                 &usb_hs1_xcvr_clk_src.clkr.hw,
2277                         },
2278                         .num_parents = 1,
2279                         .ops = &clk_branch_ops,
2280                         .flags = CLK_SET_RATE_PARENT,
2281                 },
2282         },
2283 };
2284
2285 static struct clk_branch usb_hs1_h_clk = {
2286         .hwcg_reg = 0x2900,
2287         .hwcg_bit = 6,
2288         .halt_reg = 0x2fc8,
2289         .halt_bit = 1,
2290         .clkr = {
2291                 .enable_reg = 0x2900,
2292                 .enable_mask = BIT(4),
2293                 .hw.init = &(struct clk_init_data){
2294                         .name = "usb_hs1_h_clk",
2295                         .ops = &clk_branch_ops,
2296                 },
2297         },
2298 };
2299
2300 static struct clk_rcg usb_fs1_xcvr_clk_src = {
2301         .ns_reg = 0x2968,
2302         .md_reg = 0x2964,
2303         .mn = {
2304                 .mnctr_en_bit = 8,
2305                 .mnctr_reset_bit = 7,
2306                 .mnctr_mode_shift = 5,
2307                 .n_val_shift = 16,
2308                 .m_val_shift = 16,
2309                 .width = 8,
2310         },
2311         .p = {
2312                 .pre_div_shift = 3,
2313                 .pre_div_width = 2,
2314         },
2315         .s = {
2316                 .src_sel_shift = 0,
2317                 .parent_map = gcc_pxo_pll8_pll0_map,
2318         },
2319         .freq_tbl = clk_tbl_usb,
2320         .clkr = {
2321                 .enable_reg = 0x2968,
2322                 .enable_mask = BIT(11),
2323                 .hw.init = &(struct clk_init_data){
2324                         .name = "usb_fs1_xcvr_src",
2325                         .parent_data = gcc_pxo_pll8_pll0,
2326                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
2327                         .ops = &clk_rcg_ops,
2328                         .flags = CLK_SET_RATE_GATE,
2329                 },
2330         },
2331 };
2332
2333 static struct clk_branch usb_fs1_xcvr_clk = {
2334         .halt_reg = 0x2fcc,
2335         .halt_bit = 17,
2336         .clkr = {
2337                 .enable_reg = 0x2968,
2338                 .enable_mask = BIT(9),
2339                 .hw.init = &(struct clk_init_data){
2340                         .name = "usb_fs1_xcvr_clk",
2341                         .parent_hws = (const struct clk_hw*[]){
2342                                 &usb_fs1_xcvr_clk_src.clkr.hw,
2343                         },
2344                         .num_parents = 1,
2345                         .ops = &clk_branch_ops,
2346                         .flags = CLK_SET_RATE_PARENT,
2347                 },
2348         },
2349 };
2350
2351 static struct clk_branch usb_fs1_sys_clk = {
2352         .halt_reg = 0x2fcc,
2353         .halt_bit = 18,
2354         .clkr = {
2355                 .enable_reg = 0x296c,
2356                 .enable_mask = BIT(4),
2357                 .hw.init = &(struct clk_init_data){
2358                         .name = "usb_fs1_sys_clk",
2359                         .parent_hws = (const struct clk_hw*[]){
2360                                 &usb_fs1_xcvr_clk_src.clkr.hw,
2361                         },
2362                         .num_parents = 1,
2363                         .ops = &clk_branch_ops,
2364                         .flags = CLK_SET_RATE_PARENT,
2365                 },
2366         },
2367 };
2368
2369 static struct clk_branch usb_fs1_h_clk = {
2370         .halt_reg = 0x2fcc,
2371         .halt_bit = 19,
2372         .clkr = {
2373                 .enable_reg = 0x2960,
2374                 .enable_mask = BIT(4),
2375                 .hw.init = &(struct clk_init_data){
2376                         .name = "usb_fs1_h_clk",
2377                         .ops = &clk_branch_ops,
2378                 },
2379         },
2380 };
2381
2382 static struct clk_branch ebi2_clk = {
2383         .hwcg_reg = 0x3b00,
2384         .hwcg_bit = 6,
2385         .halt_reg = 0x2fcc,
2386         .halt_bit = 1,
2387         .clkr = {
2388                 .enable_reg = 0x3b00,
2389                 .enable_mask = BIT(4),
2390                 .hw.init = &(struct clk_init_data){
2391                         .name = "ebi2_clk",
2392                         .ops = &clk_branch_ops,
2393                 },
2394         },
2395 };
2396
2397 static struct clk_branch ebi2_aon_clk = {
2398         .halt_reg = 0x2fcc,
2399         .halt_bit = 0,
2400         .clkr = {
2401                 .enable_reg = 0x3b00,
2402                 .enable_mask = BIT(8),
2403                 .hw.init = &(struct clk_init_data){
2404                         .name = "ebi2_always_on_clk",
2405                         .ops = &clk_branch_ops,
2406                 },
2407         },
2408 };
2409
2410 static const struct freq_tbl clk_tbl_gmac[] = {
2411         { 133000000, P_PLL0, 1,  50, 301 },
2412         { 266000000, P_PLL0, 1, 127, 382 },
2413         { }
2414 };
2415
2416 static struct clk_dyn_rcg gmac_core1_src = {
2417         .ns_reg[0] = 0x3cac,
2418         .ns_reg[1] = 0x3cb0,
2419         .md_reg[0] = 0x3ca4,
2420         .md_reg[1] = 0x3ca8,
2421         .bank_reg = 0x3ca0,
2422         .mn[0] = {
2423                 .mnctr_en_bit = 8,
2424                 .mnctr_reset_bit = 7,
2425                 .mnctr_mode_shift = 5,
2426                 .n_val_shift = 16,
2427                 .m_val_shift = 16,
2428                 .width = 8,
2429         },
2430         .mn[1] = {
2431                 .mnctr_en_bit = 8,
2432                 .mnctr_reset_bit = 7,
2433                 .mnctr_mode_shift = 5,
2434                 .n_val_shift = 16,
2435                 .m_val_shift = 16,
2436                 .width = 8,
2437         },
2438         .s[0] = {
2439                 .src_sel_shift = 0,
2440                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2441         },
2442         .s[1] = {
2443                 .src_sel_shift = 0,
2444                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2445         },
2446         .p[0] = {
2447                 .pre_div_shift = 3,
2448                 .pre_div_width = 2,
2449         },
2450         .p[1] = {
2451                 .pre_div_shift = 3,
2452                 .pre_div_width = 2,
2453         },
2454         .mux_sel_bit = 0,
2455         .freq_tbl = clk_tbl_gmac,
2456         .clkr = {
2457                 .enable_reg = 0x3ca0,
2458                 .enable_mask = BIT(1),
2459                 .hw.init = &(struct clk_init_data){
2460                         .name = "gmac_core1_src",
2461                         .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
2462                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
2463                         .ops = &clk_dyn_rcg_ops,
2464                 },
2465         },
2466 };
2467
2468 static struct clk_branch gmac_core1_clk = {
2469         .halt_reg = 0x3c20,
2470         .halt_bit = 4,
2471         .hwcg_reg = 0x3cb4,
2472         .hwcg_bit = 6,
2473         .clkr = {
2474                 .enable_reg = 0x3cb4,
2475                 .enable_mask = BIT(4),
2476                 .hw.init = &(struct clk_init_data){
2477                         .name = "gmac_core1_clk",
2478                         .parent_hws = (const struct clk_hw*[]){
2479                                 &gmac_core1_src.clkr.hw,
2480                         },
2481                         .num_parents = 1,
2482                         .ops = &clk_branch_ops,
2483                         .flags = CLK_SET_RATE_PARENT,
2484                 },
2485         },
2486 };
2487
2488 static struct clk_dyn_rcg gmac_core2_src = {
2489         .ns_reg[0] = 0x3ccc,
2490         .ns_reg[1] = 0x3cd0,
2491         .md_reg[0] = 0x3cc4,
2492         .md_reg[1] = 0x3cc8,
2493         .bank_reg = 0x3ca0,
2494         .mn[0] = {
2495                 .mnctr_en_bit = 8,
2496                 .mnctr_reset_bit = 7,
2497                 .mnctr_mode_shift = 5,
2498                 .n_val_shift = 16,
2499                 .m_val_shift = 16,
2500                 .width = 8,
2501         },
2502         .mn[1] = {
2503                 .mnctr_en_bit = 8,
2504                 .mnctr_reset_bit = 7,
2505                 .mnctr_mode_shift = 5,
2506                 .n_val_shift = 16,
2507                 .m_val_shift = 16,
2508                 .width = 8,
2509         },
2510         .s[0] = {
2511                 .src_sel_shift = 0,
2512                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2513         },
2514         .s[1] = {
2515                 .src_sel_shift = 0,
2516                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2517         },
2518         .p[0] = {
2519                 .pre_div_shift = 3,
2520                 .pre_div_width = 2,
2521         },
2522         .p[1] = {
2523                 .pre_div_shift = 3,
2524                 .pre_div_width = 2,
2525         },
2526         .mux_sel_bit = 0,
2527         .freq_tbl = clk_tbl_gmac,
2528         .clkr = {
2529                 .enable_reg = 0x3cc0,
2530                 .enable_mask = BIT(1),
2531                 .hw.init = &(struct clk_init_data){
2532                         .name = "gmac_core2_src",
2533                         .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
2534                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
2535                         .ops = &clk_dyn_rcg_ops,
2536                 },
2537         },
2538 };
2539
2540 static struct clk_branch gmac_core2_clk = {
2541         .halt_reg = 0x3c20,
2542         .halt_bit = 5,
2543         .hwcg_reg = 0x3cd4,
2544         .hwcg_bit = 6,
2545         .clkr = {
2546                 .enable_reg = 0x3cd4,
2547                 .enable_mask = BIT(4),
2548                 .hw.init = &(struct clk_init_data){
2549                         .name = "gmac_core2_clk",
2550                         .parent_hws = (const struct clk_hw*[]){
2551                                 &gmac_core2_src.clkr.hw,
2552                         },
2553                         .num_parents = 1,
2554                         .ops = &clk_branch_ops,
2555                         .flags = CLK_SET_RATE_PARENT,
2556                 },
2557         },
2558 };
2559
2560 static struct clk_dyn_rcg gmac_core3_src = {
2561         .ns_reg[0] = 0x3cec,
2562         .ns_reg[1] = 0x3cf0,
2563         .md_reg[0] = 0x3ce4,
2564         .md_reg[1] = 0x3ce8,
2565         .bank_reg = 0x3ce0,
2566         .mn[0] = {
2567                 .mnctr_en_bit = 8,
2568                 .mnctr_reset_bit = 7,
2569                 .mnctr_mode_shift = 5,
2570                 .n_val_shift = 16,
2571                 .m_val_shift = 16,
2572                 .width = 8,
2573         },
2574         .mn[1] = {
2575                 .mnctr_en_bit = 8,
2576                 .mnctr_reset_bit = 7,
2577                 .mnctr_mode_shift = 5,
2578                 .n_val_shift = 16,
2579                 .m_val_shift = 16,
2580                 .width = 8,
2581         },
2582         .s[0] = {
2583                 .src_sel_shift = 0,
2584                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2585         },
2586         .s[1] = {
2587                 .src_sel_shift = 0,
2588                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2589         },
2590         .p[0] = {
2591                 .pre_div_shift = 3,
2592                 .pre_div_width = 2,
2593         },
2594         .p[1] = {
2595                 .pre_div_shift = 3,
2596                 .pre_div_width = 2,
2597         },
2598         .mux_sel_bit = 0,
2599         .freq_tbl = clk_tbl_gmac,
2600         .clkr = {
2601                 .enable_reg = 0x3ce0,
2602                 .enable_mask = BIT(1),
2603                 .hw.init = &(struct clk_init_data){
2604                         .name = "gmac_core3_src",
2605                         .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
2606                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
2607                         .ops = &clk_dyn_rcg_ops,
2608                 },
2609         },
2610 };
2611
2612 static struct clk_branch gmac_core3_clk = {
2613         .halt_reg = 0x3c20,
2614         .halt_bit = 6,
2615         .hwcg_reg = 0x3cf4,
2616         .hwcg_bit = 6,
2617         .clkr = {
2618                 .enable_reg = 0x3cf4,
2619                 .enable_mask = BIT(4),
2620                 .hw.init = &(struct clk_init_data){
2621                         .name = "gmac_core3_clk",
2622                         .parent_hws = (const struct clk_hw*[]){
2623                                 &gmac_core3_src.clkr.hw,
2624                         },
2625                         .num_parents = 1,
2626                         .ops = &clk_branch_ops,
2627                         .flags = CLK_SET_RATE_PARENT,
2628                 },
2629         },
2630 };
2631
2632 static struct clk_dyn_rcg gmac_core4_src = {
2633         .ns_reg[0] = 0x3d0c,
2634         .ns_reg[1] = 0x3d10,
2635         .md_reg[0] = 0x3d04,
2636         .md_reg[1] = 0x3d08,
2637         .bank_reg = 0x3d00,
2638         .mn[0] = {
2639                 .mnctr_en_bit = 8,
2640                 .mnctr_reset_bit = 7,
2641                 .mnctr_mode_shift = 5,
2642                 .n_val_shift = 16,
2643                 .m_val_shift = 16,
2644                 .width = 8,
2645         },
2646         .mn[1] = {
2647                 .mnctr_en_bit = 8,
2648                 .mnctr_reset_bit = 7,
2649                 .mnctr_mode_shift = 5,
2650                 .n_val_shift = 16,
2651                 .m_val_shift = 16,
2652                 .width = 8,
2653         },
2654         .s[0] = {
2655                 .src_sel_shift = 0,
2656                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2657         },
2658         .s[1] = {
2659                 .src_sel_shift = 0,
2660                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2661         },
2662         .p[0] = {
2663                 .pre_div_shift = 3,
2664                 .pre_div_width = 2,
2665         },
2666         .p[1] = {
2667                 .pre_div_shift = 3,
2668                 .pre_div_width = 2,
2669         },
2670         .mux_sel_bit = 0,
2671         .freq_tbl = clk_tbl_gmac,
2672         .clkr = {
2673                 .enable_reg = 0x3d00,
2674                 .enable_mask = BIT(1),
2675                 .hw.init = &(struct clk_init_data){
2676                         .name = "gmac_core4_src",
2677                         .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
2678                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
2679                         .ops = &clk_dyn_rcg_ops,
2680                 },
2681         },
2682 };
2683
2684 static struct clk_branch gmac_core4_clk = {
2685         .halt_reg = 0x3c20,
2686         .halt_bit = 7,
2687         .hwcg_reg = 0x3d14,
2688         .hwcg_bit = 6,
2689         .clkr = {
2690                 .enable_reg = 0x3d14,
2691                 .enable_mask = BIT(4),
2692                 .hw.init = &(struct clk_init_data){
2693                         .name = "gmac_core4_clk",
2694                         .parent_hws = (const struct clk_hw*[]){
2695                                 &gmac_core4_src.clkr.hw,
2696                         },
2697                         .num_parents = 1,
2698                         .ops = &clk_branch_ops,
2699                         .flags = CLK_SET_RATE_PARENT,
2700                 },
2701         },
2702 };
2703
2704 static const struct freq_tbl clk_tbl_nss_tcm[] = {
2705         { 266000000, P_PLL0, 3, 0, 0 },
2706         { 400000000, P_PLL0, 2, 0, 0 },
2707         { }
2708 };
2709
2710 static struct clk_dyn_rcg nss_tcm_src = {
2711         .ns_reg[0] = 0x3dc4,
2712         .ns_reg[1] = 0x3dc8,
2713         .bank_reg = 0x3dc0,
2714         .s[0] = {
2715                 .src_sel_shift = 0,
2716                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2717         },
2718         .s[1] = {
2719                 .src_sel_shift = 0,
2720                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2721         },
2722         .p[0] = {
2723                 .pre_div_shift = 3,
2724                 .pre_div_width = 4,
2725         },
2726         .p[1] = {
2727                 .pre_div_shift = 3,
2728                 .pre_div_width = 4,
2729         },
2730         .mux_sel_bit = 0,
2731         .freq_tbl = clk_tbl_nss_tcm,
2732         .clkr = {
2733                 .enable_reg = 0x3dc0,
2734                 .enable_mask = BIT(1),
2735                 .hw.init = &(struct clk_init_data){
2736                         .name = "nss_tcm_src",
2737                         .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
2738                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
2739                         .ops = &clk_dyn_rcg_ops,
2740                 },
2741         },
2742 };
2743
2744 static struct clk_branch nss_tcm_clk = {
2745         .halt_reg = 0x3c20,
2746         .halt_bit = 14,
2747         .clkr = {
2748                 .enable_reg = 0x3dd0,
2749                 .enable_mask = BIT(6) | BIT(4),
2750                 .hw.init = &(struct clk_init_data){
2751                         .name = "nss_tcm_clk",
2752                         .parent_hws = (const struct clk_hw*[]){
2753                                 &nss_tcm_src.clkr.hw,
2754                         },
2755                         .num_parents = 1,
2756                         .ops = &clk_branch_ops,
2757                         .flags = CLK_SET_RATE_PARENT,
2758                 },
2759         },
2760 };
2761
2762 static const struct freq_tbl clk_tbl_nss_ipq8064[] = {
2763         { 110000000, P_PLL18, 1, 1, 5 },
2764         { 275000000, P_PLL18, 2, 0, 0 },
2765         { 550000000, P_PLL18, 1, 0, 0 },
2766         { 733000000, P_PLL18, 1, 0, 0 },
2767         { }
2768 };
2769
2770 static const struct freq_tbl clk_tbl_nss_ipq8065[] = {
2771         { 110000000, P_PLL18, 1, 1, 5 },
2772         { 275000000, P_PLL18, 2, 0, 0 },
2773         { 600000000, P_PLL18, 1, 0, 0 },
2774         { 800000000, P_PLL18, 1, 0, 0 },
2775         { }
2776 };
2777
2778 static struct clk_dyn_rcg ubi32_core1_src_clk = {
2779         .ns_reg[0] = 0x3d2c,
2780         .ns_reg[1] = 0x3d30,
2781         .md_reg[0] = 0x3d24,
2782         .md_reg[1] = 0x3d28,
2783         .bank_reg = 0x3d20,
2784         .mn[0] = {
2785                 .mnctr_en_bit = 8,
2786                 .mnctr_reset_bit = 7,
2787                 .mnctr_mode_shift = 5,
2788                 .n_val_shift = 16,
2789                 .m_val_shift = 16,
2790                 .width = 8,
2791         },
2792         .mn[1] = {
2793                 .mnctr_en_bit = 8,
2794                 .mnctr_reset_bit = 7,
2795                 .mnctr_mode_shift = 5,
2796                 .n_val_shift = 16,
2797                 .m_val_shift = 16,
2798                 .width = 8,
2799         },
2800         .s[0] = {
2801                 .src_sel_shift = 0,
2802                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2803         },
2804         .s[1] = {
2805                 .src_sel_shift = 0,
2806                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2807         },
2808         .p[0] = {
2809                 .pre_div_shift = 3,
2810                 .pre_div_width = 2,
2811         },
2812         .p[1] = {
2813                 .pre_div_shift = 3,
2814                 .pre_div_width = 2,
2815         },
2816         .mux_sel_bit = 0,
2817         /* nss freq table is selected based on the SoC compatible */
2818         .clkr = {
2819                 .enable_reg = 0x3d20,
2820                 .enable_mask = BIT(1),
2821                 .hw.init = &(struct clk_init_data){
2822                         .name = "ubi32_core1_src_clk",
2823                         .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
2824                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
2825                         .ops = &clk_dyn_rcg_ops,
2826                         .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2827                 },
2828         },
2829 };
2830
2831 static struct clk_dyn_rcg ubi32_core2_src_clk = {
2832         .ns_reg[0] = 0x3d4c,
2833         .ns_reg[1] = 0x3d50,
2834         .md_reg[0] = 0x3d44,
2835         .md_reg[1] = 0x3d48,
2836         .bank_reg = 0x3d40,
2837         .mn[0] = {
2838                 .mnctr_en_bit = 8,
2839                 .mnctr_reset_bit = 7,
2840                 .mnctr_mode_shift = 5,
2841                 .n_val_shift = 16,
2842                 .m_val_shift = 16,
2843                 .width = 8,
2844         },
2845         .mn[1] = {
2846                 .mnctr_en_bit = 8,
2847                 .mnctr_reset_bit = 7,
2848                 .mnctr_mode_shift = 5,
2849                 .n_val_shift = 16,
2850                 .m_val_shift = 16,
2851                 .width = 8,
2852         },
2853         .s[0] = {
2854                 .src_sel_shift = 0,
2855                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2856         },
2857         .s[1] = {
2858                 .src_sel_shift = 0,
2859                 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
2860         },
2861         .p[0] = {
2862                 .pre_div_shift = 3,
2863                 .pre_div_width = 2,
2864         },
2865         .p[1] = {
2866                 .pre_div_shift = 3,
2867                 .pre_div_width = 2,
2868         },
2869         .mux_sel_bit = 0,
2870         /* nss freq table is selected based on the SoC compatible */
2871         .clkr = {
2872                 .enable_reg = 0x3d40,
2873                 .enable_mask = BIT(1),
2874                 .hw.init = &(struct clk_init_data){
2875                         .name = "ubi32_core2_src_clk",
2876                         .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
2877                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
2878                         .ops = &clk_dyn_rcg_ops,
2879                         .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2880                 },
2881         },
2882 };
2883
2884 static const struct freq_tbl clk_tbl_ce5_core[] = {
2885         { 150000000, P_PLL3, 8, 1, 1 },
2886         { 213200000, P_PLL11, 5, 1, 1 },
2887         { }
2888 };
2889
2890 static struct clk_dyn_rcg ce5_core_src = {
2891         .ns_reg[0] = 0x36C4,
2892         .ns_reg[1] = 0x36C8,
2893         .bank_reg = 0x36C0,
2894         .s[0] = {
2895                 .src_sel_shift = 0,
2896                 .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
2897         },
2898         .s[1] = {
2899                 .src_sel_shift = 0,
2900                 .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
2901         },
2902         .p[0] = {
2903                 .pre_div_shift = 3,
2904                 .pre_div_width = 4,
2905         },
2906         .p[1] = {
2907                 .pre_div_shift = 3,
2908                 .pre_div_width = 4,
2909         },
2910         .mux_sel_bit = 0,
2911         .freq_tbl = clk_tbl_ce5_core,
2912         .clkr = {
2913                 .enable_reg = 0x36C0,
2914                 .enable_mask = BIT(1),
2915                 .hw.init = &(struct clk_init_data){
2916                         .name = "ce5_core_src",
2917                         .parent_data = gcc_pxo_pll3_pll0_pll14_pll18_pll11,
2918                         .num_parents = ARRAY_SIZE(gcc_pxo_pll3_pll0_pll14_pll18_pll11),
2919                         .ops = &clk_dyn_rcg_ops,
2920                 },
2921         },
2922 };
2923
2924 static struct clk_branch ce5_core_clk = {
2925         .halt_reg = 0x2FDC,
2926         .halt_bit = 5,
2927         .hwcg_reg = 0x36CC,
2928         .hwcg_bit = 6,
2929         .clkr = {
2930                 .enable_reg = 0x36CC,
2931                 .enable_mask = BIT(4),
2932                 .hw.init = &(struct clk_init_data){
2933                         .name = "ce5_core_clk",
2934                         .parent_hws = (const struct clk_hw*[]){
2935                                 &ce5_core_src.clkr.hw,
2936                         },
2937                         .num_parents = 1,
2938                         .ops = &clk_branch_ops,
2939                         .flags = CLK_SET_RATE_PARENT,
2940                 },
2941         },
2942 };
2943
2944 static const struct freq_tbl clk_tbl_ce5_a_clk[] = {
2945         { 160000000, P_PLL0, 5, 1, 1 },
2946         { 213200000, P_PLL11, 5, 1, 1 },
2947         { }
2948 };
2949
2950 static struct clk_dyn_rcg ce5_a_clk_src = {
2951         .ns_reg[0] = 0x3d84,
2952         .ns_reg[1] = 0x3d88,
2953         .bank_reg = 0x3d80,
2954         .s[0] = {
2955                 .src_sel_shift = 0,
2956                 .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
2957         },
2958         .s[1] = {
2959                 .src_sel_shift = 0,
2960                 .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
2961         },
2962         .p[0] = {
2963                 .pre_div_shift = 3,
2964                 .pre_div_width = 4,
2965         },
2966         .p[1] = {
2967                 .pre_div_shift = 3,
2968                 .pre_div_width = 4,
2969         },
2970         .mux_sel_bit = 0,
2971         .freq_tbl = clk_tbl_ce5_a_clk,
2972         .clkr = {
2973                 .enable_reg = 0x3d80,
2974                 .enable_mask = BIT(1),
2975                 .hw.init = &(struct clk_init_data){
2976                         .name = "ce5_a_clk_src",
2977                         .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
2978                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11),
2979                         .ops = &clk_dyn_rcg_ops,
2980                 },
2981         },
2982 };
2983
2984 static struct clk_branch ce5_a_clk = {
2985         .halt_reg = 0x3c20,
2986         .halt_bit = 12,
2987         .hwcg_reg = 0x3d8c,
2988         .hwcg_bit = 6,
2989         .clkr = {
2990                 .enable_reg = 0x3d8c,
2991                 .enable_mask = BIT(4),
2992                 .hw.init = &(struct clk_init_data){
2993                         .name = "ce5_a_clk",
2994                         .parent_hws = (const struct clk_hw*[]){
2995                                 &ce5_a_clk_src.clkr.hw,
2996                         },
2997                         .num_parents = 1,
2998                         .ops = &clk_branch_ops,
2999                         .flags = CLK_SET_RATE_PARENT,
3000                 },
3001         },
3002 };
3003
3004 static const struct freq_tbl clk_tbl_ce5_h_clk[] = {
3005         { 160000000, P_PLL0, 5, 1, 1 },
3006         { 213200000, P_PLL11, 5, 1, 1 },
3007         { }
3008 };
3009
3010 static struct clk_dyn_rcg ce5_h_clk_src = {
3011         .ns_reg[0] = 0x3c64,
3012         .ns_reg[1] = 0x3c68,
3013         .bank_reg = 0x3c60,
3014         .s[0] = {
3015                 .src_sel_shift = 0,
3016                 .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
3017         },
3018         .s[1] = {
3019                 .src_sel_shift = 0,
3020                 .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
3021         },
3022         .p[0] = {
3023                 .pre_div_shift = 3,
3024                 .pre_div_width = 4,
3025         },
3026         .p[1] = {
3027                 .pre_div_shift = 3,
3028                 .pre_div_width = 4,
3029         },
3030         .mux_sel_bit = 0,
3031         .freq_tbl = clk_tbl_ce5_h_clk,
3032         .clkr = {
3033                 .enable_reg = 0x3c60,
3034                 .enable_mask = BIT(1),
3035                 .hw.init = &(struct clk_init_data){
3036                         .name = "ce5_h_clk_src",
3037                         .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
3038                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11),
3039                         .ops = &clk_dyn_rcg_ops,
3040                 },
3041         },
3042 };
3043
3044 static struct clk_branch ce5_h_clk = {
3045         .halt_reg = 0x3c20,
3046         .halt_bit = 11,
3047         .hwcg_reg = 0x3c6c,
3048         .hwcg_bit = 6,
3049         .clkr = {
3050                 .enable_reg = 0x3c6c,
3051                 .enable_mask = BIT(4),
3052                 .hw.init = &(struct clk_init_data){
3053                         .name = "ce5_h_clk",
3054                         .parent_hws = (const struct clk_hw*[]){
3055                                 &ce5_h_clk_src.clkr.hw,
3056                         },
3057                         .num_parents = 1,
3058                         .ops = &clk_branch_ops,
3059                         .flags = CLK_SET_RATE_PARENT,
3060                 },
3061         },
3062 };
3063
3064 static struct clk_regmap *gcc_ipq806x_clks[] = {
3065         [PLL0] = &pll0.clkr,
3066         [PLL0_VOTE] = &pll0_vote,
3067         [PLL3] = &pll3.clkr,
3068         [PLL4_VOTE] = &pll4_vote,
3069         [PLL8] = &pll8.clkr,
3070         [PLL8_VOTE] = &pll8_vote,
3071         [PLL11] = &pll11.clkr,
3072         [PLL14] = &pll14.clkr,
3073         [PLL14_VOTE] = &pll14_vote,
3074         [PLL18] = &pll18.clkr,
3075         [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
3076         [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
3077         [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
3078         [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
3079         [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
3080         [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
3081         [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
3082         [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
3083         [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
3084         [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
3085         [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
3086         [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
3087         [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
3088         [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
3089         [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
3090         [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
3091         [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
3092         [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
3093         [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
3094         [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
3095         [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
3096         [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
3097         [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
3098         [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
3099         [GP0_SRC] = &gp0_src.clkr,
3100         [GP0_CLK] = &gp0_clk.clkr,
3101         [GP1_SRC] = &gp1_src.clkr,
3102         [GP1_CLK] = &gp1_clk.clkr,
3103         [GP2_SRC] = &gp2_src.clkr,
3104         [GP2_CLK] = &gp2_clk.clkr,
3105         [PMEM_A_CLK] = &pmem_clk.clkr,
3106         [PRNG_SRC] = &prng_src.clkr,
3107         [PRNG_CLK] = &prng_clk.clkr,
3108         [SDC1_SRC] = &sdc1_src.clkr,
3109         [SDC1_CLK] = &sdc1_clk.clkr,
3110         [SDC3_SRC] = &sdc3_src.clkr,
3111         [SDC3_CLK] = &sdc3_clk.clkr,
3112         [TSIF_REF_SRC] = &tsif_ref_src.clkr,
3113         [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
3114         [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
3115         [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
3116         [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
3117         [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
3118         [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
3119         [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
3120         [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
3121         [TSIF_H_CLK] = &tsif_h_clk.clkr,
3122         [SDC1_H_CLK] = &sdc1_h_clk.clkr,
3123         [SDC3_H_CLK] = &sdc3_h_clk.clkr,
3124         [ADM0_CLK] = &adm0_clk.clkr,
3125         [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
3126         [PCIE_A_CLK] = &pcie_a_clk.clkr,
3127         [PCIE_AUX_CLK] = &pcie_aux_clk.clkr,
3128         [PCIE_H_CLK] = &pcie_h_clk.clkr,
3129         [PCIE_PHY_CLK] = &pcie_phy_clk.clkr,
3130         [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
3131         [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
3132         [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
3133         [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
3134         [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
3135         [SATA_H_CLK] = &sata_h_clk.clkr,
3136         [SATA_CLK_SRC] = &sata_ref_src.clkr,
3137         [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
3138         [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
3139         [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
3140         [SATA_A_CLK] = &sata_a_clk.clkr,
3141         [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
3142         [PCIE_ALT_REF_SRC] = &pcie_ref_src.clkr,
3143         [PCIE_ALT_REF_CLK] = &pcie_ref_src_clk.clkr,
3144         [PCIE_1_A_CLK] = &pcie1_a_clk.clkr,
3145         [PCIE_1_AUX_CLK] = &pcie1_aux_clk.clkr,
3146         [PCIE_1_H_CLK] = &pcie1_h_clk.clkr,
3147         [PCIE_1_PHY_CLK] = &pcie1_phy_clk.clkr,
3148         [PCIE_1_ALT_REF_SRC] = &pcie1_ref_src.clkr,
3149         [PCIE_1_ALT_REF_CLK] = &pcie1_ref_src_clk.clkr,
3150         [PCIE_2_A_CLK] = &pcie2_a_clk.clkr,
3151         [PCIE_2_AUX_CLK] = &pcie2_aux_clk.clkr,
3152         [PCIE_2_H_CLK] = &pcie2_h_clk.clkr,
3153         [PCIE_2_PHY_CLK] = &pcie2_phy_clk.clkr,
3154         [PCIE_2_ALT_REF_SRC] = &pcie2_ref_src.clkr,
3155         [PCIE_2_ALT_REF_CLK] = &pcie2_ref_src_clk.clkr,
3156         [USB30_MASTER_SRC] = &usb30_master_clk_src.clkr,
3157         [USB30_0_MASTER_CLK] = &usb30_0_branch_clk.clkr,
3158         [USB30_1_MASTER_CLK] = &usb30_1_branch_clk.clkr,
3159         [USB30_UTMI_SRC] = &usb30_utmi_clk.clkr,
3160         [USB30_0_UTMI_CLK] = &usb30_0_utmi_clk_ctl.clkr,
3161         [USB30_1_UTMI_CLK] = &usb30_1_utmi_clk_ctl.clkr,
3162         [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
3163         [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_clk_src.clkr,
3164         [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
3165         [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
3166         [USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr,
3167         [USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr,
3168         [USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr,
3169         [EBI2_CLK] = &ebi2_clk.clkr,
3170         [EBI2_AON_CLK] = &ebi2_aon_clk.clkr,
3171         [GMAC_CORE1_CLK_SRC] = &gmac_core1_src.clkr,
3172         [GMAC_CORE1_CLK] = &gmac_core1_clk.clkr,
3173         [GMAC_CORE2_CLK_SRC] = &gmac_core2_src.clkr,
3174         [GMAC_CORE2_CLK] = &gmac_core2_clk.clkr,
3175         [GMAC_CORE3_CLK_SRC] = &gmac_core3_src.clkr,
3176         [GMAC_CORE3_CLK] = &gmac_core3_clk.clkr,
3177         [GMAC_CORE4_CLK_SRC] = &gmac_core4_src.clkr,
3178         [GMAC_CORE4_CLK] = &gmac_core4_clk.clkr,
3179         [UBI32_CORE1_CLK_SRC] = &ubi32_core1_src_clk.clkr,
3180         [UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr,
3181         [NSSTCM_CLK_SRC] = &nss_tcm_src.clkr,
3182         [NSSTCM_CLK] = &nss_tcm_clk.clkr,
3183         [PLL9] = &hfpll0.clkr,
3184         [PLL10] = &hfpll1.clkr,
3185         [PLL12] = &hfpll_l2.clkr,
3186         [CE5_A_CLK_SRC] = &ce5_a_clk_src.clkr,
3187         [CE5_A_CLK] = &ce5_a_clk.clkr,
3188         [CE5_H_CLK_SRC] = &ce5_h_clk_src.clkr,
3189         [CE5_H_CLK] = &ce5_h_clk.clkr,
3190         [CE5_CORE_CLK_SRC] = &ce5_core_src.clkr,
3191         [CE5_CORE_CLK] = &ce5_core_clk.clkr,
3192 };
3193
3194 static const struct qcom_reset_map gcc_ipq806x_resets[] = {
3195         [QDSS_STM_RESET] = { 0x2060, 6 },
3196         [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3197         [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3198         [AFAB_SMPSS_M0_RESET] = { 0x20b8, 0 },
3199         [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
3200         [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7 },
3201         [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
3202         [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
3203         [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
3204         [ADM0_C2_RESET] = { 0x220c, 4 },
3205         [ADM0_C1_RESET] = { 0x220c, 3 },
3206         [ADM0_C0_RESET] = { 0x220c, 2 },
3207         [ADM0_PBUS_RESET] = { 0x220c, 1 },
3208         [ADM0_RESET] = { 0x220c, 0 },
3209         [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
3210         [QDSS_POR_RESET] = { 0x2260, 4 },
3211         [QDSS_TSCTR_RESET] = { 0x2260, 3 },
3212         [QDSS_HRESET_RESET] = { 0x2260, 2 },
3213         [QDSS_AXI_RESET] = { 0x2260, 1 },
3214         [QDSS_DBG_RESET] = { 0x2260, 0 },
3215         [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
3216         [SFAB_PCIE_S_RESET] = { 0x22d8, 0 },
3217         [PCIE_EXT_RESET] = { 0x22dc, 6 },
3218         [PCIE_PHY_RESET] = { 0x22dc, 5 },
3219         [PCIE_PCI_RESET] = { 0x22dc, 4 },
3220         [PCIE_POR_RESET] = { 0x22dc, 3 },
3221         [PCIE_HCLK_RESET] = { 0x22dc, 2 },
3222         [PCIE_ACLK_RESET] = { 0x22dc, 0 },
3223         [SFAB_LPASS_RESET] = { 0x23a0, 7 },
3224         [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
3225         [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
3226         [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
3227         [SFAB_SATA_S_RESET] = { 0x2480, 7 },
3228         [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
3229         [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
3230         [DFAB_SWAY0_RESET] = { 0x2540, 7 },
3231         [DFAB_SWAY1_RESET] = { 0x2544, 7 },
3232         [DFAB_ARB0_RESET] = { 0x2560, 7 },
3233         [DFAB_ARB1_RESET] = { 0x2564, 7 },
3234         [PPSS_PROC_RESET] = { 0x2594, 1 },
3235         [PPSS_RESET] = { 0x2594, 0 },
3236         [DMA_BAM_RESET] = { 0x25c0, 7 },
3237         [SPS_TIC_H_RESET] = { 0x2600, 7 },
3238         [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
3239         [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
3240         [TSIF_H_RESET] = { 0x2700, 7 },
3241         [CE1_H_RESET] = { 0x2720, 7 },
3242         [CE1_CORE_RESET] = { 0x2724, 7 },
3243         [CE1_SLEEP_RESET] = { 0x2728, 7 },
3244         [CE2_H_RESET] = { 0x2740, 7 },
3245         [CE2_CORE_RESET] = { 0x2744, 7 },
3246         [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
3247         [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
3248         [RPM_PROC_RESET] = { 0x27c0, 7 },
3249         [PMIC_SSBI2_RESET] = { 0x280c, 12 },
3250         [SDC1_RESET] = { 0x2830, 0 },
3251         [SDC2_RESET] = { 0x2850, 0 },
3252         [SDC3_RESET] = { 0x2870, 0 },
3253         [SDC4_RESET] = { 0x2890, 0 },
3254         [USB_HS1_RESET] = { 0x2910, 0 },
3255         [USB_HSIC_RESET] = { 0x2934, 0 },
3256         [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
3257         [USB_FS1_RESET] = { 0x2974, 0 },
3258         [GSBI1_RESET] = { 0x29dc, 0 },
3259         [GSBI2_RESET] = { 0x29fc, 0 },
3260         [GSBI3_RESET] = { 0x2a1c, 0 },
3261         [GSBI4_RESET] = { 0x2a3c, 0 },
3262         [GSBI5_RESET] = { 0x2a5c, 0 },
3263         [GSBI6_RESET] = { 0x2a7c, 0 },
3264         [GSBI7_RESET] = { 0x2a9c, 0 },
3265         [SPDM_RESET] = { 0x2b6c, 0 },
3266         [SEC_CTRL_RESET] = { 0x2b80, 7 },
3267         [TLMM_H_RESET] = { 0x2ba0, 7 },
3268         [SFAB_SATA_M_RESET] = { 0x2c18, 0 },
3269         [SATA_RESET] = { 0x2c1c, 0 },
3270         [TSSC_RESET] = { 0x2ca0, 7 },
3271         [PDM_RESET] = { 0x2cc0, 12 },
3272         [MPM_H_RESET] = { 0x2da0, 7 },
3273         [MPM_RESET] = { 0x2da4, 0 },
3274         [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
3275         [PRNG_RESET] = { 0x2e80, 12 },
3276         [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
3277         [SFAB_CE3_S_RESET] = { 0x36c8, 0 },
3278         [CE3_SLEEP_RESET] = { 0x36d0, 7 },
3279         [PCIE_1_M_RESET] = { 0x3a98, 1 },
3280         [PCIE_1_S_RESET] = { 0x3a98, 0 },
3281         [PCIE_1_EXT_RESET] = { 0x3a9c, 6 },
3282         [PCIE_1_PHY_RESET] = { 0x3a9c, 5 },
3283         [PCIE_1_PCI_RESET] = { 0x3a9c, 4 },
3284         [PCIE_1_POR_RESET] = { 0x3a9c, 3 },
3285         [PCIE_1_HCLK_RESET] = { 0x3a9c, 2 },
3286         [PCIE_1_ACLK_RESET] = { 0x3a9c, 0 },
3287         [PCIE_2_M_RESET] = { 0x3ad8, 1 },
3288         [PCIE_2_S_RESET] = { 0x3ad8, 0 },
3289         [PCIE_2_EXT_RESET] = { 0x3adc, 6 },
3290         [PCIE_2_PHY_RESET] = { 0x3adc, 5 },
3291         [PCIE_2_PCI_RESET] = { 0x3adc, 4 },
3292         [PCIE_2_POR_RESET] = { 0x3adc, 3 },
3293         [PCIE_2_HCLK_RESET] = { 0x3adc, 2 },
3294         [PCIE_2_ACLK_RESET] = { 0x3adc, 0 },
3295         [SFAB_USB30_S_RESET] = { 0x3b54, 1 },
3296         [SFAB_USB30_M_RESET] = { 0x3b54, 0 },
3297         [USB30_0_PORT2_HS_PHY_RESET] = { 0x3b50, 5 },
3298         [USB30_0_MASTER_RESET] = { 0x3b50, 4 },
3299         [USB30_0_SLEEP_RESET] = { 0x3b50, 3 },
3300         [USB30_0_UTMI_PHY_RESET] = { 0x3b50, 2 },
3301         [USB30_0_POWERON_RESET] = { 0x3b50, 1 },
3302         [USB30_0_PHY_RESET] = { 0x3b50, 0 },
3303         [USB30_1_MASTER_RESET] = { 0x3b58, 4 },
3304         [USB30_1_SLEEP_RESET] = { 0x3b58, 3 },
3305         [USB30_1_UTMI_PHY_RESET] = { 0x3b58, 2 },
3306         [USB30_1_POWERON_RESET] = { 0x3b58, 1 },
3307         [USB30_1_PHY_RESET] = { 0x3b58, 0 },
3308         [NSSFB0_RESET] = { 0x3b60, 6 },
3309         [NSSFB1_RESET] = { 0x3b60, 7 },
3310         [UBI32_CORE1_CLKRST_CLAMP_RESET] = { 0x3d3c, 3},
3311         [UBI32_CORE1_CLAMP_RESET] = { 0x3d3c, 2 },
3312         [UBI32_CORE1_AHB_RESET] = { 0x3d3c, 1 },
3313         [UBI32_CORE1_AXI_RESET] = { 0x3d3c, 0 },
3314         [UBI32_CORE2_CLKRST_CLAMP_RESET] = { 0x3d5c, 3 },
3315         [UBI32_CORE2_CLAMP_RESET] = { 0x3d5c, 2 },
3316         [UBI32_CORE2_AHB_RESET] = { 0x3d5c, 1 },
3317         [UBI32_CORE2_AXI_RESET] = { 0x3d5c, 0 },
3318         [GMAC_CORE1_RESET] = { 0x3cbc, 0 },
3319         [GMAC_CORE2_RESET] = { 0x3cdc, 0 },
3320         [GMAC_CORE3_RESET] = { 0x3cfc, 0 },
3321         [GMAC_CORE4_RESET] = { 0x3d1c, 0 },
3322         [GMAC_AHB_RESET] = { 0x3e24, 0 },
3323         [CRYPTO_ENG1_RESET] = { 0x3e00, 0},
3324         [CRYPTO_ENG2_RESET] = { 0x3e04, 0},
3325         [CRYPTO_ENG3_RESET] = { 0x3e08, 0},
3326         [CRYPTO_ENG4_RESET] = { 0x3e0c, 0},
3327         [CRYPTO_AHB_RESET] = { 0x3e10, 0},
3328         [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 },
3329         [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 },
3330         [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 },
3331         [NSS_CH0_HW_RST_RX_125M_N_RESET] = { 0x3b60, 3 },
3332         [NSS_CH0_RST_TX_125M_N_RESET] = { 0x3b60, 4 },
3333         [NSS_CH1_RST_RX_CLK_N_RESET] = { 0x3b60, 5 },
3334         [NSS_CH1_RST_TX_CLK_N_RESET] = { 0x3b60, 6 },
3335         [NSS_CH1_RST_RX_125M_N_RESET] = { 0x3b60, 7 },
3336         [NSS_CH1_HW_RST_RX_125M_N_RESET] = { 0x3b60, 8 },
3337         [NSS_CH1_RST_TX_125M_N_RESET] = { 0x3b60, 9 },
3338         [NSS_CH2_RST_RX_CLK_N_RESET] = { 0x3b60, 10 },
3339         [NSS_CH2_RST_TX_CLK_N_RESET] = { 0x3b60, 11 },
3340         [NSS_CH2_RST_RX_125M_N_RESET] = { 0x3b60, 12 },
3341         [NSS_CH2_HW_RST_RX_125M_N_RESET] = { 0x3b60, 13 },
3342         [NSS_CH2_RST_TX_125M_N_RESET] = { 0x3b60, 14 },
3343         [NSS_CH3_RST_RX_CLK_N_RESET] = { 0x3b60, 15 },
3344         [NSS_CH3_RST_TX_CLK_N_RESET] = { 0x3b60, 16 },
3345         [NSS_CH3_RST_RX_125M_N_RESET] = { 0x3b60, 17 },
3346         [NSS_CH3_HW_RST_RX_125M_N_RESET] = { 0x3b60, 18 },
3347         [NSS_CH3_RST_TX_125M_N_RESET] = { 0x3b60, 19 },
3348         [NSS_RST_RX_250M_125M_N_RESET] = { 0x3b60, 20 },
3349         [NSS_RST_TX_250M_125M_N_RESET] = { 0x3b60, 21 },
3350         [NSS_QSGMII_TXPI_RST_N_RESET] = { 0x3b60, 22 },
3351         [NSS_QSGMII_CDR_RST_N_RESET] = { 0x3b60, 23 },
3352         [NSS_SGMII2_CDR_RST_N_RESET] = { 0x3b60, 24 },
3353         [NSS_SGMII3_CDR_RST_N_RESET] = { 0x3b60, 25 },
3354         [NSS_CAL_PRBS_RST_N_RESET] = { 0x3b60, 26 },
3355         [NSS_LCKDT_RST_N_RESET] = { 0x3b60, 27 },
3356         [NSS_SRDS_N_RESET] = { 0x3b60, 28 },
3357 };
3358
3359 static const struct regmap_config gcc_ipq806x_regmap_config = {
3360         .reg_bits       = 32,
3361         .reg_stride     = 4,
3362         .val_bits       = 32,
3363         .max_register   = 0x3e40,
3364         .fast_io        = true,
3365 };
3366
3367 static const struct qcom_cc_desc gcc_ipq806x_desc = {
3368         .config = &gcc_ipq806x_regmap_config,
3369         .clks = gcc_ipq806x_clks,
3370         .num_clks = ARRAY_SIZE(gcc_ipq806x_clks),
3371         .resets = gcc_ipq806x_resets,
3372         .num_resets = ARRAY_SIZE(gcc_ipq806x_resets),
3373 };
3374
3375 static const struct of_device_id gcc_ipq806x_match_table[] = {
3376         { .compatible = "qcom,gcc-ipq8064" },
3377         { }
3378 };
3379 MODULE_DEVICE_TABLE(of, gcc_ipq806x_match_table);
3380
3381 static int gcc_ipq806x_probe(struct platform_device *pdev)
3382 {
3383         struct device *dev = &pdev->dev;
3384         struct regmap *regmap;
3385         int ret;
3386
3387         ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000);
3388         if (ret)
3389                 return ret;
3390
3391         ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000);
3392         if (ret)
3393                 return ret;
3394
3395         if (of_machine_is_compatible("qcom,ipq8065")) {
3396                 ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8065;
3397                 ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8065;
3398         } else {
3399                 ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8064;
3400                 ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8064;
3401         }
3402
3403         ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc);
3404         if (ret)
3405                 return ret;
3406
3407         regmap = dev_get_regmap(dev, NULL);
3408         if (!regmap)
3409                 return -ENODEV;
3410
3411         /* Setup PLL18 static bits */
3412         regmap_update_bits(regmap, 0x31a4, 0xffffffc0, 0x40000400);
3413         regmap_write(regmap, 0x31b0, 0x3080);
3414
3415         /* Set GMAC footswitch sleep/wakeup values */
3416         regmap_write(regmap, 0x3cb8, 8);
3417         regmap_write(regmap, 0x3cd8, 8);
3418         regmap_write(regmap, 0x3cf8, 8);
3419         regmap_write(regmap, 0x3d18, 8);
3420
3421         return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
3422 }
3423
3424 static struct platform_driver gcc_ipq806x_driver = {
3425         .probe          = gcc_ipq806x_probe,
3426         .driver         = {
3427                 .name   = "gcc-ipq806x",
3428                 .of_match_table = gcc_ipq806x_match_table,
3429         },
3430 };
3431
3432 static int __init gcc_ipq806x_init(void)
3433 {
3434         return platform_driver_register(&gcc_ipq806x_driver);
3435 }
3436 core_initcall(gcc_ipq806x_init);
3437
3438 static void __exit gcc_ipq806x_exit(void)
3439 {
3440         platform_driver_unregister(&gcc_ipq806x_driver);
3441 }
3442 module_exit(gcc_ipq806x_exit);
3443
3444 MODULE_DESCRIPTION("QCOM GCC IPQ806x Driver");
3445 MODULE_LICENSE("GPL v2");
3446 MODULE_ALIAS("platform:gcc-ipq806x");