2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/clk-provider.h>
22 #include <linux/regmap.h>
23 #include <linux/reset-controller.h>
25 #include <dt-bindings/clock/qcom,gcc-apq8084.h>
26 #include <dt-bindings/reset/qcom,gcc-apq8084.h>
29 #include "clk-regmap.h"
32 #include "clk-branch.h"
46 static const struct parent_map gcc_xo_gpll0_map[] = {
51 static const char * const gcc_xo_gpll0[] = {
56 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
62 static const char * const gcc_xo_gpll0_gpll4[] = {
68 static const struct parent_map gcc_xo_sata_asic0_map[] = {
70 { P_SATA_ASIC0_CLK, 2 }
73 static const char * const gcc_xo_sata_asic0[] = {
78 static const struct parent_map gcc_xo_sata_rx_map[] = {
83 static const char * const gcc_xo_sata_rx[] = {
88 static const struct parent_map gcc_xo_pcie_map[] = {
90 { P_PCIE_0_1_PIPE_CLK, 2 }
93 static const char * const gcc_xo_pcie[] = {
98 static const struct parent_map gcc_xo_pcie_sleep_map[] = {
103 static const char * const gcc_xo_pcie_sleep[] = {
108 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
110 static struct clk_pll gpll0 = {
114 .config_reg = 0x0014,
116 .status_reg = 0x001c,
118 .clkr.hw.init = &(struct clk_init_data){
120 .parent_names = (const char *[]){ "xo" },
126 static struct clk_regmap gpll0_vote = {
127 .enable_reg = 0x1480,
128 .enable_mask = BIT(0),
129 .hw.init = &(struct clk_init_data){
130 .name = "gpll0_vote",
131 .parent_names = (const char *[]){ "gpll0" },
133 .ops = &clk_pll_vote_ops,
137 static struct clk_rcg2 config_noc_clk_src = {
140 .parent_map = gcc_xo_gpll0_map,
141 .clkr.hw.init = &(struct clk_init_data){
142 .name = "config_noc_clk_src",
143 .parent_names = gcc_xo_gpll0,
145 .ops = &clk_rcg2_ops,
149 static struct clk_rcg2 periph_noc_clk_src = {
152 .parent_map = gcc_xo_gpll0_map,
153 .clkr.hw.init = &(struct clk_init_data){
154 .name = "periph_noc_clk_src",
155 .parent_names = gcc_xo_gpll0,
157 .ops = &clk_rcg2_ops,
161 static struct clk_rcg2 system_noc_clk_src = {
164 .parent_map = gcc_xo_gpll0_map,
165 .clkr.hw.init = &(struct clk_init_data){
166 .name = "system_noc_clk_src",
167 .parent_names = gcc_xo_gpll0,
169 .ops = &clk_rcg2_ops,
173 static struct clk_pll gpll1 = {
177 .config_reg = 0x0054,
179 .status_reg = 0x005c,
181 .clkr.hw.init = &(struct clk_init_data){
183 .parent_names = (const char *[]){ "xo" },
189 static struct clk_regmap gpll1_vote = {
190 .enable_reg = 0x1480,
191 .enable_mask = BIT(1),
192 .hw.init = &(struct clk_init_data){
193 .name = "gpll1_vote",
194 .parent_names = (const char *[]){ "gpll1" },
196 .ops = &clk_pll_vote_ops,
200 static struct clk_pll gpll4 = {
204 .config_reg = 0x1dd4,
206 .status_reg = 0x1ddc,
208 .clkr.hw.init = &(struct clk_init_data){
210 .parent_names = (const char *[]){ "xo" },
216 static struct clk_regmap gpll4_vote = {
217 .enable_reg = 0x1480,
218 .enable_mask = BIT(4),
219 .hw.init = &(struct clk_init_data){
220 .name = "gpll4_vote",
221 .parent_names = (const char *[]){ "gpll4" },
223 .ops = &clk_pll_vote_ops,
227 static const struct freq_tbl ftbl_gcc_ufs_axi_clk[] = {
228 F(100000000, P_GPLL0, 6, 0, 0),
229 F(200000000, P_GPLL0, 3, 0, 0),
230 F(240000000, P_GPLL0, 2.5, 0, 0),
234 static struct clk_rcg2 ufs_axi_clk_src = {
238 .parent_map = gcc_xo_gpll0_map,
239 .freq_tbl = ftbl_gcc_ufs_axi_clk,
240 .clkr.hw.init = &(struct clk_init_data){
241 .name = "ufs_axi_clk_src",
242 .parent_names = gcc_xo_gpll0,
244 .ops = &clk_rcg2_ops,
248 static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = {
249 F(125000000, P_GPLL0, 1, 5, 24),
253 static struct clk_rcg2 usb30_master_clk_src = {
257 .parent_map = gcc_xo_gpll0_map,
258 .freq_tbl = ftbl_gcc_usb30_master_clk,
259 .clkr.hw.init = &(struct clk_init_data){
260 .name = "usb30_master_clk_src",
261 .parent_names = gcc_xo_gpll0,
263 .ops = &clk_rcg2_ops,
267 static const struct freq_tbl ftbl_gcc_usb30_sec_master_clk[] = {
268 F(125000000, P_GPLL0, 1, 5, 24),
272 static struct clk_rcg2 usb30_sec_master_clk_src = {
276 .parent_map = gcc_xo_gpll0_map,
277 .freq_tbl = ftbl_gcc_usb30_sec_master_clk,
278 .clkr.hw.init = &(struct clk_init_data){
279 .name = "usb30_sec_master_clk_src",
280 .parent_names = gcc_xo_gpll0,
282 .ops = &clk_rcg2_ops,
286 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
289 .enable_reg = 0x1bd0,
290 .enable_mask = BIT(0),
291 .hw.init = &(struct clk_init_data){
292 .name = "gcc_usb30_sec_mock_utmi_clk",
293 .parent_names = (const char *[]){
294 "usb30_sec_mock_utmi_clk_src",
297 .flags = CLK_SET_RATE_PARENT,
298 .ops = &clk_branch2_ops,
303 static struct clk_branch gcc_usb30_sec_sleep_clk = {
306 .enable_reg = 0x1bcc,
307 .enable_mask = BIT(0),
308 .hw.init = &(struct clk_init_data){
309 .name = "gcc_usb30_sec_sleep_clk",
310 .parent_names = (const char *[]){
314 .flags = CLK_SET_RATE_PARENT,
315 .ops = &clk_branch2_ops,
320 static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk[] = {
321 F(19200000, P_XO, 1, 0, 0),
322 F(50000000, P_GPLL0, 12, 0, 0),
326 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
329 .parent_map = gcc_xo_gpll0_map,
330 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
331 .clkr.hw.init = &(struct clk_init_data){
332 .name = "blsp1_qup1_i2c_apps_clk_src",
333 .parent_names = gcc_xo_gpll0,
335 .ops = &clk_rcg2_ops,
339 static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk[] = {
340 F(960000, P_XO, 10, 1, 2),
341 F(4800000, P_XO, 4, 0, 0),
342 F(9600000, P_XO, 2, 0, 0),
343 F(15000000, P_GPLL0, 10, 1, 4),
344 F(19200000, P_XO, 1, 0, 0),
345 F(25000000, P_GPLL0, 12, 1, 2),
346 F(50000000, P_GPLL0, 12, 0, 0),
350 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
354 .parent_map = gcc_xo_gpll0_map,
355 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
356 .clkr.hw.init = &(struct clk_init_data){
357 .name = "blsp1_qup1_spi_apps_clk_src",
358 .parent_names = gcc_xo_gpll0,
360 .ops = &clk_rcg2_ops,
364 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
367 .parent_map = gcc_xo_gpll0_map,
368 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
369 .clkr.hw.init = &(struct clk_init_data){
370 .name = "blsp1_qup2_i2c_apps_clk_src",
371 .parent_names = gcc_xo_gpll0,
373 .ops = &clk_rcg2_ops,
377 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
381 .parent_map = gcc_xo_gpll0_map,
382 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
383 .clkr.hw.init = &(struct clk_init_data){
384 .name = "blsp1_qup2_spi_apps_clk_src",
385 .parent_names = gcc_xo_gpll0,
387 .ops = &clk_rcg2_ops,
391 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
394 .parent_map = gcc_xo_gpll0_map,
395 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
396 .clkr.hw.init = &(struct clk_init_data){
397 .name = "blsp1_qup3_i2c_apps_clk_src",
398 .parent_names = gcc_xo_gpll0,
400 .ops = &clk_rcg2_ops,
404 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
408 .parent_map = gcc_xo_gpll0_map,
409 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
410 .clkr.hw.init = &(struct clk_init_data){
411 .name = "blsp1_qup3_spi_apps_clk_src",
412 .parent_names = gcc_xo_gpll0,
414 .ops = &clk_rcg2_ops,
418 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
421 .parent_map = gcc_xo_gpll0_map,
422 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
423 .clkr.hw.init = &(struct clk_init_data){
424 .name = "blsp1_qup4_i2c_apps_clk_src",
425 .parent_names = gcc_xo_gpll0,
427 .ops = &clk_rcg2_ops,
431 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
435 .parent_map = gcc_xo_gpll0_map,
436 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
437 .clkr.hw.init = &(struct clk_init_data){
438 .name = "blsp1_qup4_spi_apps_clk_src",
439 .parent_names = gcc_xo_gpll0,
441 .ops = &clk_rcg2_ops,
445 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
448 .parent_map = gcc_xo_gpll0_map,
449 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
450 .clkr.hw.init = &(struct clk_init_data){
451 .name = "blsp1_qup5_i2c_apps_clk_src",
452 .parent_names = gcc_xo_gpll0,
454 .ops = &clk_rcg2_ops,
458 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
462 .parent_map = gcc_xo_gpll0_map,
463 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
464 .clkr.hw.init = &(struct clk_init_data){
465 .name = "blsp1_qup5_spi_apps_clk_src",
466 .parent_names = gcc_xo_gpll0,
468 .ops = &clk_rcg2_ops,
472 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
475 .parent_map = gcc_xo_gpll0_map,
476 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
477 .clkr.hw.init = &(struct clk_init_data){
478 .name = "blsp1_qup6_i2c_apps_clk_src",
479 .parent_names = gcc_xo_gpll0,
481 .ops = &clk_rcg2_ops,
485 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
489 .parent_map = gcc_xo_gpll0_map,
490 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
491 .clkr.hw.init = &(struct clk_init_data){
492 .name = "blsp1_qup6_spi_apps_clk_src",
493 .parent_names = gcc_xo_gpll0,
495 .ops = &clk_rcg2_ops,
499 static const struct freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = {
500 F(3686400, P_GPLL0, 1, 96, 15625),
501 F(7372800, P_GPLL0, 1, 192, 15625),
502 F(14745600, P_GPLL0, 1, 384, 15625),
503 F(16000000, P_GPLL0, 5, 2, 15),
504 F(19200000, P_XO, 1, 0, 0),
505 F(24000000, P_GPLL0, 5, 1, 5),
506 F(32000000, P_GPLL0, 1, 4, 75),
507 F(40000000, P_GPLL0, 15, 0, 0),
508 F(46400000, P_GPLL0, 1, 29, 375),
509 F(48000000, P_GPLL0, 12.5, 0, 0),
510 F(51200000, P_GPLL0, 1, 32, 375),
511 F(56000000, P_GPLL0, 1, 7, 75),
512 F(58982400, P_GPLL0, 1, 1536, 15625),
513 F(60000000, P_GPLL0, 10, 0, 0),
514 F(63160000, P_GPLL0, 9.5, 0, 0),
518 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
522 .parent_map = gcc_xo_gpll0_map,
523 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
524 .clkr.hw.init = &(struct clk_init_data){
525 .name = "blsp1_uart1_apps_clk_src",
526 .parent_names = gcc_xo_gpll0,
528 .ops = &clk_rcg2_ops,
532 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
536 .parent_map = gcc_xo_gpll0_map,
537 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
538 .clkr.hw.init = &(struct clk_init_data){
539 .name = "blsp1_uart2_apps_clk_src",
540 .parent_names = gcc_xo_gpll0,
542 .ops = &clk_rcg2_ops,
546 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
550 .parent_map = gcc_xo_gpll0_map,
551 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
552 .clkr.hw.init = &(struct clk_init_data){
553 .name = "blsp1_uart3_apps_clk_src",
554 .parent_names = gcc_xo_gpll0,
556 .ops = &clk_rcg2_ops,
560 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
564 .parent_map = gcc_xo_gpll0_map,
565 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
566 .clkr.hw.init = &(struct clk_init_data){
567 .name = "blsp1_uart4_apps_clk_src",
568 .parent_names = gcc_xo_gpll0,
570 .ops = &clk_rcg2_ops,
574 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
578 .parent_map = gcc_xo_gpll0_map,
579 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
580 .clkr.hw.init = &(struct clk_init_data){
581 .name = "blsp1_uart5_apps_clk_src",
582 .parent_names = gcc_xo_gpll0,
584 .ops = &clk_rcg2_ops,
588 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
592 .parent_map = gcc_xo_gpll0_map,
593 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
594 .clkr.hw.init = &(struct clk_init_data){
595 .name = "blsp1_uart6_apps_clk_src",
596 .parent_names = gcc_xo_gpll0,
598 .ops = &clk_rcg2_ops,
602 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
605 .parent_map = gcc_xo_gpll0_map,
606 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
607 .clkr.hw.init = &(struct clk_init_data){
608 .name = "blsp2_qup1_i2c_apps_clk_src",
609 .parent_names = gcc_xo_gpll0,
611 .ops = &clk_rcg2_ops,
615 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
619 .parent_map = gcc_xo_gpll0_map,
620 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
621 .clkr.hw.init = &(struct clk_init_data){
622 .name = "blsp2_qup1_spi_apps_clk_src",
623 .parent_names = gcc_xo_gpll0,
625 .ops = &clk_rcg2_ops,
629 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
632 .parent_map = gcc_xo_gpll0_map,
633 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
634 .clkr.hw.init = &(struct clk_init_data){
635 .name = "blsp2_qup2_i2c_apps_clk_src",
636 .parent_names = gcc_xo_gpll0,
638 .ops = &clk_rcg2_ops,
642 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
646 .parent_map = gcc_xo_gpll0_map,
647 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
648 .clkr.hw.init = &(struct clk_init_data){
649 .name = "blsp2_qup2_spi_apps_clk_src",
650 .parent_names = gcc_xo_gpll0,
652 .ops = &clk_rcg2_ops,
656 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
659 .parent_map = gcc_xo_gpll0_map,
660 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
661 .clkr.hw.init = &(struct clk_init_data){
662 .name = "blsp2_qup3_i2c_apps_clk_src",
663 .parent_names = gcc_xo_gpll0,
665 .ops = &clk_rcg2_ops,
669 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
673 .parent_map = gcc_xo_gpll0_map,
674 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
675 .clkr.hw.init = &(struct clk_init_data){
676 .name = "blsp2_qup3_spi_apps_clk_src",
677 .parent_names = gcc_xo_gpll0,
679 .ops = &clk_rcg2_ops,
683 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
686 .parent_map = gcc_xo_gpll0_map,
687 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
688 .clkr.hw.init = &(struct clk_init_data){
689 .name = "blsp2_qup4_i2c_apps_clk_src",
690 .parent_names = gcc_xo_gpll0,
692 .ops = &clk_rcg2_ops,
696 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
700 .parent_map = gcc_xo_gpll0_map,
701 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
702 .clkr.hw.init = &(struct clk_init_data){
703 .name = "blsp2_qup4_spi_apps_clk_src",
704 .parent_names = gcc_xo_gpll0,
706 .ops = &clk_rcg2_ops,
710 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
713 .parent_map = gcc_xo_gpll0_map,
714 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
715 .clkr.hw.init = &(struct clk_init_data){
716 .name = "blsp2_qup5_i2c_apps_clk_src",
717 .parent_names = gcc_xo_gpll0,
719 .ops = &clk_rcg2_ops,
723 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
727 .parent_map = gcc_xo_gpll0_map,
728 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
729 .clkr.hw.init = &(struct clk_init_data){
730 .name = "blsp2_qup5_spi_apps_clk_src",
731 .parent_names = gcc_xo_gpll0,
733 .ops = &clk_rcg2_ops,
737 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
740 .parent_map = gcc_xo_gpll0_map,
741 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
742 .clkr.hw.init = &(struct clk_init_data){
743 .name = "blsp2_qup6_i2c_apps_clk_src",
744 .parent_names = gcc_xo_gpll0,
746 .ops = &clk_rcg2_ops,
750 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
754 .parent_map = gcc_xo_gpll0_map,
755 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
756 .clkr.hw.init = &(struct clk_init_data){
757 .name = "blsp2_qup6_spi_apps_clk_src",
758 .parent_names = gcc_xo_gpll0,
760 .ops = &clk_rcg2_ops,
764 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
768 .parent_map = gcc_xo_gpll0_map,
769 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
770 .clkr.hw.init = &(struct clk_init_data){
771 .name = "blsp2_uart1_apps_clk_src",
772 .parent_names = gcc_xo_gpll0,
774 .ops = &clk_rcg2_ops,
778 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
782 .parent_map = gcc_xo_gpll0_map,
783 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
784 .clkr.hw.init = &(struct clk_init_data){
785 .name = "blsp2_uart2_apps_clk_src",
786 .parent_names = gcc_xo_gpll0,
788 .ops = &clk_rcg2_ops,
792 static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
796 .parent_map = gcc_xo_gpll0_map,
797 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
798 .clkr.hw.init = &(struct clk_init_data){
799 .name = "blsp2_uart3_apps_clk_src",
800 .parent_names = gcc_xo_gpll0,
802 .ops = &clk_rcg2_ops,
806 static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
810 .parent_map = gcc_xo_gpll0_map,
811 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
812 .clkr.hw.init = &(struct clk_init_data){
813 .name = "blsp2_uart4_apps_clk_src",
814 .parent_names = gcc_xo_gpll0,
816 .ops = &clk_rcg2_ops,
820 static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
824 .parent_map = gcc_xo_gpll0_map,
825 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
826 .clkr.hw.init = &(struct clk_init_data){
827 .name = "blsp2_uart5_apps_clk_src",
828 .parent_names = gcc_xo_gpll0,
830 .ops = &clk_rcg2_ops,
834 static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
838 .parent_map = gcc_xo_gpll0_map,
839 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
840 .clkr.hw.init = &(struct clk_init_data){
841 .name = "blsp2_uart6_apps_clk_src",
842 .parent_names = gcc_xo_gpll0,
844 .ops = &clk_rcg2_ops,
848 static const struct freq_tbl ftbl_gcc_ce1_clk[] = {
849 F(50000000, P_GPLL0, 12, 0, 0),
850 F(85710000, P_GPLL0, 7, 0, 0),
851 F(100000000, P_GPLL0, 6, 0, 0),
852 F(171430000, P_GPLL0, 3.5, 0, 0),
856 static struct clk_rcg2 ce1_clk_src = {
859 .parent_map = gcc_xo_gpll0_map,
860 .freq_tbl = ftbl_gcc_ce1_clk,
861 .clkr.hw.init = &(struct clk_init_data){
862 .name = "ce1_clk_src",
863 .parent_names = gcc_xo_gpll0,
865 .ops = &clk_rcg2_ops,
869 static const struct freq_tbl ftbl_gcc_ce2_clk[] = {
870 F(50000000, P_GPLL0, 12, 0, 0),
871 F(85710000, P_GPLL0, 7, 0, 0),
872 F(100000000, P_GPLL0, 6, 0, 0),
873 F(171430000, P_GPLL0, 3.5, 0, 0),
877 static struct clk_rcg2 ce2_clk_src = {
880 .parent_map = gcc_xo_gpll0_map,
881 .freq_tbl = ftbl_gcc_ce2_clk,
882 .clkr.hw.init = &(struct clk_init_data){
883 .name = "ce2_clk_src",
884 .parent_names = gcc_xo_gpll0,
886 .ops = &clk_rcg2_ops,
890 static const struct freq_tbl ftbl_gcc_ce3_clk[] = {
891 F(50000000, P_GPLL0, 12, 0, 0),
892 F(85710000, P_GPLL0, 7, 0, 0),
893 F(100000000, P_GPLL0, 6, 0, 0),
894 F(171430000, P_GPLL0, 3.5, 0, 0),
898 static struct clk_rcg2 ce3_clk_src = {
901 .parent_map = gcc_xo_gpll0_map,
902 .freq_tbl = ftbl_gcc_ce3_clk,
903 .clkr.hw.init = &(struct clk_init_data){
904 .name = "ce3_clk_src",
905 .parent_names = gcc_xo_gpll0,
907 .ops = &clk_rcg2_ops,
911 static const struct freq_tbl ftbl_gcc_gp_clk[] = {
912 F(19200000, P_XO, 1, 0, 0),
913 F(100000000, P_GPLL0, 6, 0, 0),
914 F(200000000, P_GPLL0, 3, 0, 0),
918 static struct clk_rcg2 gp1_clk_src = {
922 .parent_map = gcc_xo_gpll0_map,
923 .freq_tbl = ftbl_gcc_gp_clk,
924 .clkr.hw.init = &(struct clk_init_data){
925 .name = "gp1_clk_src",
926 .parent_names = gcc_xo_gpll0,
928 .ops = &clk_rcg2_ops,
932 static struct clk_rcg2 gp2_clk_src = {
936 .parent_map = gcc_xo_gpll0_map,
937 .freq_tbl = ftbl_gcc_gp_clk,
938 .clkr.hw.init = &(struct clk_init_data){
939 .name = "gp2_clk_src",
940 .parent_names = gcc_xo_gpll0,
942 .ops = &clk_rcg2_ops,
946 static struct clk_rcg2 gp3_clk_src = {
950 .parent_map = gcc_xo_gpll0_map,
951 .freq_tbl = ftbl_gcc_gp_clk,
952 .clkr.hw.init = &(struct clk_init_data){
953 .name = "gp3_clk_src",
954 .parent_names = gcc_xo_gpll0,
956 .ops = &clk_rcg2_ops,
960 static const struct freq_tbl ftbl_gcc_pcie_0_1_aux_clk[] = {
961 F(1010000, P_XO, 1, 1, 19),
965 static struct clk_rcg2 pcie_0_aux_clk_src = {
969 .parent_map = gcc_xo_pcie_sleep_map,
970 .freq_tbl = ftbl_gcc_pcie_0_1_aux_clk,
971 .clkr.hw.init = &(struct clk_init_data){
972 .name = "pcie_0_aux_clk_src",
973 .parent_names = gcc_xo_pcie_sleep,
975 .ops = &clk_rcg2_ops,
979 static struct clk_rcg2 pcie_1_aux_clk_src = {
983 .parent_map = gcc_xo_pcie_sleep_map,
984 .freq_tbl = ftbl_gcc_pcie_0_1_aux_clk,
985 .clkr.hw.init = &(struct clk_init_data){
986 .name = "pcie_1_aux_clk_src",
987 .parent_names = gcc_xo_pcie_sleep,
989 .ops = &clk_rcg2_ops,
993 static const struct freq_tbl ftbl_gcc_pcie_0_1_pipe_clk[] = {
994 F(125000000, P_PCIE_0_1_PIPE_CLK, 1, 0, 0),
995 F(250000000, P_PCIE_0_1_PIPE_CLK, 1, 0, 0),
999 static struct clk_rcg2 pcie_0_pipe_clk_src = {
1002 .parent_map = gcc_xo_pcie_map,
1003 .freq_tbl = ftbl_gcc_pcie_0_1_pipe_clk,
1004 .clkr.hw.init = &(struct clk_init_data){
1005 .name = "pcie_0_pipe_clk_src",
1006 .parent_names = gcc_xo_pcie,
1008 .ops = &clk_rcg2_ops,
1012 static struct clk_rcg2 pcie_1_pipe_clk_src = {
1015 .parent_map = gcc_xo_pcie_map,
1016 .freq_tbl = ftbl_gcc_pcie_0_1_pipe_clk,
1017 .clkr.hw.init = &(struct clk_init_data){
1018 .name = "pcie_1_pipe_clk_src",
1019 .parent_names = gcc_xo_pcie,
1021 .ops = &clk_rcg2_ops,
1025 static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
1026 F(60000000, P_GPLL0, 10, 0, 0),
1030 static struct clk_rcg2 pdm2_clk_src = {
1033 .parent_map = gcc_xo_gpll0_map,
1034 .freq_tbl = ftbl_gcc_pdm2_clk,
1035 .clkr.hw.init = &(struct clk_init_data){
1036 .name = "pdm2_clk_src",
1037 .parent_names = gcc_xo_gpll0,
1039 .ops = &clk_rcg2_ops,
1043 static const struct freq_tbl ftbl_gcc_sata_asic0_clk[] = {
1044 F(75000000, P_SATA_ASIC0_CLK, 1, 0, 0),
1045 F(150000000, P_SATA_ASIC0_CLK, 1, 0, 0),
1046 F(300000000, P_SATA_ASIC0_CLK, 1, 0, 0),
1050 static struct clk_rcg2 sata_asic0_clk_src = {
1053 .parent_map = gcc_xo_sata_asic0_map,
1054 .freq_tbl = ftbl_gcc_sata_asic0_clk,
1055 .clkr.hw.init = &(struct clk_init_data){
1056 .name = "sata_asic0_clk_src",
1057 .parent_names = gcc_xo_sata_asic0,
1059 .ops = &clk_rcg2_ops,
1063 static const struct freq_tbl ftbl_gcc_sata_pmalive_clk[] = {
1064 F(19200000, P_XO, 1, 0, 0),
1065 F(50000000, P_GPLL0, 12, 0, 0),
1066 F(100000000, P_GPLL0, 6, 0, 0),
1070 static struct clk_rcg2 sata_pmalive_clk_src = {
1073 .parent_map = gcc_xo_gpll0_map,
1074 .freq_tbl = ftbl_gcc_sata_pmalive_clk,
1075 .clkr.hw.init = &(struct clk_init_data){
1076 .name = "sata_pmalive_clk_src",
1077 .parent_names = gcc_xo_gpll0,
1079 .ops = &clk_rcg2_ops,
1083 static const struct freq_tbl ftbl_gcc_sata_rx_clk[] = {
1084 F(75000000, P_SATA_RX_CLK, 1, 0, 0),
1085 F(150000000, P_SATA_RX_CLK, 1, 0, 0),
1086 F(300000000, P_SATA_RX_CLK, 1, 0, 0),
1090 static struct clk_rcg2 sata_rx_clk_src = {
1093 .parent_map = gcc_xo_sata_rx_map,
1094 .freq_tbl = ftbl_gcc_sata_rx_clk,
1095 .clkr.hw.init = &(struct clk_init_data){
1096 .name = "sata_rx_clk_src",
1097 .parent_names = gcc_xo_sata_rx,
1099 .ops = &clk_rcg2_ops,
1103 static const struct freq_tbl ftbl_gcc_sata_rx_oob_clk[] = {
1104 F(100000000, P_GPLL0, 6, 0, 0),
1108 static struct clk_rcg2 sata_rx_oob_clk_src = {
1111 .parent_map = gcc_xo_gpll0_map,
1112 .freq_tbl = ftbl_gcc_sata_rx_oob_clk,
1113 .clkr.hw.init = &(struct clk_init_data){
1114 .name = "sata_rx_oob_clk_src",
1115 .parent_names = gcc_xo_gpll0,
1117 .ops = &clk_rcg2_ops,
1121 static const struct freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = {
1122 F(144000, P_XO, 16, 3, 25),
1123 F(400000, P_XO, 12, 1, 4),
1124 F(20000000, P_GPLL0, 15, 1, 2),
1125 F(25000000, P_GPLL0, 12, 1, 2),
1126 F(50000000, P_GPLL0, 12, 0, 0),
1127 F(100000000, P_GPLL0, 6, 0, 0),
1128 F(192000000, P_GPLL4, 4, 0, 0),
1129 F(200000000, P_GPLL0, 3, 0, 0),
1130 F(384000000, P_GPLL4, 2, 0, 0),
1134 static struct clk_rcg2 sdcc1_apps_clk_src = {
1138 .parent_map = gcc_xo_gpll0_gpll4_map,
1139 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
1140 .clkr.hw.init = &(struct clk_init_data){
1141 .name = "sdcc1_apps_clk_src",
1142 .parent_names = gcc_xo_gpll0_gpll4,
1144 .ops = &clk_rcg2_ops,
1148 static struct clk_rcg2 sdcc2_apps_clk_src = {
1152 .parent_map = gcc_xo_gpll0_map,
1153 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
1154 .clkr.hw.init = &(struct clk_init_data){
1155 .name = "sdcc2_apps_clk_src",
1156 .parent_names = gcc_xo_gpll0,
1158 .ops = &clk_rcg2_ops,
1162 static struct clk_rcg2 sdcc3_apps_clk_src = {
1166 .parent_map = gcc_xo_gpll0_map,
1167 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
1168 .clkr.hw.init = &(struct clk_init_data){
1169 .name = "sdcc3_apps_clk_src",
1170 .parent_names = gcc_xo_gpll0,
1172 .ops = &clk_rcg2_ops,
1176 static struct clk_rcg2 sdcc4_apps_clk_src = {
1180 .parent_map = gcc_xo_gpll0_map,
1181 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
1182 .clkr.hw.init = &(struct clk_init_data){
1183 .name = "sdcc4_apps_clk_src",
1184 .parent_names = gcc_xo_gpll0,
1186 .ops = &clk_rcg2_ops,
1190 static const struct freq_tbl ftbl_gcc_tsif_ref_clk[] = {
1191 F(105000, P_XO, 2, 1, 91),
1195 static struct clk_rcg2 tsif_ref_clk_src = {
1199 .parent_map = gcc_xo_gpll0_map,
1200 .freq_tbl = ftbl_gcc_tsif_ref_clk,
1201 .clkr.hw.init = &(struct clk_init_data){
1202 .name = "tsif_ref_clk_src",
1203 .parent_names = gcc_xo_gpll0,
1205 .ops = &clk_rcg2_ops,
1209 static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = {
1210 F(60000000, P_GPLL0, 10, 0, 0),
1214 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1217 .parent_map = gcc_xo_gpll0_map,
1218 .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk,
1219 .clkr.hw.init = &(struct clk_init_data){
1220 .name = "usb30_mock_utmi_clk_src",
1221 .parent_names = gcc_xo_gpll0,
1223 .ops = &clk_rcg2_ops,
1227 static const struct freq_tbl ftbl_gcc_usb30_sec_mock_utmi_clk[] = {
1228 F(125000000, P_GPLL0, 1, 5, 24),
1232 static struct clk_rcg2 usb30_sec_mock_utmi_clk_src = {
1235 .parent_map = gcc_xo_gpll0_map,
1236 .freq_tbl = ftbl_gcc_usb30_sec_mock_utmi_clk,
1237 .clkr.hw.init = &(struct clk_init_data){
1238 .name = "usb30_sec_mock_utmi_clk_src",
1239 .parent_names = gcc_xo_gpll0,
1241 .ops = &clk_rcg2_ops,
1245 static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
1246 F(75000000, P_GPLL0, 8, 0, 0),
1250 static struct clk_rcg2 usb_hs_system_clk_src = {
1253 .parent_map = gcc_xo_gpll0_map,
1254 .freq_tbl = ftbl_gcc_usb_hs_system_clk,
1255 .clkr.hw.init = &(struct clk_init_data){
1256 .name = "usb_hs_system_clk_src",
1257 .parent_names = gcc_xo_gpll0,
1259 .ops = &clk_rcg2_ops,
1263 static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = {
1264 F(480000000, P_GPLL1, 1, 0, 0),
1268 static const struct parent_map usb_hsic_clk_src_map[] = {
1273 static struct clk_rcg2 usb_hsic_clk_src = {
1276 .parent_map = usb_hsic_clk_src_map,
1277 .freq_tbl = ftbl_gcc_usb_hsic_clk,
1278 .clkr.hw.init = &(struct clk_init_data){
1279 .name = "usb_hsic_clk_src",
1280 .parent_names = (const char *[]){
1285 .ops = &clk_rcg2_ops,
1289 static const struct freq_tbl ftbl_gcc_usb_hsic_ahb_clk_src[] = {
1290 F(60000000, P_GPLL1, 8, 0, 0),
1294 static struct clk_rcg2 usb_hsic_ahb_clk_src = {
1298 .parent_map = usb_hsic_clk_src_map,
1299 .freq_tbl = ftbl_gcc_usb_hsic_ahb_clk_src,
1300 .clkr.hw.init = &(struct clk_init_data){
1301 .name = "usb_hsic_ahb_clk_src",
1302 .parent_names = (const char *[]){
1307 .ops = &clk_rcg2_ops,
1311 static const struct freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = {
1312 F(9600000, P_XO, 2, 0, 0),
1316 static struct clk_rcg2 usb_hsic_io_cal_clk_src = {
1319 .parent_map = gcc_xo_gpll0_map,
1320 .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk,
1321 .clkr.hw.init = &(struct clk_init_data){
1322 .name = "usb_hsic_io_cal_clk_src",
1323 .parent_names = gcc_xo_gpll0,
1325 .ops = &clk_rcg2_ops,
1329 static struct clk_branch gcc_usb_hsic_mock_utmi_clk = {
1332 .enable_reg = 0x1f14,
1333 .enable_mask = BIT(0),
1334 .hw.init = &(struct clk_init_data){
1335 .name = "gcc_usb_hsic_mock_utmi_clk",
1336 .parent_names = (const char *[]){
1337 "usb_hsic_mock_utmi_clk_src",
1340 .flags = CLK_SET_RATE_PARENT,
1341 .ops = &clk_branch2_ops,
1346 static const struct freq_tbl ftbl_gcc_usb_hsic_mock_utmi_clk[] = {
1347 F(60000000, P_GPLL0, 10, 0, 0),
1351 static struct clk_rcg2 usb_hsic_mock_utmi_clk_src = {
1354 .parent_map = gcc_xo_gpll0_map,
1355 .freq_tbl = ftbl_gcc_usb_hsic_mock_utmi_clk,
1356 .clkr.hw.init = &(struct clk_init_data){
1357 .name = "usb_hsic_mock_utmi_clk_src",
1358 .parent_names = gcc_xo_gpll0,
1360 .ops = &clk_rcg2_ops,
1364 static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk[] = {
1365 F(75000000, P_GPLL0, 8, 0, 0),
1369 static struct clk_rcg2 usb_hsic_system_clk_src = {
1372 .parent_map = gcc_xo_gpll0_map,
1373 .freq_tbl = ftbl_gcc_usb_hsic_system_clk,
1374 .clkr.hw.init = &(struct clk_init_data){
1375 .name = "usb_hsic_system_clk_src",
1376 .parent_names = gcc_xo_gpll0,
1378 .ops = &clk_rcg2_ops,
1382 static struct clk_branch gcc_bam_dma_ahb_clk = {
1384 .halt_check = BRANCH_HALT_VOTED,
1386 .enable_reg = 0x1484,
1387 .enable_mask = BIT(12),
1388 .hw.init = &(struct clk_init_data){
1389 .name = "gcc_bam_dma_ahb_clk",
1390 .parent_names = (const char *[]){
1391 "periph_noc_clk_src",
1394 .ops = &clk_branch2_ops,
1399 static struct clk_branch gcc_blsp1_ahb_clk = {
1401 .halt_check = BRANCH_HALT_VOTED,
1403 .enable_reg = 0x1484,
1404 .enable_mask = BIT(17),
1405 .hw.init = &(struct clk_init_data){
1406 .name = "gcc_blsp1_ahb_clk",
1407 .parent_names = (const char *[]){
1408 "periph_noc_clk_src",
1411 .ops = &clk_branch2_ops,
1416 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1419 .enable_reg = 0x0648,
1420 .enable_mask = BIT(0),
1421 .hw.init = &(struct clk_init_data){
1422 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1423 .parent_names = (const char *[]){
1424 "blsp1_qup1_i2c_apps_clk_src",
1427 .flags = CLK_SET_RATE_PARENT,
1428 .ops = &clk_branch2_ops,
1433 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1436 .enable_reg = 0x0644,
1437 .enable_mask = BIT(0),
1438 .hw.init = &(struct clk_init_data){
1439 .name = "gcc_blsp1_qup1_spi_apps_clk",
1440 .parent_names = (const char *[]){
1441 "blsp1_qup1_spi_apps_clk_src",
1444 .flags = CLK_SET_RATE_PARENT,
1445 .ops = &clk_branch2_ops,
1450 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1453 .enable_reg = 0x06c8,
1454 .enable_mask = BIT(0),
1455 .hw.init = &(struct clk_init_data){
1456 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1457 .parent_names = (const char *[]){
1458 "blsp1_qup2_i2c_apps_clk_src",
1461 .flags = CLK_SET_RATE_PARENT,
1462 .ops = &clk_branch2_ops,
1467 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1470 .enable_reg = 0x06c4,
1471 .enable_mask = BIT(0),
1472 .hw.init = &(struct clk_init_data){
1473 .name = "gcc_blsp1_qup2_spi_apps_clk",
1474 .parent_names = (const char *[]){
1475 "blsp1_qup2_spi_apps_clk_src",
1478 .flags = CLK_SET_RATE_PARENT,
1479 .ops = &clk_branch2_ops,
1484 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1487 .enable_reg = 0x0748,
1488 .enable_mask = BIT(0),
1489 .hw.init = &(struct clk_init_data){
1490 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1491 .parent_names = (const char *[]){
1492 "blsp1_qup3_i2c_apps_clk_src",
1495 .flags = CLK_SET_RATE_PARENT,
1496 .ops = &clk_branch2_ops,
1501 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1504 .enable_reg = 0x0744,
1505 .enable_mask = BIT(0),
1506 .hw.init = &(struct clk_init_data){
1507 .name = "gcc_blsp1_qup3_spi_apps_clk",
1508 .parent_names = (const char *[]){
1509 "blsp1_qup3_spi_apps_clk_src",
1512 .flags = CLK_SET_RATE_PARENT,
1513 .ops = &clk_branch2_ops,
1518 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1521 .enable_reg = 0x07c8,
1522 .enable_mask = BIT(0),
1523 .hw.init = &(struct clk_init_data){
1524 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1525 .parent_names = (const char *[]){
1526 "blsp1_qup4_i2c_apps_clk_src",
1529 .flags = CLK_SET_RATE_PARENT,
1530 .ops = &clk_branch2_ops,
1535 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1538 .enable_reg = 0x07c4,
1539 .enable_mask = BIT(0),
1540 .hw.init = &(struct clk_init_data){
1541 .name = "gcc_blsp1_qup4_spi_apps_clk",
1542 .parent_names = (const char *[]){
1543 "blsp1_qup4_spi_apps_clk_src",
1546 .flags = CLK_SET_RATE_PARENT,
1547 .ops = &clk_branch2_ops,
1552 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1555 .enable_reg = 0x0848,
1556 .enable_mask = BIT(0),
1557 .hw.init = &(struct clk_init_data){
1558 .name = "gcc_blsp1_qup5_i2c_apps_clk",
1559 .parent_names = (const char *[]){
1560 "blsp1_qup5_i2c_apps_clk_src",
1563 .flags = CLK_SET_RATE_PARENT,
1564 .ops = &clk_branch2_ops,
1569 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1572 .enable_reg = 0x0844,
1573 .enable_mask = BIT(0),
1574 .hw.init = &(struct clk_init_data){
1575 .name = "gcc_blsp1_qup5_spi_apps_clk",
1576 .parent_names = (const char *[]){
1577 "blsp1_qup5_spi_apps_clk_src",
1580 .flags = CLK_SET_RATE_PARENT,
1581 .ops = &clk_branch2_ops,
1586 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1589 .enable_reg = 0x08c8,
1590 .enable_mask = BIT(0),
1591 .hw.init = &(struct clk_init_data){
1592 .name = "gcc_blsp1_qup6_i2c_apps_clk",
1593 .parent_names = (const char *[]){
1594 "blsp1_qup6_i2c_apps_clk_src",
1597 .flags = CLK_SET_RATE_PARENT,
1598 .ops = &clk_branch2_ops,
1603 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1606 .enable_reg = 0x08c4,
1607 .enable_mask = BIT(0),
1608 .hw.init = &(struct clk_init_data){
1609 .name = "gcc_blsp1_qup6_spi_apps_clk",
1610 .parent_names = (const char *[]){
1611 "blsp1_qup6_spi_apps_clk_src",
1614 .flags = CLK_SET_RATE_PARENT,
1615 .ops = &clk_branch2_ops,
1620 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1623 .enable_reg = 0x0684,
1624 .enable_mask = BIT(0),
1625 .hw.init = &(struct clk_init_data){
1626 .name = "gcc_blsp1_uart1_apps_clk",
1627 .parent_names = (const char *[]){
1628 "blsp1_uart1_apps_clk_src",
1631 .flags = CLK_SET_RATE_PARENT,
1632 .ops = &clk_branch2_ops,
1637 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1640 .enable_reg = 0x0704,
1641 .enable_mask = BIT(0),
1642 .hw.init = &(struct clk_init_data){
1643 .name = "gcc_blsp1_uart2_apps_clk",
1644 .parent_names = (const char *[]){
1645 "blsp1_uart2_apps_clk_src",
1648 .flags = CLK_SET_RATE_PARENT,
1649 .ops = &clk_branch2_ops,
1654 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1657 .enable_reg = 0x0784,
1658 .enable_mask = BIT(0),
1659 .hw.init = &(struct clk_init_data){
1660 .name = "gcc_blsp1_uart3_apps_clk",
1661 .parent_names = (const char *[]){
1662 "blsp1_uart3_apps_clk_src",
1665 .flags = CLK_SET_RATE_PARENT,
1666 .ops = &clk_branch2_ops,
1671 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1674 .enable_reg = 0x0804,
1675 .enable_mask = BIT(0),
1676 .hw.init = &(struct clk_init_data){
1677 .name = "gcc_blsp1_uart4_apps_clk",
1678 .parent_names = (const char *[]){
1679 "blsp1_uart4_apps_clk_src",
1682 .flags = CLK_SET_RATE_PARENT,
1683 .ops = &clk_branch2_ops,
1688 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1691 .enable_reg = 0x0884,
1692 .enable_mask = BIT(0),
1693 .hw.init = &(struct clk_init_data){
1694 .name = "gcc_blsp1_uart5_apps_clk",
1695 .parent_names = (const char *[]){
1696 "blsp1_uart5_apps_clk_src",
1699 .flags = CLK_SET_RATE_PARENT,
1700 .ops = &clk_branch2_ops,
1705 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1708 .enable_reg = 0x0904,
1709 .enable_mask = BIT(0),
1710 .hw.init = &(struct clk_init_data){
1711 .name = "gcc_blsp1_uart6_apps_clk",
1712 .parent_names = (const char *[]){
1713 "blsp1_uart6_apps_clk_src",
1716 .flags = CLK_SET_RATE_PARENT,
1717 .ops = &clk_branch2_ops,
1722 static struct clk_branch gcc_blsp2_ahb_clk = {
1724 .halt_check = BRANCH_HALT_VOTED,
1726 .enable_reg = 0x1484,
1727 .enable_mask = BIT(15),
1728 .hw.init = &(struct clk_init_data){
1729 .name = "gcc_blsp2_ahb_clk",
1730 .parent_names = (const char *[]){
1731 "periph_noc_clk_src",
1734 .ops = &clk_branch2_ops,
1739 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1742 .enable_reg = 0x0988,
1743 .enable_mask = BIT(0),
1744 .hw.init = &(struct clk_init_data){
1745 .name = "gcc_blsp2_qup1_i2c_apps_clk",
1746 .parent_names = (const char *[]){
1747 "blsp2_qup1_i2c_apps_clk_src",
1750 .flags = CLK_SET_RATE_PARENT,
1751 .ops = &clk_branch2_ops,
1756 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1759 .enable_reg = 0x0984,
1760 .enable_mask = BIT(0),
1761 .hw.init = &(struct clk_init_data){
1762 .name = "gcc_blsp2_qup1_spi_apps_clk",
1763 .parent_names = (const char *[]){
1764 "blsp2_qup1_spi_apps_clk_src",
1767 .flags = CLK_SET_RATE_PARENT,
1768 .ops = &clk_branch2_ops,
1773 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1776 .enable_reg = 0x0a08,
1777 .enable_mask = BIT(0),
1778 .hw.init = &(struct clk_init_data){
1779 .name = "gcc_blsp2_qup2_i2c_apps_clk",
1780 .parent_names = (const char *[]){
1781 "blsp2_qup2_i2c_apps_clk_src",
1784 .flags = CLK_SET_RATE_PARENT,
1785 .ops = &clk_branch2_ops,
1790 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1793 .enable_reg = 0x0a04,
1794 .enable_mask = BIT(0),
1795 .hw.init = &(struct clk_init_data){
1796 .name = "gcc_blsp2_qup2_spi_apps_clk",
1797 .parent_names = (const char *[]){
1798 "blsp2_qup2_spi_apps_clk_src",
1801 .flags = CLK_SET_RATE_PARENT,
1802 .ops = &clk_branch2_ops,
1807 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1810 .enable_reg = 0x0a88,
1811 .enable_mask = BIT(0),
1812 .hw.init = &(struct clk_init_data){
1813 .name = "gcc_blsp2_qup3_i2c_apps_clk",
1814 .parent_names = (const char *[]){
1815 "blsp2_qup3_i2c_apps_clk_src",
1818 .flags = CLK_SET_RATE_PARENT,
1819 .ops = &clk_branch2_ops,
1824 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1827 .enable_reg = 0x0a84,
1828 .enable_mask = BIT(0),
1829 .hw.init = &(struct clk_init_data){
1830 .name = "gcc_blsp2_qup3_spi_apps_clk",
1831 .parent_names = (const char *[]){
1832 "blsp2_qup3_spi_apps_clk_src",
1835 .flags = CLK_SET_RATE_PARENT,
1836 .ops = &clk_branch2_ops,
1841 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1844 .enable_reg = 0x0b08,
1845 .enable_mask = BIT(0),
1846 .hw.init = &(struct clk_init_data){
1847 .name = "gcc_blsp2_qup4_i2c_apps_clk",
1848 .parent_names = (const char *[]){
1849 "blsp2_qup4_i2c_apps_clk_src",
1852 .flags = CLK_SET_RATE_PARENT,
1853 .ops = &clk_branch2_ops,
1858 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1861 .enable_reg = 0x0b04,
1862 .enable_mask = BIT(0),
1863 .hw.init = &(struct clk_init_data){
1864 .name = "gcc_blsp2_qup4_spi_apps_clk",
1865 .parent_names = (const char *[]){
1866 "blsp2_qup4_spi_apps_clk_src",
1869 .flags = CLK_SET_RATE_PARENT,
1870 .ops = &clk_branch2_ops,
1875 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1878 .enable_reg = 0x0b88,
1879 .enable_mask = BIT(0),
1880 .hw.init = &(struct clk_init_data){
1881 .name = "gcc_blsp2_qup5_i2c_apps_clk",
1882 .parent_names = (const char *[]){
1883 "blsp2_qup5_i2c_apps_clk_src",
1886 .flags = CLK_SET_RATE_PARENT,
1887 .ops = &clk_branch2_ops,
1892 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1895 .enable_reg = 0x0b84,
1896 .enable_mask = BIT(0),
1897 .hw.init = &(struct clk_init_data){
1898 .name = "gcc_blsp2_qup5_spi_apps_clk",
1899 .parent_names = (const char *[]){
1900 "blsp2_qup5_spi_apps_clk_src",
1903 .flags = CLK_SET_RATE_PARENT,
1904 .ops = &clk_branch2_ops,
1909 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1912 .enable_reg = 0x0c08,
1913 .enable_mask = BIT(0),
1914 .hw.init = &(struct clk_init_data){
1915 .name = "gcc_blsp2_qup6_i2c_apps_clk",
1916 .parent_names = (const char *[]){
1917 "blsp2_qup6_i2c_apps_clk_src",
1920 .flags = CLK_SET_RATE_PARENT,
1921 .ops = &clk_branch2_ops,
1926 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1929 .enable_reg = 0x0c04,
1930 .enable_mask = BIT(0),
1931 .hw.init = &(struct clk_init_data){
1932 .name = "gcc_blsp2_qup6_spi_apps_clk",
1933 .parent_names = (const char *[]){
1934 "blsp2_qup6_spi_apps_clk_src",
1937 .flags = CLK_SET_RATE_PARENT,
1938 .ops = &clk_branch2_ops,
1943 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1946 .enable_reg = 0x09c4,
1947 .enable_mask = BIT(0),
1948 .hw.init = &(struct clk_init_data){
1949 .name = "gcc_blsp2_uart1_apps_clk",
1950 .parent_names = (const char *[]){
1951 "blsp2_uart1_apps_clk_src",
1954 .flags = CLK_SET_RATE_PARENT,
1955 .ops = &clk_branch2_ops,
1960 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1963 .enable_reg = 0x0a44,
1964 .enable_mask = BIT(0),
1965 .hw.init = &(struct clk_init_data){
1966 .name = "gcc_blsp2_uart2_apps_clk",
1967 .parent_names = (const char *[]){
1968 "blsp2_uart2_apps_clk_src",
1971 .flags = CLK_SET_RATE_PARENT,
1972 .ops = &clk_branch2_ops,
1977 static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1980 .enable_reg = 0x0ac4,
1981 .enable_mask = BIT(0),
1982 .hw.init = &(struct clk_init_data){
1983 .name = "gcc_blsp2_uart3_apps_clk",
1984 .parent_names = (const char *[]){
1985 "blsp2_uart3_apps_clk_src",
1988 .flags = CLK_SET_RATE_PARENT,
1989 .ops = &clk_branch2_ops,
1994 static struct clk_branch gcc_blsp2_uart4_apps_clk = {
1997 .enable_reg = 0x0b44,
1998 .enable_mask = BIT(0),
1999 .hw.init = &(struct clk_init_data){
2000 .name = "gcc_blsp2_uart4_apps_clk",
2001 .parent_names = (const char *[]){
2002 "blsp2_uart4_apps_clk_src",
2005 .flags = CLK_SET_RATE_PARENT,
2006 .ops = &clk_branch2_ops,
2011 static struct clk_branch gcc_blsp2_uart5_apps_clk = {
2014 .enable_reg = 0x0bc4,
2015 .enable_mask = BIT(0),
2016 .hw.init = &(struct clk_init_data){
2017 .name = "gcc_blsp2_uart5_apps_clk",
2018 .parent_names = (const char *[]){
2019 "blsp2_uart5_apps_clk_src",
2022 .flags = CLK_SET_RATE_PARENT,
2023 .ops = &clk_branch2_ops,
2028 static struct clk_branch gcc_blsp2_uart6_apps_clk = {
2031 .enable_reg = 0x0c44,
2032 .enable_mask = BIT(0),
2033 .hw.init = &(struct clk_init_data){
2034 .name = "gcc_blsp2_uart6_apps_clk",
2035 .parent_names = (const char *[]){
2036 "blsp2_uart6_apps_clk_src",
2039 .flags = CLK_SET_RATE_PARENT,
2040 .ops = &clk_branch2_ops,
2045 static struct clk_branch gcc_boot_rom_ahb_clk = {
2047 .halt_check = BRANCH_HALT_VOTED,
2049 .enable_reg = 0x1484,
2050 .enable_mask = BIT(10),
2051 .hw.init = &(struct clk_init_data){
2052 .name = "gcc_boot_rom_ahb_clk",
2053 .parent_names = (const char *[]){
2054 "config_noc_clk_src",
2057 .ops = &clk_branch2_ops,
2062 static struct clk_branch gcc_ce1_ahb_clk = {
2064 .halt_check = BRANCH_HALT_VOTED,
2066 .enable_reg = 0x1484,
2067 .enable_mask = BIT(3),
2068 .hw.init = &(struct clk_init_data){
2069 .name = "gcc_ce1_ahb_clk",
2070 .parent_names = (const char *[]){
2071 "config_noc_clk_src",
2074 .ops = &clk_branch2_ops,
2079 static struct clk_branch gcc_ce1_axi_clk = {
2081 .halt_check = BRANCH_HALT_VOTED,
2083 .enable_reg = 0x1484,
2084 .enable_mask = BIT(4),
2085 .hw.init = &(struct clk_init_data){
2086 .name = "gcc_ce1_axi_clk",
2087 .parent_names = (const char *[]){
2088 "system_noc_clk_src",
2091 .ops = &clk_branch2_ops,
2096 static struct clk_branch gcc_ce1_clk = {
2098 .halt_check = BRANCH_HALT_VOTED,
2100 .enable_reg = 0x1484,
2101 .enable_mask = BIT(5),
2102 .hw.init = &(struct clk_init_data){
2103 .name = "gcc_ce1_clk",
2104 .parent_names = (const char *[]){
2108 .flags = CLK_SET_RATE_PARENT,
2109 .ops = &clk_branch2_ops,
2114 static struct clk_branch gcc_ce2_ahb_clk = {
2116 .halt_check = BRANCH_HALT_VOTED,
2118 .enable_reg = 0x1484,
2119 .enable_mask = BIT(0),
2120 .hw.init = &(struct clk_init_data){
2121 .name = "gcc_ce2_ahb_clk",
2122 .parent_names = (const char *[]){
2123 "config_noc_clk_src",
2126 .ops = &clk_branch2_ops,
2131 static struct clk_branch gcc_ce2_axi_clk = {
2133 .halt_check = BRANCH_HALT_VOTED,
2135 .enable_reg = 0x1484,
2136 .enable_mask = BIT(1),
2137 .hw.init = &(struct clk_init_data){
2138 .name = "gcc_ce2_axi_clk",
2139 .parent_names = (const char *[]){
2140 "system_noc_clk_src",
2143 .ops = &clk_branch2_ops,
2148 static struct clk_branch gcc_ce2_clk = {
2150 .halt_check = BRANCH_HALT_VOTED,
2152 .enable_reg = 0x1484,
2153 .enable_mask = BIT(2),
2154 .hw.init = &(struct clk_init_data){
2155 .name = "gcc_ce2_clk",
2156 .parent_names = (const char *[]){
2160 .flags = CLK_SET_RATE_PARENT,
2161 .ops = &clk_branch2_ops,
2166 static struct clk_branch gcc_ce3_ahb_clk = {
2168 .halt_check = BRANCH_HALT_VOTED,
2170 .enable_reg = 0x1d0c,
2171 .enable_mask = BIT(0),
2172 .hw.init = &(struct clk_init_data){
2173 .name = "gcc_ce3_ahb_clk",
2174 .parent_names = (const char *[]){
2175 "config_noc_clk_src",
2178 .ops = &clk_branch2_ops,
2183 static struct clk_branch gcc_ce3_axi_clk = {
2185 .halt_check = BRANCH_HALT_VOTED,
2187 .enable_reg = 0x1d08,
2188 .enable_mask = BIT(0),
2189 .hw.init = &(struct clk_init_data){
2190 .name = "gcc_ce3_axi_clk",
2191 .parent_names = (const char *[]){
2192 "system_noc_clk_src",
2195 .ops = &clk_branch2_ops,
2200 static struct clk_branch gcc_ce3_clk = {
2202 .halt_check = BRANCH_HALT_VOTED,
2204 .enable_reg = 0x1d04,
2205 .enable_mask = BIT(0),
2206 .hw.init = &(struct clk_init_data){
2207 .name = "gcc_ce3_clk",
2208 .parent_names = (const char *[]){
2212 .flags = CLK_SET_RATE_PARENT,
2213 .ops = &clk_branch2_ops,
2218 static struct clk_branch gcc_gp1_clk = {
2221 .enable_reg = 0x1900,
2222 .enable_mask = BIT(0),
2223 .hw.init = &(struct clk_init_data){
2224 .name = "gcc_gp1_clk",
2225 .parent_names = (const char *[]){
2229 .flags = CLK_SET_RATE_PARENT,
2230 .ops = &clk_branch2_ops,
2235 static struct clk_branch gcc_gp2_clk = {
2238 .enable_reg = 0x1940,
2239 .enable_mask = BIT(0),
2240 .hw.init = &(struct clk_init_data){
2241 .name = "gcc_gp2_clk",
2242 .parent_names = (const char *[]){
2246 .flags = CLK_SET_RATE_PARENT,
2247 .ops = &clk_branch2_ops,
2252 static struct clk_branch gcc_gp3_clk = {
2255 .enable_reg = 0x1980,
2256 .enable_mask = BIT(0),
2257 .hw.init = &(struct clk_init_data){
2258 .name = "gcc_gp3_clk",
2259 .parent_names = (const char *[]){
2263 .flags = CLK_SET_RATE_PARENT,
2264 .ops = &clk_branch2_ops,
2269 static struct clk_branch gcc_ocmem_noc_cfg_ahb_clk = {
2272 .enable_reg = 0x0248,
2273 .enable_mask = BIT(0),
2274 .hw.init = &(struct clk_init_data){
2275 .name = "gcc_ocmem_noc_cfg_ahb_clk",
2276 .parent_names = (const char *[]){
2277 "config_noc_clk_src",
2280 .ops = &clk_branch2_ops,
2285 static struct clk_branch gcc_pcie_0_aux_clk = {
2288 .enable_reg = 0x1b10,
2289 .enable_mask = BIT(0),
2290 .hw.init = &(struct clk_init_data){
2291 .name = "gcc_pcie_0_aux_clk",
2292 .parent_names = (const char *[]){
2293 "pcie_0_aux_clk_src",
2296 .flags = CLK_SET_RATE_PARENT,
2297 .ops = &clk_branch2_ops,
2302 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2305 .enable_reg = 0x1b0c,
2306 .enable_mask = BIT(0),
2307 .hw.init = &(struct clk_init_data){
2308 .name = "gcc_pcie_0_cfg_ahb_clk",
2309 .parent_names = (const char *[]){
2310 "config_noc_clk_src",
2313 .flags = CLK_SET_RATE_PARENT,
2314 .ops = &clk_branch2_ops,
2319 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2322 .enable_reg = 0x1b08,
2323 .enable_mask = BIT(0),
2324 .hw.init = &(struct clk_init_data){
2325 .name = "gcc_pcie_0_mstr_axi_clk",
2326 .parent_names = (const char *[]){
2327 "config_noc_clk_src",
2330 .flags = CLK_SET_RATE_PARENT,
2331 .ops = &clk_branch2_ops,
2336 static struct clk_branch gcc_pcie_0_pipe_clk = {
2339 .enable_reg = 0x1b14,
2340 .enable_mask = BIT(0),
2341 .hw.init = &(struct clk_init_data){
2342 .name = "gcc_pcie_0_pipe_clk",
2343 .parent_names = (const char *[]){
2344 "pcie_0_pipe_clk_src",
2347 .flags = CLK_SET_RATE_PARENT,
2348 .ops = &clk_branch2_ops,
2353 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2356 .enable_reg = 0x1b04,
2357 .enable_mask = BIT(0),
2358 .hw.init = &(struct clk_init_data){
2359 .name = "gcc_pcie_0_slv_axi_clk",
2360 .parent_names = (const char *[]){
2361 "config_noc_clk_src",
2364 .flags = CLK_SET_RATE_PARENT,
2365 .ops = &clk_branch2_ops,
2370 static struct clk_branch gcc_pcie_1_aux_clk = {
2373 .enable_reg = 0x1b90,
2374 .enable_mask = BIT(0),
2375 .hw.init = &(struct clk_init_data){
2376 .name = "gcc_pcie_1_aux_clk",
2377 .parent_names = (const char *[]){
2378 "pcie_1_aux_clk_src",
2381 .flags = CLK_SET_RATE_PARENT,
2382 .ops = &clk_branch2_ops,
2387 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
2390 .enable_reg = 0x1b8c,
2391 .enable_mask = BIT(0),
2392 .hw.init = &(struct clk_init_data){
2393 .name = "gcc_pcie_1_cfg_ahb_clk",
2394 .parent_names = (const char *[]){
2395 "config_noc_clk_src",
2398 .flags = CLK_SET_RATE_PARENT,
2399 .ops = &clk_branch2_ops,
2404 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
2407 .enable_reg = 0x1b88,
2408 .enable_mask = BIT(0),
2409 .hw.init = &(struct clk_init_data){
2410 .name = "gcc_pcie_1_mstr_axi_clk",
2411 .parent_names = (const char *[]){
2412 "config_noc_clk_src",
2415 .flags = CLK_SET_RATE_PARENT,
2416 .ops = &clk_branch2_ops,
2421 static struct clk_branch gcc_pcie_1_pipe_clk = {
2424 .enable_reg = 0x1b94,
2425 .enable_mask = BIT(0),
2426 .hw.init = &(struct clk_init_data){
2427 .name = "gcc_pcie_1_pipe_clk",
2428 .parent_names = (const char *[]){
2429 "pcie_1_pipe_clk_src",
2432 .flags = CLK_SET_RATE_PARENT,
2433 .ops = &clk_branch2_ops,
2438 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
2441 .enable_reg = 0x1b84,
2442 .enable_mask = BIT(0),
2443 .hw.init = &(struct clk_init_data){
2444 .name = "gcc_pcie_1_slv_axi_clk",
2445 .parent_names = (const char *[]){
2446 "config_noc_clk_src",
2449 .flags = CLK_SET_RATE_PARENT,
2450 .ops = &clk_branch2_ops,
2455 static struct clk_branch gcc_pdm2_clk = {
2458 .enable_reg = 0x0ccc,
2459 .enable_mask = BIT(0),
2460 .hw.init = &(struct clk_init_data){
2461 .name = "gcc_pdm2_clk",
2462 .parent_names = (const char *[]){
2466 .flags = CLK_SET_RATE_PARENT,
2467 .ops = &clk_branch2_ops,
2472 static struct clk_branch gcc_pdm_ahb_clk = {
2475 .enable_reg = 0x0cc4,
2476 .enable_mask = BIT(0),
2477 .hw.init = &(struct clk_init_data){
2478 .name = "gcc_pdm_ahb_clk",
2479 .parent_names = (const char *[]){
2480 "periph_noc_clk_src",
2483 .ops = &clk_branch2_ops,
2488 static struct clk_branch gcc_periph_noc_usb_hsic_ahb_clk = {
2491 .enable_reg = 0x01a4,
2492 .enable_mask = BIT(0),
2493 .hw.init = &(struct clk_init_data){
2494 .name = "gcc_periph_noc_usb_hsic_ahb_clk",
2495 .parent_names = (const char *[]){
2496 "usb_hsic_ahb_clk_src",
2499 .flags = CLK_SET_RATE_PARENT,
2500 .ops = &clk_branch2_ops,
2505 static struct clk_branch gcc_prng_ahb_clk = {
2507 .halt_check = BRANCH_HALT_VOTED,
2509 .enable_reg = 0x1484,
2510 .enable_mask = BIT(13),
2511 .hw.init = &(struct clk_init_data){
2512 .name = "gcc_prng_ahb_clk",
2513 .parent_names = (const char *[]){
2514 "periph_noc_clk_src",
2517 .ops = &clk_branch2_ops,
2522 static struct clk_branch gcc_sata_asic0_clk = {
2525 .enable_reg = 0x1c54,
2526 .enable_mask = BIT(0),
2527 .hw.init = &(struct clk_init_data){
2528 .name = "gcc_sata_asic0_clk",
2529 .parent_names = (const char *[]){
2530 "sata_asic0_clk_src",
2533 .flags = CLK_SET_RATE_PARENT,
2534 .ops = &clk_branch2_ops,
2539 static struct clk_branch gcc_sata_axi_clk = {
2542 .enable_reg = 0x1c44,
2543 .enable_mask = BIT(0),
2544 .hw.init = &(struct clk_init_data){
2545 .name = "gcc_sata_axi_clk",
2546 .parent_names = (const char *[]){
2547 "config_noc_clk_src",
2550 .flags = CLK_SET_RATE_PARENT,
2551 .ops = &clk_branch2_ops,
2556 static struct clk_branch gcc_sata_cfg_ahb_clk = {
2559 .enable_reg = 0x1c48,
2560 .enable_mask = BIT(0),
2561 .hw.init = &(struct clk_init_data){
2562 .name = "gcc_sata_cfg_ahb_clk",
2563 .parent_names = (const char *[]){
2564 "config_noc_clk_src",
2567 .flags = CLK_SET_RATE_PARENT,
2568 .ops = &clk_branch2_ops,
2573 static struct clk_branch gcc_sata_pmalive_clk = {
2576 .enable_reg = 0x1c50,
2577 .enable_mask = BIT(0),
2578 .hw.init = &(struct clk_init_data){
2579 .name = "gcc_sata_pmalive_clk",
2580 .parent_names = (const char *[]){
2581 "sata_pmalive_clk_src",
2584 .flags = CLK_SET_RATE_PARENT,
2585 .ops = &clk_branch2_ops,
2590 static struct clk_branch gcc_sata_rx_clk = {
2593 .enable_reg = 0x1c58,
2594 .enable_mask = BIT(0),
2595 .hw.init = &(struct clk_init_data){
2596 .name = "gcc_sata_rx_clk",
2597 .parent_names = (const char *[]){
2601 .flags = CLK_SET_RATE_PARENT,
2602 .ops = &clk_branch2_ops,
2607 static struct clk_branch gcc_sata_rx_oob_clk = {
2610 .enable_reg = 0x1c4c,
2611 .enable_mask = BIT(0),
2612 .hw.init = &(struct clk_init_data){
2613 .name = "gcc_sata_rx_oob_clk",
2614 .parent_names = (const char *[]){
2615 "sata_rx_oob_clk_src",
2618 .flags = CLK_SET_RATE_PARENT,
2619 .ops = &clk_branch2_ops,
2624 static struct clk_branch gcc_sdcc1_ahb_clk = {
2627 .enable_reg = 0x04c8,
2628 .enable_mask = BIT(0),
2629 .hw.init = &(struct clk_init_data){
2630 .name = "gcc_sdcc1_ahb_clk",
2631 .parent_names = (const char *[]){
2632 "periph_noc_clk_src",
2635 .ops = &clk_branch2_ops,
2640 static struct clk_branch gcc_sdcc1_apps_clk = {
2643 .enable_reg = 0x04c4,
2644 .enable_mask = BIT(0),
2645 .hw.init = &(struct clk_init_data){
2646 .name = "gcc_sdcc1_apps_clk",
2647 .parent_names = (const char *[]){
2648 "sdcc1_apps_clk_src",
2651 .flags = CLK_SET_RATE_PARENT,
2652 .ops = &clk_branch2_ops,
2657 static struct clk_branch gcc_sdcc1_cdccal_ff_clk = {
2660 .enable_reg = 0x04e8,
2661 .enable_mask = BIT(0),
2662 .hw.init = &(struct clk_init_data){
2663 .name = "gcc_sdcc1_cdccal_ff_clk",
2664 .parent_names = (const char *[]){
2668 .ops = &clk_branch2_ops,
2673 static struct clk_branch gcc_sdcc1_cdccal_sleep_clk = {
2676 .enable_reg = 0x04e4,
2677 .enable_mask = BIT(0),
2678 .hw.init = &(struct clk_init_data){
2679 .name = "gcc_sdcc1_cdccal_sleep_clk",
2680 .parent_names = (const char *[]){
2684 .ops = &clk_branch2_ops,
2689 static struct clk_branch gcc_sdcc2_ahb_clk = {
2692 .enable_reg = 0x0508,
2693 .enable_mask = BIT(0),
2694 .hw.init = &(struct clk_init_data){
2695 .name = "gcc_sdcc2_ahb_clk",
2696 .parent_names = (const char *[]){
2697 "periph_noc_clk_src",
2700 .ops = &clk_branch2_ops,
2705 static struct clk_branch gcc_sdcc2_apps_clk = {
2708 .enable_reg = 0x0504,
2709 .enable_mask = BIT(0),
2710 .hw.init = &(struct clk_init_data){
2711 .name = "gcc_sdcc2_apps_clk",
2712 .parent_names = (const char *[]){
2713 "sdcc2_apps_clk_src",
2716 .flags = CLK_SET_RATE_PARENT,
2717 .ops = &clk_branch2_ops,
2722 static struct clk_branch gcc_sdcc3_ahb_clk = {
2725 .enable_reg = 0x0548,
2726 .enable_mask = BIT(0),
2727 .hw.init = &(struct clk_init_data){
2728 .name = "gcc_sdcc3_ahb_clk",
2729 .parent_names = (const char *[]){
2730 "periph_noc_clk_src",
2733 .ops = &clk_branch2_ops,
2738 static struct clk_branch gcc_sdcc3_apps_clk = {
2741 .enable_reg = 0x0544,
2742 .enable_mask = BIT(0),
2743 .hw.init = &(struct clk_init_data){
2744 .name = "gcc_sdcc3_apps_clk",
2745 .parent_names = (const char *[]){
2746 "sdcc3_apps_clk_src",
2749 .flags = CLK_SET_RATE_PARENT,
2750 .ops = &clk_branch2_ops,
2755 static struct clk_branch gcc_sdcc4_ahb_clk = {
2758 .enable_reg = 0x0588,
2759 .enable_mask = BIT(0),
2760 .hw.init = &(struct clk_init_data){
2761 .name = "gcc_sdcc4_ahb_clk",
2762 .parent_names = (const char *[]){
2763 "periph_noc_clk_src",
2766 .ops = &clk_branch2_ops,
2771 static struct clk_branch gcc_sdcc4_apps_clk = {
2774 .enable_reg = 0x0584,
2775 .enable_mask = BIT(0),
2776 .hw.init = &(struct clk_init_data){
2777 .name = "gcc_sdcc4_apps_clk",
2778 .parent_names = (const char *[]){
2779 "sdcc4_apps_clk_src",
2782 .flags = CLK_SET_RATE_PARENT,
2783 .ops = &clk_branch2_ops,
2788 static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
2791 .enable_reg = 0x013c,
2792 .enable_mask = BIT(0),
2793 .hw.init = &(struct clk_init_data){
2794 .name = "gcc_sys_noc_ufs_axi_clk",
2795 .parent_names = (const char *[]){
2799 .flags = CLK_SET_RATE_PARENT,
2800 .ops = &clk_branch2_ops,
2805 static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
2808 .enable_reg = 0x0108,
2809 .enable_mask = BIT(0),
2810 .hw.init = &(struct clk_init_data){
2811 .name = "gcc_sys_noc_usb3_axi_clk",
2812 .parent_names = (const char *[]){
2813 "usb30_master_clk_src",
2816 .flags = CLK_SET_RATE_PARENT,
2817 .ops = &clk_branch2_ops,
2822 static struct clk_branch gcc_sys_noc_usb3_sec_axi_clk = {
2825 .enable_reg = 0x0138,
2826 .enable_mask = BIT(0),
2827 .hw.init = &(struct clk_init_data){
2828 .name = "gcc_sys_noc_usb3_sec_axi_clk",
2829 .parent_names = (const char *[]){
2830 "usb30_sec_master_clk_src",
2833 .flags = CLK_SET_RATE_PARENT,
2834 .ops = &clk_branch2_ops,
2839 static struct clk_branch gcc_tsif_ahb_clk = {
2842 .enable_reg = 0x0d84,
2843 .enable_mask = BIT(0),
2844 .hw.init = &(struct clk_init_data){
2845 .name = "gcc_tsif_ahb_clk",
2846 .parent_names = (const char *[]){
2847 "periph_noc_clk_src",
2850 .ops = &clk_branch2_ops,
2855 static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2858 .enable_reg = 0x0d8c,
2859 .enable_mask = BIT(0),
2860 .hw.init = &(struct clk_init_data){
2861 .name = "gcc_tsif_inactivity_timers_clk",
2862 .parent_names = (const char *[]){
2866 .flags = CLK_SET_RATE_PARENT,
2867 .ops = &clk_branch2_ops,
2872 static struct clk_branch gcc_tsif_ref_clk = {
2875 .enable_reg = 0x0d88,
2876 .enable_mask = BIT(0),
2877 .hw.init = &(struct clk_init_data){
2878 .name = "gcc_tsif_ref_clk",
2879 .parent_names = (const char *[]){
2883 .flags = CLK_SET_RATE_PARENT,
2884 .ops = &clk_branch2_ops,
2889 static struct clk_branch gcc_ufs_ahb_clk = {
2892 .enable_reg = 0x1d48,
2893 .enable_mask = BIT(0),
2894 .hw.init = &(struct clk_init_data){
2895 .name = "gcc_ufs_ahb_clk",
2896 .parent_names = (const char *[]){
2897 "config_noc_clk_src",
2900 .flags = CLK_SET_RATE_PARENT,
2901 .ops = &clk_branch2_ops,
2906 static struct clk_branch gcc_ufs_axi_clk = {
2909 .enable_reg = 0x1d44,
2910 .enable_mask = BIT(0),
2911 .hw.init = &(struct clk_init_data){
2912 .name = "gcc_ufs_axi_clk",
2913 .parent_names = (const char *[]){
2917 .flags = CLK_SET_RATE_PARENT,
2918 .ops = &clk_branch2_ops,
2923 static struct clk_branch gcc_ufs_rx_cfg_clk = {
2926 .enable_reg = 0x1d50,
2927 .enable_mask = BIT(0),
2928 .hw.init = &(struct clk_init_data){
2929 .name = "gcc_ufs_rx_cfg_clk",
2930 .parent_names = (const char *[]){
2934 .flags = CLK_SET_RATE_PARENT,
2935 .ops = &clk_branch2_ops,
2940 static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2943 .enable_reg = 0x1d5c,
2944 .enable_mask = BIT(0),
2945 .hw.init = &(struct clk_init_data){
2946 .name = "gcc_ufs_rx_symbol_0_clk",
2947 .parent_names = (const char *[]){
2948 "ufs_rx_symbol_0_clk_src",
2951 .flags = CLK_SET_RATE_PARENT,
2952 .ops = &clk_branch2_ops,
2957 static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2960 .enable_reg = 0x1d60,
2961 .enable_mask = BIT(0),
2962 .hw.init = &(struct clk_init_data){
2963 .name = "gcc_ufs_rx_symbol_1_clk",
2964 .parent_names = (const char *[]){
2965 "ufs_rx_symbol_1_clk_src",
2968 .flags = CLK_SET_RATE_PARENT,
2969 .ops = &clk_branch2_ops,
2974 static struct clk_branch gcc_ufs_tx_cfg_clk = {
2977 .enable_reg = 0x1d4c,
2978 .enable_mask = BIT(0),
2979 .hw.init = &(struct clk_init_data){
2980 .name = "gcc_ufs_tx_cfg_clk",
2981 .parent_names = (const char *[]){
2985 .flags = CLK_SET_RATE_PARENT,
2986 .ops = &clk_branch2_ops,
2991 static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2994 .enable_reg = 0x1d54,
2995 .enable_mask = BIT(0),
2996 .hw.init = &(struct clk_init_data){
2997 .name = "gcc_ufs_tx_symbol_0_clk",
2998 .parent_names = (const char *[]){
2999 "ufs_tx_symbol_0_clk_src",
3002 .flags = CLK_SET_RATE_PARENT,
3003 .ops = &clk_branch2_ops,
3008 static struct clk_branch gcc_ufs_tx_symbol_1_clk = {
3011 .enable_reg = 0x1d58,
3012 .enable_mask = BIT(0),
3013 .hw.init = &(struct clk_init_data){
3014 .name = "gcc_ufs_tx_symbol_1_clk",
3015 .parent_names = (const char *[]){
3016 "ufs_tx_symbol_1_clk_src",
3019 .flags = CLK_SET_RATE_PARENT,
3020 .ops = &clk_branch2_ops,
3025 static struct clk_branch gcc_usb2a_phy_sleep_clk = {
3028 .enable_reg = 0x04ac,
3029 .enable_mask = BIT(0),
3030 .hw.init = &(struct clk_init_data){
3031 .name = "gcc_usb2a_phy_sleep_clk",
3032 .parent_names = (const char *[]){
3036 .ops = &clk_branch2_ops,
3041 static struct clk_branch gcc_usb2b_phy_sleep_clk = {
3044 .enable_reg = 0x04b4,
3045 .enable_mask = BIT(0),
3046 .hw.init = &(struct clk_init_data){
3047 .name = "gcc_usb2b_phy_sleep_clk",
3048 .parent_names = (const char *[]){
3052 .ops = &clk_branch2_ops,
3057 static struct clk_branch gcc_usb30_master_clk = {
3060 .enable_reg = 0x03c8,
3061 .enable_mask = BIT(0),
3062 .hw.init = &(struct clk_init_data){
3063 .name = "gcc_usb30_master_clk",
3064 .parent_names = (const char *[]){
3065 "usb30_master_clk_src",
3068 .flags = CLK_SET_RATE_PARENT,
3069 .ops = &clk_branch2_ops,
3074 static struct clk_branch gcc_usb30_sec_master_clk = {
3077 .enable_reg = 0x1bc8,
3078 .enable_mask = BIT(0),
3079 .hw.init = &(struct clk_init_data){
3080 .name = "gcc_usb30_sec_master_clk",
3081 .parent_names = (const char *[]){
3082 "usb30_sec_master_clk_src",
3085 .flags = CLK_SET_RATE_PARENT,
3086 .ops = &clk_branch2_ops,
3091 static struct clk_branch gcc_usb30_mock_utmi_clk = {
3094 .enable_reg = 0x03d0,
3095 .enable_mask = BIT(0),
3096 .hw.init = &(struct clk_init_data){
3097 .name = "gcc_usb30_mock_utmi_clk",
3098 .parent_names = (const char *[]){
3099 "usb30_mock_utmi_clk_src",
3102 .flags = CLK_SET_RATE_PARENT,
3103 .ops = &clk_branch2_ops,
3108 static struct clk_branch gcc_usb30_sleep_clk = {
3111 .enable_reg = 0x03cc,
3112 .enable_mask = BIT(0),
3113 .hw.init = &(struct clk_init_data){
3114 .name = "gcc_usb30_sleep_clk",
3115 .parent_names = (const char *[]){
3119 .ops = &clk_branch2_ops,
3124 static struct clk_branch gcc_usb_hs_ahb_clk = {
3127 .enable_reg = 0x0488,
3128 .enable_mask = BIT(0),
3129 .hw.init = &(struct clk_init_data){
3130 .name = "gcc_usb_hs_ahb_clk",
3131 .parent_names = (const char *[]){
3132 "periph_noc_clk_src",
3135 .ops = &clk_branch2_ops,
3140 static struct clk_branch gcc_usb_hs_inactivity_timers_clk = {
3143 .enable_reg = 0x048c,
3144 .enable_mask = BIT(0),
3145 .hw.init = &(struct clk_init_data){
3146 .name = "gcc_usb_hs_inactivity_timers_clk",
3147 .parent_names = (const char *[]){
3151 .flags = CLK_SET_RATE_PARENT,
3152 .ops = &clk_branch2_ops,
3157 static struct clk_branch gcc_usb_hs_system_clk = {
3160 .enable_reg = 0x0484,
3161 .enable_mask = BIT(0),
3162 .hw.init = &(struct clk_init_data){
3163 .name = "gcc_usb_hs_system_clk",
3164 .parent_names = (const char *[]){
3165 "usb_hs_system_clk_src",
3168 .flags = CLK_SET_RATE_PARENT,
3169 .ops = &clk_branch2_ops,
3174 static struct clk_branch gcc_usb_hsic_ahb_clk = {
3177 .enable_reg = 0x0408,
3178 .enable_mask = BIT(0),
3179 .hw.init = &(struct clk_init_data){
3180 .name = "gcc_usb_hsic_ahb_clk",
3181 .parent_names = (const char *[]){
3182 "periph_noc_clk_src",
3185 .ops = &clk_branch2_ops,
3190 static struct clk_branch gcc_usb_hsic_clk = {
3193 .enable_reg = 0x0410,
3194 .enable_mask = BIT(0),
3195 .hw.init = &(struct clk_init_data){
3196 .name = "gcc_usb_hsic_clk",
3197 .parent_names = (const char *[]){
3201 .flags = CLK_SET_RATE_PARENT,
3202 .ops = &clk_branch2_ops,
3207 static struct clk_branch gcc_usb_hsic_io_cal_clk = {
3210 .enable_reg = 0x0414,
3211 .enable_mask = BIT(0),
3212 .hw.init = &(struct clk_init_data){
3213 .name = "gcc_usb_hsic_io_cal_clk",
3214 .parent_names = (const char *[]){
3215 "usb_hsic_io_cal_clk_src",
3218 .flags = CLK_SET_RATE_PARENT,
3219 .ops = &clk_branch2_ops,
3224 static struct clk_branch gcc_usb_hsic_io_cal_sleep_clk = {
3227 .enable_reg = 0x0418,
3228 .enable_mask = BIT(0),
3229 .hw.init = &(struct clk_init_data){
3230 .name = "gcc_usb_hsic_io_cal_sleep_clk",
3231 .parent_names = (const char *[]){
3235 .ops = &clk_branch2_ops,
3240 static struct clk_branch gcc_usb_hsic_system_clk = {
3243 .enable_reg = 0x040c,
3244 .enable_mask = BIT(0),
3245 .hw.init = &(struct clk_init_data){
3246 .name = "gcc_usb_hsic_system_clk",
3247 .parent_names = (const char *[]){
3248 "usb_hsic_system_clk_src",
3251 .flags = CLK_SET_RATE_PARENT,
3252 .ops = &clk_branch2_ops,
3257 static struct clk_regmap *gcc_apq8084_clocks[] = {
3258 [GPLL0] = &gpll0.clkr,
3259 [GPLL0_VOTE] = &gpll0_vote,
3260 [GPLL1] = &gpll1.clkr,
3261 [GPLL1_VOTE] = &gpll1_vote,
3262 [GPLL4] = &gpll4.clkr,
3263 [GPLL4_VOTE] = &gpll4_vote,
3264 [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
3265 [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
3266 [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
3267 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
3268 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
3269 [USB30_SEC_MASTER_CLK_SRC] = &usb30_sec_master_clk_src.clkr,
3270 [USB_HSIC_AHB_CLK_SRC] = &usb_hsic_ahb_clk_src.clkr,
3271 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3272 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3273 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3274 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3275 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3276 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3277 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3278 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3279 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3280 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3281 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3282 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3283 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3284 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3285 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
3286 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
3287 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
3288 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
3289 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
3290 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
3291 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
3292 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
3293 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
3294 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
3295 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
3296 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
3297 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
3298 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
3299 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
3300 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
3301 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
3302 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
3303 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
3304 [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
3305 [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
3306 [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
3307 [CE1_CLK_SRC] = &ce1_clk_src.clkr,
3308 [CE2_CLK_SRC] = &ce2_clk_src.clkr,
3309 [CE3_CLK_SRC] = &ce3_clk_src.clkr,
3310 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
3311 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
3312 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
3313 [PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
3314 [PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
3315 [PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr,
3316 [PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr,
3317 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3318 [SATA_ASIC0_CLK_SRC] = &sata_asic0_clk_src.clkr,
3319 [SATA_PMALIVE_CLK_SRC] = &sata_pmalive_clk_src.clkr,
3320 [SATA_RX_CLK_SRC] = &sata_rx_clk_src.clkr,
3321 [SATA_RX_OOB_CLK_SRC] = &sata_rx_oob_clk_src.clkr,
3322 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3323 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3324 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
3325 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
3326 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
3327 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
3328 [USB30_SEC_MOCK_UTMI_CLK_SRC] = &usb30_sec_mock_utmi_clk_src.clkr,
3329 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
3330 [USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr,
3331 [USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr,
3332 [USB_HSIC_MOCK_UTMI_CLK_SRC] = &usb_hsic_mock_utmi_clk_src.clkr,
3333 [USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr,
3334 [GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr,
3335 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3336 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3337 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3338 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3339 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3340 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3341 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3342 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3343 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3344 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3345 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3346 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3347 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3348 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3349 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3350 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
3351 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
3352 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
3353 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
3354 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
3355 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
3356 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
3357 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
3358 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
3359 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
3360 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
3361 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
3362 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
3363 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
3364 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
3365 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
3366 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
3367 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
3368 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
3369 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
3370 [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
3371 [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
3372 [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
3373 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3374 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
3375 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
3376 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
3377 [GCC_CE2_AHB_CLK] = &gcc_ce2_ahb_clk.clkr,
3378 [GCC_CE2_AXI_CLK] = &gcc_ce2_axi_clk.clkr,
3379 [GCC_CE2_CLK] = &gcc_ce2_clk.clkr,
3380 [GCC_CE3_AHB_CLK] = &gcc_ce3_ahb_clk.clkr,
3381 [GCC_CE3_AXI_CLK] = &gcc_ce3_axi_clk.clkr,
3382 [GCC_CE3_CLK] = &gcc_ce3_clk.clkr,
3383 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3384 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3385 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3386 [GCC_OCMEM_NOC_CFG_AHB_CLK] = &gcc_ocmem_noc_cfg_ahb_clk.clkr,
3387 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3388 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3389 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3390 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3391 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3392 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3393 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3394 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3395 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3396 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3397 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3398 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3399 [GCC_PERIPH_NOC_USB_HSIC_AHB_CLK] = &gcc_periph_noc_usb_hsic_ahb_clk.clkr,
3400 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3401 [GCC_SATA_ASIC0_CLK] = &gcc_sata_asic0_clk.clkr,
3402 [GCC_SATA_AXI_CLK] = &gcc_sata_axi_clk.clkr,
3403 [GCC_SATA_CFG_AHB_CLK] = &gcc_sata_cfg_ahb_clk.clkr,
3404 [GCC_SATA_PMALIVE_CLK] = &gcc_sata_pmalive_clk.clkr,
3405 [GCC_SATA_RX_CLK] = &gcc_sata_rx_clk.clkr,
3406 [GCC_SATA_RX_OOB_CLK] = &gcc_sata_rx_oob_clk.clkr,
3407 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3408 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3409 [GCC_SDCC1_CDCCAL_FF_CLK] = &gcc_sdcc1_cdccal_ff_clk.clkr,
3410 [GCC_SDCC1_CDCCAL_SLEEP_CLK] = &gcc_sdcc1_cdccal_sleep_clk.clkr,
3411 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3412 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3413 [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
3414 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
3415 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3416 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3417 [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
3418 [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
3419 [GCC_SYS_NOC_USB3_SEC_AXI_CLK] = &gcc_sys_noc_usb3_sec_axi_clk.clkr,
3420 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3421 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
3422 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3423 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
3424 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
3425 [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
3426 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
3427 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
3428 [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
3429 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
3430 [GCC_UFS_TX_SYMBOL_1_CLK] = &gcc_ufs_tx_symbol_1_clk.clkr,
3431 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
3432 [GCC_USB2B_PHY_SLEEP_CLK] = &gcc_usb2b_phy_sleep_clk.clkr,
3433 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
3434 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
3435 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
3436 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
3437 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
3438 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
3439 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
3440 [GCC_USB_HS_INACTIVITY_TIMERS_CLK] = &gcc_usb_hs_inactivity_timers_clk.clkr,
3441 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
3442 [GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr,
3443 [GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr,
3444 [GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr,
3445 [GCC_USB_HSIC_IO_CAL_SLEEP_CLK] = &gcc_usb_hsic_io_cal_sleep_clk.clkr,
3446 [GCC_USB_HSIC_MOCK_UTMI_CLK] = &gcc_usb_hsic_mock_utmi_clk.clkr,
3447 [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr,
3450 static const struct qcom_reset_map gcc_apq8084_resets[] = {
3451 [GCC_SYSTEM_NOC_BCR] = { 0x0100 },
3452 [GCC_CONFIG_NOC_BCR] = { 0x0140 },
3453 [GCC_PERIPH_NOC_BCR] = { 0x0180 },
3454 [GCC_IMEM_BCR] = { 0x0200 },
3455 [GCC_MMSS_BCR] = { 0x0240 },
3456 [GCC_QDSS_BCR] = { 0x0300 },
3457 [GCC_USB_30_BCR] = { 0x03c0 },
3458 [GCC_USB3_PHY_BCR] = { 0x03fc },
3459 [GCC_USB_HS_HSIC_BCR] = { 0x0400 },
3460 [GCC_USB_HS_BCR] = { 0x0480 },
3461 [GCC_USB2A_PHY_BCR] = { 0x04a8 },
3462 [GCC_USB2B_PHY_BCR] = { 0x04b0 },
3463 [GCC_SDCC1_BCR] = { 0x04c0 },
3464 [GCC_SDCC2_BCR] = { 0x0500 },
3465 [GCC_SDCC3_BCR] = { 0x0540 },
3466 [GCC_SDCC4_BCR] = { 0x0580 },
3467 [GCC_BLSP1_BCR] = { 0x05c0 },
3468 [GCC_BLSP1_QUP1_BCR] = { 0x0640 },
3469 [GCC_BLSP1_UART1_BCR] = { 0x0680 },
3470 [GCC_BLSP1_QUP2_BCR] = { 0x06c0 },
3471 [GCC_BLSP1_UART2_BCR] = { 0x0700 },
3472 [GCC_BLSP1_QUP3_BCR] = { 0x0740 },
3473 [GCC_BLSP1_UART3_BCR] = { 0x0780 },
3474 [GCC_BLSP1_QUP4_BCR] = { 0x07c0 },
3475 [GCC_BLSP1_UART4_BCR] = { 0x0800 },
3476 [GCC_BLSP1_QUP5_BCR] = { 0x0840 },
3477 [GCC_BLSP1_UART5_BCR] = { 0x0880 },
3478 [GCC_BLSP1_QUP6_BCR] = { 0x08c0 },
3479 [GCC_BLSP1_UART6_BCR] = { 0x0900 },
3480 [GCC_BLSP2_BCR] = { 0x0940 },
3481 [GCC_BLSP2_QUP1_BCR] = { 0x0980 },
3482 [GCC_BLSP2_UART1_BCR] = { 0x09c0 },
3483 [GCC_BLSP2_QUP2_BCR] = { 0x0a00 },
3484 [GCC_BLSP2_UART2_BCR] = { 0x0a40 },
3485 [GCC_BLSP2_QUP3_BCR] = { 0x0a80 },
3486 [GCC_BLSP2_UART3_BCR] = { 0x0ac0 },
3487 [GCC_BLSP2_QUP4_BCR] = { 0x0b00 },
3488 [GCC_BLSP2_UART4_BCR] = { 0x0b40 },
3489 [GCC_BLSP2_QUP5_BCR] = { 0x0b80 },
3490 [GCC_BLSP2_UART5_BCR] = { 0x0bc0 },
3491 [GCC_BLSP2_QUP6_BCR] = { 0x0c00 },
3492 [GCC_BLSP2_UART6_BCR] = { 0x0c40 },
3493 [GCC_PDM_BCR] = { 0x0cc0 },
3494 [GCC_PRNG_BCR] = { 0x0d00 },
3495 [GCC_BAM_DMA_BCR] = { 0x0d40 },
3496 [GCC_TSIF_BCR] = { 0x0d80 },
3497 [GCC_TCSR_BCR] = { 0x0dc0 },
3498 [GCC_BOOT_ROM_BCR] = { 0x0e00 },
3499 [GCC_MSG_RAM_BCR] = { 0x0e40 },
3500 [GCC_TLMM_BCR] = { 0x0e80 },
3501 [GCC_MPM_BCR] = { 0x0ec0 },
3502 [GCC_MPM_AHB_RESET] = { 0x0ec4, 1 },
3503 [GCC_MPM_NON_AHB_RESET] = { 0x0ec4, 2 },
3504 [GCC_SEC_CTRL_BCR] = { 0x0f40 },
3505 [GCC_SPMI_BCR] = { 0x0fc0 },
3506 [GCC_SPDM_BCR] = { 0x1000 },
3507 [GCC_CE1_BCR] = { 0x1040 },
3508 [GCC_CE2_BCR] = { 0x1080 },
3509 [GCC_BIMC_BCR] = { 0x1100 },
3510 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x1240 },
3511 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x1248 },
3512 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x1280 },
3513 [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x1288 },
3514 [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x1290 },
3515 [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x1298 },
3516 [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x12a0 },
3517 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x12c0 },
3518 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x12c8 },
3519 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x12d0 },
3520 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x12d8 },
3521 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x12e0 },
3522 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x12e8 },
3523 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x12f0 },
3524 [GCC_DEHR_BCR] = { 0x1300 },
3525 [GCC_RBCPR_BCR] = { 0x1380 },
3526 [GCC_MSS_RESTART] = { 0x1680 },
3527 [GCC_LPASS_RESTART] = { 0x16c0 },
3528 [GCC_WCSS_RESTART] = { 0x1700 },
3529 [GCC_VENUS_RESTART] = { 0x1740 },
3530 [GCC_COPSS_SMMU_BCR] = { 0x1a40 },
3531 [GCC_SPSS_BCR] = { 0x1a80 },
3532 [GCC_PCIE_0_BCR] = { 0x1ac0 },
3533 [GCC_PCIE_0_PHY_BCR] = { 0x1b00 },
3534 [GCC_PCIE_1_BCR] = { 0x1b40 },
3535 [GCC_PCIE_1_PHY_BCR] = { 0x1b80 },
3536 [GCC_USB_30_SEC_BCR] = { 0x1bc0 },
3537 [GCC_USB3_SEC_PHY_BCR] = { 0x1bfc },
3538 [GCC_SATA_BCR] = { 0x1c40 },
3539 [GCC_CE3_BCR] = { 0x1d00 },
3540 [GCC_UFS_BCR] = { 0x1d40 },
3541 [GCC_USB30_PHY_COM_BCR] = { 0x1e80 },
3544 static const struct regmap_config gcc_apq8084_regmap_config = {
3548 .max_register = 0x1fc0,
3552 static const struct qcom_cc_desc gcc_apq8084_desc = {
3553 .config = &gcc_apq8084_regmap_config,
3554 .clks = gcc_apq8084_clocks,
3555 .num_clks = ARRAY_SIZE(gcc_apq8084_clocks),
3556 .resets = gcc_apq8084_resets,
3557 .num_resets = ARRAY_SIZE(gcc_apq8084_resets),
3560 static const struct of_device_id gcc_apq8084_match_table[] = {
3561 { .compatible = "qcom,gcc-apq8084" },
3564 MODULE_DEVICE_TABLE(of, gcc_apq8084_match_table);
3566 static int gcc_apq8084_probe(struct platform_device *pdev)
3569 struct device *dev = &pdev->dev;
3571 /* Temporary until RPM clocks supported */
3572 clk = clk_register_fixed_rate(dev, "xo", NULL, CLK_IS_ROOT, 19200000);
3574 return PTR_ERR(clk);
3576 clk = clk_register_fixed_rate(dev, "sleep_clk_src", NULL,
3577 CLK_IS_ROOT, 32768);
3579 return PTR_ERR(clk);
3581 return qcom_cc_probe(pdev, &gcc_apq8084_desc);
3584 static int gcc_apq8084_remove(struct platform_device *pdev)
3586 qcom_cc_remove(pdev);
3590 static struct platform_driver gcc_apq8084_driver = {
3591 .probe = gcc_apq8084_probe,
3592 .remove = gcc_apq8084_remove,
3594 .name = "gcc-apq8084",
3595 .of_match_table = gcc_apq8084_match_table,
3599 static int __init gcc_apq8084_init(void)
3601 return platform_driver_register(&gcc_apq8084_driver);
3603 core_initcall(gcc_apq8084_init);
3605 static void __exit gcc_apq8084_exit(void)
3607 platform_driver_unregister(&gcc_apq8084_driver);
3609 module_exit(gcc_apq8084_exit);
3611 MODULE_DESCRIPTION("QCOM GCC APQ8084 Driver");
3612 MODULE_LICENSE("GPL v2");
3613 MODULE_ALIAS("platform:gcc-apq8084");