drivers/clk/qcom/clk-smd-rpm.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2016, Linaro Limited
   4  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
   5  */
   6
   7 #include <linux/clk-provider.h>
   8 #include <linux/err.h>
   9 #include <linux/export.h>
  10 #include <linux/init.h>
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/mutex.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/soc/qcom/smd-rpm.h>
  18
  19 #include <dt-bindings/clock/qcom,rpmcc.h>
  20
  21 #define QCOM_RPM_KEY_SOFTWARE_ENABLE                    0x6e657773
  22 #define QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY     0x62636370
  23 #define QCOM_RPM_SMD_KEY_RATE                           0x007a484b
  24 #define QCOM_RPM_SMD_KEY_ENABLE                         0x62616e45
  25 #define QCOM_RPM_SMD_KEY_STATE                          0x54415453
  26 #define QCOM_RPM_SCALING_ENABLE_ID                      0x2
  27
  28 #define __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, stat_id,  \
  29                              key)                                             \
  30         static struct clk_smd_rpm _platform##_##_active;                      \
  31         static struct clk_smd_rpm _platform##_##_name = {                     \
  32                 .rpm_res_type = (type),                                       \
  33                 .rpm_clk_id = (r_id),                                         \
  34                 .rpm_status_id = (stat_id),                                   \
  35                 .rpm_key = (key),                                             \
  36                 .peer = &_platform##_##_active,                               \
  37                 .rate = INT_MAX,                                              \
  38                 .hw.init = &(struct clk_init_data){                           \
  39                         .ops = &clk_smd_rpm_ops,                              \
  40                         .name = #_name,                                       \
  41                         .parent_data =  &(const struct clk_parent_data){ \
  42                                         .fw_name = "xo",                \
  43                                         .name = "xo_board",             \
  44                         },                                              \
  45                         .num_parents = 1,                                     \
  46                 },                                                            \
  47         };                                                                    \
  48         static struct clk_smd_rpm _platform##_##_active = {                   \
  49                 .rpm_res_type = (type),                                       \
  50                 .rpm_clk_id = (r_id),                                         \
  51                 .rpm_status_id = (stat_id),                                   \
  52                 .active_only = true,                                          \
  53                 .rpm_key = (key),                                             \
  54                 .peer = &_platform##_##_name,                                 \
  55                 .rate = INT_MAX,                                              \
  56                 .hw.init = &(struct clk_init_data){                           \
  57                         .ops = &clk_smd_rpm_ops,                              \
  58                         .name = #_active,                                     \
  59                         .parent_data =  &(const struct clk_parent_data){ \
  60                                         .fw_name = "xo",                \
  61                                         .name = "xo_board",             \
  62                         },                                              \
  63                         .num_parents = 1,                                     \
  64                 },                                                            \
  65         }
  66
  67 #define __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id,    \
  68                                     stat_id, r, key)                          \
  69         static struct clk_smd_rpm _platform##_##_active;                      \
  70         static struct clk_smd_rpm _platform##_##_name = {                     \
  71                 .rpm_res_type = (type),                                       \
  72                 .rpm_clk_id = (r_id),                                         \
  73                 .rpm_status_id = (stat_id),                                   \
  74                 .rpm_key = (key),                                             \
  75                 .branch = true,                                               \
  76                 .peer = &_platform##_##_active,                               \
  77                 .rate = (r),                                                  \
  78                 .hw.init = &(struct clk_init_data){                           \
  79                         .ops = &clk_smd_rpm_branch_ops,                       \
  80                         .name = #_name,                                       \
  81                         .parent_data =  &(const struct clk_parent_data){ \
  82                                         .fw_name = "xo",                \
  83                                         .name = "xo_board",             \
  84                         },                                              \
  85                         .num_parents = 1,                                     \
  86                 },                                                            \
  87         };                                                                    \
  88         static struct clk_smd_rpm _platform##_##_active = {                   \
  89                 .rpm_res_type = (type),                                       \
  90                 .rpm_clk_id = (r_id),                                         \
  91                 .rpm_status_id = (stat_id),                                   \
  92                 .active_only = true,                                          \
  93                 .rpm_key = (key),                                             \
  94                 .branch = true,                                               \
  95                 .peer = &_platform##_##_name,                                 \
  96                 .rate = (r),                                                  \
  97                 .hw.init = &(struct clk_init_data){                           \
  98                         .ops = &clk_smd_rpm_branch_ops,                       \
  99                         .name = #_active,                                     \
 100                         .parent_data =  &(const struct clk_parent_data){ \
 101                                         .fw_name = "xo",                \
 102                                         .name = "xo_board",             \
 103                         },                                              \
 104                         .num_parents = 1,                                     \
 105                 },                                                            \
 106         }
 107
 108 #define DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id)             \
 109                 __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id,   \
 110                 0, QCOM_RPM_SMD_KEY_RATE)
 111
 112 #define DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, r)   \
 113                 __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type,  \
 114                 r_id, 0, r, QCOM_RPM_SMD_KEY_ENABLE)
 115
 116 #define DEFINE_CLK_SMD_RPM_QDSS(_platform, _name, _active, type, r_id)        \
 117                 __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id,   \
 118                 0, QCOM_RPM_SMD_KEY_STATE)
 119
 120 #define DEFINE_CLK_SMD_RPM_XO_BUFFER(_platform, _name, _active, r_id, r)      \
 121                 __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active,        \
 122                 QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, r,                           \
 123                 QCOM_RPM_KEY_SOFTWARE_ENABLE)
 124
 125 #define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_platform, _name, _active,       \
 126                                              r_id, r)                         \
 127                 __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active,        \
 128                 QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, r,                           \
 129                 QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY)
 130
 131 #define to_clk_smd_rpm(_hw) container_of(_hw, struct clk_smd_rpm, hw)
 132
 133 struct clk_smd_rpm {
 134         const int rpm_res_type;
 135         const int rpm_key;
 136         const int rpm_clk_id;
 137         const int rpm_status_id;
 138         const bool active_only;
 139         bool enabled;
 140         bool branch;
 141         struct clk_smd_rpm *peer;
 142         struct clk_hw hw;
 143         unsigned long rate;
 144         struct qcom_smd_rpm *rpm;
 145 };
 146
 147 struct clk_smd_rpm_req {
 148         __le32 key;
 149         __le32 nbytes;
 150         __le32 value;
 151 };
 152
 153 struct rpm_smd_clk_desc {
 154         struct clk_smd_rpm **clks;
 155         size_t num_clks;
 156 };
 157
 158 static DEFINE_MUTEX(rpm_smd_clk_lock);
 159
 160 static int clk_smd_rpm_handoff(struct clk_smd_rpm *r)
 161 {
 162         int ret;
 163         struct clk_smd_rpm_req req = {
 164                 .key = cpu_to_le32(r->rpm_key),
 165                 .nbytes = cpu_to_le32(sizeof(u32)),
 166                 .value = cpu_to_le32(r->branch ? 1 : INT_MAX),
 167         };
 168
 169         ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
 170                                  r->rpm_res_type, r->rpm_clk_id, &req,
 171                                  sizeof(req));
 172         if (ret)
 173                 return ret;
 174         ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,
 175                                  r->rpm_res_type, r->rpm_clk_id, &req,
 176                                  sizeof(req));
 177         if (ret)
 178                 return ret;
 179
 180         return 0;
 181 }
 182
 183 static int clk_smd_rpm_set_rate_active(struct clk_smd_rpm *r,
 184                                        unsigned long rate)
 185 {
 186         struct clk_smd_rpm_req req = {
 187                 .key = cpu_to_le32(r->rpm_key),
 188                 .nbytes = cpu_to_le32(sizeof(u32)),
 189                 .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
 190         };
 191
 192         return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
 193                                   r->rpm_res_type, r->rpm_clk_id, &req,
 194                                   sizeof(req));
 195 }
 196
 197 static int clk_smd_rpm_set_rate_sleep(struct clk_smd_rpm *r,
 198                                       unsigned long rate)
 199 {
 200         struct clk_smd_rpm_req req = {
 201                 .key = cpu_to_le32(r->rpm_key),
 202                 .nbytes = cpu_to_le32(sizeof(u32)),
 203                 .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
 204         };
 205
 206         return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,
 207                                   r->rpm_res_type, r->rpm_clk_id, &req,
 208                                   sizeof(req));
 209 }
 210
 211 static void to_active_sleep(struct clk_smd_rpm *r, unsigned long rate,
 212                             unsigned long *active, unsigned long *sleep)
 213 {
 214         *active = rate;
 215
 216         /*
 217          * Active-only clocks don't care what the rate is during sleep. So,
 218          * they vote for zero.
 219          */
 220         if (r->active_only)
 221                 *sleep = 0;
 222         else
 223                 *sleep = *active;
 224 }
 225
 226 static int clk_smd_rpm_prepare(struct clk_hw *hw)
 227 {
 228         struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
 229         struct clk_smd_rpm *peer = r->peer;
 230         unsigned long this_rate = 0, this_sleep_rate = 0;
 231         unsigned long peer_rate = 0, peer_sleep_rate = 0;
 232         unsigned long active_rate, sleep_rate;
 233         int ret = 0;
 234
 235         mutex_lock(&rpm_smd_clk_lock);
 236
 237         /* Don't send requests to the RPM if the rate has not been set. */
 238         if (!r->rate)
 239                 goto out;
 240
 241         to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);
 242
 243         /* Take peer clock's rate into account only if it's enabled. */
 244         if (peer->enabled)
 245                 to_active_sleep(peer, peer->rate,
 246                                 &peer_rate, &peer_sleep_rate);
 247
 248         active_rate = max(this_rate, peer_rate);
 249
 250         if (r->branch)
 251                 active_rate = !!active_rate;
 252
 253         ret = clk_smd_rpm_set_rate_active(r, active_rate);
 254         if (ret)
 255                 goto out;
 256
 257         sleep_rate = max(this_sleep_rate, peer_sleep_rate);
 258         if (r->branch)
 259                 sleep_rate = !!sleep_rate;
 260
 261         ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
 262         if (ret)
 263                 /* Undo the active set vote and restore it */
 264                 ret = clk_smd_rpm_set_rate_active(r, peer_rate);
 265
 266 out:
 267         if (!ret)
 268                 r->enabled = true;
 269
 270         mutex_unlock(&rpm_smd_clk_lock);
 271
 272         return ret;
 273 }
 274
 275 static void clk_smd_rpm_unprepare(struct clk_hw *hw)
 276 {
 277         struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
 278         struct clk_smd_rpm *peer = r->peer;
 279         unsigned long peer_rate = 0, peer_sleep_rate = 0;
 280         unsigned long active_rate, sleep_rate;
 281         int ret;
 282
 283         mutex_lock(&rpm_smd_clk_lock);
 284
 285         if (!r->rate)
 286                 goto out;
 287
 288         /* Take peer clock's rate into account only if it's enabled. */
 289         if (peer->enabled)
 290                 to_active_sleep(peer, peer->rate, &peer_rate,
 291                                 &peer_sleep_rate);
 292
 293         active_rate = r->branch ? !!peer_rate : peer_rate;
 294         ret = clk_smd_rpm_set_rate_active(r, active_rate);
 295         if (ret)
 296                 goto out;
 297
 298         sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;
 299         ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
 300         if (ret)
 301                 goto out;
 302
 303         r->enabled = false;
 304
 305 out:
 306         mutex_unlock(&rpm_smd_clk_lock);
 307 }
 308
 309 static int clk_smd_rpm_set_rate(struct clk_hw *hw, unsigned long rate,
 310                                 unsigned long parent_rate)
 311 {
 312         struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
 313         struct clk_smd_rpm *peer = r->peer;
 314         unsigned long active_rate, sleep_rate;
 315         unsigned long this_rate = 0, this_sleep_rate = 0;
 316         unsigned long peer_rate = 0, peer_sleep_rate = 0;
 317         int ret = 0;
 318
 319         mutex_lock(&rpm_smd_clk_lock);
 320
 321         if (!r->enabled)
 322                 goto out;
 323
 324         to_active_sleep(r, rate, &this_rate, &this_sleep_rate);
 325
 326         /* Take peer clock's rate into account only if it's enabled. */
 327         if (peer->enabled)
 328                 to_active_sleep(peer, peer->rate,
 329                                 &peer_rate, &peer_sleep_rate);
 330
 331         active_rate = max(this_rate, peer_rate);
 332         ret = clk_smd_rpm_set_rate_active(r, active_rate);
 333         if (ret)
 334                 goto out;
 335
 336         sleep_rate = max(this_sleep_rate, peer_sleep_rate);
 337         ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
 338         if (ret)
 339                 goto out;
 340
 341         r->rate = rate;
 342
 343 out:
 344         mutex_unlock(&rpm_smd_clk_lock);
 345
 346         return ret;
 347 }
 348
 349 static long clk_smd_rpm_round_rate(struct clk_hw *hw, unsigned long rate,
 350                                    unsigned long *parent_rate)
 351 {
 352         /*
 353          * RPM handles rate rounding and we don't have a way to
 354          * know what the rate will be, so just return whatever
 355          * rate is requested.
 356          */
 357         return rate;
 358 }
 359
 360 static unsigned long clk_smd_rpm_recalc_rate(struct clk_hw *hw,
 361                                              unsigned long parent_rate)
 362 {
 363         struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
 364
 365         /*
 366          * RPM handles rate rounding and we don't have a way to
 367          * know what the rate will be, so just return whatever
 368          * rate was set.
 369          */
 370         return r->rate;
 371 }
 372
 373 static int clk_smd_rpm_enable_scaling(struct qcom_smd_rpm *rpm)
 374 {
 375         int ret;
 376         struct clk_smd_rpm_req req = {
 377                 .key = cpu_to_le32(QCOM_RPM_SMD_KEY_ENABLE),
 378                 .nbytes = cpu_to_le32(sizeof(u32)),
 379                 .value = cpu_to_le32(1),
 380         };
 381
 382         ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_SLEEP_STATE,
 383                                  QCOM_SMD_RPM_MISC_CLK,
 384                                  QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
 385         if (ret) {
 386                 pr_err("RPM clock scaling (sleep set) not enabled!\n");
 387                 return ret;
 388         }
 389
 390         ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_ACTIVE_STATE,
 391                                  QCOM_SMD_RPM_MISC_CLK,
 392                                  QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
 393         if (ret) {
 394                 pr_err("RPM clock scaling (active set) not enabled!\n");
 395                 return ret;
 396         }
 397
 398         pr_debug("%s: RPM clock scaling is enabled\n", __func__);
 399         return 0;
 400 }
 401
 402 static const struct clk_ops clk_smd_rpm_ops = {
 403         .prepare        = clk_smd_rpm_prepare,
 404         .unprepare      = clk_smd_rpm_unprepare,
 405         .set_rate       = clk_smd_rpm_set_rate,
 406         .round_rate     = clk_smd_rpm_round_rate,
 407         .recalc_rate    = clk_smd_rpm_recalc_rate,
 408 };
 409
 410 static const struct clk_ops clk_smd_rpm_branch_ops = {
 411         .prepare        = clk_smd_rpm_prepare,
 412         .unprepare      = clk_smd_rpm_unprepare,
 413         .recalc_rate    = clk_smd_rpm_recalc_rate,
 414 };
 415
 416 DEFINE_CLK_SMD_RPM_BRANCH(sdm660, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0, 19200000);
 417 DEFINE_CLK_SMD_RPM(msm8916, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
 418 DEFINE_CLK_SMD_RPM(msm8916, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
 419 DEFINE_CLK_SMD_RPM(msm8916, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
 420 DEFINE_CLK_SMD_RPM(qcs404, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0);
 421 DEFINE_CLK_SMD_RPM_QDSS(msm8916, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);
 422 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk1, bb_clk1_a, 1, 19200000);
 423 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk2, bb_clk2_a, 2, 19200000);
 424 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk1, rf_clk1_a, 4, 19200000);
 425 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk2, rf_clk2_a, 5, 19200000);
 426 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk1_pin, bb_clk1_a_pin, 1, 19200000);
 427 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk2_pin, bb_clk2_a_pin, 2, 19200000);
 428 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk1_pin, rf_clk1_a_pin, 4, 19200000);
 429 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk2_pin, rf_clk2_a_pin, 5, 19200000);
 430
 431 static struct clk_smd_rpm *msm8909_clks[] = {
 432         [RPM_SMD_PCNOC_CLK]             = &msm8916_pcnoc_clk,
 433         [RPM_SMD_PCNOC_A_CLK]           = &msm8916_pcnoc_a_clk,
 434         [RPM_SMD_SNOC_CLK]              = &msm8916_snoc_clk,
 435         [RPM_SMD_SNOC_A_CLK]            = &msm8916_snoc_a_clk,
 436         [RPM_SMD_BIMC_CLK]              = &msm8916_bimc_clk,
 437         [RPM_SMD_BIMC_A_CLK]            = &msm8916_bimc_a_clk,
 438         [RPM_SMD_QPIC_CLK]              = &qcs404_qpic_clk,
 439         [RPM_SMD_QPIC_CLK_A]            = &qcs404_qpic_a_clk,
 440         [RPM_SMD_QDSS_CLK]              = &msm8916_qdss_clk,
 441         [RPM_SMD_QDSS_A_CLK]            = &msm8916_qdss_a_clk,
 442         [RPM_SMD_BB_CLK1]               = &msm8916_bb_clk1,
 443         [RPM_SMD_BB_CLK1_A]             = &msm8916_bb_clk1_a,
 444         [RPM_SMD_BB_CLK2]               = &msm8916_bb_clk2,
 445         [RPM_SMD_BB_CLK2_A]             = &msm8916_bb_clk2_a,
 446         [RPM_SMD_RF_CLK1]               = &msm8916_rf_clk1,
 447         [RPM_SMD_RF_CLK1_A]             = &msm8916_rf_clk1_a,
 448         [RPM_SMD_RF_CLK2]               = &msm8916_rf_clk2,
 449         [RPM_SMD_RF_CLK2_A]             = &msm8916_rf_clk2_a,
 450         [RPM_SMD_BB_CLK1_PIN]           = &msm8916_bb_clk1_pin,
 451         [RPM_SMD_BB_CLK1_A_PIN]         = &msm8916_bb_clk1_a_pin,
 452         [RPM_SMD_BB_CLK2_PIN]           = &msm8916_bb_clk2_pin,
 453         [RPM_SMD_BB_CLK2_A_PIN]         = &msm8916_bb_clk2_a_pin,
 454         [RPM_SMD_RF_CLK1_PIN]           = &msm8916_rf_clk1_pin,
 455         [RPM_SMD_RF_CLK1_A_PIN]         = &msm8916_rf_clk1_a_pin,
 456         [RPM_SMD_RF_CLK2_PIN]           = &msm8916_rf_clk2_pin,
 457         [RPM_SMD_RF_CLK2_A_PIN]         = &msm8916_rf_clk2_a_pin,
 458 };
 459
 460 static const struct rpm_smd_clk_desc rpm_clk_msm8909 = {
 461         .clks = msm8909_clks,
 462         .num_clks = ARRAY_SIZE(msm8909_clks),
 463 };
 464
 465 static struct clk_smd_rpm *msm8916_clks[] = {
 466         [RPM_SMD_PCNOC_CLK]             = &msm8916_pcnoc_clk,
 467         [RPM_SMD_PCNOC_A_CLK]           = &msm8916_pcnoc_a_clk,
 468         [RPM_SMD_SNOC_CLK]              = &msm8916_snoc_clk,
 469         [RPM_SMD_SNOC_A_CLK]            = &msm8916_snoc_a_clk,
 470         [RPM_SMD_BIMC_CLK]              = &msm8916_bimc_clk,
 471         [RPM_SMD_BIMC_A_CLK]            = &msm8916_bimc_a_clk,
 472         [RPM_SMD_QDSS_CLK]              = &msm8916_qdss_clk,
 473         [RPM_SMD_QDSS_A_CLK]            = &msm8916_qdss_a_clk,
 474         [RPM_SMD_BB_CLK1]               = &msm8916_bb_clk1,
 475         [RPM_SMD_BB_CLK1_A]             = &msm8916_bb_clk1_a,
 476         [RPM_SMD_BB_CLK2]               = &msm8916_bb_clk2,
 477         [RPM_SMD_BB_CLK2_A]             = &msm8916_bb_clk2_a,
 478         [RPM_SMD_RF_CLK1]               = &msm8916_rf_clk1,
 479         [RPM_SMD_RF_CLK1_A]             = &msm8916_rf_clk1_a,
 480         [RPM_SMD_RF_CLK2]               = &msm8916_rf_clk2,
 481         [RPM_SMD_RF_CLK2_A]             = &msm8916_rf_clk2_a,
 482         [RPM_SMD_BB_CLK1_PIN]           = &msm8916_bb_clk1_pin,
 483         [RPM_SMD_BB_CLK1_A_PIN]         = &msm8916_bb_clk1_a_pin,
 484         [RPM_SMD_BB_CLK2_PIN]           = &msm8916_bb_clk2_pin,
 485         [RPM_SMD_BB_CLK2_A_PIN]         = &msm8916_bb_clk2_a_pin,
 486         [RPM_SMD_RF_CLK1_PIN]           = &msm8916_rf_clk1_pin,
 487         [RPM_SMD_RF_CLK1_A_PIN]         = &msm8916_rf_clk1_a_pin,
 488         [RPM_SMD_RF_CLK2_PIN]           = &msm8916_rf_clk2_pin,
 489         [RPM_SMD_RF_CLK2_A_PIN]         = &msm8916_rf_clk2_a_pin,
 490 };
 491
 492 static const struct rpm_smd_clk_desc rpm_clk_msm8916 = {
 493         .clks = msm8916_clks,
 494         .num_clks = ARRAY_SIZE(msm8916_clks),
 495 };
 496
 497 DEFINE_CLK_SMD_RPM(msm8936, sysmmnoc_clk, sysmmnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
 498
 499 static struct clk_smd_rpm *msm8936_clks[] = {
 500         [RPM_SMD_PCNOC_CLK]             = &msm8916_pcnoc_clk,
 501         [RPM_SMD_PCNOC_A_CLK]           = &msm8916_pcnoc_a_clk,
 502         [RPM_SMD_SNOC_CLK]              = &msm8916_snoc_clk,
 503         [RPM_SMD_SNOC_A_CLK]            = &msm8916_snoc_a_clk,
 504         [RPM_SMD_BIMC_CLK]              = &msm8916_bimc_clk,
 505         [RPM_SMD_BIMC_A_CLK]            = &msm8916_bimc_a_clk,
 506         [RPM_SMD_SYSMMNOC_CLK]          = &msm8936_sysmmnoc_clk,
 507         [RPM_SMD_SYSMMNOC_A_CLK]        = &msm8936_sysmmnoc_a_clk,
 508         [RPM_SMD_QDSS_CLK]              = &msm8916_qdss_clk,
 509         [RPM_SMD_QDSS_A_CLK]            = &msm8916_qdss_a_clk,
 510         [RPM_SMD_BB_CLK1]               = &msm8916_bb_clk1,
 511         [RPM_SMD_BB_CLK1_A]             = &msm8916_bb_clk1_a,
 512         [RPM_SMD_BB_CLK2]               = &msm8916_bb_clk2,
 513         [RPM_SMD_BB_CLK2_A]             = &msm8916_bb_clk2_a,
 514         [RPM_SMD_RF_CLK1]               = &msm8916_rf_clk1,
 515         [RPM_SMD_RF_CLK1_A]             = &msm8916_rf_clk1_a,
 516         [RPM_SMD_RF_CLK2]               = &msm8916_rf_clk2,
 517         [RPM_SMD_RF_CLK2_A]             = &msm8916_rf_clk2_a,
 518         [RPM_SMD_BB_CLK1_PIN]           = &msm8916_bb_clk1_pin,
 519         [RPM_SMD_BB_CLK1_A_PIN]         = &msm8916_bb_clk1_a_pin,
 520         [RPM_SMD_BB_CLK2_PIN]           = &msm8916_bb_clk2_pin,
 521         [RPM_SMD_BB_CLK2_A_PIN]         = &msm8916_bb_clk2_a_pin,
 522         [RPM_SMD_RF_CLK1_PIN]           = &msm8916_rf_clk1_pin,
 523         [RPM_SMD_RF_CLK1_A_PIN]         = &msm8916_rf_clk1_a_pin,
 524         [RPM_SMD_RF_CLK2_PIN]           = &msm8916_rf_clk2_pin,
 525         [RPM_SMD_RF_CLK2_A_PIN]         = &msm8916_rf_clk2_a_pin,
 526 };
 527
 528 static const struct rpm_smd_clk_desc rpm_clk_msm8936 = {
 529                 .clks = msm8936_clks,
 530                 .num_clks = ARRAY_SIZE(msm8936_clks),
 531 };
 532
 533 DEFINE_CLK_SMD_RPM(msm8974, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
 534 DEFINE_CLK_SMD_RPM(msm8974, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, QCOM_SMD_RPM_BUS_CLK, 3);
 535 DEFINE_CLK_SMD_RPM(msm8974, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1);
 536 DEFINE_CLK_SMD_RPM(msm8974, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
 537 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d0, cxo_d0_a, 1, 19200000);
 538 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d1, cxo_d1_a, 2, 19200000);
 539 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a0, cxo_a0_a, 4, 19200000);
 540 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a1, cxo_a1_a, 5, 19200000);
 541 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a2, cxo_a2_a, 6, 19200000);
 542 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, diff_clk, diff_a_clk, 7, 19200000);
 543 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk1, div_a_clk1, 11, 19200000);
 544 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk2, div_a_clk2, 12, 19200000);
 545 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d0_pin, cxo_d0_a_pin, 1, 19200000);
 546 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d1_pin, cxo_d1_a_pin, 2, 19200000);
 547 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a0_pin, cxo_a0_a_pin, 4, 19200000);
 548 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a1_pin, cxo_a1_a_pin, 5, 19200000);
 549 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a2_pin, cxo_a2_a_pin, 6, 19200000);
 550
 551 static struct clk_smd_rpm *msm8974_clks[] = {
 552         [RPM_SMD_PNOC_CLK]              = &msm8916_pcnoc_clk,
 553         [RPM_SMD_PNOC_A_CLK]            = &msm8916_pcnoc_a_clk,
 554         [RPM_SMD_SNOC_CLK]              = &msm8916_snoc_clk,
 555         [RPM_SMD_SNOC_A_CLK]            = &msm8916_snoc_a_clk,
 556         [RPM_SMD_CNOC_CLK]              = &msm8974_cnoc_clk,
 557         [RPM_SMD_CNOC_A_CLK]            = &msm8974_cnoc_a_clk,
 558         [RPM_SMD_MMSSNOC_AHB_CLK]       = &msm8974_mmssnoc_ahb_clk,
 559         [RPM_SMD_MMSSNOC_AHB_A_CLK]     = &msm8974_mmssnoc_ahb_a_clk,
 560         [RPM_SMD_BIMC_CLK]              = &msm8916_bimc_clk,
 561         [RPM_SMD_GFX3D_CLK_SRC]         = &msm8974_gfx3d_clk_src,
 562         [RPM_SMD_GFX3D_A_CLK_SRC]       = &msm8974_gfx3d_a_clk_src,
 563         [RPM_SMD_BIMC_A_CLK]            = &msm8916_bimc_a_clk,
 564         [RPM_SMD_OCMEMGX_CLK]           = &msm8974_ocmemgx_clk,
 565         [RPM_SMD_OCMEMGX_A_CLK]         = &msm8974_ocmemgx_a_clk,
 566         [RPM_SMD_QDSS_CLK]              = &msm8916_qdss_clk,
 567         [RPM_SMD_QDSS_A_CLK]            = &msm8916_qdss_a_clk,
 568         [RPM_SMD_CXO_D0]                = &msm8974_cxo_d0,
 569         [RPM_SMD_CXO_D0_A]              = &msm8974_cxo_d0_a,
 570         [RPM_SMD_CXO_D1]                = &msm8974_cxo_d1,
 571         [RPM_SMD_CXO_D1_A]              = &msm8974_cxo_d1_a,
 572         [RPM_SMD_CXO_A0]                = &msm8974_cxo_a0,
 573         [RPM_SMD_CXO_A0_A]              = &msm8974_cxo_a0_a,
 574         [RPM_SMD_CXO_A1]                = &msm8974_cxo_a1,
 575         [RPM_SMD_CXO_A1_A]              = &msm8974_cxo_a1_a,
 576         [RPM_SMD_CXO_A2]                = &msm8974_cxo_a2,
 577         [RPM_SMD_CXO_A2_A]              = &msm8974_cxo_a2_a,
 578         [RPM_SMD_DIFF_CLK]              = &msm8974_diff_clk,
 579         [RPM_SMD_DIFF_A_CLK]            = &msm8974_diff_a_clk,
 580         [RPM_SMD_DIV_CLK1]              = &msm8974_div_clk1,
 581         [RPM_SMD_DIV_A_CLK1]            = &msm8974_div_a_clk1,
 582         [RPM_SMD_DIV_CLK2]              = &msm8974_div_clk2,
 583         [RPM_SMD_DIV_A_CLK2]            = &msm8974_div_a_clk2,
 584         [RPM_SMD_CXO_D0_PIN]            = &msm8974_cxo_d0_pin,
 585         [RPM_SMD_CXO_D0_A_PIN]          = &msm8974_cxo_d0_a_pin,
 586         [RPM_SMD_CXO_D1_PIN]            = &msm8974_cxo_d1_pin,
 587         [RPM_SMD_CXO_D1_A_PIN]          = &msm8974_cxo_d1_a_pin,
 588         [RPM_SMD_CXO_A0_PIN]            = &msm8974_cxo_a0_pin,
 589         [RPM_SMD_CXO_A0_A_PIN]          = &msm8974_cxo_a0_a_pin,
 590         [RPM_SMD_CXO_A1_PIN]            = &msm8974_cxo_a1_pin,
 591         [RPM_SMD_CXO_A1_A_PIN]          = &msm8974_cxo_a1_a_pin,
 592         [RPM_SMD_CXO_A2_PIN]            = &msm8974_cxo_a2_pin,
 593         [RPM_SMD_CXO_A2_A_PIN]          = &msm8974_cxo_a2_a_pin,
 594 };
 595
 596 static const struct rpm_smd_clk_desc rpm_clk_msm8974 = {
 597         .clks = msm8974_clks,
 598         .num_clks = ARRAY_SIZE(msm8974_clks),
 599 };
 600
 601 DEFINE_CLK_SMD_RPM(msm8976, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
 602
 603 static struct clk_smd_rpm *msm8976_clks[] = {
 604         [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
 605         [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
 606         [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
 607         [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk,
 608         [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
 609         [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
 610         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
 611         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
 612         [RPM_SMD_SYSMMNOC_CLK]  = &msm8936_sysmmnoc_clk,
 613         [RPM_SMD_SYSMMNOC_A_CLK] = &msm8936_sysmmnoc_a_clk,
 614         [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
 615         [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
 616         [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
 617         [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
 618         [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
 619         [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
 620         [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
 621         [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
 622         [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
 623         [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
 624         [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
 625         [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
 626         [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
 627         [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
 628         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
 629         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
 630 };
 631
 632 static const struct rpm_smd_clk_desc rpm_clk_msm8976 = {
 633         .clks = msm8976_clks,
 634         .num_clks = ARRAY_SIZE(msm8976_clks),
 635 };
 636
 637 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk3, div_clk3_a, 13, 19200000);
 638 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, ln_bb_clk, ln_bb_a_clk, 8, 19200000);
 639
 640 DEFINE_CLK_SMD_RPM(msm8992, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
 641 DEFINE_CLK_SMD_RPM(msm8992, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1);
 642
 643 DEFINE_CLK_SMD_RPM_BRANCH(msm8992, mss_cfg_ahb_clk, mss_cfg_ahb_a_clk,
 644                           QCOM_SMD_RPM_MCFG_CLK, 0, 19200000);
 645 static struct clk_smd_rpm *msm8992_clks[] = {
 646         [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
 647         [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
 648         [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk,
 649         [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk,
 650         [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk,
 651         [RPM_SMD_OCMEMGX_A_CLK] = &msm8974_ocmemgx_a_clk,
 652         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
 653         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
 654         [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
 655         [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
 656         [RPM_SMD_GFX3D_CLK_SRC] = &msm8974_gfx3d_clk_src,
 657         [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8974_gfx3d_a_clk_src,
 658         [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
 659         [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
 660         [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
 661         [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
 662         [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
 663         [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
 664         [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
 665         [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
 666         [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
 667         [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
 668         [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
 669         [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
 670         [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
 671         [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
 672         [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3,
 673         [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a,
 674         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
 675         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
 676         [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk,
 677         [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
 678         [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk,
 679         [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk,
 680         [RPM_SMD_MSS_CFG_AHB_CLK] = &msm8992_mss_cfg_ahb_clk,
 681         [RPM_SMD_MSS_CFG_AHB_A_CLK] = &msm8992_mss_cfg_ahb_a_clk,
 682         [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
 683         [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
 684         [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
 685         [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
 686         [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
 687         [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
 688         [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
 689         [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
 690         [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
 691         [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
 692         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
 693         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
 694         [RPM_SMD_CE2_CLK] = &msm8992_ce2_clk,
 695         [RPM_SMD_CE2_A_CLK] = &msm8992_ce2_a_clk,
 696 };
 697
 698 static const struct rpm_smd_clk_desc rpm_clk_msm8992 = {
 699         .clks = msm8992_clks,
 700         .num_clks = ARRAY_SIZE(msm8992_clks),
 701 };
 702
 703 DEFINE_CLK_SMD_RPM(msm8994, ce3_clk, ce3_a_clk, QCOM_SMD_RPM_CE_CLK, 2);
 704
 705 static struct clk_smd_rpm *msm8994_clks[] = {
 706         [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
 707         [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
 708         [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk,
 709         [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk,
 710         [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk,
 711         [RPM_SMD_OCMEMGX_A_CLK] = &msm8974_ocmemgx_a_clk,
 712         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
 713         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
 714         [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
 715         [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
 716         [RPM_SMD_GFX3D_CLK_SRC] = &msm8974_gfx3d_clk_src,
 717         [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8974_gfx3d_a_clk_src,
 718         [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
 719         [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
 720         [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
 721         [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
 722         [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
 723         [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
 724         [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
 725         [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
 726         [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
 727         [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
 728         [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
 729         [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
 730         [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
 731         [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
 732         [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3,
 733         [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a,
 734         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
 735         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
 736         [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk,
 737         [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
 738         [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk,
 739         [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk,
 740         [RPM_SMD_MSS_CFG_AHB_CLK] = &msm8992_mss_cfg_ahb_clk,
 741         [RPM_SMD_MSS_CFG_AHB_A_CLK] = &msm8992_mss_cfg_ahb_a_clk,
 742         [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
 743         [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
 744         [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
 745         [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
 746         [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
 747         [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
 748         [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
 749         [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
 750         [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
 751         [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
 752         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
 753         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
 754         [RPM_SMD_CE2_CLK] = &msm8992_ce2_clk,
 755         [RPM_SMD_CE2_A_CLK] = &msm8992_ce2_a_clk,
 756         [RPM_SMD_CE3_CLK] = &msm8994_ce3_clk,
 757         [RPM_SMD_CE3_A_CLK] = &msm8994_ce3_a_clk,
 758 };
 759
 760 static const struct rpm_smd_clk_desc rpm_clk_msm8994 = {
 761         .clks = msm8994_clks,
 762         .num_clks = ARRAY_SIZE(msm8994_clks),
 763 };
 764
 765 DEFINE_CLK_SMD_RPM(msm8996, mmssnoc_axi_rpm_clk, mmssnoc_axi_rpm_a_clk,
 766                    QCOM_SMD_RPM_MMAXI_CLK, 0);
 767 DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre1_noc_clk, aggre1_noc_a_clk,
 768                           QCOM_SMD_RPM_AGGR_CLK, 1, 1000);
 769 DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre2_noc_clk, aggre2_noc_a_clk,
 770                           QCOM_SMD_RPM_AGGR_CLK, 2, 1000);
 771
 772 static struct clk_smd_rpm *msm8996_clks[] = {
 773         [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
 774         [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk,
 775         [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
 776         [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
 777         [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
 778         [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
 779         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
 780         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
 781         [RPM_SMD_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk,
 782         [RPM_SMD_MMAXI_A_CLK] = &msm8996_mmssnoc_axi_rpm_a_clk,
 783         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
 784         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
 785         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
 786         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
 787         [RPM_SMD_AGGR1_NOC_CLK] = &msm8996_aggre1_noc_clk,
 788         [RPM_SMD_AGGR1_NOC_A_CLK] = &msm8996_aggre1_noc_a_clk,
 789         [RPM_SMD_AGGR2_NOC_CLK] = &msm8996_aggre2_noc_clk,
 790         [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8996_aggre2_noc_a_clk,
 791         [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
 792         [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
 793         [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
 794         [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
 795         [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
 796         [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
 797         [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
 798         [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
 799         [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
 800         [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
 801         [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk,
 802         [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
 803         [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
 804         [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
 805         [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
 806         [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
 807         [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3,
 808         [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a,
 809         [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
 810         [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
 811         [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
 812         [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
 813         [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
 814         [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
 815         [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
 816         [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
 817 };
 818
 819 static const struct rpm_smd_clk_desc rpm_clk_msm8996 = {
 820         .clks = msm8996_clks,
 821         .num_clks = ARRAY_SIZE(msm8996_clks),
 822 };
 823
 824 DEFINE_CLK_SMD_RPM(qcs404, bimc_gpu_clk, bimc_gpu_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
 825 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, ln_bb_clk_pin, ln_bb_clk_a_pin, 8, 19200000);
 826
 827 static struct clk_smd_rpm *qcs404_clks[] = {
 828         [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
 829         [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
 830         [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk,
 831         [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk,
 832         [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
 833         [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
 834         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
 835         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
 836         [RPM_SMD_BIMC_GPU_CLK] = &qcs404_bimc_gpu_clk,
 837         [RPM_SMD_BIMC_GPU_A_CLK] = &qcs404_bimc_gpu_a_clk,
 838         [RPM_SMD_QPIC_CLK] = &qcs404_qpic_clk,
 839         [RPM_SMD_QPIC_CLK_A] = &qcs404_qpic_a_clk,
 840         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
 841         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
 842         [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
 843         [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
 844         [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk,
 845         [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
 846 };
 847
 848 static const struct rpm_smd_clk_desc rpm_clk_qcs404 = {
 849         .clks = qcs404_clks,
 850         .num_clks = ARRAY_SIZE(qcs404_clks),
 851 };
 852
 853 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk3, ln_bb_clk3_a, 3, 19200000);
 854 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3_pin, ln_bb_clk3_a_pin, 3, 19200000);
 855 DEFINE_CLK_SMD_RPM(msm8998, aggre1_noc_clk, aggre1_noc_a_clk,
 856                    QCOM_SMD_RPM_AGGR_CLK, 1);
 857 DEFINE_CLK_SMD_RPM(msm8998, aggre2_noc_clk, aggre2_noc_a_clk,
 858                    QCOM_SMD_RPM_AGGR_CLK, 2);
 859 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, rf_clk3, rf_clk3_a, 6, 19200000);
 860 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk3_pin, rf_clk3_a_pin, 6, 19200000);
 861
 862 static struct clk_smd_rpm *msm8998_clks[] = {
 863         [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
 864         [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
 865         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
 866         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
 867         [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
 868         [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk,
 869         [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
 870         [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
 871         [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
 872         [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
 873         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
 874         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
 875         [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
 876         [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
 877         [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
 878         [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
 879         [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3,
 880         [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a,
 881         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
 882         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
 883         [RPM_SMD_LN_BB_CLK1] = &msm8916_bb_clk1,
 884         [RPM_SMD_LN_BB_CLK1_A] = &msm8916_bb_clk1_a,
 885         [RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2,
 886         [RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a,
 887         [RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3,
 888         [RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a,
 889         [RPM_SMD_LN_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
 890         [RPM_SMD_LN_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
 891         [RPM_SMD_LN_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
 892         [RPM_SMD_LN_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
 893         [RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin,
 894         [RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin,
 895         [RPM_SMD_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk,
 896         [RPM_SMD_MMAXI_A_CLK] = &msm8996_mmssnoc_axi_rpm_a_clk,
 897         [RPM_SMD_AGGR1_NOC_CLK] = &msm8998_aggre1_noc_clk,
 898         [RPM_SMD_AGGR1_NOC_A_CLK] = &msm8998_aggre1_noc_a_clk,
 899         [RPM_SMD_AGGR2_NOC_CLK] = &msm8998_aggre2_noc_clk,
 900         [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8998_aggre2_noc_a_clk,
 901         [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
 902         [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
 903         [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
 904         [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
 905         [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
 906         [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
 907         [RPM_SMD_RF_CLK3] = &msm8998_rf_clk3,
 908         [RPM_SMD_RF_CLK3_A] = &msm8998_rf_clk3_a,
 909         [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
 910         [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
 911         [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
 912         [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
 913         [RPM_SMD_RF_CLK3_PIN] = &msm8998_rf_clk3_pin,
 914         [RPM_SMD_RF_CLK3_A_PIN] = &msm8998_rf_clk3_a_pin,
 915 };
 916
 917 static const struct rpm_smd_clk_desc rpm_clk_msm8998 = {
 918         .clks = msm8998_clks,
 919         .num_clks = ARRAY_SIZE(msm8998_clks),
 920 };
 921
 922 static struct clk_smd_rpm *sdm660_clks[] = {
 923         [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
 924         [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
 925         [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
 926         [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
 927         [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
 928         [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
 929         [RPM_SMD_CNOC_PERIPH_CLK] = &msm8916_pcnoc_clk,
 930         [RPM_SMD_CNOC_PERIPH_A_CLK] = &msm8916_pcnoc_a_clk,
 931         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
 932         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
 933         [RPM_SMD_MMSSNOC_AXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk,
 934         [RPM_SMD_MMSSNOC_AXI_CLK_A] = &msm8996_mmssnoc_axi_rpm_a_clk,
 935         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
 936         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
 937         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
 938         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
 939         [RPM_SMD_AGGR2_NOC_CLK] = &msm8998_aggre2_noc_clk,
 940         [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8998_aggre2_noc_a_clk,
 941         [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
 942         [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
 943         [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
 944         [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
 945         [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
 946         [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
 947         [RPM_SMD_LN_BB_CLK] = &msm8916_bb_clk1,
 948         [RPM_SMD_LN_BB_A_CLK] = &msm8916_bb_clk1_a,
 949         [RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2,
 950         [RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a,
 951         [RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3,
 952         [RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a,
 953         [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
 954         [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
 955         [RPM_SMD_LN_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
 956         [RPM_SMD_LN_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
 957         [RPM_SMD_LN_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
 958         [RPM_SMD_LN_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
 959         [RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin,
 960         [RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin,
 961 };
 962
 963 static const struct rpm_smd_clk_desc rpm_clk_sdm660 = {
 964         .clks = sdm660_clks,
 965         .num_clks = ARRAY_SIZE(sdm660_clks),
 966 };
 967
 968 static struct clk_smd_rpm *mdm9607_clks[] = {
 969         [RPM_SMD_XO_CLK_SRC]            = &sdm660_bi_tcxo,
 970         [RPM_SMD_XO_A_CLK_SRC]          = &sdm660_bi_tcxo_a,
 971         [RPM_SMD_PCNOC_CLK]             = &msm8916_pcnoc_clk,
 972         [RPM_SMD_PCNOC_A_CLK]           = &msm8916_pcnoc_a_clk,
 973         [RPM_SMD_BIMC_CLK]              = &msm8916_bimc_clk,
 974         [RPM_SMD_BIMC_A_CLK]            = &msm8916_bimc_a_clk,
 975         [RPM_SMD_QPIC_CLK]              = &qcs404_qpic_clk,
 976         [RPM_SMD_QPIC_CLK_A]            = &qcs404_qpic_a_clk,
 977         [RPM_SMD_QDSS_CLK]              = &msm8916_qdss_clk,
 978         [RPM_SMD_QDSS_A_CLK]            = &msm8916_qdss_a_clk,
 979         [RPM_SMD_BB_CLK1]               = &msm8916_bb_clk1,
 980         [RPM_SMD_BB_CLK1_A]             = &msm8916_bb_clk1_a,
 981         [RPM_SMD_BB_CLK1_PIN]           = &msm8916_bb_clk1_pin,
 982         [RPM_SMD_BB_CLK1_A_PIN]         = &msm8916_bb_clk1_a_pin,
 983 };
 984
 985 static const struct rpm_smd_clk_desc rpm_clk_mdm9607 = {
 986         .clks = mdm9607_clks,
 987         .num_clks = ARRAY_SIZE(mdm9607_clks),
 988 };
 989
 990 static struct clk_smd_rpm *msm8953_clks[] = {
 991         [RPM_SMD_XO_CLK_SRC]            = &sdm660_bi_tcxo,
 992         [RPM_SMD_XO_A_CLK_SRC]          = &sdm660_bi_tcxo_a,
 993         [RPM_SMD_PCNOC_CLK]             = &msm8916_pcnoc_clk,
 994         [RPM_SMD_PCNOC_A_CLK]           = &msm8916_pcnoc_a_clk,
 995         [RPM_SMD_SNOC_CLK]              = &msm8916_snoc_clk,
 996         [RPM_SMD_SNOC_A_CLK]            = &msm8916_snoc_a_clk,
 997         [RPM_SMD_BIMC_CLK]              = &msm8916_bimc_clk,
 998         [RPM_SMD_BIMC_A_CLK]            = &msm8916_bimc_a_clk,
 999         [RPM_SMD_IPA_CLK]               = &msm8976_ipa_clk,
1000         [RPM_SMD_IPA_A_CLK]             = &msm8976_ipa_a_clk,
1001         [RPM_SMD_SYSMMNOC_CLK]          = &msm8936_sysmmnoc_clk,
1002         [RPM_SMD_SYSMMNOC_A_CLK]        = &msm8936_sysmmnoc_a_clk,
1003         [RPM_SMD_QDSS_CLK]              = &msm8916_qdss_clk,
1004         [RPM_SMD_QDSS_A_CLK]            = &msm8916_qdss_a_clk,
1005         [RPM_SMD_BB_CLK1]               = &msm8916_bb_clk1,
1006         [RPM_SMD_BB_CLK1_A]             = &msm8916_bb_clk1_a,
1007         [RPM_SMD_BB_CLK2]               = &msm8916_bb_clk2,
1008         [RPM_SMD_BB_CLK2_A]             = &msm8916_bb_clk2_a,
1009         [RPM_SMD_RF_CLK2]               = &msm8916_rf_clk2,
1010         [RPM_SMD_RF_CLK2_A]             = &msm8916_rf_clk2_a,
1011         [RPM_SMD_RF_CLK3]               = &msm8992_ln_bb_clk,
1012         [RPM_SMD_RF_CLK3_A]             = &msm8992_ln_bb_a_clk,
1013         [RPM_SMD_DIV_CLK2]              = &msm8974_div_clk2,
1014         [RPM_SMD_DIV_A_CLK2]            = &msm8974_div_a_clk2,
1015         [RPM_SMD_BB_CLK1_PIN]           = &msm8916_bb_clk1_pin,
1016         [RPM_SMD_BB_CLK1_A_PIN]         = &msm8916_bb_clk1_a_pin,
1017         [RPM_SMD_BB_CLK2_PIN]           = &msm8916_bb_clk2_pin,
1018         [RPM_SMD_BB_CLK2_A_PIN]         = &msm8916_bb_clk2_a_pin,
1019 };
1020
1021 static const struct rpm_smd_clk_desc rpm_clk_msm8953 = {
1022         .clks = msm8953_clks,
1023         .num_clks = ARRAY_SIZE(msm8953_clks),
1024 };
1025
1026 /* SM6125 */
1027 DEFINE_CLK_SMD_RPM(sm6125, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
1028 DEFINE_CLK_SMD_RPM(sm6125, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
1029 DEFINE_CLK_SMD_RPM_BRANCH(sm6125, qdss_clk, qdss_a_clk,
1030                                         QCOM_SMD_RPM_MISC_CLK, 1, 19200000);
1031 DEFINE_CLK_SMD_RPM(sm6125, qup_clk, qup_a_clk, QCOM_SMD_RPM_QUP_CLK, 0);
1032 DEFINE_CLK_SMD_RPM(sm6125, mmnrt_clk, mmnrt_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 0);
1033 DEFINE_CLK_SMD_RPM(sm6125, mmrt_clk, mmrt_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 1);
1034 DEFINE_CLK_SMD_RPM(sm6125, snoc_periph_clk, snoc_periph_a_clk,
1035                                                 QCOM_SMD_RPM_BUS_CLK, 0);
1036 DEFINE_CLK_SMD_RPM(sm6125, snoc_lpass_clk, snoc_lpass_a_clk,
1037                                                 QCOM_SMD_RPM_BUS_CLK, 5);
1038
1039 static struct clk_smd_rpm *sm6125_clks[] = {
1040         [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
1041         [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
1042         [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk,
1043         [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk,
1044         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
1045         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
1046         [RPM_SMD_QDSS_CLK] = &sm6125_qdss_clk,
1047         [RPM_SMD_QDSS_A_CLK] = &sm6125_qdss_a_clk,
1048         [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
1049         [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
1050         [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
1051         [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
1052         [RPM_SMD_CNOC_CLK] = &sm6125_cnoc_clk,
1053         [RPM_SMD_CNOC_A_CLK] = &sm6125_cnoc_a_clk,
1054         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
1055         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
1056         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
1057         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
1058         [RPM_SMD_LN_BB_CLK1] = &msm8916_bb_clk1,
1059         [RPM_SMD_LN_BB_CLK1_A] = &msm8916_bb_clk1_a,
1060         [RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2,
1061         [RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a,
1062         [RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3,
1063         [RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a,
1064         [RPM_SMD_QUP_CLK] = &sm6125_qup_clk,
1065         [RPM_SMD_QUP_A_CLK] = &sm6125_qup_a_clk,
1066         [RPM_SMD_MMRT_CLK] = &sm6125_mmrt_clk,
1067         [RPM_SMD_MMRT_A_CLK] = &sm6125_mmrt_a_clk,
1068         [RPM_SMD_MMNRT_CLK] = &sm6125_mmnrt_clk,
1069         [RPM_SMD_MMNRT_A_CLK] = &sm6125_mmnrt_a_clk,
1070         [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_snoc_periph_clk,
1071         [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_snoc_periph_a_clk,
1072         [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_snoc_lpass_clk,
1073         [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_snoc_lpass_a_clk,
1074 };
1075
1076 static const struct rpm_smd_clk_desc rpm_clk_sm6125 = {
1077         .clks = sm6125_clks,
1078         .num_clks = ARRAY_SIZE(sm6125_clks),
1079 };
1080
1081 /* SM6115 */
1082 static struct clk_smd_rpm *sm6115_clks[] = {
1083         [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
1084         [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
1085         [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk,
1086         [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk,
1087         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
1088         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
1089         [RPM_SMD_QDSS_CLK] = &sm6125_qdss_clk,
1090         [RPM_SMD_QDSS_A_CLK] = &sm6125_qdss_a_clk,
1091         [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
1092         [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
1093         [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
1094         [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
1095         [RPM_SMD_CNOC_CLK] = &sm6125_cnoc_clk,
1096         [RPM_SMD_CNOC_A_CLK] = &sm6125_cnoc_a_clk,
1097         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
1098         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
1099         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
1100         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
1101         [RPM_SMD_QUP_CLK] = &sm6125_qup_clk,
1102         [RPM_SMD_QUP_A_CLK] = &sm6125_qup_a_clk,
1103         [RPM_SMD_MMRT_CLK] = &sm6125_mmrt_clk,
1104         [RPM_SMD_MMRT_A_CLK] = &sm6125_mmrt_a_clk,
1105         [RPM_SMD_MMNRT_CLK] = &sm6125_mmnrt_clk,
1106         [RPM_SMD_MMNRT_A_CLK] = &sm6125_mmnrt_a_clk,
1107         [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_snoc_periph_clk,
1108         [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_snoc_periph_a_clk,
1109         [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_snoc_lpass_clk,
1110         [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_snoc_lpass_a_clk,
1111         [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
1112         [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
1113         [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
1114         [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
1115 };
1116
1117 static const struct rpm_smd_clk_desc rpm_clk_sm6115 = {
1118         .clks = sm6115_clks,
1119         .num_clks = ARRAY_SIZE(sm6115_clks),
1120 };
1121
1122 /* SM6375 */
1123 DEFINE_CLK_SMD_RPM(sm6375, mmnrt_clk, mmnrt_a_clk, QCOM_SMD_RPM_MMXI_CLK, 0);
1124 DEFINE_CLK_SMD_RPM(sm6375, mmrt_clk, mmrt_a_clk, QCOM_SMD_RPM_MMXI_CLK, 1);
1125 DEFINE_CLK_SMD_RPM(qcm2290, hwkm_clk, hwkm_a_clk, QCOM_SMD_RPM_HWKM_CLK, 0);
1126 DEFINE_CLK_SMD_RPM(qcm2290, pka_clk, pka_a_clk, QCOM_SMD_RPM_PKA_CLK, 0);
1127 DEFINE_CLK_SMD_RPM_BRANCH(sm6375, bimc_freq_log, bimc_freq_log_a, QCOM_SMD_RPM_MISC_CLK, 4, 1);
1128 static struct clk_smd_rpm *sm6375_clks[] = {
1129         [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
1130         [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
1131         [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk,
1132         [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk,
1133         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
1134         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
1135         [RPM_SMD_QDSS_CLK] = &sm6125_qdss_clk,
1136         [RPM_SMD_QDSS_A_CLK] = &sm6125_qdss_a_clk,
1137         [RPM_SMD_CNOC_CLK] = &sm6125_cnoc_clk,
1138         [RPM_SMD_CNOC_A_CLK] = &sm6125_cnoc_a_clk,
1139         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
1140         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
1141         [RPM_SMD_QUP_CLK] = &sm6125_qup_clk,
1142         [RPM_SMD_QUP_A_CLK] = &sm6125_qup_a_clk,
1143         [RPM_SMD_MMRT_CLK] = &sm6375_mmrt_clk,
1144         [RPM_SMD_MMRT_A_CLK] = &sm6375_mmrt_a_clk,
1145         [RPM_SMD_MMNRT_CLK] = &sm6375_mmnrt_clk,
1146         [RPM_SMD_MMNRT_A_CLK] = &sm6375_mmnrt_a_clk,
1147         [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_snoc_periph_clk,
1148         [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_snoc_periph_a_clk,
1149         [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_snoc_lpass_clk,
1150         [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_snoc_lpass_a_clk,
1151         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
1152         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
1153         [RPM_SMD_HWKM_CLK] = &qcm2290_hwkm_clk,
1154         [RPM_SMD_HWKM_A_CLK] = &qcm2290_hwkm_a_clk,
1155         [RPM_SMD_PKA_CLK] = &qcm2290_pka_clk,
1156         [RPM_SMD_PKA_A_CLK] = &qcm2290_pka_a_clk,
1157         [RPM_SMD_BIMC_FREQ_LOG] = &sm6375_bimc_freq_log,
1158 };
1159
1160 static const struct rpm_smd_clk_desc rpm_clk_sm6375 = {
1161         .clks = sm6375_clks,
1162         .num_clks = ARRAY_SIZE(sm6375_clks),
1163 };
1164
1165 /* QCM2290 */
1166 DEFINE_CLK_SMD_RPM_XO_BUFFER(qcm2290, ln_bb_clk2, ln_bb_clk2_a, 0x2, 19200000);
1167 DEFINE_CLK_SMD_RPM_XO_BUFFER(qcm2290, rf_clk3, rf_clk3_a, 6, 38400000);
1168
1169 DEFINE_CLK_SMD_RPM(qcm2290, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0);
1170 DEFINE_CLK_SMD_RPM(qcm2290, cpuss_gnoc_clk, cpuss_gnoc_a_clk,
1171                    QCOM_SMD_RPM_MEM_CLK, 1);
1172 DEFINE_CLK_SMD_RPM(qcm2290, bimc_gpu_clk, bimc_gpu_a_clk,
1173                    QCOM_SMD_RPM_MEM_CLK, 2);
1174
1175 static struct clk_smd_rpm *qcm2290_clks[] = {
1176         [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
1177         [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
1178         [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk,
1179         [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk,
1180         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
1181         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
1182         [RPM_SMD_QDSS_CLK] = &sm6125_qdss_clk,
1183         [RPM_SMD_QDSS_A_CLK] = &sm6125_qdss_a_clk,
1184         [RPM_SMD_LN_BB_CLK2] = &qcm2290_ln_bb_clk2,
1185         [RPM_SMD_LN_BB_CLK2_A] = &qcm2290_ln_bb_clk2_a,
1186         [RPM_SMD_RF_CLK3] = &qcm2290_rf_clk3,
1187         [RPM_SMD_RF_CLK3_A] = &qcm2290_rf_clk3_a,
1188         [RPM_SMD_CNOC_CLK] = &sm6125_cnoc_clk,
1189         [RPM_SMD_CNOC_A_CLK] = &sm6125_cnoc_a_clk,
1190         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
1191         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
1192         [RPM_SMD_QUP_CLK] = &sm6125_qup_clk,
1193         [RPM_SMD_QUP_A_CLK] = &sm6125_qup_a_clk,
1194         [RPM_SMD_MMRT_CLK] = &sm6125_mmrt_clk,
1195         [RPM_SMD_MMRT_A_CLK] = &sm6125_mmrt_a_clk,
1196         [RPM_SMD_MMNRT_CLK] = &sm6125_mmnrt_clk,
1197         [RPM_SMD_MMNRT_A_CLK] = &sm6125_mmnrt_a_clk,
1198         [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_snoc_periph_clk,
1199         [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_snoc_periph_a_clk,
1200         [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_snoc_lpass_clk,
1201         [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_snoc_lpass_a_clk,
1202         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
1203         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
1204         [RPM_SMD_QPIC_CLK] = &qcm2290_qpic_clk,
1205         [RPM_SMD_QPIC_CLK_A] = &qcm2290_qpic_a_clk,
1206         [RPM_SMD_HWKM_CLK] = &qcm2290_hwkm_clk,
1207         [RPM_SMD_HWKM_A_CLK] = &qcm2290_hwkm_a_clk,
1208         [RPM_SMD_PKA_CLK] = &qcm2290_pka_clk,
1209         [RPM_SMD_PKA_A_CLK] = &qcm2290_pka_a_clk,
1210         [RPM_SMD_BIMC_GPU_CLK] = &qcm2290_bimc_gpu_clk,
1211         [RPM_SMD_BIMC_GPU_A_CLK] = &qcm2290_bimc_gpu_a_clk,
1212         [RPM_SMD_CPUSS_GNOC_CLK] = &qcm2290_cpuss_gnoc_clk,
1213         [RPM_SMD_CPUSS_GNOC_A_CLK] = &qcm2290_cpuss_gnoc_a_clk,
1214 };
1215
1216 static const struct rpm_smd_clk_desc rpm_clk_qcm2290 = {
1217         .clks = qcm2290_clks,
1218         .num_clks = ARRAY_SIZE(qcm2290_clks),
1219 };
1220
1221 static const struct of_device_id rpm_smd_clk_match_table[] = {
1222         { .compatible = "qcom,rpmcc-mdm9607", .data = &rpm_clk_mdm9607 },
1223         { .compatible = "qcom,rpmcc-msm8226", .data = &rpm_clk_msm8974 },
1224         { .compatible = "qcom,rpmcc-msm8909", .data = &rpm_clk_msm8909 },
1225         { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
1226         { .compatible = "qcom,rpmcc-msm8936", .data = &rpm_clk_msm8936 },
1227         { .compatible = "qcom,rpmcc-msm8953", .data = &rpm_clk_msm8953 },
1228         { .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 },
1229         { .compatible = "qcom,rpmcc-msm8976", .data = &rpm_clk_msm8976 },
1230         { .compatible = "qcom,rpmcc-msm8992", .data = &rpm_clk_msm8992 },
1231         { .compatible = "qcom,rpmcc-msm8994", .data = &rpm_clk_msm8994 },
1232         { .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 },
1233         { .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 },
1234         { .compatible = "qcom,rpmcc-qcm2290", .data = &rpm_clk_qcm2290 },
1235         { .compatible = "qcom,rpmcc-qcs404",  .data = &rpm_clk_qcs404  },
1236         { .compatible = "qcom,rpmcc-sdm660",  .data = &rpm_clk_sdm660  },
1237         { .compatible = "qcom,rpmcc-sm6115",  .data = &rpm_clk_sm6115  },
1238         { .compatible = "qcom,rpmcc-sm6125",  .data = &rpm_clk_sm6125  },
1239         { .compatible = "qcom,rpmcc-sm6375",  .data = &rpm_clk_sm6375  },
1240         { }
1241 };
1242 MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
1243
1244 static struct clk_hw *qcom_smdrpm_clk_hw_get(struct of_phandle_args *clkspec,
1245                                              void *data)
1246 {
1247         const struct rpm_smd_clk_desc *desc = data;
1248         unsigned int idx = clkspec->args[0];
1249
1250         if (idx >= desc->num_clks) {
1251                 pr_err("%s: invalid index %u\n", __func__, idx);
1252                 return ERR_PTR(-EINVAL);
1253         }
1254
1255         return desc->clks[idx] ? &desc->clks[idx]->hw : ERR_PTR(-ENOENT);
1256 }
1257
1258 static int rpm_smd_clk_probe(struct platform_device *pdev)
1259 {
1260         int ret;
1261         size_t num_clks, i;
1262         struct qcom_smd_rpm *rpm;
1263         struct clk_smd_rpm **rpm_smd_clks;
1264         const struct rpm_smd_clk_desc *desc;
1265
1266         rpm = dev_get_drvdata(pdev->dev.parent);
1267         if (!rpm) {
1268                 dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
1269                 return -ENODEV;
1270         }
1271
1272         desc = of_device_get_match_data(&pdev->dev);
1273         if (!desc)
1274                 return -EINVAL;
1275
1276         rpm_smd_clks = desc->clks;
1277         num_clks = desc->num_clks;
1278
1279         for (i = 0; i < num_clks; i++) {
1280                 if (!rpm_smd_clks[i])
1281                         continue;
1282
1283                 rpm_smd_clks[i]->rpm = rpm;
1284
1285                 ret = clk_smd_rpm_handoff(rpm_smd_clks[i]);
1286                 if (ret)
1287                         goto err;
1288         }
1289
1290         ret = clk_smd_rpm_enable_scaling(rpm);
1291         if (ret)
1292                 goto err;
1293
1294         for (i = 0; i < num_clks; i++) {
1295                 if (!rpm_smd_clks[i])
1296                         continue;
1297
1298                 ret = devm_clk_hw_register(&pdev->dev, &rpm_smd_clks[i]->hw);
1299                 if (ret)
1300                         goto err;
1301         }
1302
1303         ret = devm_of_clk_add_hw_provider(&pdev->dev, qcom_smdrpm_clk_hw_get,
1304                                           (void *)desc);
1305         if (ret)
1306                 goto err;
1307
1308         return 0;
1309 err:
1310         dev_err(&pdev->dev, "Error registering SMD clock driver (%d)\n", ret);
1311         return ret;
1312 }
1313
1314 static struct platform_driver rpm_smd_clk_driver = {
1315         .driver = {
1316                 .name = "qcom-clk-smd-rpm",
1317                 .of_match_table = rpm_smd_clk_match_table,
1318         },
1319         .probe = rpm_smd_clk_probe,
1320 };
1321
1322 static int __init rpm_smd_clk_init(void)
1323 {
1324         return platform_driver_register(&rpm_smd_clk_driver);
1325 }
1326 core_initcall(rpm_smd_clk_init);
1327
1328 static void __exit rpm_smd_clk_exit(void)
1329 {
1330         platform_driver_unregister(&rpm_smd_clk_driver);
1331 }
1332 module_exit(rpm_smd_clk_exit);
1333
1334 MODULE_DESCRIPTION("Qualcomm RPM over SMD Clock Controller Driver");
1335 MODULE_LICENSE("GPL v2");
1336 MODULE_ALIAS("platform:qcom-clk-smd-rpm");