1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2013, 2018, The Linux Foundation. All rights reserved. */
4 #ifndef __QCOM_CLK_RCG_H__
5 #define __QCOM_CLK_RCG_H__
7 #include <linux/clk-provider.h>
8 #include "clk-regmap.h"
10 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
21 * struct mn - M/N:D counter
22 * @mnctr_en_bit: bit to enable mn counter
23 * @mnctr_reset_bit: bit to assert mn counter reset
24 * @mnctr_mode_shift: lowest bit of mn counter mode field
25 * @n_val_shift: lowest bit of n value field
26 * @m_val_shift: lowest bit of m value field
27 * @width: number of bits in m/n/d values
28 * @reset_in_cc: true if the mnctr_reset_bit is in the CC register
34 #define MNCTR_MODE_DUAL 0x2
35 #define MNCTR_MODE_MASK 0x3
43 * struct pre_div - pre-divider
44 * @pre_div_shift: lowest bit of pre divider field
45 * @pre_div_width: number of bits in predivider
53 * struct src_sel - source selector
54 * @src_sel_shift: lowest bit of source selection field
55 * @parent_map: map from software's parent index to hardware's src_sel field
59 #define SRC_SEL_MASK 0x7
60 const struct parent_map *parent_map;
64 * struct clk_rcg - root clock generator
66 * @ns_reg: NS register
67 * @md_reg: MD register
71 * @freq_tbl: frequency table
72 * @clkr: regmap clock handle
73 * @lock: register lock
83 const struct freq_tbl *freq_tbl;
85 struct clk_regmap clkr;
88 extern const struct clk_ops clk_rcg_ops;
89 extern const struct clk_ops clk_rcg_floor_ops;
90 extern const struct clk_ops clk_rcg_bypass_ops;
91 extern const struct clk_ops clk_rcg_bypass2_ops;
92 extern const struct clk_ops clk_rcg_pixel_ops;
93 extern const struct clk_ops clk_rcg_esc_ops;
94 extern const struct clk_ops clk_rcg_lcc_ops;
96 #define to_clk_rcg(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg, clkr)
99 * struct clk_dyn_rcg - root clock generator with glitch free mux
101 * @mux_sel_bit: bit to switch glitch free mux
102 * @ns_reg: NS0 and NS1 register
103 * @md_reg: MD0 and MD1 register
104 * @bank_reg: register to XOR @mux_sel_bit into to switch glitch free mux
105 * @mn: mn counter (banked)
106 * @s: source selector (banked)
107 * @freq_tbl: frequency table
108 * @clkr: regmap clock handle
109 * @lock: register lock
122 const struct freq_tbl *freq_tbl;
124 struct clk_regmap clkr;
127 extern const struct clk_ops clk_dyn_rcg_ops;
129 #define to_clk_dyn_rcg(_hw) \
130 container_of(to_clk_regmap(_hw), struct clk_dyn_rcg, clkr)
133 * struct clk_rcg2 - root clock generator
135 * @cmd_rcgr: corresponds to *_CMD_RCGR
136 * @mnd_width: number of bits in m/n/d values
137 * @hid_width: number of bits in half integer divider
138 * @safe_src_index: safe src index value
139 * @parent_map: map from software's parent index to hardware's src_sel field
140 * @freq_tbl: frequency table
141 * @clkr: regmap clock handle
142 * @cfg_off: defines the cfg register offset from the CMD_RCGR + CFG_REG
143 * @parked_cfg: cached value of the CFG register for parked RCGs
150 const struct parent_map *parent_map;
151 const struct freq_tbl *freq_tbl;
152 struct clk_regmap clkr;
157 #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr)
159 struct clk_rcg2_gfx3d {
165 #define to_clk_rcg2_gfx3d(_hw) \
166 container_of(to_clk_rcg2(_hw), struct clk_rcg2_gfx3d, rcg)
168 extern const struct clk_ops clk_rcg2_ops;
169 extern const struct clk_ops clk_rcg2_floor_ops;
170 extern const struct clk_ops clk_edp_pixel_ops;
171 extern const struct clk_ops clk_byte_ops;
172 extern const struct clk_ops clk_byte2_ops;
173 extern const struct clk_ops clk_pixel_ops;
174 extern const struct clk_ops clk_gfx3d_ops;
175 extern const struct clk_ops clk_rcg2_shared_ops;
176 extern const struct clk_ops clk_dp_ops;
178 struct clk_rcg_dfs_data {
179 struct clk_rcg2 *rcg;
180 struct clk_init_data *init;
183 #define DEFINE_RCG_DFS(r) \
184 { .rcg = &r, .init = &r##_init }
186 extern int qcom_cc_register_rcg_dfs(struct regmap *regmap,
187 const struct clk_rcg_dfs_data *rcgs,