1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
7 #include <linux/kernel.h>
8 #include <linux/export.h>
9 #include <linux/clk-provider.h>
10 #include <linux/regmap.h>
11 #include <linux/delay.h>
13 #include "clk-alpha-pll.h"
16 #define PLL_MODE(p) ((p)->offset + 0x0)
17 # define PLL_OUTCTRL BIT(0)
18 # define PLL_BYPASSNL BIT(1)
19 # define PLL_RESET_N BIT(2)
20 # define PLL_OFFLINE_REQ BIT(7)
21 # define PLL_LOCK_COUNT_SHIFT 8
22 # define PLL_LOCK_COUNT_MASK 0x3f
23 # define PLL_BIAS_COUNT_SHIFT 14
24 # define PLL_BIAS_COUNT_MASK 0x3f
25 # define PLL_VOTE_FSM_ENA BIT(20)
26 # define PLL_FSM_ENA BIT(20)
27 # define PLL_VOTE_FSM_RESET BIT(21)
28 # define PLL_UPDATE BIT(22)
29 # define PLL_UPDATE_BYPASS BIT(23)
30 # define PLL_FSM_LEGACY_MODE BIT(24)
31 # define PLL_OFFLINE_ACK BIT(28)
32 # define ALPHA_PLL_ACK_LATCH BIT(29)
33 # define PLL_ACTIVE_FLAG BIT(30)
34 # define PLL_LOCK_DET BIT(31)
36 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
37 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
38 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
39 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
41 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
42 # define PLL_POST_DIV_SHIFT 8
43 # define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0)
44 # define PLL_ALPHA_EN BIT(24)
45 # define PLL_ALPHA_MODE BIT(25)
46 # define PLL_VCO_SHIFT 20
47 # define PLL_VCO_MASK 0x3
49 #define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U])
50 #define PLL_USER_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1])
52 #define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
53 #define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
54 #define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1])
55 #define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
56 #define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
57 #define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
58 #define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS])
59 #define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
60 #define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC])
62 const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
63 [CLK_ALPHA_PLL_TYPE_DEFAULT] = {
64 [PLL_OFF_L_VAL] = 0x04,
65 [PLL_OFF_ALPHA_VAL] = 0x08,
66 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
67 [PLL_OFF_USER_CTL] = 0x10,
68 [PLL_OFF_USER_CTL_U] = 0x14,
69 [PLL_OFF_CONFIG_CTL] = 0x18,
70 [PLL_OFF_TEST_CTL] = 0x1c,
71 [PLL_OFF_TEST_CTL_U] = 0x20,
72 [PLL_OFF_STATUS] = 0x24,
74 [CLK_ALPHA_PLL_TYPE_HUAYRA] = {
75 [PLL_OFF_L_VAL] = 0x04,
76 [PLL_OFF_ALPHA_VAL] = 0x08,
77 [PLL_OFF_USER_CTL] = 0x10,
78 [PLL_OFF_CONFIG_CTL] = 0x14,
79 [PLL_OFF_CONFIG_CTL_U] = 0x18,
80 [PLL_OFF_TEST_CTL] = 0x1c,
81 [PLL_OFF_TEST_CTL_U] = 0x20,
82 [PLL_OFF_STATUS] = 0x24,
84 [CLK_ALPHA_PLL_TYPE_BRAMMO] = {
85 [PLL_OFF_L_VAL] = 0x04,
86 [PLL_OFF_ALPHA_VAL] = 0x08,
87 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
88 [PLL_OFF_USER_CTL] = 0x10,
89 [PLL_OFF_CONFIG_CTL] = 0x18,
90 [PLL_OFF_TEST_CTL] = 0x1c,
91 [PLL_OFF_STATUS] = 0x24,
93 [CLK_ALPHA_PLL_TYPE_FABIA] = {
94 [PLL_OFF_L_VAL] = 0x04,
95 [PLL_OFF_USER_CTL] = 0x0c,
96 [PLL_OFF_USER_CTL_U] = 0x10,
97 [PLL_OFF_CONFIG_CTL] = 0x14,
98 [PLL_OFF_CONFIG_CTL_U] = 0x18,
99 [PLL_OFF_TEST_CTL] = 0x1c,
100 [PLL_OFF_TEST_CTL_U] = 0x20,
101 [PLL_OFF_STATUS] = 0x24,
102 [PLL_OFF_OPMODE] = 0x2c,
103 [PLL_OFF_FRAC] = 0x38,
105 [CLK_ALPHA_PLL_TYPE_TRION] = {
106 [PLL_OFF_L_VAL] = 0x04,
107 [PLL_OFF_CAL_L_VAL] = 0x08,
108 [PLL_OFF_USER_CTL] = 0x0c,
109 [PLL_OFF_USER_CTL_U] = 0x10,
110 [PLL_OFF_USER_CTL_U1] = 0x14,
111 [PLL_OFF_CONFIG_CTL] = 0x18,
112 [PLL_OFF_CONFIG_CTL_U] = 0x1c,
113 [PLL_OFF_CONFIG_CTL_U1] = 0x20,
114 [PLL_OFF_TEST_CTL] = 0x24,
115 [PLL_OFF_TEST_CTL_U] = 0x28,
116 [PLL_OFF_TEST_CTL_U1] = 0x2c,
117 [PLL_OFF_STATUS] = 0x30,
118 [PLL_OFF_OPMODE] = 0x38,
119 [PLL_OFF_ALPHA_VAL] = 0x40,
121 [CLK_ALPHA_PLL_TYPE_AGERA] = {
122 [PLL_OFF_L_VAL] = 0x04,
123 [PLL_OFF_ALPHA_VAL] = 0x08,
124 [PLL_OFF_USER_CTL] = 0x0c,
125 [PLL_OFF_CONFIG_CTL] = 0x10,
126 [PLL_OFF_CONFIG_CTL_U] = 0x14,
127 [PLL_OFF_TEST_CTL] = 0x18,
128 [PLL_OFF_TEST_CTL_U] = 0x1c,
129 [PLL_OFF_STATUS] = 0x2c,
131 [CLK_ALPHA_PLL_TYPE_ZONDA] = {
132 [PLL_OFF_L_VAL] = 0x04,
133 [PLL_OFF_ALPHA_VAL] = 0x08,
134 [PLL_OFF_USER_CTL] = 0x0c,
135 [PLL_OFF_CONFIG_CTL] = 0x10,
136 [PLL_OFF_CONFIG_CTL_U] = 0x14,
137 [PLL_OFF_CONFIG_CTL_U1] = 0x18,
138 [PLL_OFF_TEST_CTL] = 0x1c,
139 [PLL_OFF_TEST_CTL_U] = 0x20,
140 [PLL_OFF_TEST_CTL_U1] = 0x24,
141 [PLL_OFF_OPMODE] = 0x28,
142 [PLL_OFF_STATUS] = 0x38,
144 [CLK_ALPHA_PLL_TYPE_LUCID_EVO] = {
145 [PLL_OFF_OPMODE] = 0x04,
146 [PLL_OFF_STATUS] = 0x0c,
147 [PLL_OFF_L_VAL] = 0x10,
148 [PLL_OFF_ALPHA_VAL] = 0x14,
149 [PLL_OFF_USER_CTL] = 0x18,
150 [PLL_OFF_USER_CTL_U] = 0x1c,
151 [PLL_OFF_CONFIG_CTL] = 0x20,
152 [PLL_OFF_CONFIG_CTL_U] = 0x24,
153 [PLL_OFF_CONFIG_CTL_U1] = 0x28,
154 [PLL_OFF_TEST_CTL] = 0x2c,
155 [PLL_OFF_TEST_CTL_U] = 0x30,
156 [PLL_OFF_TEST_CTL_U1] = 0x34,
158 [CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = {
159 [PLL_OFF_OPMODE] = 0x04,
160 [PLL_OFF_STATUS] = 0x0c,
161 [PLL_OFF_L_VAL] = 0x10,
162 [PLL_OFF_USER_CTL] = 0x14,
163 [PLL_OFF_USER_CTL_U] = 0x18,
164 [PLL_OFF_CONFIG_CTL] = 0x1c,
165 [PLL_OFF_CONFIG_CTL_U] = 0x20,
166 [PLL_OFF_CONFIG_CTL_U1] = 0x24,
167 [PLL_OFF_TEST_CTL] = 0x28,
168 [PLL_OFF_TEST_CTL_U] = 0x2c,
170 [CLK_ALPHA_PLL_TYPE_DEFAULT_EVO] = {
171 [PLL_OFF_L_VAL] = 0x04,
172 [PLL_OFF_ALPHA_VAL] = 0x08,
173 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
174 [PLL_OFF_TEST_CTL] = 0x10,
175 [PLL_OFF_TEST_CTL_U] = 0x14,
176 [PLL_OFF_USER_CTL] = 0x18,
177 [PLL_OFF_USER_CTL_U] = 0x1c,
178 [PLL_OFF_CONFIG_CTL] = 0x20,
179 [PLL_OFF_STATUS] = 0x24,
181 [CLK_ALPHA_PLL_TYPE_BRAMMO_EVO] = {
182 [PLL_OFF_L_VAL] = 0x04,
183 [PLL_OFF_ALPHA_VAL] = 0x08,
184 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
185 [PLL_OFF_TEST_CTL] = 0x10,
186 [PLL_OFF_TEST_CTL_U] = 0x14,
187 [PLL_OFF_USER_CTL] = 0x18,
188 [PLL_OFF_CONFIG_CTL] = 0x1C,
189 [PLL_OFF_STATUS] = 0x20,
192 EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
195 * Even though 40 bits are present, use only 32 for ease of calculation.
197 #define ALPHA_REG_BITWIDTH 40
198 #define ALPHA_REG_16BIT_WIDTH 16
199 #define ALPHA_BITWIDTH 32U
200 #define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH)
202 #define PLL_HUAYRA_M_WIDTH 8
203 #define PLL_HUAYRA_M_SHIFT 8
204 #define PLL_HUAYRA_M_MASK 0xff
205 #define PLL_HUAYRA_N_SHIFT 0
206 #define PLL_HUAYRA_N_MASK 0xff
207 #define PLL_HUAYRA_ALPHA_WIDTH 16
209 #define PLL_STANDBY 0x0
211 #define PLL_OUT_MASK 0x7
212 #define PLL_RATE_MARGIN 500
214 /* TRION PLL specific settings and offsets */
215 #define TRION_PLL_CAL_VAL 0x44
216 #define TRION_PCAL_DONE BIT(26)
218 /* LUCID PLL specific settings and offsets */
219 #define LUCID_PCAL_DONE BIT(27)
221 /* LUCID 5LPE PLL specific settings and offsets */
222 #define LUCID_5LPE_PCAL_DONE BIT(11)
223 #define LUCID_5LPE_ALPHA_PLL_ACK_LATCH BIT(13)
224 #define LUCID_5LPE_PLL_LATCH_INPUT BIT(14)
225 #define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21)
227 /* LUCID EVO PLL specific settings and offsets */
228 #define LUCID_EVO_PCAL_NOT_DONE BIT(8)
229 #define LUCID_EVO_ENABLE_VOTE_RUN BIT(25)
230 #define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0)
231 #define LUCID_EVO_PLL_CAL_L_VAL_SHIFT 16
233 /* ZONDA PLL specific */
234 #define ZONDA_PLL_OUT_MASK 0xf
235 #define ZONDA_STAY_IN_CFA BIT(16)
236 #define ZONDA_PLL_FREQ_LOCK_DET BIT(29)
238 #define pll_alpha_width(p) \
239 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
240 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
242 #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4)
244 #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \
245 struct clk_alpha_pll, clkr)
247 #define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \
248 struct clk_alpha_pll_postdiv, clkr)
250 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
256 const char *name = clk_hw_get_name(&pll->clkr.hw);
258 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
262 for (count = 200; count > 0; count--) {
263 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
266 if (inverse && !(val & mask))
268 else if ((val & mask) == mask)
274 WARN(1, "%s failed to %s!\n", name, action);
278 #define wait_for_pll_enable_active(pll) \
279 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
281 #define wait_for_pll_enable_lock(pll) \
282 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
284 #define wait_for_zonda_pll_freq_lock(pll) \
285 wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable")
287 #define wait_for_pll_disable(pll) \
288 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
290 #define wait_for_pll_offline(pll) \
291 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
293 #define wait_for_pll_update(pll) \
294 wait_for_pll(pll, PLL_UPDATE, 1, "update")
296 #define wait_for_pll_update_ack_set(pll) \
297 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set")
299 #define wait_for_pll_update_ack_clear(pll) \
300 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear")
302 static void clk_alpha_pll_write_config(struct regmap *regmap, unsigned int reg,
306 regmap_write(regmap, reg, val);
309 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
310 const struct alpha_pll_config *config)
314 regmap_write(regmap, PLL_L_VAL(pll), config->l);
315 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
316 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
318 if (pll_has_64bit_config(pll))
319 regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
320 config->config_ctl_hi_val);
322 if (pll_alpha_width(pll) > 32)
323 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);
325 val = config->main_output_mask;
326 val |= config->aux_output_mask;
327 val |= config->aux2_output_mask;
328 val |= config->early_output_mask;
329 val |= config->pre_div_val;
330 val |= config->post_div_val;
331 val |= config->vco_val;
332 val |= config->alpha_en_mask;
333 val |= config->alpha_mode_mask;
335 mask = config->main_output_mask;
336 mask |= config->aux_output_mask;
337 mask |= config->aux2_output_mask;
338 mask |= config->early_output_mask;
339 mask |= config->pre_div_mask;
340 mask |= config->post_div_mask;
341 mask |= config->vco_mask;
343 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
345 if (pll->flags & SUPPORTS_FSM_MODE)
346 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
348 EXPORT_SYMBOL_GPL(clk_alpha_pll_configure);
350 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
353 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
356 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
362 if (pll->flags & SUPPORTS_OFFLINE_REQ)
363 val &= ~PLL_OFFLINE_REQ;
365 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val);
369 /* Make sure enable request goes through before waiting for update */
372 return wait_for_pll_enable_active(pll);
375 static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw)
378 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
381 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
385 if (pll->flags & SUPPORTS_OFFLINE_REQ) {
386 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
387 PLL_OFFLINE_REQ, PLL_OFFLINE_REQ);
391 ret = wait_for_pll_offline(pll);
397 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
402 wait_for_pll_disable(pll);
405 static int pll_is_enabled(struct clk_hw *hw, u32 mask)
408 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
411 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
415 return !!(val & mask);
418 static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw)
420 return pll_is_enabled(hw, PLL_ACTIVE_FLAG);
423 static int clk_alpha_pll_is_enabled(struct clk_hw *hw)
425 return pll_is_enabled(hw, PLL_LOCK_DET);
428 static int clk_alpha_pll_enable(struct clk_hw *hw)
431 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
434 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
435 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
439 /* If in FSM mode, just vote for it */
440 if (val & PLL_VOTE_FSM_ENA) {
441 ret = clk_enable_regmap(hw);
444 return wait_for_pll_enable_active(pll);
447 /* Skip if already enabled */
448 if ((val & mask) == mask)
451 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
452 PLL_BYPASSNL, PLL_BYPASSNL);
457 * H/W requires a 5us delay between disabling the bypass and
458 * de-asserting the reset.
463 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
464 PLL_RESET_N, PLL_RESET_N);
468 ret = wait_for_pll_enable_lock(pll);
472 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
473 PLL_OUTCTRL, PLL_OUTCTRL);
475 /* Ensure that the write above goes through before returning. */
480 static void clk_alpha_pll_disable(struct clk_hw *hw)
483 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
486 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
490 /* If in FSM mode, just unvote it */
491 if (val & PLL_VOTE_FSM_ENA) {
492 clk_disable_regmap(hw);
497 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
499 /* Delay of 2 output clock ticks required until output is disabled */
503 mask = PLL_RESET_N | PLL_BYPASSNL;
504 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
508 alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width)
510 return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width));
514 alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a,
521 remainder = do_div(quotient, prate);
529 /* Upper ALPHA_BITWIDTH bits of Alpha */
530 quotient = remainder << ALPHA_SHIFT(alpha_width);
532 remainder = do_div(quotient, prate);
538 return alpha_pll_calc_rate(prate, *l, *a, alpha_width);
541 static const struct pll_vco *
542 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate)
544 const struct pll_vco *v = pll->vco_table;
545 const struct pll_vco *end = v + pll->num_vco;
548 if (rate >= v->min_freq && rate <= v->max_freq)
555 clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
557 u32 l, low, high, ctl;
558 u64 a = 0, prate = parent_rate;
559 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
560 u32 alpha_width = pll_alpha_width(pll);
562 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
564 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
565 if (ctl & PLL_ALPHA_EN) {
566 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low);
567 if (alpha_width > 32) {
568 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
570 a = (u64)high << 32 | low;
572 a = low & GENMASK(alpha_width - 1, 0);
575 if (alpha_width > ALPHA_BITWIDTH)
576 a >>= alpha_width - ALPHA_BITWIDTH;
579 return alpha_pll_calc_rate(prate, l, a, alpha_width);
583 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll)
588 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode);
590 /* Latch the input to the PLL */
591 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
594 /* Wait for 2 reference cycle before checking ACK bit */
598 * PLL will latch the new L, Alpha and freq control word.
599 * PLL will respond by raising PLL_ACK_LATCH output when new programming
600 * has been latched in and PLL is being updated. When
601 * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared
602 * automatically by hardware when PLL_ACK_LATCH is asserted by PLL.
604 if (mode & PLL_UPDATE_BYPASS) {
605 ret = wait_for_pll_update_ack_set(pll);
609 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0);
611 ret = wait_for_pll_update(pll);
616 ret = wait_for_pll_update_ack_clear(pll);
620 /* Wait for PLL output to stabilize */
626 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll,
627 int (*is_enabled)(struct clk_hw *))
629 if (!is_enabled(&pll->clkr.hw) ||
630 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE))
633 return __clk_alpha_pll_update_latch(pll);
636 static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
638 int (*is_enabled)(struct clk_hw *))
640 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
641 const struct pll_vco *vco;
642 u32 l, alpha_width = pll_alpha_width(pll);
645 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
646 vco = alpha_pll_find_vco(pll, rate);
647 if (pll->vco_table && !vco) {
648 pr_err("%s: alpha pll not in a valid vco range\n",
649 clk_hw_get_name(hw));
653 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
655 if (alpha_width > ALPHA_BITWIDTH)
656 a <<= alpha_width - ALPHA_BITWIDTH;
658 if (alpha_width > 32)
659 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32);
661 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
664 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
665 PLL_VCO_MASK << PLL_VCO_SHIFT,
666 vco->val << PLL_VCO_SHIFT);
669 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
670 PLL_ALPHA_EN, PLL_ALPHA_EN);
672 return clk_alpha_pll_update_latch(pll, is_enabled);
675 static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
678 return __clk_alpha_pll_set_rate(hw, rate, prate,
679 clk_alpha_pll_is_enabled);
682 static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate,
685 return __clk_alpha_pll_set_rate(hw, rate, prate,
686 clk_alpha_pll_hwfsm_is_enabled);
689 static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
690 unsigned long *prate)
692 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
693 u32 l, alpha_width = pll_alpha_width(pll);
695 unsigned long min_freq, max_freq;
697 rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width);
698 if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
701 min_freq = pll->vco_table[0].min_freq;
702 max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
704 return clamp(rate, min_freq, max_freq);
708 alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a)
711 * a contains 16 bit alpha_val in two’s complement number in the range
714 if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
717 return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH);
721 alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate,
728 remainder = do_div(quotient, prate);
736 quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH;
737 remainder = do_div(quotient, prate);
743 * alpha_val should be in two’s complement number in the range
744 * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value
745 * since alpha value will be subtracted in this case.
747 if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
751 return alpha_huayra_pll_calc_rate(prate, *l, *a);
755 alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
757 u64 rate = parent_rate, tmp;
758 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
759 u32 l, alpha = 0, ctl, alpha_m, alpha_n;
761 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
762 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
764 if (ctl & PLL_ALPHA_EN) {
765 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha);
767 * Depending upon alpha_mode, it can be treated as M/N value or
768 * as a two’s complement number. When alpha_mode=1,
769 * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N
773 * M is a signed number (-128 to 127) and N is unsigned
774 * (0 to 255). M/N has to be within +/-0.5.
776 * When alpha_mode=0, it is a two’s complement number in the
779 * Fout=FIN*(L+(alpha_val)/2^16)
781 * where alpha_val is two’s complement number.
783 if (!(ctl & PLL_ALPHA_MODE))
784 return alpha_huayra_pll_calc_rate(rate, l, alpha);
786 alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK;
787 alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK;
791 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) {
792 alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m;
794 do_div(tmp, alpha_n);
798 do_div(tmp, alpha_n);
805 return alpha_huayra_pll_calc_rate(rate, l, alpha);
808 static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate,
811 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
812 u32 l, a, ctl, cur_alpha = 0;
814 rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a);
816 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
818 if (ctl & PLL_ALPHA_EN)
819 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha);
822 * Huayra PLL supports PLL dynamic programming. User can change L_VAL,
823 * without having to go through the power on sequence.
825 if (clk_alpha_pll_is_enabled(hw)) {
826 if (cur_alpha != a) {
827 pr_err("%s: clock needs to be gated\n",
828 clk_hw_get_name(hw));
832 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
833 /* Ensure that the write above goes to detect L val change. */
835 return wait_for_pll_enable_lock(pll);
838 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
839 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
842 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
845 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
846 PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN);
851 static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
852 unsigned long *prate)
856 return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
859 static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
860 struct regmap *regmap)
862 u32 mode_val, opmode_val;
865 ret = regmap_read(regmap, PLL_MODE(pll), &mode_val);
866 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
870 return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL));
873 static int clk_trion_pll_is_enabled(struct clk_hw *hw)
875 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
877 return trion_pll_is_enabled(pll, pll->clkr.regmap);
880 static int clk_trion_pll_enable(struct clk_hw *hw)
882 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
883 struct regmap *regmap = pll->clkr.regmap;
887 ret = regmap_read(regmap, PLL_MODE(pll), &val);
891 /* If in FSM mode, just vote for it */
892 if (val & PLL_VOTE_FSM_ENA) {
893 ret = clk_enable_regmap(hw);
896 return wait_for_pll_enable_active(pll);
899 /* Set operation mode to RUN */
900 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
902 ret = wait_for_pll_enable_lock(pll);
906 /* Enable the PLL outputs */
907 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
908 PLL_OUT_MASK, PLL_OUT_MASK);
912 /* Enable the global PLL outputs */
913 return regmap_update_bits(regmap, PLL_MODE(pll),
914 PLL_OUTCTRL, PLL_OUTCTRL);
917 static void clk_trion_pll_disable(struct clk_hw *hw)
919 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
920 struct regmap *regmap = pll->clkr.regmap;
924 ret = regmap_read(regmap, PLL_MODE(pll), &val);
928 /* If in FSM mode, just unvote it */
929 if (val & PLL_VOTE_FSM_ENA) {
930 clk_disable_regmap(hw);
934 /* Disable the global PLL output */
935 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
939 /* Disable the PLL outputs */
940 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
945 /* Place the PLL mode in STANDBY */
946 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
947 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
951 clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
953 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
954 u32 l, frac, alpha_width = pll_alpha_width(pll);
956 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
957 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
959 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
962 const struct clk_ops clk_alpha_pll_fixed_ops = {
963 .enable = clk_alpha_pll_enable,
964 .disable = clk_alpha_pll_disable,
965 .is_enabled = clk_alpha_pll_is_enabled,
966 .recalc_rate = clk_alpha_pll_recalc_rate,
968 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops);
970 const struct clk_ops clk_alpha_pll_ops = {
971 .enable = clk_alpha_pll_enable,
972 .disable = clk_alpha_pll_disable,
973 .is_enabled = clk_alpha_pll_is_enabled,
974 .recalc_rate = clk_alpha_pll_recalc_rate,
975 .round_rate = clk_alpha_pll_round_rate,
976 .set_rate = clk_alpha_pll_set_rate,
978 EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);
980 const struct clk_ops clk_alpha_pll_huayra_ops = {
981 .enable = clk_alpha_pll_enable,
982 .disable = clk_alpha_pll_disable,
983 .is_enabled = clk_alpha_pll_is_enabled,
984 .recalc_rate = alpha_pll_huayra_recalc_rate,
985 .round_rate = alpha_pll_huayra_round_rate,
986 .set_rate = alpha_pll_huayra_set_rate,
988 EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops);
990 const struct clk_ops clk_alpha_pll_hwfsm_ops = {
991 .enable = clk_alpha_pll_hwfsm_enable,
992 .disable = clk_alpha_pll_hwfsm_disable,
993 .is_enabled = clk_alpha_pll_hwfsm_is_enabled,
994 .recalc_rate = clk_alpha_pll_recalc_rate,
995 .round_rate = clk_alpha_pll_round_rate,
996 .set_rate = clk_alpha_pll_hwfsm_set_rate,
998 EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
1000 const struct clk_ops clk_alpha_pll_fixed_trion_ops = {
1001 .enable = clk_trion_pll_enable,
1002 .disable = clk_trion_pll_disable,
1003 .is_enabled = clk_trion_pll_is_enabled,
1004 .recalc_rate = clk_trion_pll_recalc_rate,
1005 .round_rate = clk_alpha_pll_round_rate,
1007 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops);
1009 static unsigned long
1010 clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1012 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1015 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
1017 ctl >>= PLL_POST_DIV_SHIFT;
1018 ctl &= PLL_POST_DIV_MASK(pll);
1020 return parent_rate >> fls(ctl);
1023 static const struct clk_div_table clk_alpha_div_table[] = {
1032 static const struct clk_div_table clk_alpha_2bit_div_table[] = {
1040 clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
1041 unsigned long *prate)
1043 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1044 const struct clk_div_table *table;
1046 if (pll->width == 2)
1047 table = clk_alpha_2bit_div_table;
1049 table = clk_alpha_div_table;
1051 return divider_round_rate(hw, rate, prate, table,
1052 pll->width, CLK_DIVIDER_POWER_OF_TWO);
1056 clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate,
1057 unsigned long *prate)
1059 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1062 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
1064 ctl >>= PLL_POST_DIV_SHIFT;
1065 ctl &= BIT(pll->width) - 1;
1066 div = 1 << fls(ctl);
1068 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
1069 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate);
1071 return DIV_ROUND_UP_ULL((u64)*prate, div);
1074 static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1075 unsigned long parent_rate)
1077 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1080 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */
1081 div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1;
1083 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1084 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
1085 div << PLL_POST_DIV_SHIFT);
1088 const struct clk_ops clk_alpha_pll_postdiv_ops = {
1089 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
1090 .round_rate = clk_alpha_pll_postdiv_round_rate,
1091 .set_rate = clk_alpha_pll_postdiv_set_rate,
1093 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops);
1095 const struct clk_ops clk_alpha_pll_postdiv_ro_ops = {
1096 .round_rate = clk_alpha_pll_postdiv_round_ro_rate,
1097 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
1099 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops);
1101 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1102 const struct alpha_pll_config *config)
1106 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1107 clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha);
1108 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1109 config->config_ctl_val);
1110 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1111 config->config_ctl_hi_val);
1112 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1113 config->user_ctl_val);
1114 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
1115 config->user_ctl_hi_val);
1116 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1117 config->test_ctl_val);
1118 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1119 config->test_ctl_hi_val);
1121 if (config->post_div_mask) {
1122 mask = config->post_div_mask;
1123 val = config->post_div_val;
1124 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
1127 if (pll->flags & SUPPORTS_FSM_LEGACY_MODE)
1128 regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE,
1129 PLL_FSM_LEGACY_MODE);
1131 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
1134 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1136 EXPORT_SYMBOL_GPL(clk_fabia_pll_configure);
1138 static int alpha_pll_fabia_enable(struct clk_hw *hw)
1141 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1142 u32 val, opmode_val;
1143 struct regmap *regmap = pll->clkr.regmap;
1145 ret = regmap_read(regmap, PLL_MODE(pll), &val);
1149 /* If in FSM mode, just vote for it */
1150 if (val & PLL_VOTE_FSM_ENA) {
1151 ret = clk_enable_regmap(hw);
1154 return wait_for_pll_enable_active(pll);
1157 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
1161 /* Skip If PLL is already running */
1162 if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL))
1165 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1169 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1173 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N,
1178 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
1182 ret = wait_for_pll_enable_lock(pll);
1186 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
1187 PLL_OUT_MASK, PLL_OUT_MASK);
1191 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL,
1195 static void alpha_pll_fabia_disable(struct clk_hw *hw)
1198 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1200 struct regmap *regmap = pll->clkr.regmap;
1202 ret = regmap_read(regmap, PLL_MODE(pll), &val);
1206 /* If in FSM mode, just unvote it */
1207 if (val & PLL_FSM_ENA) {
1208 clk_disable_regmap(hw);
1212 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1216 /* Disable main outputs */
1217 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
1221 /* Place the PLL in STANDBY */
1222 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1225 static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw,
1226 unsigned long parent_rate)
1228 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1229 u32 l, frac, alpha_width = pll_alpha_width(pll);
1231 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
1232 regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac);
1234 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
1238 * Due to limited number of bits for fractional rate programming, the
1239 * rounded up rate could be marginally higher than the requested rate.
1241 static int alpha_pll_check_rate_margin(struct clk_hw *hw,
1242 unsigned long rrate, unsigned long rate)
1244 unsigned long rate_margin = rate + PLL_RATE_MARGIN;
1246 if (rrate > rate_margin || rrate < rate) {
1247 pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n",
1248 clk_hw_get_name(hw), rrate, rate, rate_margin);
1255 static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
1256 unsigned long prate)
1258 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1259 u32 l, alpha_width = pll_alpha_width(pll);
1260 unsigned long rrate;
1264 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1266 ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1270 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1271 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a);
1273 return __clk_alpha_pll_update_latch(pll);
1276 static int alpha_pll_fabia_prepare(struct clk_hw *hw)
1278 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1279 const struct pll_vco *vco;
1280 struct clk_hw *parent_hw;
1281 unsigned long cal_freq, rrate;
1282 u32 cal_l, val, alpha_width = pll_alpha_width(pll);
1283 const char *name = clk_hw_get_name(hw);
1287 /* Check if calibration needs to be done i.e. PLL is in reset */
1288 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1292 /* Return early if calibration is not needed. */
1293 if (val & PLL_RESET_N)
1296 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw));
1298 pr_err("%s: alpha pll not in a valid vco range\n", name);
1302 cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq +
1303 pll->vco_table[0].max_freq) * 54, 100);
1305 parent_hw = clk_hw_get_parent(hw);
1309 rrate = alpha_pll_round_rate(cal_freq, clk_hw_get_rate(parent_hw),
1310 &cal_l, &a, alpha_width);
1312 ret = alpha_pll_check_rate_margin(hw, rrate, cal_freq);
1316 /* Setup PLL for calibration frequency */
1317 regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l);
1319 /* Bringup the PLL at calibration frequency */
1320 ret = clk_alpha_pll_enable(hw);
1322 pr_err("%s: alpha pll calibration failed\n", name);
1326 clk_alpha_pll_disable(hw);
1331 const struct clk_ops clk_alpha_pll_fabia_ops = {
1332 .prepare = alpha_pll_fabia_prepare,
1333 .enable = alpha_pll_fabia_enable,
1334 .disable = alpha_pll_fabia_disable,
1335 .is_enabled = clk_alpha_pll_is_enabled,
1336 .set_rate = alpha_pll_fabia_set_rate,
1337 .recalc_rate = alpha_pll_fabia_recalc_rate,
1338 .round_rate = clk_alpha_pll_round_rate,
1340 EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops);
1342 const struct clk_ops clk_alpha_pll_fixed_fabia_ops = {
1343 .enable = alpha_pll_fabia_enable,
1344 .disable = alpha_pll_fabia_disable,
1345 .is_enabled = clk_alpha_pll_is_enabled,
1346 .recalc_rate = alpha_pll_fabia_recalc_rate,
1347 .round_rate = clk_alpha_pll_round_rate,
1349 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops);
1351 static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw,
1352 unsigned long parent_rate)
1354 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1355 u32 i, div = 1, val;
1358 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1362 val >>= pll->post_div_shift;
1363 val &= BIT(pll->width) - 1;
1365 for (i = 0; i < pll->num_post_div; i++) {
1366 if (pll->post_div_table[i].val == val) {
1367 div = pll->post_div_table[i].div;
1372 return (parent_rate / div);
1375 static unsigned long
1376 clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1378 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1379 struct regmap *regmap = pll->clkr.regmap;
1380 u32 i, div = 1, val;
1382 regmap_read(regmap, PLL_USER_CTL(pll), &val);
1384 val >>= pll->post_div_shift;
1385 val &= PLL_POST_DIV_MASK(pll);
1387 for (i = 0; i < pll->num_post_div; i++) {
1388 if (pll->post_div_table[i].val == val) {
1389 div = pll->post_div_table[i].div;
1394 return (parent_rate / div);
1398 clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
1399 unsigned long *prate)
1401 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1403 return divider_round_rate(hw, rate, prate, pll->post_div_table,
1404 pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1408 clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1409 unsigned long parent_rate)
1411 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1412 struct regmap *regmap = pll->clkr.regmap;
1413 int i, val = 0, div;
1415 div = DIV_ROUND_UP_ULL(parent_rate, rate);
1416 for (i = 0; i < pll->num_post_div; i++) {
1417 if (pll->post_div_table[i].div == div) {
1418 val = pll->post_div_table[i].val;
1423 return regmap_update_bits(regmap, PLL_USER_CTL(pll),
1424 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
1425 val << PLL_POST_DIV_SHIFT);
1428 const struct clk_ops clk_alpha_pll_postdiv_trion_ops = {
1429 .recalc_rate = clk_trion_pll_postdiv_recalc_rate,
1430 .round_rate = clk_trion_pll_postdiv_round_rate,
1431 .set_rate = clk_trion_pll_postdiv_set_rate,
1433 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops);
1435 static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,
1436 unsigned long rate, unsigned long *prate)
1438 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1440 return divider_round_rate(hw, rate, prate, pll->post_div_table,
1441 pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1444 static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw,
1445 unsigned long rate, unsigned long parent_rate)
1447 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1448 int i, val = 0, div, ret;
1451 * If the PLL is in FSM mode, then treat set_rate callback as a
1454 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1458 if (val & PLL_VOTE_FSM_ENA)
1461 div = DIV_ROUND_UP_ULL(parent_rate, rate);
1462 for (i = 0; i < pll->num_post_div; i++) {
1463 if (pll->post_div_table[i].div == div) {
1464 val = pll->post_div_table[i].val;
1469 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1470 (BIT(pll->width) - 1) << pll->post_div_shift,
1471 val << pll->post_div_shift);
1474 const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = {
1475 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1476 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1477 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
1479 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
1482 * clk_trion_pll_configure - configure the trion pll
1484 * @pll: clk alpha pll
1485 * @regmap: register map
1486 * @config: configuration to apply for pll
1488 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1489 const struct alpha_pll_config *config)
1492 * If the bootloader left the PLL enabled it's likely that there are
1493 * RCGs that will lock up if we disable the PLL below.
1495 if (trion_pll_is_enabled(pll, regmap)) {
1496 pr_debug("Trion PLL is already enabled, skipping configuration\n");
1500 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1501 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL);
1502 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1503 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1504 config->config_ctl_val);
1505 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1506 config->config_ctl_hi_val);
1507 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll),
1508 config->config_ctl_hi1_val);
1509 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1510 config->user_ctl_val);
1511 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
1512 config->user_ctl_hi_val);
1513 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll),
1514 config->user_ctl_hi1_val);
1515 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1516 config->test_ctl_val);
1517 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1518 config->test_ctl_hi_val);
1519 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll),
1520 config->test_ctl_hi1_val);
1522 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
1525 /* Disable PLL output */
1526 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1528 /* Set operation mode to OFF */
1529 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1531 /* Place the PLL in STANDBY mode */
1532 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1534 EXPORT_SYMBOL_GPL(clk_trion_pll_configure);
1537 * The TRION PLL requires a power-on self-calibration which happens when the
1538 * PLL comes out of reset. Calibrate in case it is not completed.
1540 static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done)
1542 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1546 /* Return early if calibration is not needed. */
1547 regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val);
1548 if (val & pcal_done)
1551 /* On/off to calibrate */
1552 ret = clk_trion_pll_enable(hw);
1554 clk_trion_pll_disable(hw);
1559 static int alpha_pll_trion_prepare(struct clk_hw *hw)
1561 return __alpha_pll_trion_prepare(hw, TRION_PCAL_DONE);
1564 static int alpha_pll_lucid_prepare(struct clk_hw *hw)
1566 return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE);
1569 static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
1570 unsigned long prate, u32 latch_bit, u32 latch_ack)
1572 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1573 unsigned long rrate;
1574 u32 val, l, alpha_width = pll_alpha_width(pll);
1578 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1580 ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1584 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1585 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
1587 /* Latch the PLL input */
1588 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit);
1592 /* Wait for 2 reference cycles before checking the ACK bit. */
1594 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1595 if (!(val & latch_ack)) {
1596 pr_err("Lucid PLL latch failed. Output may be unstable!\n");
1600 /* Return the latch input to 0 */
1601 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0);
1605 if (clk_hw_is_enabled(hw)) {
1606 ret = wait_for_pll_enable_lock(pll);
1611 /* Wait for PLL output to stabilize */
1616 static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
1617 unsigned long prate)
1619 return __alpha_pll_trion_set_rate(hw, rate, prate, PLL_UPDATE, ALPHA_PLL_ACK_LATCH);
1622 const struct clk_ops clk_alpha_pll_trion_ops = {
1623 .prepare = alpha_pll_trion_prepare,
1624 .enable = clk_trion_pll_enable,
1625 .disable = clk_trion_pll_disable,
1626 .is_enabled = clk_trion_pll_is_enabled,
1627 .recalc_rate = clk_trion_pll_recalc_rate,
1628 .round_rate = clk_alpha_pll_round_rate,
1629 .set_rate = alpha_pll_trion_set_rate,
1631 EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops);
1633 const struct clk_ops clk_alpha_pll_lucid_ops = {
1634 .prepare = alpha_pll_lucid_prepare,
1635 .enable = clk_trion_pll_enable,
1636 .disable = clk_trion_pll_disable,
1637 .is_enabled = clk_trion_pll_is_enabled,
1638 .recalc_rate = clk_trion_pll_recalc_rate,
1639 .round_rate = clk_alpha_pll_round_rate,
1640 .set_rate = alpha_pll_trion_set_rate,
1642 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops);
1644 const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = {
1645 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1646 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1647 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
1649 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops);
1651 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1652 const struct alpha_pll_config *config)
1654 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1655 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1656 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1657 config->user_ctl_val);
1658 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1659 config->config_ctl_val);
1660 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1661 config->config_ctl_hi_val);
1662 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1663 config->test_ctl_val);
1664 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1665 config->test_ctl_hi_val);
1667 EXPORT_SYMBOL_GPL(clk_agera_pll_configure);
1669 static int clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate,
1670 unsigned long prate)
1672 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1673 u32 l, alpha_width = pll_alpha_width(pll);
1675 unsigned long rrate;
1678 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1679 ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1683 /* change L_VAL without having to go through the power on sequence */
1684 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1685 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
1687 if (clk_hw_is_enabled(hw))
1688 return wait_for_pll_enable_lock(pll);
1693 const struct clk_ops clk_alpha_pll_agera_ops = {
1694 .enable = clk_alpha_pll_enable,
1695 .disable = clk_alpha_pll_disable,
1696 .is_enabled = clk_alpha_pll_is_enabled,
1697 .recalc_rate = alpha_pll_fabia_recalc_rate,
1698 .round_rate = clk_alpha_pll_round_rate,
1699 .set_rate = clk_alpha_pll_agera_set_rate,
1701 EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops);
1703 static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw)
1705 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1709 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1713 /* If in FSM mode, just vote for it */
1714 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {
1715 ret = clk_enable_regmap(hw);
1718 return wait_for_pll_enable_lock(pll);
1721 /* Check if PLL is already enabled, return if enabled */
1722 ret = trion_pll_is_enabled(pll, pll->clkr.regmap);
1726 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1730 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN);
1732 ret = wait_for_pll_enable_lock(pll);
1736 /* Enable the PLL outputs */
1737 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
1741 /* Enable the global PLL outputs */
1742 return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
1745 static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw)
1747 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1751 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1755 /* If in FSM mode, just unvote it */
1756 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {
1757 clk_disable_regmap(hw);
1761 /* Disable the global PLL output */
1762 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1766 /* Disable the PLL outputs */
1767 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
1771 /* Place the PLL mode in STANDBY */
1772 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY);
1776 * The Lucid 5LPE PLL requires a power-on self-calibration which happens
1777 * when the PLL comes out of reset. Calibrate in case it is not completed.
1779 static int alpha_pll_lucid_5lpe_prepare(struct clk_hw *hw)
1781 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1786 /* Return early if calibration is not needed. */
1787 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1788 if (val & LUCID_5LPE_PCAL_DONE)
1791 p = clk_hw_get_parent(hw);
1795 ret = alpha_pll_lucid_5lpe_enable(hw);
1799 alpha_pll_lucid_5lpe_disable(hw);
1804 static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate,
1805 unsigned long prate)
1807 return __alpha_pll_trion_set_rate(hw, rate, prate,
1808 LUCID_5LPE_PLL_LATCH_INPUT,
1809 LUCID_5LPE_ALPHA_PLL_ACK_LATCH);
1812 static int __clk_lucid_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1813 unsigned long parent_rate,
1814 unsigned long enable_vote_run)
1816 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1817 struct regmap *regmap = pll->clkr.regmap;
1818 int i, val, div, ret;
1822 * If the PLL is in FSM mode, then treat set_rate callback as a
1825 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
1829 if (val & enable_vote_run)
1832 if (!pll->post_div_table) {
1833 pr_err("Missing the post_div_table for the %s PLL\n",
1834 clk_hw_get_name(&pll->clkr.hw));
1838 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
1839 for (i = 0; i < pll->num_post_div; i++) {
1840 if (pll->post_div_table[i].div == div) {
1841 val = pll->post_div_table[i].val;
1846 mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift);
1847 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1848 mask, val << pll->post_div_shift);
1851 static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1852 unsigned long parent_rate)
1854 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_5LPE_ENABLE_VOTE_RUN);
1857 const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = {
1858 .prepare = alpha_pll_lucid_5lpe_prepare,
1859 .enable = alpha_pll_lucid_5lpe_enable,
1860 .disable = alpha_pll_lucid_5lpe_disable,
1861 .is_enabled = clk_trion_pll_is_enabled,
1862 .recalc_rate = clk_trion_pll_recalc_rate,
1863 .round_rate = clk_alpha_pll_round_rate,
1864 .set_rate = alpha_pll_lucid_5lpe_set_rate,
1866 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_5lpe_ops);
1868 const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = {
1869 .enable = alpha_pll_lucid_5lpe_enable,
1870 .disable = alpha_pll_lucid_5lpe_disable,
1871 .is_enabled = clk_trion_pll_is_enabled,
1872 .recalc_rate = clk_trion_pll_recalc_rate,
1873 .round_rate = clk_alpha_pll_round_rate,
1875 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_5lpe_ops);
1877 const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = {
1878 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1879 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1880 .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate,
1882 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops);
1884 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1885 const struct alpha_pll_config *config)
1887 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1888 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1889 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
1890 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
1891 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
1892 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
1893 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
1894 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val);
1895 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
1896 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
1897 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
1899 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0);
1901 /* Disable PLL output */
1902 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1904 /* Set operation mode to OFF */
1905 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1907 /* Place the PLL in STANDBY mode */
1908 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1910 EXPORT_SYMBOL_GPL(clk_zonda_pll_configure);
1912 static int clk_zonda_pll_enable(struct clk_hw *hw)
1914 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1915 struct regmap *regmap = pll->clkr.regmap;
1919 regmap_read(regmap, PLL_MODE(pll), &val);
1921 /* If in FSM mode, just vote for it */
1922 if (val & PLL_VOTE_FSM_ENA) {
1923 ret = clk_enable_regmap(hw);
1926 return wait_for_pll_enable_active(pll);
1929 /* Get the PLL out of bypass mode */
1930 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL);
1933 * H/W requires a 1us delay between disabling the bypass and
1934 * de-asserting the reset.
1938 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1940 /* Set operation mode to RUN */
1941 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
1943 regmap_read(regmap, PLL_TEST_CTL(pll), &val);
1945 /* If cfa mode then poll for freq lock */
1946 if (val & ZONDA_STAY_IN_CFA)
1947 ret = wait_for_zonda_pll_freq_lock(pll);
1949 ret = wait_for_pll_enable_lock(pll);
1953 /* Enable the PLL outputs */
1954 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK);
1956 /* Enable the global PLL outputs */
1957 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
1962 static void clk_zonda_pll_disable(struct clk_hw *hw)
1964 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1965 struct regmap *regmap = pll->clkr.regmap;
1968 regmap_read(regmap, PLL_MODE(pll), &val);
1970 /* If in FSM mode, just unvote it */
1971 if (val & PLL_VOTE_FSM_ENA) {
1972 clk_disable_regmap(hw);
1976 /* Disable the global PLL output */
1977 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1979 /* Disable the PLL outputs */
1980 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0);
1982 /* Put the PLL in bypass and reset */
1983 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0);
1985 /* Place the PLL mode in OFF state */
1986 regmap_write(regmap, PLL_OPMODE(pll), 0x0);
1989 static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
1990 unsigned long prate)
1992 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1993 unsigned long rrate;
1995 u32 l, alpha_width = pll_alpha_width(pll);
1999 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
2001 ret = alpha_pll_check_rate_margin(hw, rrate, rate);
2005 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
2006 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
2008 /* Wait before polling for the frequency latch */
2011 /* Read stay in cfa mode */
2012 regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val);
2014 /* If cfa mode then poll for freq lock */
2015 if (test_ctl_val & ZONDA_STAY_IN_CFA)
2016 ret = wait_for_zonda_pll_freq_lock(pll);
2018 ret = wait_for_pll_enable_lock(pll);
2022 /* Wait for PLL output to stabilize */
2027 const struct clk_ops clk_alpha_pll_zonda_ops = {
2028 .enable = clk_zonda_pll_enable,
2029 .disable = clk_zonda_pll_disable,
2030 .is_enabled = clk_trion_pll_is_enabled,
2031 .recalc_rate = clk_trion_pll_recalc_rate,
2032 .round_rate = clk_alpha_pll_round_rate,
2033 .set_rate = clk_zonda_pll_set_rate,
2035 EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops);
2037 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2038 const struct alpha_pll_config *config)
2040 u32 lval = config->l;
2042 lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT;
2043 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval);
2044 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
2045 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2046 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2047 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2048 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
2049 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2050 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2051 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2052 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
2054 /* Disable PLL output */
2055 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2057 /* Set operation mode to STANDBY and de-assert the reset */
2058 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2059 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2061 EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure);
2063 static int alpha_pll_lucid_evo_enable(struct clk_hw *hw)
2065 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2066 struct regmap *regmap = pll->clkr.regmap;
2070 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
2074 /* If in FSM mode, just vote for it */
2075 if (val & LUCID_EVO_ENABLE_VOTE_RUN) {
2076 ret = clk_enable_regmap(hw);
2079 return wait_for_pll_enable_lock(pll);
2082 /* Check if PLL is already enabled */
2083 ret = trion_pll_is_enabled(pll, regmap);
2087 pr_warn("%s PLL is already enabled\n", clk_hw_get_name(&pll->clkr.hw));
2091 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2095 /* Set operation mode to RUN */
2096 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
2098 ret = wait_for_pll_enable_lock(pll);
2102 /* Enable the PLL outputs */
2103 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
2107 /* Enable the global PLL outputs */
2108 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
2112 /* Ensure that the write above goes through before returning. */
2117 static void _alpha_pll_lucid_evo_disable(struct clk_hw *hw, bool reset)
2119 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2120 struct regmap *regmap = pll->clkr.regmap;
2124 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
2128 /* If in FSM mode, just unvote it */
2129 if (val & LUCID_EVO_ENABLE_VOTE_RUN) {
2130 clk_disable_regmap(hw);
2134 /* Disable the global PLL output */
2135 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2139 /* Disable the PLL outputs */
2140 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
2144 /* Place the PLL mode in STANDBY */
2145 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2148 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 0);
2151 static int _alpha_pll_lucid_evo_prepare(struct clk_hw *hw, bool reset)
2153 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2158 /* Return early if calibration is not needed. */
2159 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
2160 if (!(val & LUCID_EVO_PCAL_NOT_DONE))
2163 p = clk_hw_get_parent(hw);
2167 ret = alpha_pll_lucid_evo_enable(hw);
2171 _alpha_pll_lucid_evo_disable(hw, reset);
2176 static void alpha_pll_lucid_evo_disable(struct clk_hw *hw)
2178 _alpha_pll_lucid_evo_disable(hw, false);
2181 static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw)
2183 return _alpha_pll_lucid_evo_prepare(hw, false);
2186 static void alpha_pll_reset_lucid_evo_disable(struct clk_hw *hw)
2188 _alpha_pll_lucid_evo_disable(hw, true);
2191 static int alpha_pll_reset_lucid_evo_prepare(struct clk_hw *hw)
2193 return _alpha_pll_lucid_evo_prepare(hw, true);
2196 static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw,
2197 unsigned long parent_rate)
2199 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2200 struct regmap *regmap = pll->clkr.regmap;
2203 regmap_read(regmap, PLL_L_VAL(pll), &l);
2204 l &= LUCID_EVO_PLL_L_VAL_MASK;
2205 regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac);
2207 return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll));
2210 static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
2211 unsigned long parent_rate)
2213 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_EVO_ENABLE_VOTE_RUN);
2216 const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = {
2217 .enable = alpha_pll_lucid_evo_enable,
2218 .disable = alpha_pll_lucid_evo_disable,
2219 .is_enabled = clk_trion_pll_is_enabled,
2220 .recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2221 .round_rate = clk_alpha_pll_round_rate,
2223 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops);
2225 const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = {
2226 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
2227 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
2228 .set_rate = clk_lucid_evo_pll_postdiv_set_rate,
2230 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops);
2232 const struct clk_ops clk_alpha_pll_lucid_evo_ops = {
2233 .prepare = alpha_pll_lucid_evo_prepare,
2234 .enable = alpha_pll_lucid_evo_enable,
2235 .disable = alpha_pll_lucid_evo_disable,
2236 .is_enabled = clk_trion_pll_is_enabled,
2237 .recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2238 .round_rate = clk_alpha_pll_round_rate,
2239 .set_rate = alpha_pll_lucid_5lpe_set_rate,
2241 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops);
2243 const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops = {
2244 .prepare = alpha_pll_reset_lucid_evo_prepare,
2245 .enable = alpha_pll_lucid_evo_enable,
2246 .disable = alpha_pll_reset_lucid_evo_disable,
2247 .is_enabled = clk_trion_pll_is_enabled,
2248 .recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2249 .round_rate = clk_alpha_pll_round_rate,
2250 .set_rate = alpha_pll_lucid_5lpe_set_rate,
2252 EXPORT_SYMBOL_GPL(clk_alpha_pll_reset_lucid_evo_ops);
2254 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2255 const struct alpha_pll_config *config)
2257 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2258 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2259 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2260 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2261 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2262 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
2263 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
2264 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2266 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2268 regmap_update_bits(regmap, PLL_MODE(pll),
2269 PLL_RESET_N | PLL_BYPASSNL | PLL_OUTCTRL,
2270 PLL_RESET_N | PLL_BYPASSNL);
2272 EXPORT_SYMBOL_GPL(clk_rivian_evo_pll_configure);
2274 static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw,
2275 unsigned long parent_rate)
2277 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2280 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
2282 return parent_rate * l;
2285 static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate,
2286 unsigned long *prate)
2288 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2289 unsigned long min_freq, max_freq;
2293 rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0);
2294 if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
2297 min_freq = pll->vco_table[0].min_freq;
2298 max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
2300 return clamp(rate, min_freq, max_freq);
2303 const struct clk_ops clk_alpha_pll_rivian_evo_ops = {
2304 .enable = alpha_pll_lucid_5lpe_enable,
2305 .disable = alpha_pll_lucid_5lpe_disable,
2306 .is_enabled = clk_trion_pll_is_enabled,
2307 .recalc_rate = clk_rivian_evo_pll_recalc_rate,
2308 .round_rate = clk_rivian_evo_pll_round_rate,
2310 EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops);