drivers/clk/qcom/camcc-sc7180.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk-provider.h>
   7 #include <linux/err.h>
   8 #include <linux/module.h>
   9 #include <linux/of.h>
  10 #include <linux/of_device.h>
  11 #include <linux/pm_clock.h>
  12 #include <linux/pm_runtime.h>
  13 #include <linux/regmap.h>
  14
  15 #include <dt-bindings/clock/qcom,camcc-sc7180.h>
  16
  17 #include "clk-alpha-pll.h"
  18 #include "clk-branch.h"
  19 #include "clk-rcg.h"
  20 #include "clk-regmap.h"
  21 #include "common.h"
  22 #include "gdsc.h"
  23 #include "reset.h"
  24
  25 enum {
  26         P_BI_TCXO,
  27         P_CAM_CC_PLL0_OUT_EVEN,
  28         P_CAM_CC_PLL1_OUT_EVEN,
  29         P_CAM_CC_PLL2_OUT_AUX,
  30         P_CAM_CC_PLL2_OUT_EARLY,
  31         P_CAM_CC_PLL3_OUT_MAIN,
  32         P_CORE_BI_PLL_TEST_SE,
  33 };
  34
  35 static const struct pll_vco agera_vco[] = {
  36         { 600000000, 3300000000UL, 0 },
  37 };
  38
  39 static const struct pll_vco fabia_vco[] = {
  40         { 249600000, 2000000000UL, 0 },
  41 };
  42
  43 /* 600MHz configuration */
  44 static const struct alpha_pll_config cam_cc_pll0_config = {
  45         .l = 0x1f,
  46         .alpha = 0x4000,
  47         .config_ctl_val = 0x20485699,
  48         .config_ctl_hi_val = 0x00002067,
  49         .test_ctl_val = 0x40000000,
  50         .user_ctl_hi_val = 0x00004805,
  51         .user_ctl_val = 0x00000001,
  52 };
  53
  54 static struct clk_alpha_pll cam_cc_pll0 = {
  55         .offset = 0x0,
  56         .vco_table = fabia_vco,
  57         .num_vco = ARRAY_SIZE(fabia_vco),
  58         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  59         .clkr = {
  60                 .hw.init = &(struct clk_init_data){
  61                         .name = "cam_cc_pll0",
  62                         .parent_data = &(const struct clk_parent_data){
  63                                 .fw_name = "bi_tcxo",
  64                         },
  65                         .num_parents = 1,
  66                         .ops = &clk_alpha_pll_fabia_ops,
  67                 },
  68         },
  69 };
  70
  71 /* 860MHz configuration */
  72 static const struct alpha_pll_config cam_cc_pll1_config = {
  73         .l = 0x2a,
  74         .alpha = 0x1555,
  75         .config_ctl_val = 0x20485699,
  76         .config_ctl_hi_val = 0x00002067,
  77         .test_ctl_val = 0x40000000,
  78         .user_ctl_hi_val = 0x00004805,
  79 };
  80
  81 static struct clk_alpha_pll cam_cc_pll1 = {
  82         .offset = 0x1000,
  83         .vco_table = fabia_vco,
  84         .num_vco = ARRAY_SIZE(fabia_vco),
  85         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  86         .clkr = {
  87                 .hw.init = &(struct clk_init_data){
  88                         .name = "cam_cc_pll1",
  89                         .parent_data = &(const struct clk_parent_data){
  90                                 .fw_name = "bi_tcxo",
  91                         },
  92                         .num_parents = 1,
  93                         .ops = &clk_alpha_pll_fabia_ops,
  94                 },
  95         },
  96 };
  97
  98 /* 1920MHz configuration */
  99 static const struct alpha_pll_config cam_cc_pll2_config = {
 100         .l = 0x64,
 101         .config_ctl_val = 0x20000800,
 102         .config_ctl_hi_val = 0x400003D2,
 103         .test_ctl_val = 0x04000400,
 104         .test_ctl_hi_val = 0x00004000,
 105         .user_ctl_val = 0x0000030F,
 106 };
 107
 108 static struct clk_alpha_pll cam_cc_pll2 = {
 109         .offset = 0x2000,
 110         .vco_table = agera_vco,
 111         .num_vco = ARRAY_SIZE(agera_vco),
 112         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA],
 113         .clkr = {
 114                 .hw.init = &(struct clk_init_data){
 115                         .name = "cam_cc_pll2",
 116                         .parent_data = &(const struct clk_parent_data){
 117                                 .fw_name = "bi_tcxo",
 118                         },
 119                         .num_parents = 1,
 120                         .ops = &clk_alpha_pll_agera_ops,
 121                 },
 122         },
 123 };
 124
 125 static struct clk_fixed_factor cam_cc_pll2_out_early = {
 126         .mult = 1,
 127         .div = 2,
 128         .hw.init = &(struct clk_init_data){
 129                 .name = "cam_cc_pll2_out_early",
 130                 .parent_names = (const char *[]){ "cam_cc_pll2" },
 131                 .num_parents = 1,
 132                 .ops = &clk_fixed_factor_ops,
 133         },
 134 };
 135
 136 static const struct clk_div_table post_div_table_cam_cc_pll2_out_aux[] = {
 137         { 0x3, 4 },
 138         { }
 139 };
 140
 141 static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux = {
 142         .offset = 0x2000,
 143         .post_div_shift = 8,
 144         .post_div_table = post_div_table_cam_cc_pll2_out_aux,
 145         .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_aux),
 146         .width = 2,
 147         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA],
 148         .clkr.hw.init = &(struct clk_init_data){
 149                 .name = "cam_cc_pll2_out_aux",
 150                 .parent_data = &(const struct clk_parent_data){
 151                         .hw = &cam_cc_pll2.clkr.hw,
 152                 },
 153                 .num_parents = 1,
 154                 .flags = CLK_SET_RATE_PARENT,
 155                 .ops = &clk_alpha_pll_postdiv_ops,
 156         },
 157 };
 158
 159 /* 1080MHz configuration */
 160 static const struct alpha_pll_config cam_cc_pll3_config = {
 161         .l = 0x38,
 162         .alpha = 0x4000,
 163         .config_ctl_val = 0x20485699,
 164         .config_ctl_hi_val = 0x00002067,
 165         .test_ctl_val = 0x40000000,
 166         .user_ctl_hi_val = 0x00004805,
 167 };
 168
 169 static struct clk_alpha_pll cam_cc_pll3 = {
 170         .offset = 0x3000,
 171         .vco_table = fabia_vco,
 172         .num_vco = ARRAY_SIZE(fabia_vco),
 173         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 174         .clkr = {
 175                 .hw.init = &(struct clk_init_data){
 176                         .name = "cam_cc_pll3",
 177                         .parent_data = &(const struct clk_parent_data){
 178                                 .fw_name = "bi_tcxo",
 179                         },
 180                         .num_parents = 1,
 181                         .ops = &clk_alpha_pll_fabia_ops,
 182                 },
 183         },
 184 };
 185
 186 static const struct parent_map cam_cc_parent_map_0[] = {
 187         { P_BI_TCXO, 0 },
 188         { P_CAM_CC_PLL1_OUT_EVEN, 2 },
 189         { P_CAM_CC_PLL0_OUT_EVEN, 6 },
 190         { P_CORE_BI_PLL_TEST_SE, 7 },
 191 };
 192
 193 static const struct clk_parent_data cam_cc_parent_data_0[] = {
 194         { .fw_name = "bi_tcxo" },
 195         { .hw = &cam_cc_pll1.clkr.hw },
 196         { .hw = &cam_cc_pll0.clkr.hw },
 197         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 198 };
 199
 200 static const struct parent_map cam_cc_parent_map_1[] = {
 201         { P_BI_TCXO, 0 },
 202         { P_CAM_CC_PLL2_OUT_AUX, 1 },
 203         { P_CORE_BI_PLL_TEST_SE, 7 },
 204 };
 205
 206 static const struct clk_parent_data cam_cc_parent_data_1[] = {
 207         { .fw_name = "bi_tcxo" },
 208         { .hw = &cam_cc_pll2_out_aux.clkr.hw },
 209         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 210 };
 211
 212 static const struct parent_map cam_cc_parent_map_2[] = {
 213         { P_BI_TCXO, 0 },
 214         { P_CAM_CC_PLL2_OUT_EARLY, 4 },
 215         { P_CAM_CC_PLL3_OUT_MAIN, 5 },
 216         { P_CAM_CC_PLL0_OUT_EVEN, 6 },
 217         { P_CORE_BI_PLL_TEST_SE, 7 },
 218 };
 219
 220 static const struct clk_parent_data cam_cc_parent_data_2[] = {
 221         { .fw_name = "bi_tcxo" },
 222         { .hw = &cam_cc_pll2_out_early.hw },
 223         { .hw = &cam_cc_pll3.clkr.hw },
 224         { .hw = &cam_cc_pll0.clkr.hw },
 225         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 226 };
 227
 228 static const struct parent_map cam_cc_parent_map_3[] = {
 229         { P_BI_TCXO, 0 },
 230         { P_CAM_CC_PLL1_OUT_EVEN, 2 },
 231         { P_CAM_CC_PLL2_OUT_EARLY, 4 },
 232         { P_CAM_CC_PLL3_OUT_MAIN, 5 },
 233         { P_CAM_CC_PLL0_OUT_EVEN, 6 },
 234         { P_CORE_BI_PLL_TEST_SE, 7 },
 235 };
 236
 237 static const struct clk_parent_data cam_cc_parent_data_3[] = {
 238         { .fw_name = "bi_tcxo" },
 239         { .hw = &cam_cc_pll1.clkr.hw },
 240         { .hw = &cam_cc_pll2_out_early.hw },
 241         { .hw = &cam_cc_pll3.clkr.hw },
 242         { .hw = &cam_cc_pll0.clkr.hw },
 243         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 244 };
 245
 246 static const struct parent_map cam_cc_parent_map_4[] = {
 247         { P_BI_TCXO, 0 },
 248         { P_CAM_CC_PLL3_OUT_MAIN, 5 },
 249         { P_CAM_CC_PLL0_OUT_EVEN, 6 },
 250         { P_CORE_BI_PLL_TEST_SE, 7 },
 251 };
 252
 253 static const struct clk_parent_data cam_cc_parent_data_4[] = {
 254         { .fw_name = "bi_tcxo" },
 255         { .hw = &cam_cc_pll3.clkr.hw },
 256         { .hw = &cam_cc_pll0.clkr.hw },
 257         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 258 };
 259
 260 static const struct parent_map cam_cc_parent_map_5[] = {
 261         { P_BI_TCXO, 0 },
 262         { P_CAM_CC_PLL0_OUT_EVEN, 6 },
 263         { P_CORE_BI_PLL_TEST_SE, 7 },
 264 };
 265
 266 static const struct clk_parent_data cam_cc_parent_data_5[] = {
 267         { .fw_name = "bi_tcxo" },
 268         { .hw = &cam_cc_pll0.clkr.hw },
 269         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 270 };
 271
 272 static const struct parent_map cam_cc_parent_map_6[] = {
 273         { P_BI_TCXO, 0 },
 274         { P_CAM_CC_PLL1_OUT_EVEN, 2 },
 275         { P_CAM_CC_PLL3_OUT_MAIN, 5 },
 276         { P_CAM_CC_PLL0_OUT_EVEN, 6 },
 277         { P_CORE_BI_PLL_TEST_SE, 7 },
 278 };
 279
 280 static const struct clk_parent_data cam_cc_parent_data_6[] = {
 281         { .fw_name = "bi_tcxo" },
 282         { .hw = &cam_cc_pll1.clkr.hw },
 283         { .hw = &cam_cc_pll3.clkr.hw },
 284         { .hw = &cam_cc_pll0.clkr.hw },
 285         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 286 };
 287
 288 static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
 289         F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
 290         F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
 291         F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0),
 292         F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0),
 293         F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
 294         { }
 295 };
 296
 297 static struct clk_rcg2 cam_cc_bps_clk_src = {
 298         .cmd_rcgr = 0x6010,
 299         .mnd_width = 0,
 300         .hid_width = 5,
 301         .parent_map = cam_cc_parent_map_2,
 302         .freq_tbl = ftbl_cam_cc_bps_clk_src,
 303         .clkr.hw.init = &(struct clk_init_data){
 304                 .name = "cam_cc_bps_clk_src",
 305                 .parent_data = cam_cc_parent_data_2,
 306                 .num_parents = 5,
 307                 .ops = &clk_rcg2_shared_ops,
 308         },
 309 };
 310
 311 static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = {
 312         F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
 313         F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0),
 314         F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
 315         { }
 316 };
 317
 318 static struct clk_rcg2 cam_cc_cci_0_clk_src = {
 319         .cmd_rcgr = 0xb0d8,
 320         .mnd_width = 8,
 321         .hid_width = 5,
 322         .parent_map = cam_cc_parent_map_5,
 323         .freq_tbl = ftbl_cam_cc_cci_0_clk_src,
 324         .clkr.hw.init = &(struct clk_init_data){
 325                 .name = "cam_cc_cci_0_clk_src",
 326                 .parent_data = cam_cc_parent_data_5,
 327                 .num_parents = 3,
 328                 .ops = &clk_rcg2_shared_ops,
 329         },
 330 };
 331
 332 static struct clk_rcg2 cam_cc_cci_1_clk_src = {
 333         .cmd_rcgr = 0xb14c,
 334         .mnd_width = 8,
 335         .hid_width = 5,
 336         .parent_map = cam_cc_parent_map_5,
 337         .freq_tbl = ftbl_cam_cc_cci_0_clk_src,
 338         .clkr.hw.init = &(struct clk_init_data){
 339                 .name = "cam_cc_cci_1_clk_src",
 340                 .parent_data = cam_cc_parent_data_5,
 341                 .num_parents = 3,
 342                 .ops = &clk_rcg2_shared_ops,
 343         },
 344 };
 345
 346 static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
 347         F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
 348         F(270000000, P_CAM_CC_PLL3_OUT_MAIN, 4, 0, 0),
 349         F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
 350         { }
 351 };
 352
 353 static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
 354         .cmd_rcgr = 0x9064,
 355         .mnd_width = 0,
 356         .hid_width = 5,
 357         .parent_map = cam_cc_parent_map_3,
 358         .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
 359         .clkr.hw.init = &(struct clk_init_data){
 360                 .name = "cam_cc_cphy_rx_clk_src",
 361                 .parent_data = cam_cc_parent_data_3,
 362                 .num_parents = 6,
 363                 .ops = &clk_rcg2_shared_ops,
 364         },
 365 };
 366
 367 static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = {
 368         F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
 369         { }
 370 };
 371
 372 static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
 373         .cmd_rcgr = 0x5004,
 374         .mnd_width = 0,
 375         .hid_width = 5,
 376         .parent_map = cam_cc_parent_map_0,
 377         .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
 378         .clkr.hw.init = &(struct clk_init_data){
 379                 .name = "cam_cc_csi0phytimer_clk_src",
 380                 .parent_data = cam_cc_parent_data_0,
 381                 .num_parents = 4,
 382                 .ops = &clk_rcg2_shared_ops,
 383         },
 384 };
 385
 386 static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
 387         .cmd_rcgr = 0x5028,
 388         .mnd_width = 0,
 389         .hid_width = 5,
 390         .parent_map = cam_cc_parent_map_0,
 391         .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
 392         .clkr.hw.init = &(struct clk_init_data){
 393                 .name = "cam_cc_csi1phytimer_clk_src",
 394                 .parent_data = cam_cc_parent_data_0,
 395                 .num_parents = 4,
 396                 .ops = &clk_rcg2_shared_ops,
 397         },
 398 };
 399
 400 static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
 401         .cmd_rcgr = 0x504c,
 402         .mnd_width = 0,
 403         .hid_width = 5,
 404         .parent_map = cam_cc_parent_map_0,
 405         .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
 406         .clkr.hw.init = &(struct clk_init_data){
 407                 .name = "cam_cc_csi2phytimer_clk_src",
 408                 .parent_data = cam_cc_parent_data_0,
 409                 .num_parents = 4,
 410                 .ops = &clk_rcg2_shared_ops,
 411         },
 412 };
 413
 414 static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
 415         .cmd_rcgr = 0x5070,
 416         .mnd_width = 0,
 417         .hid_width = 5,
 418         .parent_map = cam_cc_parent_map_0,
 419         .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
 420         .clkr.hw.init = &(struct clk_init_data){
 421                 .name = "cam_cc_csi3phytimer_clk_src",
 422                 .parent_data = cam_cc_parent_data_0,
 423                 .num_parents = 4,
 424                 .ops = &clk_rcg2_shared_ops,
 425         },
 426 };
 427
 428 static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {
 429         F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
 430         F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
 431         F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
 432         F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0),
 433         { }
 434 };
 435
 436 static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
 437         .cmd_rcgr = 0x603c,
 438         .mnd_width = 0,
 439         .hid_width = 5,
 440         .parent_map = cam_cc_parent_map_0,
 441         .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
 442         .clkr.hw.init = &(struct clk_init_data){
 443                 .name = "cam_cc_fast_ahb_clk_src",
 444                 .parent_data = cam_cc_parent_data_0,
 445                 .num_parents = 4,
 446                 .ops = &clk_rcg2_shared_ops,
 447         },
 448 };
 449
 450 static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = {
 451         F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0),
 452         F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
 453         F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0),
 454         F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0),
 455         F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
 456         { }
 457 };
 458
 459 static struct clk_rcg2 cam_cc_icp_clk_src = {
 460         .cmd_rcgr = 0xb088,
 461         .mnd_width = 0,
 462         .hid_width = 5,
 463         .parent_map = cam_cc_parent_map_2,
 464         .freq_tbl = ftbl_cam_cc_icp_clk_src,
 465         .clkr.hw.init = &(struct clk_init_data){
 466                 .name = "cam_cc_icp_clk_src",
 467                 .parent_data = cam_cc_parent_data_2,
 468                 .num_parents = 5,
 469                 .ops = &clk_rcg2_shared_ops,
 470         },
 471 };
 472
 473 static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = {
 474         F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0),
 475         F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
 476         F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0),
 477         F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
 478         { }
 479 };
 480
 481 static struct clk_rcg2 cam_cc_ife_0_clk_src = {
 482         .cmd_rcgr = 0x9010,
 483         .mnd_width = 0,
 484         .hid_width = 5,
 485         .parent_map = cam_cc_parent_map_4,
 486         .freq_tbl = ftbl_cam_cc_ife_0_clk_src,
 487         .clkr.hw.init = &(struct clk_init_data){
 488                 .name = "cam_cc_ife_0_clk_src",
 489                 .parent_data = cam_cc_parent_data_4,
 490                 .num_parents = 4,
 491                 .ops = &clk_rcg2_shared_ops,
 492         },
 493 };
 494
 495 static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = {
 496         F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
 497         F(270000000, P_CAM_CC_PLL3_OUT_MAIN, 4, 0, 0),
 498         F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
 499         F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0),
 500         { }
 501 };
 502
 503 static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = {
 504         .cmd_rcgr = 0x903c,
 505         .mnd_width = 0,
 506         .hid_width = 5,
 507         .parent_map = cam_cc_parent_map_3,
 508         .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
 509         .clkr.hw.init = &(struct clk_init_data){
 510                 .name = "cam_cc_ife_0_csid_clk_src",
 511                 .parent_data = cam_cc_parent_data_3,
 512                 .num_parents = 6,
 513                 .ops = &clk_rcg2_shared_ops,
 514         },
 515 };
 516
 517 static struct clk_rcg2 cam_cc_ife_1_clk_src = {
 518         .cmd_rcgr = 0xa010,
 519         .mnd_width = 0,
 520         .hid_width = 5,
 521         .parent_map = cam_cc_parent_map_4,
 522         .freq_tbl = ftbl_cam_cc_ife_0_clk_src,
 523         .clkr.hw.init = &(struct clk_init_data){
 524                 .name = "cam_cc_ife_1_clk_src",
 525                 .parent_data = cam_cc_parent_data_4,
 526                 .num_parents = 4,
 527                 .ops = &clk_rcg2_shared_ops,
 528         },
 529 };
 530
 531 static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = {
 532         .cmd_rcgr = 0xa034,
 533         .mnd_width = 0,
 534         .hid_width = 5,
 535         .parent_map = cam_cc_parent_map_3,
 536         .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
 537         .clkr.hw.init = &(struct clk_init_data){
 538                 .name = "cam_cc_ife_1_csid_clk_src",
 539                 .parent_data = cam_cc_parent_data_3,
 540                 .num_parents = 6,
 541                 .ops = &clk_rcg2_shared_ops,
 542         },
 543 };
 544
 545 static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
 546         .cmd_rcgr = 0xb004,
 547         .mnd_width = 0,
 548         .hid_width = 5,
 549         .parent_map = cam_cc_parent_map_4,
 550         .freq_tbl = ftbl_cam_cc_ife_0_clk_src,
 551         .clkr.hw.init = &(struct clk_init_data){
 552                 .name = "cam_cc_ife_lite_clk_src",
 553                 .parent_data = cam_cc_parent_data_4,
 554                 .num_parents = 4,
 555                 .flags = CLK_SET_RATE_PARENT,
 556                 .ops = &clk_rcg2_shared_ops,
 557         },
 558 };
 559
 560 static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
 561         .cmd_rcgr = 0xb024,
 562         .mnd_width = 0,
 563         .hid_width = 5,
 564         .parent_map = cam_cc_parent_map_3,
 565         .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
 566         .clkr.hw.init = &(struct clk_init_data){
 567                 .name = "cam_cc_ife_lite_csid_clk_src",
 568                 .parent_data = cam_cc_parent_data_3,
 569                 .num_parents = 6,
 570                 .ops = &clk_rcg2_shared_ops,
 571         },
 572 };
 573
 574 static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] = {
 575         F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0),
 576         F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
 577         F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0),
 578         F(540000000, P_CAM_CC_PLL3_OUT_MAIN, 2, 0, 0),
 579         F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
 580         { }
 581 };
 582
 583 static struct clk_rcg2 cam_cc_ipe_0_clk_src = {
 584         .cmd_rcgr = 0x7010,
 585         .mnd_width = 0,
 586         .hid_width = 5,
 587         .parent_map = cam_cc_parent_map_2,
 588         .freq_tbl = ftbl_cam_cc_ipe_0_clk_src,
 589         .clkr.hw.init = &(struct clk_init_data){
 590                 .name = "cam_cc_ipe_0_clk_src",
 591                 .parent_data = cam_cc_parent_data_2,
 592                 .num_parents = 5,
 593                 .ops = &clk_rcg2_shared_ops,
 594         },
 595 };
 596
 597 static const struct freq_tbl ftbl_cam_cc_jpeg_clk_src[] = {
 598         F(66666667, P_CAM_CC_PLL0_OUT_EVEN, 9, 0, 0),
 599         F(133333333, P_CAM_CC_PLL0_OUT_EVEN, 4.5, 0, 0),
 600         F(216000000, P_CAM_CC_PLL3_OUT_MAIN, 5, 0, 0),
 601         F(320000000, P_CAM_CC_PLL2_OUT_EARLY, 3, 0, 0),
 602         F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
 603         { }
 604 };
 605
 606 static struct clk_rcg2 cam_cc_jpeg_clk_src = {
 607         .cmd_rcgr = 0xb04c,
 608         .mnd_width = 0,
 609         .hid_width = 5,
 610         .parent_map = cam_cc_parent_map_2,
 611         .freq_tbl = ftbl_cam_cc_jpeg_clk_src,
 612         .clkr.hw.init = &(struct clk_init_data){
 613                 .name = "cam_cc_jpeg_clk_src",
 614                 .parent_data = cam_cc_parent_data_2,
 615                 .num_parents = 5,
 616                 .ops = &clk_rcg2_shared_ops,
 617         },
 618 };
 619
 620 static const struct freq_tbl ftbl_cam_cc_lrme_clk_src[] = {
 621         F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
 622         F(216000000, P_CAM_CC_PLL3_OUT_MAIN, 5, 0, 0),
 623         F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
 624         F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0),
 625         { }
 626 };
 627
 628 static struct clk_rcg2 cam_cc_lrme_clk_src = {
 629         .cmd_rcgr = 0xb0f8,
 630         .mnd_width = 0,
 631         .hid_width = 5,
 632         .parent_map = cam_cc_parent_map_6,
 633         .freq_tbl = ftbl_cam_cc_lrme_clk_src,
 634         .clkr.hw.init = &(struct clk_init_data){
 635                 .name = "cam_cc_lrme_clk_src",
 636                 .parent_data = cam_cc_parent_data_6,
 637                 .num_parents = 5,
 638                 .ops = &clk_rcg2_shared_ops,
 639         },
 640 };
 641
 642 static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = {
 643         F(19200000, P_BI_TCXO, 1, 0, 0),
 644         F(24000000, P_CAM_CC_PLL2_OUT_AUX, 10, 1, 2),
 645         F(64000000, P_CAM_CC_PLL2_OUT_AUX, 7.5, 0, 0),
 646         { }
 647 };
 648
 649 static struct clk_rcg2 cam_cc_mclk0_clk_src = {
 650         .cmd_rcgr = 0x4004,
 651         .mnd_width = 8,
 652         .hid_width = 5,
 653         .parent_map = cam_cc_parent_map_1,
 654         .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
 655         .clkr.hw.init = &(struct clk_init_data){
 656                 .name = "cam_cc_mclk0_clk_src",
 657                 .parent_data = cam_cc_parent_data_1,
 658                 .num_parents = 3,
 659                 .ops = &clk_rcg2_shared_ops,
 660         },
 661 };
 662
 663 static struct clk_rcg2 cam_cc_mclk1_clk_src = {
 664         .cmd_rcgr = 0x4024,
 665         .mnd_width = 8,
 666         .hid_width = 5,
 667         .parent_map = cam_cc_parent_map_1,
 668         .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
 669         .clkr.hw.init = &(struct clk_init_data){
 670                 .name = "cam_cc_mclk1_clk_src",
 671                 .parent_data = cam_cc_parent_data_1,
 672                 .num_parents = 3,
 673                 .ops = &clk_rcg2_shared_ops,
 674         },
 675 };
 676
 677 static struct clk_rcg2 cam_cc_mclk2_clk_src = {
 678         .cmd_rcgr = 0x4044,
 679         .mnd_width = 8,
 680         .hid_width = 5,
 681         .parent_map = cam_cc_parent_map_1,
 682         .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
 683         .clkr.hw.init = &(struct clk_init_data){
 684                 .name = "cam_cc_mclk2_clk_src",
 685                 .parent_data = cam_cc_parent_data_1,
 686                 .num_parents = 3,
 687                 .ops = &clk_rcg2_shared_ops,
 688         },
 689 };
 690
 691 static struct clk_rcg2 cam_cc_mclk3_clk_src = {
 692         .cmd_rcgr = 0x4064,
 693         .mnd_width = 8,
 694         .hid_width = 5,
 695         .parent_map = cam_cc_parent_map_1,
 696         .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
 697         .clkr.hw.init = &(struct clk_init_data){
 698                 .name = "cam_cc_mclk3_clk_src",
 699                 .parent_data = cam_cc_parent_data_1,
 700                 .num_parents = 3,
 701                 .ops = &clk_rcg2_shared_ops,
 702         },
 703 };
 704
 705 static struct clk_rcg2 cam_cc_mclk4_clk_src = {
 706         .cmd_rcgr = 0x4084,
 707         .mnd_width = 8,
 708         .hid_width = 5,
 709         .parent_map = cam_cc_parent_map_1,
 710         .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
 711         .clkr.hw.init = &(struct clk_init_data){
 712                 .name = "cam_cc_mclk4_clk_src",
 713                 .parent_data = cam_cc_parent_data_1,
 714                 .num_parents = 3,
 715                 .ops = &clk_rcg2_shared_ops,
 716         },
 717 };
 718
 719 static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
 720         F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
 721         { }
 722 };
 723
 724 static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
 725         .cmd_rcgr = 0x6058,
 726         .mnd_width = 0,
 727         .hid_width = 5,
 728         .parent_map = cam_cc_parent_map_0,
 729         .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
 730         .clkr.hw.init = &(struct clk_init_data){
 731                 .name = "cam_cc_slow_ahb_clk_src",
 732                 .parent_data = cam_cc_parent_data_0,
 733                 .num_parents = 4,
 734                 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 735                 .ops = &clk_rcg2_shared_ops,
 736         },
 737 };
 738
 739 static struct clk_branch cam_cc_bps_ahb_clk = {
 740         .halt_reg = 0x6070,
 741         .halt_check = BRANCH_HALT,
 742         .clkr = {
 743                 .enable_reg = 0x6070,
 744                 .enable_mask = BIT(0),
 745                 .hw.init = &(struct clk_init_data){
 746                         .name = "cam_cc_bps_ahb_clk",
 747                         .parent_data = &(const struct clk_parent_data){
 748                                 .hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
 749                         },
 750                         .num_parents = 1,
 751                         .flags = CLK_SET_RATE_PARENT,
 752                         .ops = &clk_branch2_ops,
 753                 },
 754         },
 755 };
 756
 757 static struct clk_branch cam_cc_bps_areg_clk = {
 758         .halt_reg = 0x6054,
 759         .halt_check = BRANCH_HALT,
 760         .clkr = {
 761                 .enable_reg = 0x6054,
 762                 .enable_mask = BIT(0),
 763                 .hw.init = &(struct clk_init_data){
 764                         .name = "cam_cc_bps_areg_clk",
 765                         .parent_data = &(const struct clk_parent_data){
 766                                 .hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
 767                         },
 768                         .num_parents = 1,
 769                         .flags = CLK_SET_RATE_PARENT,
 770                         .ops = &clk_branch2_ops,
 771                 },
 772         },
 773 };
 774
 775 static struct clk_branch cam_cc_bps_axi_clk = {
 776         .halt_reg = 0x6038,
 777         .halt_check = BRANCH_HALT,
 778         .clkr = {
 779                 .enable_reg = 0x6038,
 780                 .enable_mask = BIT(0),
 781                 .hw.init = &(struct clk_init_data){
 782                         .name = "cam_cc_bps_axi_clk",
 783                         .ops = &clk_branch2_ops,
 784                 },
 785         },
 786 };
 787
 788 static struct clk_branch cam_cc_bps_clk = {
 789         .halt_reg = 0x6028,
 790         .halt_check = BRANCH_HALT,
 791         .clkr = {
 792                 .enable_reg = 0x6028,
 793                 .enable_mask = BIT(0),
 794                 .hw.init = &(struct clk_init_data){
 795                         .name = "cam_cc_bps_clk",
 796                         .parent_data = &(const struct clk_parent_data){
 797                                 .hw = &cam_cc_bps_clk_src.clkr.hw,
 798                         },
 799                         .num_parents = 1,
 800                         .flags = CLK_SET_RATE_PARENT,
 801                         .ops = &clk_branch2_ops,
 802                 },
 803         },
 804 };
 805
 806 static struct clk_branch cam_cc_camnoc_axi_clk = {
 807         .halt_reg = 0xb124,
 808         .halt_check = BRANCH_HALT,
 809         .clkr = {
 810                 .enable_reg = 0xb124,
 811                 .enable_mask = BIT(0),
 812                 .hw.init = &(struct clk_init_data){
 813                         .name = "cam_cc_camnoc_axi_clk",
 814                         .ops = &clk_branch2_ops,
 815                 },
 816         },
 817 };
 818
 819 static struct clk_branch cam_cc_cci_0_clk = {
 820         .halt_reg = 0xb0f0,
 821         .halt_check = BRANCH_HALT,
 822         .clkr = {
 823                 .enable_reg = 0xb0f0,
 824                 .enable_mask = BIT(0),
 825                 .hw.init = &(struct clk_init_data){
 826                         .name = "cam_cc_cci_0_clk",
 827                         .parent_data = &(const struct clk_parent_data){
 828                                 .hw = &cam_cc_cci_0_clk_src.clkr.hw,
 829                         },
 830                         .num_parents = 1,
 831                         .flags = CLK_SET_RATE_PARENT,
 832                         .ops = &clk_branch2_ops,
 833                 },
 834         },
 835 };
 836
 837 static struct clk_branch cam_cc_cci_1_clk = {
 838         .halt_reg = 0xb164,
 839         .halt_check = BRANCH_HALT,
 840         .clkr = {
 841                 .enable_reg = 0xb164,
 842                 .enable_mask = BIT(0),
 843                 .hw.init = &(struct clk_init_data){
 844                         .name = "cam_cc_cci_1_clk",
 845                         .parent_data = &(const struct clk_parent_data){
 846                                 .hw = &cam_cc_cci_1_clk_src.clkr.hw,
 847                         },
 848                         .num_parents = 1,
 849                         .flags = CLK_SET_RATE_PARENT,
 850                         .ops = &clk_branch2_ops,
 851                 },
 852         },
 853 };
 854
 855 static struct clk_branch cam_cc_core_ahb_clk = {
 856         .halt_reg = 0xb144,
 857         .halt_check = BRANCH_HALT_DELAY,
 858         .clkr = {
 859                 .enable_reg = 0xb144,
 860                 .enable_mask = BIT(0),
 861                 .hw.init = &(struct clk_init_data){
 862                         .name = "cam_cc_core_ahb_clk",
 863                         .parent_data = &(const struct clk_parent_data){
 864                                 .hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
 865                         },
 866                         .num_parents = 1,
 867                         .flags = CLK_SET_RATE_PARENT,
 868                         .ops = &clk_branch2_ops,
 869                 },
 870         },
 871 };
 872
 873 static struct clk_branch cam_cc_cpas_ahb_clk = {
 874         .halt_reg = 0xb11c,
 875         .halt_check = BRANCH_HALT,
 876         .clkr = {
 877                 .enable_reg = 0xb11c,
 878                 .enable_mask = BIT(0),
 879                 .hw.init = &(struct clk_init_data){
 880                         .name = "cam_cc_cpas_ahb_clk",
 881                         .parent_data = &(const struct clk_parent_data){
 882                                 .hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
 883                         },
 884                         .num_parents = 1,
 885                         .flags = CLK_SET_RATE_PARENT,
 886                         .ops = &clk_branch2_ops,
 887                 },
 888         },
 889 };
 890
 891 static struct clk_branch cam_cc_csi0phytimer_clk = {
 892         .halt_reg = 0x501c,
 893         .halt_check = BRANCH_HALT,
 894         .clkr = {
 895                 .enable_reg = 0x501c,
 896                 .enable_mask = BIT(0),
 897                 .hw.init = &(struct clk_init_data){
 898                         .name = "cam_cc_csi0phytimer_clk",
 899                         .parent_data = &(const struct clk_parent_data){
 900                                 .hw = &cam_cc_csi0phytimer_clk_src.clkr.hw,
 901                         },
 902                         .num_parents = 1,
 903                         .flags = CLK_SET_RATE_PARENT,
 904                         .ops = &clk_branch2_ops,
 905                 },
 906         },
 907 };
 908
 909 static struct clk_branch cam_cc_csi1phytimer_clk = {
 910         .halt_reg = 0x5040,
 911         .halt_check = BRANCH_HALT,
 912         .clkr = {
 913                 .enable_reg = 0x5040,
 914                 .enable_mask = BIT(0),
 915                 .hw.init = &(struct clk_init_data){
 916                         .name = "cam_cc_csi1phytimer_clk",
 917                         .parent_data = &(const struct clk_parent_data){
 918                                 .hw = &cam_cc_csi1phytimer_clk_src.clkr.hw,
 919                         },
 920                         .num_parents = 1,
 921                         .flags = CLK_SET_RATE_PARENT,
 922                         .ops = &clk_branch2_ops,
 923                 },
 924         },
 925 };
 926
 927 static struct clk_branch cam_cc_csi2phytimer_clk = {
 928         .halt_reg = 0x5064,
 929         .halt_check = BRANCH_HALT,
 930         .clkr = {
 931                 .enable_reg = 0x5064,
 932                 .enable_mask = BIT(0),
 933                 .hw.init = &(struct clk_init_data){
 934                         .name = "cam_cc_csi2phytimer_clk",
 935                         .parent_data = &(const struct clk_parent_data){
 936                                 .hw = &cam_cc_csi2phytimer_clk_src.clkr.hw,
 937                         },
 938                         .num_parents = 1,
 939                         .flags = CLK_SET_RATE_PARENT,
 940                         .ops = &clk_branch2_ops,
 941                 },
 942         },
 943 };
 944
 945 static struct clk_branch cam_cc_csi3phytimer_clk = {
 946         .halt_reg = 0x5088,
 947         .halt_check = BRANCH_HALT,
 948         .clkr = {
 949                 .enable_reg = 0x5088,
 950                 .enable_mask = BIT(0),
 951                 .hw.init = &(struct clk_init_data){
 952                         .name = "cam_cc_csi3phytimer_clk",
 953                         .parent_data = &(const struct clk_parent_data){
 954                                 .hw = &cam_cc_csi3phytimer_clk_src.clkr.hw,
 955                         },
 956                         .num_parents = 1,
 957                         .flags = CLK_SET_RATE_PARENT,
 958                         .ops = &clk_branch2_ops,
 959                 },
 960         },
 961 };
 962
 963 static struct clk_branch cam_cc_csiphy0_clk = {
 964         .halt_reg = 0x5020,
 965         .halt_check = BRANCH_HALT,
 966         .clkr = {
 967                 .enable_reg = 0x5020,
 968                 .enable_mask = BIT(0),
 969                 .hw.init = &(struct clk_init_data){
 970                         .name = "cam_cc_csiphy0_clk",
 971                         .parent_data = &(const struct clk_parent_data){
 972                                 .hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
 973                         },
 974                         .num_parents = 1,
 975                         .flags = CLK_SET_RATE_PARENT,
 976                         .ops = &clk_branch2_ops,
 977                 },
 978         },
 979 };
 980
 981 static struct clk_branch cam_cc_csiphy1_clk = {
 982         .halt_reg = 0x5044,
 983         .halt_check = BRANCH_HALT,
 984         .clkr = {
 985                 .enable_reg = 0x5044,
 986                 .enable_mask = BIT(0),
 987                 .hw.init = &(struct clk_init_data){
 988                         .name = "cam_cc_csiphy1_clk",
 989                         .parent_data = &(const struct clk_parent_data){
 990                                 .hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
 991                         },
 992                         .num_parents = 1,
 993                         .flags = CLK_SET_RATE_PARENT,
 994                         .ops = &clk_branch2_ops,
 995                 },
 996         },
 997 };
 998
 999 static struct clk_branch cam_cc_csiphy2_clk = {
1000         .halt_reg = 0x5068,
1001         .halt_check = BRANCH_HALT,
1002         .clkr = {
1003                 .enable_reg = 0x5068,
1004                 .enable_mask = BIT(0),
1005                 .hw.init = &(struct clk_init_data){
1006                         .name = "cam_cc_csiphy2_clk",
1007                         .parent_data = &(const struct clk_parent_data){
1008                                 .hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
1009                         },
1010                         .num_parents = 1,
1011                         .flags = CLK_SET_RATE_PARENT,
1012                         .ops = &clk_branch2_ops,
1013                 },
1014         },
1015 };
1016
1017 static struct clk_branch cam_cc_csiphy3_clk = {
1018         .halt_reg = 0x508c,
1019         .halt_check = BRANCH_HALT,
1020         .clkr = {
1021                 .enable_reg = 0x508c,
1022                 .enable_mask = BIT(0),
1023                 .hw.init = &(struct clk_init_data){
1024                         .name = "cam_cc_csiphy3_clk",
1025                         .parent_data = &(const struct clk_parent_data){
1026                                 .hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
1027                         },
1028                         .num_parents = 1,
1029                         .flags = CLK_SET_RATE_PARENT,
1030                         .ops = &clk_branch2_ops,
1031                 },
1032         },
1033 };
1034
1035 static struct clk_branch cam_cc_icp_clk = {
1036         .halt_reg = 0xb0a0,
1037         .halt_check = BRANCH_HALT,
1038         .clkr = {
1039                 .enable_reg = 0xb0a0,
1040                 .enable_mask = BIT(0),
1041                 .hw.init = &(struct clk_init_data){
1042                         .name = "cam_cc_icp_clk",
1043                         .parent_data = &(const struct clk_parent_data){
1044                                 .hw = &cam_cc_icp_clk_src.clkr.hw,
1045                         },
1046                         .num_parents = 1,
1047                         .flags = CLK_SET_RATE_PARENT,
1048                         .ops = &clk_branch2_ops,
1049                 },
1050         },
1051 };
1052
1053 static struct clk_branch cam_cc_ife_0_axi_clk = {
1054         .halt_reg = 0x9080,
1055         .halt_check = BRANCH_HALT,
1056         .clkr = {
1057                 .enable_reg = 0x9080,
1058                 .enable_mask = BIT(0),
1059                 .hw.init = &(struct clk_init_data){
1060                         .name = "cam_cc_ife_0_axi_clk",
1061                         .ops = &clk_branch2_ops,
1062                 },
1063         },
1064 };
1065
1066 static struct clk_branch cam_cc_ife_0_clk = {
1067         .halt_reg = 0x9028,
1068         .halt_check = BRANCH_HALT,
1069         .clkr = {
1070                 .enable_reg = 0x9028,
1071                 .enable_mask = BIT(0),
1072                 .hw.init = &(struct clk_init_data){
1073                         .name = "cam_cc_ife_0_clk",
1074                         .parent_data = &(const struct clk_parent_data){
1075                                 .hw = &cam_cc_ife_0_clk_src.clkr.hw,
1076                         },
1077                         .num_parents = 1,
1078                         .flags = CLK_SET_RATE_PARENT,
1079                         .ops = &clk_branch2_ops,
1080                 },
1081         },
1082 };
1083
1084 static struct clk_branch cam_cc_ife_0_cphy_rx_clk = {
1085         .halt_reg = 0x907c,
1086         .halt_check = BRANCH_HALT,
1087         .clkr = {
1088                 .enable_reg = 0x907c,
1089                 .enable_mask = BIT(0),
1090                 .hw.init = &(struct clk_init_data){
1091                         .name = "cam_cc_ife_0_cphy_rx_clk",
1092                         .parent_data = &(const struct clk_parent_data){
1093                                 .hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
1094                         },
1095                         .num_parents = 1,
1096                         .flags = CLK_SET_RATE_PARENT,
1097                         .ops = &clk_branch2_ops,
1098                 },
1099         },
1100 };
1101
1102 static struct clk_branch cam_cc_ife_0_csid_clk = {
1103         .halt_reg = 0x9054,
1104         .halt_check = BRANCH_HALT,
1105         .clkr = {
1106                 .enable_reg = 0x9054,
1107                 .enable_mask = BIT(0),
1108                 .hw.init = &(struct clk_init_data){
1109                         .name = "cam_cc_ife_0_csid_clk",
1110                         .parent_data = &(const struct clk_parent_data){
1111                                 .hw = &cam_cc_ife_0_csid_clk_src.clkr.hw,
1112                         },
1113                         .num_parents = 1,
1114                         .flags = CLK_SET_RATE_PARENT,
1115                         .ops = &clk_branch2_ops,
1116                 },
1117         },
1118 };
1119
1120 static struct clk_branch cam_cc_ife_0_dsp_clk = {
1121         .halt_reg = 0x9038,
1122         .halt_check = BRANCH_HALT,
1123         .clkr = {
1124                 .enable_reg = 0x9038,
1125                 .enable_mask = BIT(0),
1126                 .hw.init = &(struct clk_init_data){
1127                         .name = "cam_cc_ife_0_dsp_clk",
1128                         .parent_data = &(const struct clk_parent_data){
1129                                 .hw = &cam_cc_ife_0_clk_src.clkr.hw,
1130                         },
1131                         .num_parents = 1,
1132                         .flags = CLK_SET_RATE_PARENT,
1133                         .ops = &clk_branch2_ops,
1134                 },
1135         },
1136 };
1137
1138 static struct clk_branch cam_cc_ife_1_axi_clk = {
1139         .halt_reg = 0xa058,
1140         .halt_check = BRANCH_HALT,
1141         .clkr = {
1142                 .enable_reg = 0xa058,
1143                 .enable_mask = BIT(0),
1144                 .hw.init = &(struct clk_init_data){
1145                         .name = "cam_cc_ife_1_axi_clk",
1146                         .ops = &clk_branch2_ops,
1147                 },
1148         },
1149 };
1150
1151 static struct clk_branch cam_cc_ife_1_clk = {
1152         .halt_reg = 0xa028,
1153         .halt_check = BRANCH_HALT,
1154         .clkr = {
1155                 .enable_reg = 0xa028,
1156                 .enable_mask = BIT(0),
1157                 .hw.init = &(struct clk_init_data){
1158                         .name = "cam_cc_ife_1_clk",
1159                         .parent_data = &(const struct clk_parent_data){
1160                                 .hw = &cam_cc_ife_1_clk_src.clkr.hw,
1161                         },
1162                         .num_parents = 1,
1163                         .flags = CLK_SET_RATE_PARENT,
1164                         .ops = &clk_branch2_ops,
1165                 },
1166         },
1167 };
1168
1169 static struct clk_branch cam_cc_ife_1_cphy_rx_clk = {
1170         .halt_reg = 0xa054,
1171         .halt_check = BRANCH_HALT,
1172         .clkr = {
1173                 .enable_reg = 0xa054,
1174                 .enable_mask = BIT(0),
1175                 .hw.init = &(struct clk_init_data){
1176                         .name = "cam_cc_ife_1_cphy_rx_clk",
1177                         .parent_data = &(const struct clk_parent_data){
1178                                 .hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
1179                         },
1180                         .num_parents = 1,
1181                         .flags = CLK_SET_RATE_PARENT,
1182                         .ops = &clk_branch2_ops,
1183                 },
1184         },
1185 };
1186
1187 static struct clk_branch cam_cc_ife_1_csid_clk = {
1188         .halt_reg = 0xa04c,
1189         .halt_check = BRANCH_HALT,
1190         .clkr = {
1191                 .enable_reg = 0xa04c,
1192                 .enable_mask = BIT(0),
1193                 .hw.init = &(struct clk_init_data){
1194                         .name = "cam_cc_ife_1_csid_clk",
1195                         .parent_data = &(const struct clk_parent_data){
1196                                 .hw = &cam_cc_ife_1_csid_clk_src.clkr.hw,
1197                         },
1198                         .num_parents = 1,
1199                         .flags = CLK_SET_RATE_PARENT,
1200                         .ops = &clk_branch2_ops,
1201                 },
1202         },
1203 };
1204
1205 static struct clk_branch cam_cc_ife_1_dsp_clk = {
1206         .halt_reg = 0xa030,
1207         .halt_check = BRANCH_HALT,
1208         .clkr = {
1209                 .enable_reg = 0xa030,
1210                 .enable_mask = BIT(0),
1211                 .hw.init = &(struct clk_init_data){
1212                         .name = "cam_cc_ife_1_dsp_clk",
1213                         .parent_data = &(const struct clk_parent_data){
1214                                 .hw = &cam_cc_ife_1_clk_src.clkr.hw,
1215                         },
1216                         .num_parents = 1,
1217                         .flags = CLK_SET_RATE_PARENT,
1218                         .ops = &clk_branch2_ops,
1219                 },
1220         },
1221 };
1222
1223 static struct clk_branch cam_cc_ife_lite_clk = {
1224         .halt_reg = 0xb01c,
1225         .halt_check = BRANCH_HALT,
1226         .clkr = {
1227                 .enable_reg = 0xb01c,
1228                 .enable_mask = BIT(0),
1229                 .hw.init = &(struct clk_init_data){
1230                         .name = "cam_cc_ife_lite_clk",
1231                         .parent_data = &(const struct clk_parent_data){
1232                                 .hw = &cam_cc_ife_lite_clk_src.clkr.hw,
1233                         },
1234                         .num_parents = 1,
1235                         .flags = CLK_SET_RATE_PARENT,
1236                         .ops = &clk_branch2_ops,
1237                 },
1238         },
1239 };
1240
1241 static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
1242         .halt_reg = 0xb044,
1243         .halt_check = BRANCH_HALT,
1244         .clkr = {
1245                 .enable_reg = 0xb044,
1246                 .enable_mask = BIT(0),
1247                 .hw.init = &(struct clk_init_data){
1248                         .name = "cam_cc_ife_lite_cphy_rx_clk",
1249                         .parent_data = &(const struct clk_parent_data){
1250                                 .hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
1251                         },
1252                         .num_parents = 1,
1253                         .flags = CLK_SET_RATE_PARENT,
1254                         .ops = &clk_branch2_ops,
1255                 },
1256         },
1257 };
1258
1259 static struct clk_branch cam_cc_ife_lite_csid_clk = {
1260         .halt_reg = 0xb03c,
1261         .halt_check = BRANCH_HALT,
1262         .clkr = {
1263                 .enable_reg = 0xb03c,
1264                 .enable_mask = BIT(0),
1265                 .hw.init = &(struct clk_init_data){
1266                         .name = "cam_cc_ife_lite_csid_clk",
1267                         .parent_data = &(const struct clk_parent_data){
1268                                 .hw = &cam_cc_ife_lite_csid_clk_src.clkr.hw,
1269                         },
1270                         .num_parents = 1,
1271                         .flags = CLK_SET_RATE_PARENT,
1272                         .ops = &clk_branch2_ops,
1273                 },
1274         },
1275 };
1276
1277 static struct clk_branch cam_cc_ipe_0_ahb_clk = {
1278         .halt_reg = 0x7040,
1279         .halt_check = BRANCH_HALT,
1280         .clkr = {
1281                 .enable_reg = 0x7040,
1282                 .enable_mask = BIT(0),
1283                 .hw.init = &(struct clk_init_data){
1284                         .name = "cam_cc_ipe_0_ahb_clk",
1285                         .parent_data = &(const struct clk_parent_data){
1286                                 .hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
1287                         },
1288                         .num_parents = 1,
1289                         .flags = CLK_SET_RATE_PARENT,
1290                         .ops = &clk_branch2_ops,
1291                 },
1292         },
1293 };
1294
1295 static struct clk_branch cam_cc_ipe_0_areg_clk = {
1296         .halt_reg = 0x703c,
1297         .halt_check = BRANCH_HALT,
1298         .clkr = {
1299                 .enable_reg = 0x703c,
1300                 .enable_mask = BIT(0),
1301                 .hw.init = &(struct clk_init_data){
1302                         .name = "cam_cc_ipe_0_areg_clk",
1303                         .parent_data = &(const struct clk_parent_data){
1304                                 .hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
1305                         },
1306                         .num_parents = 1,
1307                         .flags = CLK_SET_RATE_PARENT,
1308                         .ops = &clk_branch2_ops,
1309                 },
1310         },
1311 };
1312
1313 static struct clk_branch cam_cc_ipe_0_axi_clk = {
1314         .halt_reg = 0x7038,
1315         .halt_check = BRANCH_HALT,
1316         .clkr = {
1317                 .enable_reg = 0x7038,
1318                 .enable_mask = BIT(0),
1319                 .hw.init = &(struct clk_init_data){
1320                         .name = "cam_cc_ipe_0_axi_clk",
1321                         .ops = &clk_branch2_ops,
1322                 },
1323         },
1324 };
1325
1326 static struct clk_branch cam_cc_ipe_0_clk = {
1327         .halt_reg = 0x7028,
1328         .halt_check = BRANCH_HALT,
1329         .clkr = {
1330                 .enable_reg = 0x7028,
1331                 .enable_mask = BIT(0),
1332                 .hw.init = &(struct clk_init_data){
1333                         .name = "cam_cc_ipe_0_clk",
1334                         .parent_data = &(const struct clk_parent_data){
1335                                 .hw = &cam_cc_ipe_0_clk_src.clkr.hw,
1336                         },
1337                         .num_parents = 1,
1338                         .flags = CLK_SET_RATE_PARENT,
1339                         .ops = &clk_branch2_ops,
1340                 },
1341         },
1342 };
1343
1344 static struct clk_branch cam_cc_jpeg_clk = {
1345         .halt_reg = 0xb064,
1346         .halt_check = BRANCH_HALT,
1347         .clkr = {
1348                 .enable_reg = 0xb064,
1349                 .enable_mask = BIT(0),
1350                 .hw.init = &(struct clk_init_data){
1351                         .name = "cam_cc_jpeg_clk",
1352                         .parent_data = &(const struct clk_parent_data){
1353                                 .hw = &cam_cc_jpeg_clk_src.clkr.hw,
1354                         },
1355                         .num_parents = 1,
1356                         .flags = CLK_SET_RATE_PARENT,
1357                         .ops = &clk_branch2_ops,
1358                 },
1359         },
1360 };
1361
1362 static struct clk_branch cam_cc_lrme_clk = {
1363         .halt_reg = 0xb110,
1364         .halt_check = BRANCH_HALT,
1365         .clkr = {
1366                 .enable_reg = 0xb110,
1367                 .enable_mask = BIT(0),
1368                 .hw.init = &(struct clk_init_data){
1369                         .name = "cam_cc_lrme_clk",
1370                         .parent_data = &(const struct clk_parent_data){
1371                                 .hw = &cam_cc_lrme_clk_src.clkr.hw,
1372                         },
1373                         .num_parents = 1,
1374                         .flags = CLK_SET_RATE_PARENT,
1375                         .ops = &clk_branch2_ops,
1376                 },
1377         },
1378 };
1379
1380 static struct clk_branch cam_cc_mclk0_clk = {
1381         .halt_reg = 0x401c,
1382         .halt_check = BRANCH_HALT,
1383         .clkr = {
1384                 .enable_reg = 0x401c,
1385                 .enable_mask = BIT(0),
1386                 .hw.init = &(struct clk_init_data){
1387                         .name = "cam_cc_mclk0_clk",
1388                         .parent_data = &(const struct clk_parent_data){
1389                                 .hw = &cam_cc_mclk0_clk_src.clkr.hw,
1390                         },
1391                         .num_parents = 1,
1392                         .flags = CLK_SET_RATE_PARENT,
1393                         .ops = &clk_branch2_ops,
1394                 },
1395         },
1396 };
1397
1398 static struct clk_branch cam_cc_mclk1_clk = {
1399         .halt_reg = 0x403c,
1400         .halt_check = BRANCH_HALT,
1401         .clkr = {
1402                 .enable_reg = 0x403c,
1403                 .enable_mask = BIT(0),
1404                 .hw.init = &(struct clk_init_data){
1405                         .name = "cam_cc_mclk1_clk",
1406                         .parent_data = &(const struct clk_parent_data){
1407                                 .hw = &cam_cc_mclk1_clk_src.clkr.hw,
1408                         },
1409                         .num_parents = 1,
1410                         .flags = CLK_SET_RATE_PARENT,
1411                         .ops = &clk_branch2_ops,
1412                 },
1413         },
1414 };
1415
1416 static struct clk_branch cam_cc_mclk2_clk = {
1417         .halt_reg = 0x405c,
1418         .halt_check = BRANCH_HALT,
1419         .clkr = {
1420                 .enable_reg = 0x405c,
1421                 .enable_mask = BIT(0),
1422                 .hw.init = &(struct clk_init_data){
1423                         .name = "cam_cc_mclk2_clk",
1424                         .parent_data = &(const struct clk_parent_data){
1425                                 .hw = &cam_cc_mclk2_clk_src.clkr.hw,
1426                         },
1427                         .num_parents = 1,
1428                         .flags = CLK_SET_RATE_PARENT,
1429                         .ops = &clk_branch2_ops,
1430                 },
1431         },
1432 };
1433
1434 static struct clk_branch cam_cc_mclk3_clk = {
1435         .halt_reg = 0x407c,
1436         .halt_check = BRANCH_HALT,
1437         .clkr = {
1438                 .enable_reg = 0x407c,
1439                 .enable_mask = BIT(0),
1440                 .hw.init = &(struct clk_init_data){
1441                         .name = "cam_cc_mclk3_clk",
1442                         .parent_data = &(const struct clk_parent_data){
1443                                 .hw = &cam_cc_mclk3_clk_src.clkr.hw,
1444                         },
1445                         .num_parents = 1,
1446                         .flags = CLK_SET_RATE_PARENT,
1447                         .ops = &clk_branch2_ops,
1448                 },
1449         },
1450 };
1451
1452 static struct clk_branch cam_cc_mclk4_clk = {
1453         .halt_reg = 0x409c,
1454         .halt_check = BRANCH_HALT,
1455         .clkr = {
1456                 .enable_reg = 0x409c,
1457                 .enable_mask = BIT(0),
1458                 .hw.init = &(struct clk_init_data){
1459                         .name = "cam_cc_mclk4_clk",
1460                         .parent_data = &(const struct clk_parent_data){
1461                                 .hw = &cam_cc_mclk4_clk_src.clkr.hw,
1462                         },
1463                         .num_parents = 1,
1464                         .flags = CLK_SET_RATE_PARENT,
1465                         .ops = &clk_branch2_ops,
1466                 },
1467         },
1468 };
1469
1470 static struct clk_branch cam_cc_soc_ahb_clk = {
1471         .halt_reg = 0xb140,
1472         .halt_check = BRANCH_HALT,
1473         .clkr = {
1474                 .enable_reg = 0xb140,
1475                 .enable_mask = BIT(0),
1476                 .hw.init = &(struct clk_init_data){
1477                         .name = "cam_cc_soc_ahb_clk",
1478                         .ops = &clk_branch2_ops,
1479                 },
1480         },
1481 };
1482
1483 static struct clk_branch cam_cc_sys_tmr_clk = {
1484         .halt_reg = 0xb0a8,
1485         .halt_check = BRANCH_HALT,
1486         .clkr = {
1487                 .enable_reg = 0xb0a8,
1488                 .enable_mask = BIT(0),
1489                 .hw.init = &(struct clk_init_data){
1490                         .name = "cam_cc_sys_tmr_clk",
1491                         .ops = &clk_branch2_ops,
1492                 },
1493         },
1494 };
1495
1496 static struct gdsc bps_gdsc = {
1497         .gdscr = 0x6004,
1498         .pd = {
1499                 .name = "bps_gdsc",
1500         },
1501         .pwrsts = PWRSTS_OFF_ON,
1502         .flags = HW_CTRL,
1503 };
1504
1505 static struct gdsc ife_0_gdsc = {
1506         .gdscr = 0x9004,
1507         .pd = {
1508                 .name = "ife_0_gdsc",
1509         },
1510         .pwrsts = PWRSTS_OFF_ON,
1511 };
1512
1513 static struct gdsc ife_1_gdsc = {
1514         .gdscr = 0xa004,
1515         .pd = {
1516                 .name = "ife_1_gdsc",
1517         },
1518         .pwrsts = PWRSTS_OFF_ON,
1519 };
1520
1521 static struct gdsc ipe_0_gdsc = {
1522         .gdscr = 0x7004,
1523         .pd = {
1524                 .name = "ipe_0_gdsc",
1525         },
1526         .pwrsts = PWRSTS_OFF_ON,
1527         .flags = HW_CTRL,
1528 };
1529
1530 static struct gdsc titan_top_gdsc = {
1531         .gdscr = 0xb134,
1532         .pd = {
1533                 .name = "titan_top_gdsc",
1534         },
1535         .pwrsts = PWRSTS_OFF_ON,
1536 };
1537
1538 static struct clk_hw *cam_cc_sc7180_hws[] = {
1539         [CAM_CC_PLL2_OUT_EARLY] = &cam_cc_pll2_out_early.hw,
1540 };
1541
1542 static struct clk_regmap *cam_cc_sc7180_clocks[] = {
1543         [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr,
1544         [CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr,
1545         [CAM_CC_BPS_AXI_CLK] = &cam_cc_bps_axi_clk.clkr,
1546         [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr,
1547         [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr,
1548         [CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr,
1549         [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr,
1550         [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr,
1551         [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr,
1552         [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr,
1553         [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr,
1554         [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr,
1555         [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr,
1556         [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr,
1557         [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr,
1558         [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr,
1559         [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,
1560         [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,
1561         [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,
1562         [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr,
1563         [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr,
1564         [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,
1565         [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,
1566         [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,
1567         [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr,
1568         [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
1569         [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
1570         [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
1571         [CAM_CC_IFE_0_AXI_CLK] = &cam_cc_ife_0_axi_clk.clkr,
1572         [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr,
1573         [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr,
1574         [CAM_CC_IFE_0_CPHY_RX_CLK] = &cam_cc_ife_0_cphy_rx_clk.clkr,
1575         [CAM_CC_IFE_0_CSID_CLK] = &cam_cc_ife_0_csid_clk.clkr,
1576         [CAM_CC_IFE_0_CSID_CLK_SRC] = &cam_cc_ife_0_csid_clk_src.clkr,
1577         [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr,
1578         [CAM_CC_IFE_1_AXI_CLK] = &cam_cc_ife_1_axi_clk.clkr,
1579         [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr,
1580         [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr,
1581         [CAM_CC_IFE_1_CPHY_RX_CLK] = &cam_cc_ife_1_cphy_rx_clk.clkr,
1582         [CAM_CC_IFE_1_CSID_CLK] = &cam_cc_ife_1_csid_clk.clkr,
1583         [CAM_CC_IFE_1_CSID_CLK_SRC] = &cam_cc_ife_1_csid_clk_src.clkr,
1584         [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr,
1585         [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr,
1586         [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr,
1587         [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr,
1588         [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr,
1589         [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr,
1590         [CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr,
1591         [CAM_CC_IPE_0_AREG_CLK] = &cam_cc_ipe_0_areg_clk.clkr,
1592         [CAM_CC_IPE_0_AXI_CLK] = &cam_cc_ipe_0_axi_clk.clkr,
1593         [CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr,
1594         [CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr,
1595         [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr,
1596         [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr,
1597         [CAM_CC_LRME_CLK] = &cam_cc_lrme_clk.clkr,
1598         [CAM_CC_LRME_CLK_SRC] = &cam_cc_lrme_clk_src.clkr,
1599         [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr,
1600         [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr,
1601         [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr,
1602         [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr,
1603         [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr,
1604         [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr,
1605         [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr,
1606         [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr,
1607         [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr,
1608         [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr,
1609         [CAM_CC_PLL0] = &cam_cc_pll0.clkr,
1610         [CAM_CC_PLL1] = &cam_cc_pll1.clkr,
1611         [CAM_CC_PLL2] = &cam_cc_pll2.clkr,
1612         [CAM_CC_PLL2_OUT_AUX] = &cam_cc_pll2_out_aux.clkr,
1613         [CAM_CC_PLL3] = &cam_cc_pll3.clkr,
1614         [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
1615         [CAM_CC_SOC_AHB_CLK] = &cam_cc_soc_ahb_clk.clkr,
1616         [CAM_CC_SYS_TMR_CLK] = &cam_cc_sys_tmr_clk.clkr,
1617 };
1618 static struct gdsc *cam_cc_sc7180_gdscs[] = {
1619         [BPS_GDSC] = &bps_gdsc,
1620         [IFE_0_GDSC] = &ife_0_gdsc,
1621         [IFE_1_GDSC] = &ife_1_gdsc,
1622         [IPE_0_GDSC] = &ipe_0_gdsc,
1623         [TITAN_TOP_GDSC] = &titan_top_gdsc,
1624 };
1625
1626 static const struct regmap_config cam_cc_sc7180_regmap_config = {
1627         .reg_bits = 32,
1628         .reg_stride = 4,
1629         .val_bits = 32,
1630         .max_register = 0xd028,
1631         .fast_io = true,
1632 };
1633
1634 static const struct qcom_cc_desc cam_cc_sc7180_desc = {
1635         .config = &cam_cc_sc7180_regmap_config,
1636         .clk_hws = cam_cc_sc7180_hws,
1637         .num_clk_hws = ARRAY_SIZE(cam_cc_sc7180_hws),
1638         .clks = cam_cc_sc7180_clocks,
1639         .num_clks = ARRAY_SIZE(cam_cc_sc7180_clocks),
1640         .gdscs = cam_cc_sc7180_gdscs,
1641         .num_gdscs = ARRAY_SIZE(cam_cc_sc7180_gdscs),
1642 };
1643
1644 static const struct of_device_id cam_cc_sc7180_match_table[] = {
1645         { .compatible = "qcom,sc7180-camcc" },
1646         { }
1647 };
1648 MODULE_DEVICE_TABLE(of, cam_cc_sc7180_match_table);
1649
1650 static int cam_cc_sc7180_probe(struct platform_device *pdev)
1651 {
1652         struct regmap *regmap;
1653         int ret;
1654
1655         ret = devm_pm_runtime_enable(&pdev->dev);
1656         if (ret < 0)
1657                 return ret;
1658
1659         ret = devm_pm_clk_create(&pdev->dev);
1660         if (ret < 0)
1661                 return ret;
1662
1663         ret = pm_clk_add(&pdev->dev, "xo");
1664         if (ret < 0) {
1665                 dev_err(&pdev->dev, "Failed to acquire XO clock\n");
1666                 return ret;
1667         }
1668
1669         ret = pm_clk_add(&pdev->dev, "iface");
1670         if (ret < 0) {
1671                 dev_err(&pdev->dev, "Failed to acquire iface clock\n");
1672                 return ret;
1673         }
1674
1675         ret = pm_runtime_get(&pdev->dev);
1676         if (ret)
1677                 return ret;
1678
1679         regmap = qcom_cc_map(pdev, &cam_cc_sc7180_desc);
1680         if (IS_ERR(regmap)) {
1681                 ret = PTR_ERR(regmap);
1682                 pm_runtime_put(&pdev->dev);
1683                 return ret;
1684         }
1685
1686         clk_fabia_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
1687         clk_fabia_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
1688         clk_agera_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
1689         clk_fabia_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
1690
1691         ret = qcom_cc_really_probe(pdev, &cam_cc_sc7180_desc, regmap);
1692         pm_runtime_put(&pdev->dev);
1693         if (ret < 0) {
1694                 dev_err(&pdev->dev, "Failed to register CAM CC clocks\n");
1695                 return ret;
1696         }
1697
1698         return 0;
1699 }
1700
1701 static const struct dev_pm_ops cam_cc_pm_ops = {
1702         SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
1703 };
1704
1705 static struct platform_driver cam_cc_sc7180_driver = {
1706         .probe = cam_cc_sc7180_probe,
1707         .driver = {
1708                 .name = "cam_cc-sc7180",
1709                 .of_match_table = cam_cc_sc7180_match_table,
1710                 .pm = &cam_cc_pm_ops,
1711         },
1712 };
1713
1714 static int __init cam_cc_sc7180_init(void)
1715 {
1716         return platform_driver_register(&cam_cc_sc7180_driver);
1717 }
1718 subsys_initcall(cam_cc_sc7180_init);
1719
1720 static void __exit cam_cc_sc7180_exit(void)
1721 {
1722         platform_driver_unregister(&cam_cc_sc7180_driver);
1723 }
1724 module_exit(cam_cc_sc7180_exit);
1725
1726 MODULE_DESCRIPTION("QTI CAM_CC SC7180 Driver");
1727 MODULE_LICENSE("GPL v2");