1 // SPDX-License-Identifier: GPL-2.0+
3 * Common clock driver for Actions Semi SoCs.
5 * Copyright (C) 2015 Actions Semi Co., Ltd.
6 * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
13 #if defined(CONFIG_MACH_S900)
14 #include <asm/arch-owl/regs_s900.h>
15 #include <dt-bindings/clock/actions,s900-cmu.h>
16 #elif defined(CONFIG_MACH_S700)
17 #include <asm/arch-owl/regs_s700.h>
18 #include <dt-bindings/clock/actions,s700-cmu.h>
20 #include <linux/bitops.h>
21 #include <linux/delay.h>
23 void owl_clk_init(struct owl_clk_priv *priv)
25 u32 bus_clk = 0, core_pll, dev_pll;
27 #if defined(CONFIG_MACH_S900)
28 /* Enable ASSIST_PLL */
29 setbits_le32(priv->base + CMU_ASSISTPLL, BIT(0));
30 udelay(PLL_STABILITY_WAIT_US);
33 /* Source HOSC to DEV_CLK */
34 clrbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
36 /* Configure BUS_CLK */
37 bus_clk |= (CMU_PDBGDIV_DIV | CMU_PERDIV_DIV | CMU_NOCDIV_DIV |
38 CMU_DMMCLK_SRC | CMU_APBCLK_DIV | CMU_AHBCLK_DIV |
39 CMU_NOCCLK_SRC | CMU_CORECLK_HOSC);
40 writel(bus_clk, priv->base + CMU_BUSCLK);
42 udelay(PLL_STABILITY_WAIT_US);
44 /* Configure CORE_PLL */
45 core_pll = readl(priv->base + CMU_COREPLL);
46 core_pll |= (CMU_COREPLL_EN | CMU_COREPLL_HOSC_EN | CMU_COREPLL_OUT);
47 writel(core_pll, priv->base + CMU_COREPLL);
49 udelay(PLL_STABILITY_WAIT_US);
51 /* Configure DEV_PLL */
52 dev_pll = readl(priv->base + CMU_DEVPLL);
53 dev_pll |= (CMU_DEVPLL_EN | CMU_DEVPLL_OUT);
54 writel(dev_pll, priv->base + CMU_DEVPLL);
56 udelay(PLL_STABILITY_WAIT_US);
58 /* Source CORE_PLL for CORE_CLK */
59 clrsetbits_le32(priv->base + CMU_BUSCLK, CMU_CORECLK_MASK,
62 /* Source DEV_PLL for DEV_CLK */
63 setbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
65 udelay(PLL_STABILITY_WAIT_US);
68 int owl_clk_enable(struct clk *clk)
70 struct owl_clk_priv *priv = dev_get_priv(clk->dev);
71 enum owl_soc model = dev_get_driver_data(clk->dev);
77 /* Source HOSC for UART5 interface */
78 clrbits_le32(priv->base + CMU_UART5CLK, CMU_UARTCLK_SRC_DEVPLL);
79 /* Enable UART5 interface clock */
80 setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
85 /* Source HOSC for UART3 interface */
86 clrbits_le32(priv->base + CMU_UART3CLK, CMU_UARTCLK_SRC_DEVPLL);
87 /* Enable UART3 interface clock */
88 setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3);
97 int owl_clk_disable(struct clk *clk)
99 struct owl_clk_priv *priv = dev_get_priv(clk->dev);
100 enum owl_soc model = dev_get_driver_data(clk->dev);
106 /* Disable UART5 interface clock */
107 clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
112 /* Disable UART3 interface clock */
113 clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3);
122 static int owl_clk_probe(struct udevice *dev)
124 struct owl_clk_priv *priv = dev_get_priv(dev);
126 priv->base = dev_read_addr(dev);
127 if (priv->base == FDT_ADDR_T_NONE)
130 /* setup necessary clocks */
136 static const struct clk_ops owl_clk_ops = {
137 .enable = owl_clk_enable,
138 .disable = owl_clk_disable,
141 static const struct udevice_id owl_clk_ids[] = {
142 #if defined(CONFIG_MACH_S900)
143 { .compatible = "actions,s900-cmu", .data = S900 },
144 #elif defined(CONFIG_MACH_S700)
145 { .compatible = "actions,s700-cmu", .data = S700 },
150 U_BOOT_DRIVER(clk_owl) = {
153 .of_match = owl_clk_ids,
155 .priv_auto_alloc_size = sizeof(struct owl_clk_priv),
156 .probe = owl_clk_probe,