2 * Copyright 2012 Freescale Semiconductor, Inc.
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 #include <linux/clk-provider.h>
13 #include <linux/err.h>
15 #include <linux/slab.h>
19 * struct clk_ref - mxs reference clock
20 * @hw: clk_hw for the reference clock
21 * @reg: register address
22 * @idx: the index of the reference clock within the same register
24 * The mxs reference clock sources from pll. Every 4 reference clocks share
25 * one register space, and @idx is used to identify them. Each reference
26 * clock has a gate control and a fractional * divider. The rate is calculated
27 * as pll rate * (18 / FRAC), where FRAC = 18 ~ 35.
35 #define to_clk_ref(_hw) container_of(_hw, struct clk_ref, hw)
37 static int clk_ref_enable(struct clk_hw *hw)
39 struct clk_ref *ref = to_clk_ref(hw);
41 writel_relaxed(1 << ((ref->idx + 1) * 8 - 1), ref->reg + CLR);
46 static void clk_ref_disable(struct clk_hw *hw)
48 struct clk_ref *ref = to_clk_ref(hw);
50 writel_relaxed(1 << ((ref->idx + 1) * 8 - 1), ref->reg + SET);
53 static unsigned long clk_ref_recalc_rate(struct clk_hw *hw,
54 unsigned long parent_rate)
56 struct clk_ref *ref = to_clk_ref(hw);
57 u64 tmp = parent_rate;
58 u8 frac = (readl_relaxed(ref->reg) >> (ref->idx * 8)) & 0x3f;
66 static long clk_ref_round_rate(struct clk_hw *hw, unsigned long rate,
69 unsigned long parent_rate = *prate;
70 u64 tmp = parent_rate;
73 tmp = tmp * 18 + rate / 2;
89 static int clk_ref_set_rate(struct clk_hw *hw, unsigned long rate,
90 unsigned long parent_rate)
92 struct clk_ref *ref = to_clk_ref(hw);
94 u64 tmp = parent_rate;
96 u8 frac, shift = ref->idx * 8;
98 tmp = tmp * 18 + rate / 2;
107 spin_lock_irqsave(&mxs_lock, flags);
109 val = readl_relaxed(ref->reg);
110 val &= ~(0x3f << shift);
111 val |= frac << shift;
112 writel_relaxed(val, ref->reg);
114 spin_unlock_irqrestore(&mxs_lock, flags);
119 static const struct clk_ops clk_ref_ops = {
120 .enable = clk_ref_enable,
121 .disable = clk_ref_disable,
122 .recalc_rate = clk_ref_recalc_rate,
123 .round_rate = clk_ref_round_rate,
124 .set_rate = clk_ref_set_rate,
127 struct clk *mxs_clk_ref(const char *name, const char *parent_name,
128 void __iomem *reg, u8 idx)
132 struct clk_init_data init;
134 ref = kzalloc(sizeof(*ref), GFP_KERNEL);
136 return ERR_PTR(-ENOMEM);
139 init.ops = &clk_ref_ops;
141 init.parent_names = (parent_name ? &parent_name: NULL);
142 init.num_parents = (parent_name ? 1 : 0);
146 ref->hw.init = &init;
148 clk = clk_register(NULL, &ref->hw);