1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2012 Freescale Semiconductor, Inc.
6 #include <linux/clk-provider.h>
7 #include <linux/delay.h>
10 #include <linux/slab.h>
14 * struct clk_pll - mxs pll clock
15 * @hw: clk_hw for the pll
16 * @base: base address of the pll
17 * @power: the shift of power bit
18 * @rate: the clock rate of the pll
20 * The mxs pll is a fixed rate clock with power and gate control,
21 * and the shift of gate bit is always 31.
30 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
32 static int clk_pll_prepare(struct clk_hw *hw)
34 struct clk_pll *pll = to_clk_pll(hw);
36 writel_relaxed(1 << pll->power, pll->base + SET);
43 static void clk_pll_unprepare(struct clk_hw *hw)
45 struct clk_pll *pll = to_clk_pll(hw);
47 writel_relaxed(1 << pll->power, pll->base + CLR);
50 static int clk_pll_enable(struct clk_hw *hw)
52 struct clk_pll *pll = to_clk_pll(hw);
54 writel_relaxed(1 << 31, pll->base + CLR);
59 static void clk_pll_disable(struct clk_hw *hw)
61 struct clk_pll *pll = to_clk_pll(hw);
63 writel_relaxed(1 << 31, pll->base + SET);
66 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
67 unsigned long parent_rate)
69 struct clk_pll *pll = to_clk_pll(hw);
74 static const struct clk_ops clk_pll_ops = {
75 .prepare = clk_pll_prepare,
76 .unprepare = clk_pll_unprepare,
77 .enable = clk_pll_enable,
78 .disable = clk_pll_disable,
79 .recalc_rate = clk_pll_recalc_rate,
82 struct clk *mxs_clk_pll(const char *name, const char *parent_name,
83 void __iomem *base, u8 power, unsigned long rate)
87 struct clk_init_data init;
89 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
91 return ERR_PTR(-ENOMEM);
94 init.ops = &clk_pll_ops;
96 init.parent_names = (parent_name ? &parent_name: NULL);
97 init.num_parents = (parent_name ? 1 : 0);
102 pll->hw.init = &init;
104 clk = clk_register(NULL, &pll->hw);